1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Support for Intel Camera Imaging ISP subsystem. 4 * Copyright (c) 2015, Intel Corporation. 5 */ 6 7 #ifndef _SH_CSS_DEFS_H_ 8 #define _SH_CSS_DEFS_H_ 9 10 #include "isp.h" 11 12 /*#include "vamem.h"*/ /* Cannot include for VAMEM properties this file is visible on ISP -> pipeline generator */ 13 14 #include "math_support.h" /* max(), min, etc etc */ 15 16 /* ID's for refcount */ 17 #define IA_CSS_REFCOUNT_PARAM_SET_POOL 0xCAFE0001 18 #define IA_CSS_REFCOUNT_PARAM_BUFFER 0xCAFE0002 19 20 /* Digital Image Stabilization */ 21 #define SH_CSS_DIS_DECI_FACTOR_LOG2 6 22 23 /* UV offset: 1:uv=-128...127, 0:uv=0...255 */ 24 #define SH_CSS_UV_OFFSET_IS_0 0 25 26 /* Bits of bayer is adjusted as 13 in ISP */ 27 #define SH_CSS_BAYER_BITS 13 28 29 /* Max value of bayer data (unsigned 13bit in ISP) */ 30 #define SH_CSS_BAYER_MAXVAL ((1U << SH_CSS_BAYER_BITS) - 1) 31 32 /* Bits of yuv in ISP */ 33 #define SH_CSS_ISP_YUV_BITS 8 34 35 #define SH_CSS_DP_GAIN_SHIFT 5 36 #define SH_CSS_BNR_GAIN_SHIFT 13 37 #define SH_CSS_YNR_GAIN_SHIFT 13 38 #define SH_CSS_AE_YCOEF_SHIFT 13 39 #define SH_CSS_AF_FIR_SHIFT 13 40 #define SH_CSS_YEE_DETAIL_GAIN_SHIFT 8 /* [u5.8] */ 41 #define SH_CSS_YEE_SCALE_SHIFT 8 42 #define SH_CSS_TNR_COEF_SHIFT 13 43 #define SH_CSS_MACC_COEF_SHIFT 11 /* [s2.11] for ISP1 */ 44 #define SH_CSS_MACC2_COEF_SHIFT 13 /* [s[exp].[13-exp]] for ISP2 */ 45 #define SH_CSS_DIS_COEF_SHIFT 13 46 47 /* enumeration of the bayer downscale factors. When a binary supports multiple 48 * factors, the OR of these defines is used to build the mask of supported 49 * factors. The BDS factor is used in pre-processor expressions so we cannot 50 * use an enum here. */ 51 #define SH_CSS_BDS_FACTOR_1_00 (0) 52 #define SH_CSS_BDS_FACTOR_1_25 (1) 53 #define SH_CSS_BDS_FACTOR_1_50 (2) 54 #define SH_CSS_BDS_FACTOR_2_00 (3) 55 #define SH_CSS_BDS_FACTOR_2_25 (4) 56 #define SH_CSS_BDS_FACTOR_2_50 (5) 57 #define SH_CSS_BDS_FACTOR_3_00 (6) 58 #define SH_CSS_BDS_FACTOR_4_00 (7) 59 #define SH_CSS_BDS_FACTOR_4_50 (8) 60 #define SH_CSS_BDS_FACTOR_5_00 (9) 61 #define SH_CSS_BDS_FACTOR_6_00 (10) 62 #define SH_CSS_BDS_FACTOR_8_00 (11) 63 #define NUM_BDS_FACTORS (12) 64 65 #define PACK_BDS_FACTOR(factor) (1 << (factor)) 66 67 /* Following macros should match with the type enum ia_css_pipe_version in 68 * ia_css_pipe_public.h. The reason to add these macros is that enum type 69 * will be evaluted to 0 in preprocessing time. */ 70 #define SH_CSS_ISP_PIPE_VERSION_1 1 71 #define SH_CSS_ISP_PIPE_VERSION_2_2 2 72 #define SH_CSS_ISP_PIPE_VERSION_2_6_1 3 73 #define SH_CSS_ISP_PIPE_VERSION_2_7 4 74 75 /*--------------- sRGB Gamma ----------------- 76 CCM : YCgCo[0,8191] -> RGB[0,4095] 77 sRGB Gamma : RGB [0,4095] -> RGB[0,8191] 78 CSC : RGB [0,8191] -> YUV[0,8191] 79 80 CCM: 81 Y[0,8191],CgCo[-4096,4095],coef[-8192,8191] -> RGB[0,4095] 82 83 sRGB Gamma: 84 RGB[0,4095] -(interpolation step16)-> RGB[0,255] -(LUT 12bit)-> RGB[0,4095] -> RGB[0,8191] 85 86 CSC: 87 RGB[0,8191],coef[-8192,8191] -> RGB[0,8191] 88 --------------------------------------------*/ 89 /* Bits of input/output of sRGB Gamma */ 90 #define SH_CSS_RGB_GAMMA_INPUT_BITS 12 /* [0,4095] */ 91 #define SH_CSS_RGB_GAMMA_OUTPUT_BITS 13 /* [0,8191] */ 92 93 /* Bits of fractional part of interpolation in vamem, [0,4095]->[0,255] */ 94 #define SH_CSS_RGB_GAMMA_FRAC_BITS \ 95 (SH_CSS_RGB_GAMMA_INPUT_BITS - SH_CSS_ISP_RGB_GAMMA_TABLE_SIZE_LOG2) 96 #define SH_CSS_RGB_GAMMA_ONE BIT(SH_CSS_RGB_GAMMA_FRAC_BITS) 97 98 /* Bits of input of CCM, = 13, Y[0,8191],CgCo[-4096,4095] */ 99 #define SH_CSS_YUV2RGB_CCM_INPUT_BITS SH_CSS_BAYER_BITS 100 101 /* Bits of output of CCM, = 12, RGB[0,4095] */ 102 #define SH_CSS_YUV2RGB_CCM_OUTPUT_BITS SH_CSS_RGB_GAMMA_INPUT_BITS 103 104 /* Maximum value of output of CCM */ 105 #define SH_CSS_YUV2RGB_CCM_MAX_OUTPUT \ 106 ((1 << SH_CSS_YUV2RGB_CCM_OUTPUT_BITS) - 1) 107 108 #define SH_CSS_NUM_INPUT_BUF_LINES 4 109 110 /* Left cropping only applicable for sufficiently large nway */ 111 #define SH_CSS_MAX_LEFT_CROPPING 12 112 #define SH_CSS_MAX_TOP_CROPPING 12 113 114 #define SH_CSS_SP_MAX_WIDTH 1280 115 116 /* This is the maximum grid we can handle in the ISP binaries. 117 * The host code makes sure no bigger grid is ever selected. */ 118 #define SH_CSS_MAX_BQ_GRID_WIDTH 80 119 #define SH_CSS_MAX_BQ_GRID_HEIGHT 60 120 121 /* The minimum dvs envelope is 12x12(for IPU2) to make sure the 122 * invalid rows/columns that result from filter initialization are skipped. */ 123 #define SH_CSS_MIN_DVS_ENVELOPE 12U 124 125 /* The FPGA system (vec_nelems == 16) only supports up to 5MP */ 126 #define SH_CSS_MAX_SENSOR_WIDTH 4608 127 #define SH_CSS_MAX_SENSOR_HEIGHT 3450 128 129 /* Limited to reduce vmem pressure */ 130 #if ISP_VMEM_DEPTH >= 3072 131 #define SH_CSS_MAX_CONTINUOUS_SENSOR_WIDTH SH_CSS_MAX_SENSOR_WIDTH 132 #define SH_CSS_MAX_CONTINUOUS_SENSOR_HEIGHT SH_CSS_MAX_SENSOR_HEIGHT 133 #else 134 #define SH_CSS_MAX_CONTINUOUS_SENSOR_WIDTH 3264 135 #define SH_CSS_MAX_CONTINUOUS_SENSOR_HEIGHT 2448 136 #endif 137 /* When using bayer decimation */ 138 /* 139 #define SH_CSS_MAX_CONTINUOUS_SENSOR_WIDTH_DEC 4224 140 #define SH_CSS_MAX_CONTINUOUS_SENSOR_HEIGHT_DEC 3168 141 */ 142 #define SH_CSS_MAX_CONTINUOUS_SENSOR_WIDTH_DEC SH_CSS_MAX_SENSOR_WIDTH 143 #define SH_CSS_MAX_CONTINUOUS_SENSOR_HEIGHT_DEC SH_CSS_MAX_SENSOR_HEIGHT 144 145 #define SH_CSS_MIN_SENSOR_WIDTH 2 146 #define SH_CSS_MIN_SENSOR_HEIGHT 2 147 148 /* 149 #define SH_CSS_MAX_VF_WIDTH_DEC 1920 150 #define SH_CSS_MAX_VF_HEIGHT_DEC 1080 151 */ 152 #define SH_CSS_MAX_VF_WIDTH_DEC SH_CSS_MAX_VF_WIDTH 153 #define SH_CSS_MAX_VF_HEIGHT_DEC SH_CSS_MAX_VF_HEIGHT 154 155 /* We use 16 bits per coordinate component, including integer 156 and fractional bits */ 157 #define SH_CSS_MORPH_TABLE_GRID ISP_VEC_NELEMS 158 #define SH_CSS_MORPH_TABLE_ELEM_BYTES 2 159 #define SH_CSS_MORPH_TABLE_ELEMS_PER_DDR_WORD \ 160 (HIVE_ISP_DDR_WORD_BYTES / SH_CSS_MORPH_TABLE_ELEM_BYTES) 161 162 #define SH_CSS_MAX_SCTBL_WIDTH_PER_COLOR (SH_CSS_MAX_BQ_GRID_WIDTH + 1) 163 #define SH_CSS_MAX_SCTBL_HEIGHT_PER_COLOR (SH_CSS_MAX_BQ_GRID_HEIGHT + 1) 164 165 #define SH_CSS_MAX_SCTBL_ALIGNED_WIDTH_PER_COLOR \ 166 CEIL_MUL(SH_CSS_MAX_SCTBL_WIDTH_PER_COLOR, ISP_VEC_NELEMS) 167 168 /* Each line of this table is aligned to the maximum line width. */ 169 #define SH_CSS_MAX_S3ATBL_WIDTH SH_CSS_MAX_BQ_GRID_WIDTH 170 171 /* Video mode specific DVS define */ 172 /* The video binary supports a delay of 1 or 2 frames */ 173 #define MAX_DVS_FRAME_DELAY 2 174 /* +1 because DVS reads the previous and writes the current frame concurrently */ 175 #define MAX_NUM_VIDEO_DELAY_FRAMES (MAX_DVS_FRAME_DELAY + 1) 176 177 #define NUM_VIDEO_TNR_FRAMES 2 178 179 /* Note that this is the define used to configure all data structures common for all modes */ 180 /* It should be equal or bigger to the max number of DVS frames for all possible modes */ 181 /* Rules: these implement logic shared between the host code and ISP firmware. 182 The ISP firmware needs these rules to be applied at pre-processor time, 183 that's why these are macros, not functions. */ 184 #define _ISP_BQS(num) ((num) / 2) 185 #define _ISP_VECS(width) CEIL_DIV(width, ISP_VEC_NELEMS) 186 187 #define ISP_BQ_GRID_WIDTH(elements_per_line, deci_factor_log2) \ 188 CEIL_SHIFT(elements_per_line / 2, deci_factor_log2) 189 #define ISP_BQ_GRID_HEIGHT(lines_per_frame, deci_factor_log2) \ 190 CEIL_SHIFT(lines_per_frame / 2, deci_factor_log2) 191 #define ISP_C_VECTORS_PER_LINE(elements_per_line) \ 192 _ISP_VECS(elements_per_line / 2) 193 194 /* The morphing table is similar to the shading table in the sense that we 195 have 1 more value than we have cells in the grid. */ 196 #define _ISP_MORPH_TABLE_WIDTH(int_width) \ 197 (CEIL_DIV(int_width, SH_CSS_MORPH_TABLE_GRID) + 1) 198 #define _ISP_MORPH_TABLE_HEIGHT(int_height) \ 199 (CEIL_DIV(int_height, SH_CSS_MORPH_TABLE_GRID) + 1) 200 #define _ISP_MORPH_TABLE_ALIGNED_WIDTH(width) \ 201 CEIL_MUL(_ISP_MORPH_TABLE_WIDTH(width), \ 202 SH_CSS_MORPH_TABLE_ELEMS_PER_DDR_WORD) 203 204 #define _ISP_SCTBL_WIDTH_PER_COLOR(input_width, deci_factor_log2) \ 205 (ISP_BQ_GRID_WIDTH(input_width, deci_factor_log2) + 1) 206 #define _ISP_SCTBL_HEIGHT(input_height, deci_factor_log2) \ 207 (ISP_BQ_GRID_HEIGHT(input_height, deci_factor_log2) + 1) 208 #define _ISP_SCTBL_ALIGNED_WIDTH_PER_COLOR(input_width, deci_factor_log2) \ 209 CEIL_MUL(_ISP_SCTBL_WIDTH_PER_COLOR(input_width, deci_factor_log2), \ 210 ISP_VEC_NELEMS) 211 212 /* To position the shading center grid point on the center of output image, 213 * one more grid cell is needed as margin. */ 214 #define SH_CSS_SCTBL_CENTERING_MARGIN 1 215 216 /* The shading table width and height are the number of grids, not cells. The last grid should be counted. */ 217 #define SH_CSS_SCTBL_LAST_GRID_COUNT 1 218 219 /* Number of horizontal grids per color in the shading table. */ 220 #define _ISP2401_SCTBL_WIDTH_PER_COLOR(input_width, deci_factor_log2) \ 221 (ISP_BQ_GRID_WIDTH(input_width, deci_factor_log2) + \ 222 SH_CSS_SCTBL_CENTERING_MARGIN + SH_CSS_SCTBL_LAST_GRID_COUNT) 223 224 /* Number of vertical grids per color in the shading table. */ 225 #define _ISP2401_SCTBL_HEIGHT(input_height, deci_factor_log2) \ 226 (ISP_BQ_GRID_HEIGHT(input_height, deci_factor_log2) + \ 227 SH_CSS_SCTBL_CENTERING_MARGIN + SH_CSS_SCTBL_LAST_GRID_COUNT) 228 229 /* ISP2401: Legacy API: Number of horizontal grids per color in the shading table. */ 230 #define _ISP_SCTBL_LEGACY_WIDTH_PER_COLOR(input_width, deci_factor_log2) \ 231 (ISP_BQ_GRID_WIDTH(input_width, deci_factor_log2) + SH_CSS_SCTBL_LAST_GRID_COUNT) 232 233 /* ISP2401: Legacy API: Number of vertical grids per color in the shading table. */ 234 #define _ISP_SCTBL_LEGACY_HEIGHT(input_height, deci_factor_log2) \ 235 (ISP_BQ_GRID_HEIGHT(input_height, deci_factor_log2) + SH_CSS_SCTBL_LAST_GRID_COUNT) 236 237 /* ***************************************************************** 238 * Statistics for 3A (Auto Focus, Auto White Balance, Auto Exposure) 239 * *****************************************************************/ 240 /* if left cropping is used, 3A statistics are also cropped by 2 vectors. */ 241 #define _ISP_S3ATBL_WIDTH(in_width, deci_factor_log2) \ 242 (_ISP_BQS(in_width) >> deci_factor_log2) 243 #define _ISP_S3ATBL_HEIGHT(in_height, deci_factor_log2) \ 244 (_ISP_BQS(in_height) >> deci_factor_log2) 245 #define _ISP_S3A_ELEMS_ISP_WIDTH(width, left_crop) \ 246 (width - ((left_crop) ? 2 * ISP_VEC_NELEMS : 0)) 247 248 #define _ISP_S3ATBL_ISP_WIDTH(in_width, deci_factor_log2) \ 249 CEIL_SHIFT(_ISP_BQS(in_width), deci_factor_log2) 250 #define _ISP_S3ATBL_ISP_HEIGHT(in_height, deci_factor_log2) \ 251 CEIL_SHIFT(_ISP_BQS(in_height), deci_factor_log2) 252 #define ISP_S3ATBL_VECTORS \ 253 _ISP_VECS(SH_CSS_MAX_S3ATBL_WIDTH * \ 254 (sizeof(struct ia_css_3a_output) / sizeof(int32_t))) 255 #define ISP_S3ATBL_HI_LO_STRIDE \ 256 (ISP_S3ATBL_VECTORS * ISP_VEC_NELEMS) 257 #define ISP_S3ATBL_HI_LO_STRIDE_BYTES \ 258 (sizeof(unsigned short) * ISP_S3ATBL_HI_LO_STRIDE) 259 260 /* Viewfinder support */ 261 #define __ISP_MAX_VF_OUTPUT_WIDTH(width, left_crop) \ 262 (width - 2 * ISP_VEC_NELEMS + ((left_crop) ? 2 * ISP_VEC_NELEMS : 0)) 263 264 #define __ISP_VF_OUTPUT_WIDTH_VECS(out_width, vf_log_downscale) \ 265 (_ISP_VECS((out_width) >> (vf_log_downscale))) 266 267 #define _ISP_VF_OUTPUT_WIDTH(vf_out_vecs) ((vf_out_vecs) * ISP_VEC_NELEMS) 268 #define _ISP_VF_OUTPUT_HEIGHT(out_height, vf_log_ds) \ 269 ((out_height) >> (vf_log_ds)) 270 271 #define _ISP_LOG_VECTOR_STEP(mode) \ 272 ((mode) == IA_CSS_BINARY_MODE_CAPTURE_PP ? 2 : 1) 273 274 /* It is preferred to have not more than 2x scaling at one step 275 * in GDC (assumption is for capture_pp and yuv_scale stages) */ 276 #define MAX_PREFERRED_YUV_DS_PER_STEP 2 277 278 /* Rules for computing the internal width. This is extremely complicated 279 * and definitely needs to be commented and explained. */ 280 #define _ISP_LEFT_CROP_EXTRA(left_crop) ((left_crop) > 0 ? 2 * ISP_VEC_NELEMS : 0) 281 282 #define __ISP_MIN_INTERNAL_WIDTH(num_chunks, pipelining, mode) \ 283 ((num_chunks) * (pipelining) * (1 << _ISP_LOG_VECTOR_STEP(mode)) * \ 284 ISP_VEC_NELEMS) 285 286 #define __ISP_PADDED_OUTPUT_WIDTH(out_width, dvs_env_width, left_crop) \ 287 ((out_width) + MAX(dvs_env_width, _ISP_LEFT_CROP_EXTRA(left_crop))) 288 289 #define __ISP_CHUNK_STRIDE_ISP(mode) \ 290 ((1 << _ISP_LOG_VECTOR_STEP(mode)) * ISP_VEC_NELEMS) 291 292 #define __ISP_CHUNK_STRIDE_DDR(c_subsampling, num_chunks) \ 293 ((c_subsampling) * (num_chunks) * HIVE_ISP_DDR_WORD_BYTES) 294 #define __ISP_INTERNAL_WIDTH(out_width, \ 295 dvs_env_width, \ 296 left_crop, \ 297 mode, \ 298 c_subsampling, \ 299 num_chunks, \ 300 pipelining) \ 301 CEIL_MUL2(CEIL_MUL2(MAX(__ISP_PADDED_OUTPUT_WIDTH(out_width, \ 302 dvs_env_width, \ 303 left_crop), \ 304 __ISP_MIN_INTERNAL_WIDTH(num_chunks, \ 305 pipelining, \ 306 mode) \ 307 ), \ 308 __ISP_CHUNK_STRIDE_ISP(mode) \ 309 ), \ 310 __ISP_CHUNK_STRIDE_DDR(c_subsampling, num_chunks) \ 311 ) 312 313 #define __ISP_INTERNAL_HEIGHT(out_height, dvs_env_height, top_crop) \ 314 ((out_height) + (dvs_env_height) + top_crop) 315 316 /* @GC: Input can be up to sensor resolution when either bayer downscaling 317 * or raw binning is enabled. 318 * Also, during continuous mode, we need to align to 4*NWAY since input 319 * should support binning */ 320 #define _ISP_MAX_INPUT_WIDTH(max_internal_width, enable_ds, enable_fixed_bayer_ds, enable_raw_bin, \ 321 enable_continuous) \ 322 ((enable_ds) ? \ 323 SH_CSS_MAX_SENSOR_WIDTH :\ 324 (enable_fixed_bayer_ds) ? \ 325 CEIL_MUL(SH_CSS_MAX_CONTINUOUS_SENSOR_WIDTH_DEC, 4 * ISP_VEC_NELEMS) : \ 326 (enable_raw_bin) ? \ 327 CEIL_MUL(SH_CSS_MAX_CONTINUOUS_SENSOR_WIDTH, 4 * ISP_VEC_NELEMS) : \ 328 (enable_continuous) ? \ 329 SH_CSS_MAX_CONTINUOUS_SENSOR_WIDTH \ 330 : max_internal_width) 331 332 #define _ISP_INPUT_WIDTH(internal_width, ds_input_width, enable_ds) \ 333 ((enable_ds) ? (ds_input_width) : (internal_width)) 334 335 #define _ISP_MAX_INPUT_HEIGHT(max_internal_height, enable_ds, enable_fixed_bayer_ds, enable_raw_bin, \ 336 enable_continuous) \ 337 ((enable_ds) ? \ 338 SH_CSS_MAX_SENSOR_HEIGHT :\ 339 (enable_fixed_bayer_ds) ? \ 340 SH_CSS_MAX_CONTINUOUS_SENSOR_HEIGHT_DEC : \ 341 (enable_raw_bin || enable_continuous) ? \ 342 SH_CSS_MAX_CONTINUOUS_SENSOR_HEIGHT \ 343 : max_internal_height) 344 345 #define _ISP_INPUT_HEIGHT(internal_height, ds_input_height, enable_ds) \ 346 ((enable_ds) ? (ds_input_height) : (internal_height)) 347 348 #define SH_CSS_MAX_STAGES 8 /* primary_stage[1-6], capture_pp, vf_pp */ 349 350 /* For CSI2+ input system, it requires extra paddinga from vmem */ 351 #define _ISP_EXTRA_PADDING_VECS 0 352 353 #endif /* _SH_CSS_DEFS_H_ */ 354