1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef _shader_code_gfx10_h_ 25 #define _shader_code_gfx10_h_ 26 27 static const uint32_t bufferclear_cs_shader_gfx10[] = { 28 0xD7460004, 0x04010C08, 0x7E000204, 0x7E020205, 29 0x7E040206, 0x7E060207, 0xE01C2000, 0x80000004, 30 0xBF810000 31 }; 32 33 static const uint32_t buffercopy_cs_shader_gfx10[] = { 34 0xD7460001, 0x04010C08, 0xE00C2000, 0x80000201, 35 0xBF8C3F70, 0xE01C2000, 0x80010201, 0xBF810000 36 }; 37 38 static const uint32_t ps_const_shader_gfx10[] = { 39 0x7E000200, 0x7E020201, 0x7E040202, 0x7E060203, 40 0x5E000300, 0x5E020702, 0xBF800000, 0xBF800000, 41 0xF8001C0F, 0x00000100, 0xBF810000 42 }; 43 44 #define ps_const_shader_patchinfo_code_size_gfx10 6 45 46 static const uint32_t ps_const_shader_patchinfo_code_gfx10[][10][6] = { 47 {{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001890, 0x00000000 }, 48 { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001801, 0x00000000 }, 49 { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001803, 0x00000100 }, 50 { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001803, 0x00000300 }, 51 { 0x5E000300, 0x5E020702, 0xBF800000, 0xBF800000, 0xF8001C0F, 0x00000100 }, 52 { 0xD7690000, 0x00020300, 0xD7690001, 0x00020702, 0xF8001C0F, 0x00000100 }, 53 { 0xD7680000, 0x00020300, 0xD7680001, 0x00020702, 0xF8001C0F, 0x00000100 }, 54 { 0xD76A0000, 0x00020300, 0xD76A0001, 0x00020702, 0xF8001C0F, 0x00000100 }, 55 { 0xD76B0000, 0x00020300, 0xD76B0001, 0x00020702, 0xF8001C0F, 0x00000100 }, 56 { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF800180F, 0x03020100 } 57 } 58 }; 59 60 static const uint32_t ps_const_shader_patchinfo_offset_gfx10[] = { 61 0x00000004 62 }; 63 64 #define ps_const_num_sh_registers_gfx10 2 65 66 static const struct reg_info ps_const_sh_registers_gfx10[] = { 67 {0x2C0A, 0x000C0000},//{ mmSPI_SHADER_PGM_RSRC1_PS, 0x000C0000 }, 68 {0x2C0B, 0x00000008}, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000008 } 69 }; 70 71 static const struct reg_info ps_const_context_registers_gfx10[] = 72 { 73 {0xA1B4, 0x00000002}, //{ mmSPI_PS_INPUT_ADDR, 0x00000002 }, 74 {0xA1B6, 0x00000000}, //{ mmSPI_PS_IN_CONTROL, 0x00000000 }, 75 {0xA08F, 0x0000000F}, //{ mmCB_SHADER_MASK, 0x0000000F }, 76 {0xA203, 0x00000010}, //{ mmDB_SHADER_CONTROL, 0x00000010 }, 77 {0xA1C4, 0x00000000}, //{ mmSPI_SHADER_Z_FORMAT, 0x00000000 }, 78 {0xA1B8, 0x00000000}, //{ mmSPI_BARYC_CNTL, 0x00000000 /* Always 0 for now */}, 79 {0xA1C5, 0x00000004}, //{ mmSPI_SHADER_COL_FORMAT, 0x00000004 /* SI_EXPORT_FMT_FP16_ABGR */ } 80 }; 81 82 #define ps_const_num_context_registers_gfx10 7 83 84 static const uint32_t ps_tex_shader_gfx10[] = { 85 0xBEFC030C, 0xBE8E047E, 0xBEFE0A7E, 0xC8080000, 86 0xC80C0100, 0xC8090001, 0xC80D0101, 0xF0800F0A, 87 0x00400402, 0x00000003, 0xBEFE040E, 0xBF8C0F70, 88 0x5E000B04, 0x5E020F06, 0xBF800000, 0xBF800000, 89 0xF8001C0F, 0x00000100, 0xBF810000 90 }; 91 92 static const uint32_t ps_tex_shader_patchinfo_offset_gfx10[] = { 93 0x0000000C 94 }; 95 96 #define ps_tex_shader_patchinfo_code_size_gfx10 6 97 98 static const uint32_t ps_tex_shader_patchinfo_code_gfx10[][10][6] = { 99 {{ 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001890, 0x00000000 }, 100 { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001801, 0x00000004 }, 101 { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001803, 0x00000504 }, 102 { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF8001803, 0x00000704 }, 103 { 0x5E000B04, 0x5E020F06, 0xBF800000, 0xBF800000, 0xF8001C0F, 0x00000100 }, 104 { 0xD7690000, 0x00020B04, 0xD7690001, 0x00020F06, 0xF8001C0F, 0x00000100 }, 105 { 0xD7680000, 0x00020B04, 0xD7680001, 0x00020F06, 0xF8001C0F, 0x00000100 }, 106 { 0xD76A0000, 0x00020B04, 0xD76A0001, 0x00020F06, 0xF8001C0F, 0x00000100 }, 107 { 0xD76B0000, 0x00020B04, 0xD76B0001, 0x00020F06, 0xF8001C0F, 0x00000100 }, 108 { 0xBF800000, 0xBF800000, 0xBF800000, 0xBF800000, 0xF800180F, 0x07060504 } 109 } 110 }; 111 112 static const struct reg_info ps_tex_sh_registers_gfx10[] = 113 { 114 {0x2C0A, 0xc0081}, //0x020C0080 }, //{ mmSPI_SHADER_PGM_RSRC1_PS, 0x020C0080 }, 115 {0x2C0B, 0x00000018 }, //{ mmSPI_SHADER_PGM_RSRC2_PS, 0x00000018 } 116 }; 117 118 #define ps_tex_num_sh_registers_gfx10 2 119 120 // Holds Context Register Information 121 static const struct reg_info ps_tex_context_registers_gfx10[] = 122 { 123 {0xA1B4, 0x00000002}, //{ mmSPI_PS_INPUT_ADDR, 0x00000002 }, 124 {0xA1B6, 0x00000001}, //{ mmSPI_PS_IN_CONTROL, 0x00000001 }, 125 {0xA08F, 0x0000000F}, //{ mmCB_SHADER_MASK, 0x0000000F }, 126 {0xA203, 0x00000010}, //{ mmDB_SHADER_CONTROL, 0x00000010 }, 127 {0xA1C4, 0x00000000}, //{ mmSPI_SHADER_Z_FORMAT, 0x00000000 }, 128 {0xA1B8, 0x00000000}, //{ mmSPI_BARYC_CNTL, 0x00000000 /* Always 0 for now */}, 129 {0xA1C5, 0x00000004}, //{ mmSPI_SHADER_COL_FORMAT, 0x00000004 /* SI_EXPORT_FMT_FP16_ABGR */ } 130 }; 131 132 #define ps_tex_num_context_registers_gfx10 7 133 134 static const uint32_t vs_RectPosTexFast_shader_gfx10[] = { 135 0x7E000B00, 0x060000F3, 0x7E020202, 0x7E040206, 136 0x7C040080, 0x060000F3, 0xD5010001, 0x01AA0200, 137 0x7E060203, 0xD5010002, 0x01AA0404, 0x7E080207, 138 0x7C040080, 0xD5010000, 0x01A80101, 0xD5010001, 139 0x01AA0601, 0x7E060208, 0x7E0A02F2, 0xD5010002, 140 0x01A80902, 0xD5010004, 0x01AA0805, 0x7E0C0209, 141 0xF80008CF, 0x05030100, 0xF800020F, 0x05060402, 142 0xBF810000 143 }; 144 145 static const struct reg_info vs_RectPosTexFast_sh_registers_gfx10[] = 146 { 147 {0x2C4A, 0x080C0041 }, //{ mmSPI_SHADER_PGM_RSRC1_VS, 0x080C0041 }, 148 {0x2C4B, 0x00000018 }, //{ mmSPI_SHADER_PGM_RSRC2_VS, 0x00000018 } 149 }; 150 151 #define vs_RectPosTexFast_num_sh_registers_gfx10 2 152 153 // Holds Context Register Information 154 static const struct reg_info vs_RectPosTexFast_context_registers_gfx10[] = 155 { 156 {0xA1B1, 0x00000000}, //{ mmSPI_VS_OUT_CONFIG, 0x00000000 }, 157 {0xA1C3, 0x00000000}, //{ mmSPI_SHADER_POS_FORMAT, 0x00000000 /* Always 0 for now */} 158 }; 159 160 #define vs_RectPosTexFast_num_context_registers_gfx10 2 161 162 static const uint32_t preamblecache_gfx10[] = { 163 0xc0026900, 0x81, 0x80000000, 0x40004000, 0xc0026900, 0x8c, 0xaa99aaaa, 0x0, 164 0xc0026900, 0x90, 0x80000000, 0x40004000, 0xc0026900, 0x94, 0x80000000, 0x40004000, 165 0xc0026900, 0xb4, 0x0, 0x3f800000, 0xc0016900, 0x103, 0x0, 166 0xc0016900, 0x208, 0x0, 0xc0016900, 0x290, 0x0, 167 0xc0016900, 0x2a1, 0x0, 0xc0026900, 0x2ad, 0x0, 0x0, 168 0xc0016900, 0x2d5, 0x10000, 0xc0016900, 0x2dc, 0x0, 169 0xc0066900, 0x2de, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xc0026900, 0x2e5, 0x0, 0x0, 170 0xc0056900, 0x2f9, 0x5, 0x3f800000, 0x3f800000, 0x3f800000, 0x3f800000, 171 0xc0046900, 0x310, 0, 0x3, 0, 0x100000, 0xc0026900, 0x316, 0xe, 0x20, 172 0xc0016900, 0x349, 0x0, 0xc0016900, 0x358, 0x0, 0xc0016900, 0x367, 0x0, 173 0xc0016900, 0x376, 0x0, 0xc0016900, 0x385, 0x0, 0xc0016900, 0x6, 0x0, 174 0xc0056900, 0xe8, 0x0, 0x0, 0x0, 0x0, 0x0, 175 0xc0076900, 0x1e1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 176 0xc0026900, 0x204, 0x90000, 0x4, 0xc0046900, 0x20c, 0x0, 0x0, 0x0, 0x0, 177 0xc0016900, 0x2b2, 0x0, 0xc0026900, 0x30e, 0xffffffff, 0xffffffff, 178 0xc0016900, 0x314, 0x0, 0xc0016900, 0x10a, 0, 0xc0016900, 0x2a6, 0, 0xc0016900, 0x210, 0, 179 0xc0016900, 0x2db, 0, 0xc0016900, 0x1d4, 0, 0xc0002f00, 0x1, 0xc0016900, 0x1, 0x1, 0xc0016900, 0xe, 0x2, 180 0xc0016900, 0x206, 0x300, 0xc0016900, 0x212, 0x200, 0xc0017900, 0x7b, 0x20, 0xc0017a00, 0x20000243, 0x0, 181 0xc0017900, 0x249, 0, 0xc0017900, 0x24a, 0, 0xc0017900, 0x24b, 0, 0xc0017900, 0x259, 0xffffffff, 182 0xc0017900, 0x25f, 0, 0xc0017900, 0x260, 0, 0xc0017900, 0x262, 0, 183 0xc0017600, 0x45, 0x0, 0xc0017600, 0x6, 0x0, 184 0xc0067600, 0x70, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 185 0xc0067600, 0x30, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 186 }; 187 188 static const uint32_t cached_cmd_gfx10[] = { 189 0xc0016900, 0x0, 0x0, 0xc0026900, 0x3, 0x2a, 0x0, 190 0xc0046900, 0xa, 0x0, 0x0, 0x0, 0x200020, 191 0xc0016900, 0x83, 0xffff, 0xc0026900, 0x8e, 0xf, 0xf, 192 0xc0056900, 0x105, 0x0, 0x0, 0x0, 0x0, 0x18, 193 0xc0026900, 0x10b, 0x0, 0x0, 0xc0016900, 0x1e0, 0x0, 194 0xc0036900, 0x200, 0x0, 0x10000, 0xcc0011, 195 0xc0026900, 0x292, 0x20, 0x6020000, 196 0xc0026900, 0x2b0, 0x0, 0x0, 0xc0016900, 0x2f8, 0x0 197 }; 198 199 #define sh_reg_base_gfx10 0x2C00 200 #define context_reg_base_gfx10 0xA000 201 202 #endif 203