1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * SPDX-License-Identifier: MIT
5 */
6
7 #include "si_build_pm4.h"
8 #include "si_query.h"
9 #include "si_shader_internal.h"
10 #include "sid.h"
11 #include "util/fast_idiv_by_const.h"
12 #include "util/format/u_format.h"
13 #include "util/format/u_format_s3tc.h"
14 #include "util/u_dual_blend.h"
15 #include "util/u_helpers.h"
16 #include "util/u_memory.h"
17 #include "util/u_resource.h"
18 #include "util/u_upload_mgr.h"
19 #include "util/u_blend.h"
20
21 #include "ac_cmdbuf.h"
22 #include "ac_descriptors.h"
23 #include "ac_formats.h"
24 #include "gfx10_format_table.h"
25
26 /* 12.4 fixed-point */
si_pack_float_12p4(float x)27 static unsigned si_pack_float_12p4(float x)
28 {
29 return x <= 0 ? 0 : x >= 4096 ? 0xffff : x * 16;
30 }
31
32 /*
33 * Inferred framebuffer and blender state.
34 *
35 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
36 * if there is not enough PS outputs.
37 */
si_emit_cb_render_state(struct si_context * sctx,unsigned index)38 static void si_emit_cb_render_state(struct si_context *sctx, unsigned index)
39 {
40 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
41 struct si_state_blend *blend = sctx->queued.named.blend;
42 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
43 * but you never know. */
44 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit & blend->cb_target_mask;
45 unsigned i;
46
47 /* Avoid a hang that happens when dual source blending is enabled
48 * but there is not enough color outputs. This is undefined behavior,
49 * so disable color writes completely.
50 *
51 * Reproducible with Unigine Heaven 4.0 and drirc missing.
52 */
53 if (blend->dual_src_blend && sctx->shader.ps.cso &&
54 (sctx->shader.ps.cso->info.colors_written & 0x3) != 0x3)
55 cb_target_mask = 0;
56
57 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
58 * I think we don't have to do anything between IBs.
59 */
60 if (sctx->screen->dpbb_allowed && sctx->last_cb_target_mask != cb_target_mask &&
61 sctx->screen->pbb_context_states_per_bin > 1) {
62 sctx->last_cb_target_mask = cb_target_mask;
63
64 radeon_begin(cs);
65 radeon_event_write(V_028A90_BREAK_BATCH);
66 radeon_end();
67 }
68
69 uint32_t cb_dcc_control = 0;
70
71 if (sctx->gfx_level >= GFX8 && sctx->gfx_level < GFX12) {
72 /* DCC MSAA workaround.
73 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
74 * COMBINER_DISABLE, but that would be more complicated.
75 */
76 bool oc_disable =
77 blend->dcc_msaa_corruption_4bit & cb_target_mask && sctx->framebuffer.nr_samples >= 2;
78
79 if (sctx->gfx_level >= GFX11) {
80 cb_dcc_control =
81 S_028424_SAMPLE_MASK_TRACKER_DISABLE(oc_disable) |
82 S_028424_SAMPLE_MASK_TRACKER_WATERMARK(sctx->screen->info.has_dedicated_vram ? 0 : 15);
83 } else {
84 cb_dcc_control =
85 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(sctx->gfx_level <= GFX9) |
86 S_028424_OVERWRITE_COMBINER_WATERMARK(sctx->gfx_level >= GFX10 ? 6 : 4) |
87 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable) |
88 S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx->gfx_level < GFX11 &&
89 sctx->screen->info.has_dcc_constant_encode);
90 }
91 }
92
93 uint32_t sx_ps_downconvert = 0;
94 uint32_t sx_blend_opt_epsilon = 0;
95 uint32_t sx_blend_opt_control = 0;
96
97 /* RB+ register settings. */
98 if (sctx->screen->info.rbplus_allowed) {
99 unsigned spi_shader_col_format =
100 sctx->shader.ps.cso ? sctx->shader.ps.current->key.ps.part.epilog.spi_shader_col_format
101 : 0;
102 unsigned num_cbufs = util_last_bit(sctx->framebuffer.colorbuf_enabled_4bit &
103 blend->cb_target_enabled_4bit) / 4;
104
105 for (i = 0; i < num_cbufs; i++) {
106 struct si_surface *surf = (struct si_surface *)sctx->framebuffer.state.cbufs[i];
107 unsigned format, swap, spi_format, colormask;
108 bool has_alpha, has_rgb;
109
110 if (!surf) {
111 /* If the color buffer is not set, the driver sets 32_R
112 * as the SPI color format, because the hw doesn't allow
113 * holes between color outputs, so also set this to
114 * enable RB+.
115 */
116 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
117 continue;
118 }
119
120 format = sctx->gfx_level >= GFX11 ? G_028C70_FORMAT_GFX11(surf->cb.cb_color_info):
121 G_028C70_FORMAT_GFX6(surf->cb.cb_color_info);
122 swap = G_028C70_COMP_SWAP(surf->cb.cb_color_info);
123 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
124 colormask = (cb_target_mask >> (i * 4)) & 0xf;
125
126 /* Set if RGB and A are present. */
127 has_alpha = !(sctx->gfx_level >= GFX11 ? G_028C74_FORCE_DST_ALPHA_1_GFX11(surf->cb.cb_color_attrib):
128 G_028C74_FORCE_DST_ALPHA_1_GFX6(surf->cb.cb_color_attrib));
129
130 if (format == V_028C70_COLOR_8 || format == V_028C70_COLOR_16 ||
131 format == V_028C70_COLOR_32)
132 has_rgb = !has_alpha;
133 else
134 has_rgb = true;
135
136 /* Check the colormask and export format. */
137 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
138 has_rgb = false;
139 if (!(colormask & PIPE_MASK_A))
140 has_alpha = false;
141
142 if (spi_format == V_028714_SPI_SHADER_ZERO) {
143 has_rgb = false;
144 has_alpha = false;
145 }
146
147 /* Disable value checking for disabled channels. */
148 if (!has_rgb)
149 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
150 if (!has_alpha)
151 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
152
153 /* Enable down-conversion for 32bpp and smaller formats. */
154 switch (format) {
155 case V_028C70_COLOR_8:
156 case V_028C70_COLOR_8_8:
157 case V_028C70_COLOR_8_8_8_8:
158 /* For 1 and 2-channel formats, use the superset thereof. */
159 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
160 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
161 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
162 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
163 if (G_028C70_NUMBER_TYPE(surf->cb.cb_color_info) != V_028C70_NUMBER_SRGB)
164 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT_0_5 << (i * 4);
165 }
166 break;
167
168 case V_028C70_COLOR_5_6_5:
169 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
170 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
171 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT_0_5 << (i * 4);
172 }
173 break;
174
175 case V_028C70_COLOR_1_5_5_5:
176 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
177 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
178 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT_0_5 << (i * 4);
179 }
180 break;
181
182 case V_028C70_COLOR_4_4_4_4:
183 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
184 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
185 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT_0_5 << (i * 4);
186 }
187 break;
188
189 case V_028C70_COLOR_32:
190 if (swap == V_028C70_SWAP_STD && spi_format == V_028714_SPI_SHADER_32_R)
191 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
192 else if (swap == V_028C70_SWAP_ALT_REV && spi_format == V_028714_SPI_SHADER_32_AR)
193 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
194 break;
195
196 case V_028C70_COLOR_16:
197 case V_028C70_COLOR_16_16:
198 /* For 1-channel formats, use the superset thereof. */
199 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
200 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
201 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
202 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
203 if (swap == V_028C70_SWAP_STD || swap == V_028C70_SWAP_STD_REV)
204 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
205 else
206 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
207 }
208 break;
209
210 case V_028C70_COLOR_10_11_11:
211 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR)
212 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
213 break;
214
215 case V_028C70_COLOR_2_10_10_10:
216 case V_028C70_COLOR_10_10_10_2:
217 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
218 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
219 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT_0_5 << (i * 4);
220 }
221 break;
222
223 case V_028C70_COLOR_5_9_9_9:
224 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR)
225 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_9_9_9_E5 << (i * 4);
226 break;
227 }
228 }
229
230 /* If there are no color outputs, the first color export is
231 * always enabled as 32_R, so also set this to enable RB+.
232 */
233 if (!sx_ps_downconvert)
234 sx_ps_downconvert = V_028754_SX_RT_EXPORT_32_R;
235 }
236
237 if (sctx->gfx_level >= GFX12) {
238 /* GFX12 doesn't have CB_FDCC_CONTROL. */
239 assert(cb_dcc_control == 0);
240
241 radeon_begin(cs);
242 gfx12_begin_context_regs();
243 gfx12_opt_set_context_reg(R_028850_CB_TARGET_MASK, SI_TRACKED_CB_TARGET_MASK,
244 cb_target_mask);
245 gfx12_opt_set_context_reg(R_028754_SX_PS_DOWNCONVERT, SI_TRACKED_SX_PS_DOWNCONVERT,
246 sx_ps_downconvert);
247 gfx12_opt_set_context_reg(R_028758_SX_BLEND_OPT_EPSILON, SI_TRACKED_SX_BLEND_OPT_EPSILON,
248 sx_blend_opt_epsilon);
249 gfx12_opt_set_context_reg(R_02875C_SX_BLEND_OPT_CONTROL, SI_TRACKED_SX_BLEND_OPT_CONTROL,
250 sx_blend_opt_control);
251 gfx12_end_context_regs();
252 radeon_end(); /* don't track context rolls on GFX12 */
253 } else if (sctx->screen->info.has_set_context_pairs_packed) {
254 radeon_begin(cs);
255 gfx11_begin_packed_context_regs();
256 gfx11_opt_set_context_reg(R_028238_CB_TARGET_MASK, SI_TRACKED_CB_TARGET_MASK,
257 cb_target_mask);
258 gfx11_opt_set_context_reg(R_028424_CB_DCC_CONTROL, SI_TRACKED_CB_DCC_CONTROL,
259 cb_dcc_control);
260 gfx11_opt_set_context_reg(R_028754_SX_PS_DOWNCONVERT, SI_TRACKED_SX_PS_DOWNCONVERT,
261 sx_ps_downconvert);
262 gfx11_opt_set_context_reg(R_028758_SX_BLEND_OPT_EPSILON, SI_TRACKED_SX_BLEND_OPT_EPSILON,
263 sx_blend_opt_epsilon);
264 gfx11_opt_set_context_reg(R_02875C_SX_BLEND_OPT_CONTROL, SI_TRACKED_SX_BLEND_OPT_CONTROL,
265 sx_blend_opt_control);
266 gfx11_end_packed_context_regs();
267 radeon_end(); /* don't track context rolls on GFX11 */
268 } else {
269 radeon_begin(cs);
270 radeon_opt_set_context_reg(R_028238_CB_TARGET_MASK, SI_TRACKED_CB_TARGET_MASK,
271 cb_target_mask);
272 if (sctx->gfx_level >= GFX8) {
273 radeon_opt_set_context_reg(R_028424_CB_DCC_CONTROL, SI_TRACKED_CB_DCC_CONTROL,
274 cb_dcc_control);
275 }
276 if (sctx->screen->info.rbplus_allowed) {
277 radeon_opt_set_context_reg3(R_028754_SX_PS_DOWNCONVERT, SI_TRACKED_SX_PS_DOWNCONVERT,
278 sx_ps_downconvert, sx_blend_opt_epsilon, sx_blend_opt_control);
279 }
280 radeon_end_update_context_roll();
281 }
282 }
283
284 /*
285 * Blender functions
286 */
287
si_translate_blend_function(int blend_func)288 static uint32_t si_translate_blend_function(int blend_func)
289 {
290 switch (blend_func) {
291 case PIPE_BLEND_ADD:
292 return V_028780_COMB_DST_PLUS_SRC;
293 case PIPE_BLEND_SUBTRACT:
294 return V_028780_COMB_SRC_MINUS_DST;
295 case PIPE_BLEND_REVERSE_SUBTRACT:
296 return V_028780_COMB_DST_MINUS_SRC;
297 case PIPE_BLEND_MIN:
298 return V_028780_COMB_MIN_DST_SRC;
299 case PIPE_BLEND_MAX:
300 return V_028780_COMB_MAX_DST_SRC;
301 default:
302 PRINT_ERR("Unknown blend function %d\n", blend_func);
303 assert(0);
304 break;
305 }
306 return 0;
307 }
308
si_translate_blend_factor(enum amd_gfx_level gfx_level,int blend_fact)309 static uint32_t si_translate_blend_factor(enum amd_gfx_level gfx_level, int blend_fact)
310 {
311 switch (blend_fact) {
312 case PIPE_BLENDFACTOR_ONE:
313 return V_028780_BLEND_ONE;
314 case PIPE_BLENDFACTOR_SRC_COLOR:
315 return V_028780_BLEND_SRC_COLOR;
316 case PIPE_BLENDFACTOR_SRC_ALPHA:
317 return V_028780_BLEND_SRC_ALPHA;
318 case PIPE_BLENDFACTOR_DST_ALPHA:
319 return V_028780_BLEND_DST_ALPHA;
320 case PIPE_BLENDFACTOR_DST_COLOR:
321 return V_028780_BLEND_DST_COLOR;
322 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
323 return V_028780_BLEND_SRC_ALPHA_SATURATE;
324 case PIPE_BLENDFACTOR_CONST_COLOR:
325 return gfx_level >= GFX11 ? V_028780_BLEND_CONSTANT_COLOR_GFX11:
326 V_028780_BLEND_CONSTANT_COLOR_GFX6;
327 case PIPE_BLENDFACTOR_CONST_ALPHA:
328 return gfx_level >= GFX11 ? V_028780_BLEND_CONSTANT_ALPHA_GFX11 :
329 V_028780_BLEND_CONSTANT_ALPHA_GFX6;
330 case PIPE_BLENDFACTOR_ZERO:
331 return V_028780_BLEND_ZERO;
332 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
333 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
334 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
335 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
336 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
337 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
338 case PIPE_BLENDFACTOR_INV_DST_COLOR:
339 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
340 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
341 return gfx_level >= GFX11 ? V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR_GFX11:
342 V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR_GFX6;
343 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
344 return gfx_level >= GFX11 ? V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA_GFX11:
345 V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA_GFX6;
346 case PIPE_BLENDFACTOR_SRC1_COLOR:
347 return gfx_level >= GFX11 ? V_028780_BLEND_SRC1_COLOR_GFX11:
348 V_028780_BLEND_SRC1_COLOR_GFX6;
349 case PIPE_BLENDFACTOR_SRC1_ALPHA:
350 return gfx_level >= GFX11 ? V_028780_BLEND_SRC1_ALPHA_GFX11:
351 V_028780_BLEND_SRC1_ALPHA_GFX6;
352 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
353 return gfx_level >= GFX11 ? V_028780_BLEND_INV_SRC1_COLOR_GFX11:
354 V_028780_BLEND_INV_SRC1_COLOR_GFX6;
355 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
356 return gfx_level >= GFX11 ? V_028780_BLEND_INV_SRC1_ALPHA_GFX11:
357 V_028780_BLEND_INV_SRC1_ALPHA_GFX6;
358 default:
359 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact);
360 assert(0);
361 break;
362 }
363 return 0;
364 }
365
si_translate_blend_opt_function(int blend_func)366 static uint32_t si_translate_blend_opt_function(int blend_func)
367 {
368 switch (blend_func) {
369 case PIPE_BLEND_ADD:
370 return V_028760_OPT_COMB_ADD;
371 case PIPE_BLEND_SUBTRACT:
372 return V_028760_OPT_COMB_SUBTRACT;
373 case PIPE_BLEND_REVERSE_SUBTRACT:
374 return V_028760_OPT_COMB_REVSUBTRACT;
375 case PIPE_BLEND_MIN:
376 return V_028760_OPT_COMB_MIN;
377 case PIPE_BLEND_MAX:
378 return V_028760_OPT_COMB_MAX;
379 default:
380 return V_028760_OPT_COMB_BLEND_DISABLED;
381 }
382 }
383
si_translate_blend_opt_factor(int blend_fact,bool is_alpha)384 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
385 {
386 switch (blend_fact) {
387 case PIPE_BLENDFACTOR_ZERO:
388 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
389 case PIPE_BLENDFACTOR_ONE:
390 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
391 case PIPE_BLENDFACTOR_SRC_COLOR:
392 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
393 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
394 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
395 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
396 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
397 case PIPE_BLENDFACTOR_SRC_ALPHA:
398 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
399 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
400 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
401 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
402 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
403 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
404 default:
405 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
406 }
407 }
408
si_blend_check_commutativity(struct si_screen * sscreen,struct si_state_blend * blend,enum pipe_blend_func func,enum pipe_blendfactor src,enum pipe_blendfactor dst,unsigned chanmask)409 static void si_blend_check_commutativity(struct si_screen *sscreen, struct si_state_blend *blend,
410 enum pipe_blend_func func, enum pipe_blendfactor src,
411 enum pipe_blendfactor dst, unsigned chanmask)
412 {
413 /* Src factor is allowed when it does not depend on Dst */
414 static const uint32_t src_allowed =
415 (1u << PIPE_BLENDFACTOR_ONE) | (1u << PIPE_BLENDFACTOR_SRC_COLOR) |
416 (1u << PIPE_BLENDFACTOR_SRC_ALPHA) | (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) |
417 (1u << PIPE_BLENDFACTOR_CONST_COLOR) | (1u << PIPE_BLENDFACTOR_CONST_ALPHA) |
418 (1u << PIPE_BLENDFACTOR_SRC1_COLOR) | (1u << PIPE_BLENDFACTOR_SRC1_ALPHA) |
419 (1u << PIPE_BLENDFACTOR_ZERO) | (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR) |
420 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA) | (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR) |
421 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA) | (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR) |
422 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA);
423
424 if (dst == PIPE_BLENDFACTOR_ONE && (src_allowed & (1u << src)) &&
425 (func == PIPE_BLEND_MAX || func == PIPE_BLEND_MIN))
426 blend->commutative_4bit |= chanmask;
427 }
428
429 /**
430 * Get rid of DST in the blend factors by commuting the operands:
431 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
432 */
si_blend_remove_dst(unsigned * func,unsigned * src_factor,unsigned * dst_factor,unsigned expected_dst,unsigned replacement_src)433 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor, unsigned *dst_factor,
434 unsigned expected_dst, unsigned replacement_src)
435 {
436 if (*src_factor == expected_dst && *dst_factor == PIPE_BLENDFACTOR_ZERO) {
437 *src_factor = PIPE_BLENDFACTOR_ZERO;
438 *dst_factor = replacement_src;
439
440 /* Commuting the operands requires reversing subtractions. */
441 if (*func == PIPE_BLEND_SUBTRACT)
442 *func = PIPE_BLEND_REVERSE_SUBTRACT;
443 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
444 *func = PIPE_BLEND_SUBTRACT;
445 }
446 }
447
si_create_blend_state_mode(struct pipe_context * ctx,const struct pipe_blend_state * state,unsigned mode)448 static void *si_create_blend_state_mode(struct pipe_context *ctx,
449 const struct pipe_blend_state *state, unsigned mode)
450 {
451 struct si_context *sctx = (struct si_context *)ctx;
452 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
453 struct si_pm4_state *pm4 = &blend->pm4;
454 uint32_t sx_mrt_blend_opt[8] = {0};
455 uint32_t color_control = 0;
456 bool logicop_enable = state->logicop_enable && state->logicop_func != PIPE_LOGICOP_COPY;
457
458 if (!blend)
459 return NULL;
460
461 si_pm4_clear_state(pm4, sctx->screen, false);
462
463 blend->alpha_to_coverage = state->alpha_to_coverage;
464 blend->alpha_to_one = state->alpha_to_one;
465 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
466 blend->logicop_enable = logicop_enable;
467 blend->allows_noop_optimization =
468 state->rt[0].rgb_func == PIPE_BLEND_ADD &&
469 state->rt[0].alpha_func == PIPE_BLEND_ADD &&
470 state->rt[0].rgb_src_factor == PIPE_BLENDFACTOR_DST_COLOR &&
471 state->rt[0].alpha_src_factor == PIPE_BLENDFACTOR_DST_COLOR &&
472 state->rt[0].rgb_dst_factor == PIPE_BLENDFACTOR_ZERO &&
473 state->rt[0].alpha_dst_factor == PIPE_BLENDFACTOR_ZERO &&
474 mode == V_028808_CB_NORMAL;
475
476 unsigned num_shader_outputs = state->max_rt + 1; /* estimate */
477 if (blend->dual_src_blend)
478 num_shader_outputs = MAX2(num_shader_outputs, 2);
479
480 if (logicop_enable) {
481 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
482 } else {
483 color_control |= S_028808_ROP3(0xcc);
484 }
485
486 unsigned db_alpha_to_mask;
487 if (state->alpha_to_coverage && state->alpha_to_coverage_dither) {
488 db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
489 S_028B70_ALPHA_TO_MASK_OFFSET0(3) | S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
490 S_028B70_ALPHA_TO_MASK_OFFSET2(0) | S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
491 S_028B70_OFFSET_ROUND(1);
492 } else {
493 db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
494 S_028B70_ALPHA_TO_MASK_OFFSET0(2) | S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
495 S_028B70_ALPHA_TO_MASK_OFFSET2(2) | S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
496 S_028B70_OFFSET_ROUND(0);
497 }
498
499 if (sctx->gfx_level >= GFX12)
500 ac_pm4_set_reg(&pm4->base, R_02807C_DB_ALPHA_TO_MASK, db_alpha_to_mask);
501 else
502 ac_pm4_set_reg(&pm4->base, R_028B70_DB_ALPHA_TO_MASK, db_alpha_to_mask);
503
504 blend->cb_target_mask = 0;
505 blend->cb_target_enabled_4bit = 0;
506
507 unsigned last_blend_cntl;
508
509 for (int i = 0; i < num_shader_outputs; i++) {
510 /* state->rt entries > 0 only written if independent blending */
511 const int j = state->independent_blend_enable ? i : 0;
512
513 unsigned eqRGB = state->rt[j].rgb_func;
514 unsigned srcRGB = state->rt[j].rgb_src_factor;
515 unsigned dstRGB = state->rt[j].rgb_dst_factor;
516 unsigned eqA = state->rt[j].alpha_func;
517 unsigned srcA = state->rt[j].alpha_src_factor;
518 unsigned dstA = state->rt[j].alpha_dst_factor;
519
520 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
521 unsigned blend_cntl = 0;
522
523 sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
524 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
525
526 /* Only set dual source blending for MRT0 to avoid a hang. */
527 if (i >= 1 && blend->dual_src_blend) {
528 if (i == 1) {
529 if (sctx->gfx_level >= GFX11)
530 blend_cntl = last_blend_cntl;
531 else
532 blend_cntl = S_028780_ENABLE(1);
533 }
534
535 ac_pm4_set_reg(&pm4->base, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
536 continue;
537 }
538
539 /* Only addition and subtraction equations are supported with
540 * dual source blending.
541 */
542 if (blend->dual_src_blend && (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
543 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
544 assert(!"Unsupported equation for dual source blending");
545 ac_pm4_set_reg(&pm4->base, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
546 continue;
547 }
548
549 /* cb_render_state will disable unused ones */
550 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
551 if (state->rt[j].colormask)
552 blend->cb_target_enabled_4bit |= 0xf << (4 * i);
553
554 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
555 ac_pm4_set_reg(&pm4->base, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
556 continue;
557 }
558
559 si_blend_check_commutativity(sctx->screen, blend, eqRGB, srcRGB, dstRGB, 0x7 << (4 * i));
560 si_blend_check_commutativity(sctx->screen, blend, eqA, srcA, dstA, 0x8 << (4 * i));
561
562 /* Blending optimizations for RB+.
563 * These transformations don't change the behavior.
564 *
565 * First, get rid of DST in the blend factors:
566 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
567 */
568 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB, PIPE_BLENDFACTOR_DST_COLOR,
569 PIPE_BLENDFACTOR_SRC_COLOR);
570 si_blend_remove_dst(&eqA, &srcA, &dstA, PIPE_BLENDFACTOR_DST_COLOR,
571 PIPE_BLENDFACTOR_SRC_COLOR);
572 si_blend_remove_dst(&eqA, &srcA, &dstA, PIPE_BLENDFACTOR_DST_ALPHA,
573 PIPE_BLENDFACTOR_SRC_ALPHA);
574
575 /* Look up the ideal settings from tables. */
576 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
577 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
578 srcA_opt = si_translate_blend_opt_factor(srcA, true);
579 dstA_opt = si_translate_blend_opt_factor(dstA, true);
580
581 /* Handle interdependencies. */
582 if (util_blend_factor_uses_dest(srcRGB, false))
583 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
584 if (util_blend_factor_uses_dest(srcA, false))
585 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
586
587 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
588 (dstRGB == PIPE_BLENDFACTOR_ZERO || dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
589 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
590 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
591
592 /* Set the final value. */
593 sx_mrt_blend_opt[i] = S_028760_COLOR_SRC_OPT(srcRGB_opt) |
594 S_028760_COLOR_DST_OPT(dstRGB_opt) |
595 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
596 S_028760_ALPHA_SRC_OPT(srcA_opt) | S_028760_ALPHA_DST_OPT(dstA_opt) |
597 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
598
599 /* Alpha-to-coverage with blending enabled, depth writes enabled, and having no MRTZ export
600 * should disable SX blend optimizations.
601 *
602 * TODO: Add a piglit test for this. It should fail on gfx11 without this.
603 */
604 if (sctx->gfx_level >= GFX11 && state->alpha_to_coverage && i == 0) {
605 sx_mrt_blend_opt[0] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
606 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
607 }
608
609 /* Set blend state. */
610 blend_cntl |= S_028780_ENABLE(1);
611 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
612 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(sctx->gfx_level, srcRGB));
613 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(sctx->gfx_level, dstRGB));
614
615 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
616 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
617 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
618 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(sctx->gfx_level, srcA));
619 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(sctx->gfx_level, dstA));
620 }
621 ac_pm4_set_reg(&pm4->base, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
622 last_blend_cntl = blend_cntl;
623
624 blend->blend_enable_4bit |= 0xfu << (i * 4);
625
626 if (sctx->gfx_level >= GFX8 && sctx->gfx_level <= GFX10)
627 blend->dcc_msaa_corruption_4bit |= 0xfu << (i * 4);
628
629 /* This is only important for formats without alpha. */
630 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA || dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
631 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
632 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
633 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
634 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
635 }
636
637 if (sctx->gfx_level >= GFX8 && sctx->gfx_level <= GFX10 && logicop_enable)
638 blend->dcc_msaa_corruption_4bit |= blend->cb_target_enabled_4bit;
639
640 if (blend->cb_target_mask) {
641 color_control |= S_028808_MODE(mode);
642 } else {
643 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
644 }
645
646 if (sctx->screen->info.rbplus_allowed) {
647 /* Disable RB+ blend optimizations for dual source blending.
648 * Vulkan does this.
649 */
650 if (blend->dual_src_blend) {
651 for (int i = 0; i < num_shader_outputs; i++) {
652 sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
653 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
654 }
655 }
656
657 for (int i = 0; i < num_shader_outputs; i++)
658 ac_pm4_set_reg(&pm4->base, R_028760_SX_MRT0_BLEND_OPT + i * 4, sx_mrt_blend_opt[i]);
659
660 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
661 if (blend->dual_src_blend || logicop_enable || mode == V_028808_CB_RESOLVE ||
662 /* Disabling RB+ improves blending performance in synthetic tests on GFX11. */
663 (sctx->gfx_level == GFX11 && blend->blend_enable_4bit))
664 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
665 }
666
667 if (sctx->gfx_level >= GFX12)
668 ac_pm4_set_reg(&pm4->base, R_028858_CB_COLOR_CONTROL, color_control);
669 else
670 ac_pm4_set_reg(&pm4->base, R_028808_CB_COLOR_CONTROL, color_control);
671
672 ac_pm4_finalize(&pm4->base);
673 return blend;
674 }
675
si_create_blend_state(struct pipe_context * ctx,const struct pipe_blend_state * state)676 static void *si_create_blend_state(struct pipe_context *ctx, const struct pipe_blend_state *state)
677 {
678 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
679 }
680
si_check_blend_dst_sampler_noop(struct si_context * sctx)681 static bool si_check_blend_dst_sampler_noop(struct si_context *sctx)
682 {
683 if (sctx->framebuffer.state.nr_cbufs == 1) {
684 struct si_shader_selector *sel = sctx->shader.ps.cso;
685
686 if (unlikely(sel->info.writes_1_if_tex_is_1 == 0xff)) {
687 /* Wait for the shader to be ready. */
688 util_queue_fence_wait(&sel->ready);
689 assert(sel->nir_binary);
690
691 struct nir_shader *nir = si_deserialize_shader(sel);
692
693 /* Determine if this fragment shader always writes vec4(1) if a specific texture
694 * is all 1s.
695 */
696 float in[4] = { 1.0, 1.0, 1.0, 1.0 };
697 float out[4];
698 int texunit;
699 if (si_nir_is_output_const_if_tex_is_const(nir, in, out, &texunit) &&
700 !memcmp(in, out, 4 * sizeof(float))) {
701 sel->info.writes_1_if_tex_is_1 = 1 + texunit;
702 } else {
703 sel->info.writes_1_if_tex_is_1 = 0;
704 }
705
706 ralloc_free(nir);
707 }
708
709 if (sel->info.writes_1_if_tex_is_1 &&
710 sel->info.writes_1_if_tex_is_1 != 0xff) {
711 /* Now check if the texture is cleared to 1 */
712 int unit = sctx->shader.ps.cso->info.writes_1_if_tex_is_1 - 1;
713 struct si_samplers *samp = &sctx->samplers[PIPE_SHADER_FRAGMENT];
714 if ((1u << unit) & samp->enabled_mask) {
715 struct si_texture* tex = (struct si_texture*) samp->views[unit]->texture;
716 if (tex->is_depth &&
717 tex->depth_cleared_level_mask & BITFIELD_BIT(samp->views[unit]->u.tex.first_level) &&
718 tex->depth_clear_value[0] == 1) {
719 return false;
720 }
721 /* TODO: handle color textures */
722 }
723 }
724 }
725
726 return true;
727 }
728
si_draw_blend_dst_sampler_noop(struct pipe_context * ctx,const struct pipe_draw_info * info,unsigned drawid_offset,const struct pipe_draw_indirect_info * indirect,const struct pipe_draw_start_count_bias * draws,unsigned num_draws)729 static void si_draw_blend_dst_sampler_noop(struct pipe_context *ctx,
730 const struct pipe_draw_info *info,
731 unsigned drawid_offset,
732 const struct pipe_draw_indirect_info *indirect,
733 const struct pipe_draw_start_count_bias *draws,
734 unsigned num_draws) {
735 struct si_context *sctx = (struct si_context *)ctx;
736
737 if (!si_check_blend_dst_sampler_noop(sctx))
738 return;
739
740 sctx->real_draw_vbo(ctx, info, drawid_offset, indirect, draws, num_draws);
741 }
742
si_draw_vstate_blend_dst_sampler_noop(struct pipe_context * ctx,struct pipe_vertex_state * state,uint32_t partial_velem_mask,struct pipe_draw_vertex_state_info info,const struct pipe_draw_start_count_bias * draws,unsigned num_draws)743 static void si_draw_vstate_blend_dst_sampler_noop(struct pipe_context *ctx,
744 struct pipe_vertex_state *state,
745 uint32_t partial_velem_mask,
746 struct pipe_draw_vertex_state_info info,
747 const struct pipe_draw_start_count_bias *draws,
748 unsigned num_draws) {
749 struct si_context *sctx = (struct si_context *)ctx;
750
751 if (!si_check_blend_dst_sampler_noop(sctx))
752 return;
753
754 sctx->real_draw_vertex_state(ctx, state, partial_velem_mask, info, draws, num_draws);
755 }
756
si_bind_blend_state(struct pipe_context * ctx,void * state)757 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
758 {
759 struct si_context *sctx = (struct si_context *)ctx;
760 struct si_state_blend *old_blend = sctx->queued.named.blend;
761 struct si_state_blend *blend = (struct si_state_blend *)state;
762
763 if (!blend)
764 blend = (struct si_state_blend *)sctx->noop_blend;
765
766 si_pm4_bind_state(sctx, blend, blend);
767
768 if (old_blend->cb_target_mask != blend->cb_target_mask ||
769 old_blend->dual_src_blend != blend->dual_src_blend ||
770 (old_blend->dcc_msaa_corruption_4bit != blend->dcc_msaa_corruption_4bit &&
771 sctx->framebuffer.has_dcc_msaa))
772 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
773
774 if ((sctx->screen->info.has_export_conflict_bug &&
775 old_blend->blend_enable_4bit != blend->blend_enable_4bit) ||
776 (sctx->occlusion_query_mode == SI_OCCLUSION_QUERY_MODE_PRECISE_BOOLEAN &&
777 !!old_blend->cb_target_mask != !!blend->cb_target_enabled_4bit))
778 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
779
780 if (old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit ||
781 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
782 old_blend->alpha_to_one != blend->alpha_to_one ||
783 old_blend->dual_src_blend != blend->dual_src_blend ||
784 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
785 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
786 si_ps_key_update_framebuffer_blend_rasterizer(sctx);
787
788 if (old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit ||
789 old_blend->alpha_to_coverage != blend->alpha_to_coverage)
790 si_update_ps_inputs_read_or_disabled(sctx);
791
792 if (sctx->screen->dpbb_allowed &&
793 (old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
794 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
795 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit))
796 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
797
798 if (sctx->screen->info.has_out_of_order_rast &&
799 ((old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
800 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit ||
801 old_blend->commutative_4bit != blend->commutative_4bit ||
802 old_blend->logicop_enable != blend->logicop_enable)))
803 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
804
805 /* RB+ depth-only rendering. See the comment where we set rbplus_depth_only_opt for more
806 * information.
807 */
808 if (sctx->screen->info.rbplus_allowed &&
809 !!old_blend->cb_target_mask != !!blend->cb_target_mask) {
810 sctx->framebuffer.dirty_cbufs |= BITFIELD_BIT(0);
811 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
812 }
813
814 if (likely(!radeon_uses_secure_bos(sctx->ws))) {
815 if (unlikely(blend->allows_noop_optimization)) {
816 si_install_draw_wrapper(sctx, si_draw_blend_dst_sampler_noop,
817 si_draw_vstate_blend_dst_sampler_noop);
818 } else {
819 si_install_draw_wrapper(sctx, NULL, NULL);
820 }
821 }
822 }
823
si_delete_blend_state(struct pipe_context * ctx,void * state)824 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
825 {
826 struct si_context *sctx = (struct si_context *)ctx;
827
828 if (sctx->queued.named.blend == state)
829 si_bind_blend_state(ctx, sctx->noop_blend);
830
831 si_pm4_free_state(sctx, (struct si_pm4_state*)state, SI_STATE_IDX(blend));
832 }
833
si_set_blend_color(struct pipe_context * ctx,const struct pipe_blend_color * state)834 static void si_set_blend_color(struct pipe_context *ctx, const struct pipe_blend_color *state)
835 {
836 struct si_context *sctx = (struct si_context *)ctx;
837 static const struct pipe_blend_color zeros;
838
839 sctx->blend_color = *state;
840 sctx->blend_color_any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
841 si_mark_atom_dirty(sctx, &sctx->atoms.s.blend_color);
842 }
843
si_emit_blend_color(struct si_context * sctx,unsigned index)844 static void si_emit_blend_color(struct si_context *sctx, unsigned index)
845 {
846 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
847
848 radeon_begin(cs);
849 radeon_set_context_reg_seq(R_028414_CB_BLEND_RED, 4);
850 radeon_emit_array((uint32_t *)sctx->blend_color.color, 4);
851 radeon_end();
852 }
853
854 /*
855 * Clipping
856 */
857
si_set_clip_state(struct pipe_context * ctx,const struct pipe_clip_state * state)858 static void si_set_clip_state(struct pipe_context *ctx, const struct pipe_clip_state *state)
859 {
860 struct si_context *sctx = (struct si_context *)ctx;
861 struct pipe_constant_buffer cb;
862 static const struct pipe_clip_state zeros;
863
864 if (memcmp(&sctx->clip_state, state, sizeof(*state)) == 0)
865 return;
866
867 sctx->clip_state = *state;
868 sctx->clip_state_any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
869 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_state);
870
871 cb.buffer = NULL;
872 cb.user_buffer = state->ucp;
873 cb.buffer_offset = 0;
874 cb.buffer_size = 4 * 4 * 8;
875 si_set_internal_const_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
876 }
877
si_emit_clip_state(struct si_context * sctx,unsigned index)878 static void si_emit_clip_state(struct si_context *sctx, unsigned index)
879 {
880 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
881
882 radeon_begin(cs);
883 if (sctx->gfx_level >= GFX12)
884 radeon_set_context_reg_seq(R_0282D0_PA_CL_UCP_0_X, 6 * 4);
885 else
886 radeon_set_context_reg_seq(R_0285BC_PA_CL_UCP_0_X, 6 * 4);
887 radeon_emit_array((uint32_t *)sctx->clip_state.ucp, 6 * 4);
888 radeon_end();
889 }
890
si_emit_clip_regs(struct si_context * sctx,unsigned index)891 static void si_emit_clip_regs(struct si_context *sctx, unsigned index)
892 {
893 struct si_shader *vs = si_get_vs(sctx)->current;
894 struct si_shader_selector *vs_sel = vs->selector;
895 struct si_shader_info *info = &vs_sel->info;
896 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
897 bool window_space = vs_sel->stage == MESA_SHADER_VERTEX ?
898 info->base.vs.window_space_position : 0;
899 unsigned clipdist_mask = vs_sel->info.clipdist_mask;
900 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SI_USER_CLIP_PLANE_MASK;
901 unsigned culldist_mask = vs_sel->info.culldist_mask;
902
903 /* Clip distances on points have no effect, so need to be implemented
904 * as cull distances. This applies for the clipvertex case as well.
905 *
906 * Setting this for primitives other than points should have no adverse
907 * effects.
908 */
909 clipdist_mask &= rs->clip_plane_enable;
910 culldist_mask |= clipdist_mask;
911
912 unsigned pa_cl_cntl = S_02881C_BYPASS_VTX_RATE_COMBINER(sctx->gfx_level >= GFX10_3 &&
913 !sctx->screen->options.vrs2x2) |
914 S_02881C_BYPASS_PRIM_RATE_COMBINER(sctx->gfx_level >= GFX10_3) |
915 clipdist_mask | (culldist_mask << 8);
916
917 unsigned pa_cl_clip_cntl = rs->pa_cl_clip_cntl | ucp_mask |
918 S_028810_CLIP_DISABLE(window_space);
919 unsigned pa_cl_vs_out_cntl = pa_cl_cntl | vs->pa_cl_vs_out_cntl;
920
921 if (sctx->gfx_level >= GFX12) {
922 radeon_begin(&sctx->gfx_cs);
923 gfx12_begin_context_regs();
924 gfx12_opt_set_context_reg(R_028810_PA_CL_CLIP_CNTL, SI_TRACKED_PA_CL_CLIP_CNTL,
925 pa_cl_clip_cntl);
926 gfx12_opt_set_context_reg(R_028818_PA_CL_VS_OUT_CNTL, SI_TRACKED_PA_CL_VS_OUT_CNTL,
927 pa_cl_vs_out_cntl);
928 gfx12_end_context_regs();
929 radeon_end(); /* don't track context rolls on GFX12 */
930 } else if (sctx->screen->info.has_set_context_pairs_packed) {
931 radeon_begin(&sctx->gfx_cs);
932 gfx11_begin_packed_context_regs();
933 gfx11_opt_set_context_reg(R_028810_PA_CL_CLIP_CNTL, SI_TRACKED_PA_CL_CLIP_CNTL,
934 pa_cl_clip_cntl);
935 gfx11_opt_set_context_reg(R_02881C_PA_CL_VS_OUT_CNTL, SI_TRACKED_PA_CL_VS_OUT_CNTL,
936 pa_cl_vs_out_cntl);
937 gfx11_end_packed_context_regs();
938 radeon_end(); /* don't track context rolls on GFX11 */
939 } else {
940 radeon_begin(&sctx->gfx_cs);
941 radeon_opt_set_context_reg(R_028810_PA_CL_CLIP_CNTL, SI_TRACKED_PA_CL_CLIP_CNTL,
942 pa_cl_clip_cntl);
943 radeon_opt_set_context_reg(R_02881C_PA_CL_VS_OUT_CNTL, SI_TRACKED_PA_CL_VS_OUT_CNTL,
944 pa_cl_vs_out_cntl);
945 radeon_end_update_context_roll();
946 }
947 }
948
949 /*
950 * Rasterizer
951 */
952
si_translate_fill(uint32_t func)953 static uint32_t si_translate_fill(uint32_t func)
954 {
955 switch (func) {
956 case PIPE_POLYGON_MODE_FILL:
957 return V_028814_X_DRAW_TRIANGLES;
958 case PIPE_POLYGON_MODE_LINE:
959 return V_028814_X_DRAW_LINES;
960 case PIPE_POLYGON_MODE_POINT:
961 return V_028814_X_DRAW_POINTS;
962 default:
963 assert(0);
964 return V_028814_X_DRAW_POINTS;
965 }
966 }
967
si_create_rs_state(struct pipe_context * ctx,const struct pipe_rasterizer_state * state)968 static void *si_create_rs_state(struct pipe_context *ctx, const struct pipe_rasterizer_state *state)
969 {
970 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
971 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
972
973 if (!rs) {
974 return NULL;
975 }
976
977 rs->scissor_enable = state->scissor;
978 rs->clip_halfz = state->clip_halfz;
979 rs->two_side = state->light_twoside;
980 rs->multisample_enable = state->multisample;
981 rs->force_persample_interp = state->force_persample_interp;
982 rs->clip_plane_enable = state->clip_plane_enable;
983 rs->half_pixel_center = state->half_pixel_center;
984 rs->line_stipple_enable = state->line_stipple_enable;
985 rs->poly_stipple_enable = state->poly_stipple_enable;
986 rs->line_smooth = state->line_smooth;
987 rs->line_width = state->line_width;
988 rs->poly_smooth = state->poly_smooth;
989 rs->point_smooth = state->point_smooth;
990 rs->uses_poly_offset = state->offset_point || state->offset_line || state->offset_tri;
991 rs->clamp_fragment_color = state->clamp_fragment_color;
992 rs->clamp_vertex_color = state->clamp_vertex_color;
993 rs->flatshade = state->flatshade;
994 rs->flatshade_first = state->flatshade_first;
995 rs->sprite_coord_enable = state->sprite_coord_enable;
996 rs->rasterizer_discard = state->rasterizer_discard;
997 rs->bottom_edge_rule = state->bottom_edge_rule;
998 rs->polygon_mode_is_lines =
999 (state->fill_front == PIPE_POLYGON_MODE_LINE && !(state->cull_face & PIPE_FACE_FRONT)) ||
1000 (state->fill_back == PIPE_POLYGON_MODE_LINE && !(state->cull_face & PIPE_FACE_BACK));
1001 rs->polygon_mode_is_points =
1002 (state->fill_front == PIPE_POLYGON_MODE_POINT && !(state->cull_face & PIPE_FACE_FRONT)) ||
1003 (state->fill_back == PIPE_POLYGON_MODE_POINT && !(state->cull_face & PIPE_FACE_BACK));
1004 rs->pa_sc_line_stipple = state->line_stipple_enable ?
1005 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
1006 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
1007 /* TODO: implement line stippling with perpendicular end caps. */
1008 /* Line width > 2 is an internal recommendation. */
1009 rs->perpendicular_end_caps = state->multisample &&
1010 state->line_width > 2 && !state->line_stipple_enable;
1011
1012 rs->pa_cl_clip_cntl = S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
1013 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip_near) |
1014 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_far) |
1015 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
1016 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
1017
1018 rs->ngg_cull_flags_tris = SI_NGG_CULL_TRIANGLES |
1019 SI_NGG_CULL_CLIP_PLANE_ENABLE(state->clip_plane_enable);
1020 rs->ngg_cull_flags_tris_y_inverted = rs->ngg_cull_flags_tris;
1021
1022 rs->ngg_cull_flags_lines = SI_NGG_CULL_LINES |
1023 (!rs->perpendicular_end_caps ? SI_NGG_CULL_SMALL_LINES_DIAMOND_EXIT : 0) |
1024 SI_NGG_CULL_CLIP_PLANE_ENABLE(state->clip_plane_enable);
1025
1026 if (rs->rasterizer_discard) {
1027 rs->ngg_cull_flags_tris |= SI_NGG_CULL_FRONT_FACE |
1028 SI_NGG_CULL_BACK_FACE;
1029 rs->ngg_cull_flags_tris_y_inverted = rs->ngg_cull_flags_tris;
1030 } else {
1031 bool cull_front, cull_back;
1032
1033 if (!state->front_ccw) {
1034 cull_front = !!(state->cull_face & PIPE_FACE_FRONT);
1035 cull_back = !!(state->cull_face & PIPE_FACE_BACK);
1036 } else {
1037 cull_back = !!(state->cull_face & PIPE_FACE_FRONT);
1038 cull_front = !!(state->cull_face & PIPE_FACE_BACK);
1039 }
1040
1041 if (cull_front) {
1042 rs->ngg_cull_flags_tris |= SI_NGG_CULL_FRONT_FACE;
1043 rs->ngg_cull_flags_tris_y_inverted |= SI_NGG_CULL_BACK_FACE;
1044 }
1045
1046 if (cull_back) {
1047 rs->ngg_cull_flags_tris |= SI_NGG_CULL_BACK_FACE;
1048 rs->ngg_cull_flags_tris_y_inverted |= SI_NGG_CULL_FRONT_FACE;
1049 }
1050 }
1051
1052 /* Force gl_FrontFacing to true or false if the other face is culled. */
1053 if (util_bitcount(state->cull_face) == 1) {
1054 if (state->cull_face & PIPE_FACE_FRONT)
1055 rs->force_front_face_input = -1;
1056 else
1057 rs->force_front_face_input = 1;
1058 }
1059
1060 rs->spi_interp_control_0 = S_0286D4_FLAT_SHADE_ENA(1) |
1061 S_0286D4_PNT_SPRITE_ENA(state->point_quad_rasterization) |
1062 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
1063 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
1064 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
1065 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
1066 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode !=
1067 PIPE_SPRITE_COORD_UPPER_LEFT);
1068
1069 /* point size 12.4 fixed point */
1070 float psize_min, psize_max;
1071 unsigned tmp = (unsigned)(state->point_size * 8.0);
1072 rs->pa_su_point_size = S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp);
1073
1074 if (state->point_size_per_vertex) {
1075 psize_min = util_get_min_point_size(state);
1076 psize_max = SI_MAX_POINT_SIZE;
1077 } else {
1078 /* Force the point size to be as if the vertex output was disabled. */
1079 psize_min = state->point_size;
1080 psize_max = state->point_size;
1081 }
1082 rs->max_point_size = psize_max;
1083
1084 /* Divide by two, because 0.5 = 1 pixel. */
1085 rs->pa_su_point_minmax = S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min / 2)) |
1086 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max / 2));
1087 rs->pa_su_line_cntl = S_028A08_WIDTH(si_pack_float_12p4(state->line_width / 2));
1088
1089 rs->pa_sc_mode_cntl_0 = S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
1090 S_028A48_MSAA_ENABLE(state->multisample || state->poly_smooth ||
1091 state->line_smooth) |
1092 S_028A48_VPORT_SCISSOR_ENABLE(1) |
1093 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.gfx_level >= GFX9);
1094
1095 bool polygon_mode_enabled =
1096 (state->fill_front != PIPE_POLYGON_MODE_FILL && !(state->cull_face & PIPE_FACE_FRONT)) ||
1097 (state->fill_back != PIPE_POLYGON_MODE_FILL && !(state->cull_face & PIPE_FACE_BACK));
1098
1099 rs->pa_su_sc_mode_cntl = S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
1100 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
1101 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
1102 S_028814_FACE(!state->front_ccw) |
1103 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
1104 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
1105 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
1106 S_028814_POLY_MODE(polygon_mode_enabled) |
1107 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
1108 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)) |
1109 /* this must be set if POLY_MODE or PERPENDICULAR_ENDCAP_ENA is set */
1110 S_028814_KEEP_TOGETHER_ENABLE(sscreen->info.gfx_level >= GFX10 &&
1111 sscreen->info.gfx_level < GFX12 ?
1112 polygon_mode_enabled ||
1113 rs->perpendicular_end_caps : 0);
1114 if (sscreen->info.gfx_level >= GFX10) {
1115 rs->pa_cl_ngg_cntl = S_028838_INDEX_BUF_EDGE_FLAG_ENA(rs->polygon_mode_is_points ||
1116 rs->polygon_mode_is_lines) |
1117 S_028838_VERTEX_REUSE_DEPTH(sscreen->info.gfx_level >= GFX10_3 ? 30 : 0);
1118 }
1119
1120 if (state->bottom_edge_rule) {
1121 /* OpenGL windows should set this. */
1122 rs->pa_sc_edgerule = S_028230_ER_TRI(0xA) |
1123 S_028230_ER_POINT(0x5) |
1124 S_028230_ER_RECT(0x9) |
1125 S_028230_ER_LINE_LR(0x2A) |
1126 S_028230_ER_LINE_RL(0x2A) |
1127 S_028230_ER_LINE_TB(0xA) |
1128 S_028230_ER_LINE_BT(0xA);
1129 } else {
1130 /* OpenGL FBOs and Direct3D should set this. */
1131 rs->pa_sc_edgerule = S_028230_ER_TRI(0xA) |
1132 S_028230_ER_POINT(0x6) |
1133 S_028230_ER_RECT(0xA) |
1134 S_028230_ER_LINE_LR(0x19) |
1135 S_028230_ER_LINE_RL(0x25) |
1136 S_028230_ER_LINE_TB(0xA) |
1137 S_028230_ER_LINE_BT(0xA);
1138 }
1139
1140 if (rs->uses_poly_offset) {
1141 /* Calculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
1142 rs->pa_su_poly_offset_clamp = fui(state->offset_clamp);
1143 rs->pa_su_poly_offset_frontback_scale = fui(state->offset_scale * 16);
1144
1145 if (!state->offset_units_unscaled) {
1146 /* 16-bit zbuffer */
1147 rs->pa_su_poly_offset_db_fmt_cntl[0] = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1148 rs->pa_su_poly_offset_frontback_offset[0] = fui(state->offset_units * 4);
1149
1150 /* 24-bit zbuffer */
1151 rs->pa_su_poly_offset_db_fmt_cntl[1] = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1152 rs->pa_su_poly_offset_frontback_offset[1] = fui(state->offset_units * 2);
1153
1154 /* 32-bit zbuffer */
1155 rs->pa_su_poly_offset_db_fmt_cntl[2] = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1156 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1157 rs->pa_su_poly_offset_frontback_offset[2] = fui(state->offset_units);
1158 } else {
1159 rs->pa_su_poly_offset_frontback_offset[0] = fui(state->offset_units);
1160 rs->pa_su_poly_offset_frontback_offset[1] = fui(state->offset_units);
1161 rs->pa_su_poly_offset_frontback_offset[2] = fui(state->offset_units);
1162 }
1163 }
1164
1165 return rs;
1166 }
1167
si_pm4_emit_rasterizer(struct si_context * sctx,unsigned index)1168 static void si_pm4_emit_rasterizer(struct si_context *sctx, unsigned index)
1169 {
1170 struct si_state_rasterizer *state = sctx->queued.named.rasterizer;
1171
1172 if (sctx->screen->info.gfx_level >= GFX12) {
1173 radeon_begin(&sctx->gfx_cs);
1174 gfx12_begin_context_regs();
1175 if (state->line_stipple_enable) {
1176 gfx12_opt_set_context_reg(R_028A0C_PA_SC_LINE_STIPPLE, SI_TRACKED_PA_SC_LINE_STIPPLE,
1177 state->pa_sc_line_stipple);
1178 }
1179
1180 gfx12_opt_set_context_reg(R_028644_SPI_INTERP_CONTROL_0, SI_TRACKED_SPI_INTERP_CONTROL_0,
1181 state->spi_interp_control_0);
1182 gfx12_opt_set_context_reg(R_028A00_PA_SU_POINT_SIZE, SI_TRACKED_PA_SU_POINT_SIZE,
1183 state->pa_su_point_size);
1184 gfx12_opt_set_context_reg(R_028A04_PA_SU_POINT_MINMAX, SI_TRACKED_PA_SU_POINT_MINMAX,
1185 state->pa_su_point_minmax);
1186 gfx12_opt_set_context_reg(R_028A08_PA_SU_LINE_CNTL, SI_TRACKED_PA_SU_LINE_CNTL,
1187 state->pa_su_line_cntl);
1188 gfx12_opt_set_context_reg(R_028A48_PA_SC_MODE_CNTL_0, SI_TRACKED_PA_SC_MODE_CNTL_0,
1189 state->pa_sc_mode_cntl_0);
1190 gfx12_opt_set_context_reg(R_02881C_PA_SU_SC_MODE_CNTL, SI_TRACKED_PA_SU_SC_MODE_CNTL,
1191 state->pa_su_sc_mode_cntl);
1192 gfx12_opt_set_context_reg(R_028838_PA_CL_NGG_CNTL, SI_TRACKED_PA_CL_NGG_CNTL,
1193 state->pa_cl_ngg_cntl);
1194 gfx12_opt_set_context_reg(R_028230_PA_SC_EDGERULE, SI_TRACKED_PA_SC_EDGERULE,
1195 state->pa_sc_edgerule);
1196
1197 if (state->uses_poly_offset && sctx->framebuffer.state.zsbuf) {
1198 unsigned db_format_index =
1199 ((struct si_surface *)sctx->framebuffer.state.zsbuf)->db_format_index;
1200
1201 gfx12_opt_set_context_reg(R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1202 SI_TRACKED_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1203 state->pa_su_poly_offset_db_fmt_cntl[db_format_index]);
1204 gfx12_opt_set_context_reg(R_028B7C_PA_SU_POLY_OFFSET_CLAMP,
1205 SI_TRACKED_PA_SU_POLY_OFFSET_CLAMP,
1206 state->pa_su_poly_offset_clamp);
1207 gfx12_opt_set_context_reg(R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
1208 SI_TRACKED_PA_SU_POLY_OFFSET_FRONT_SCALE,
1209 state->pa_su_poly_offset_frontback_scale);
1210 gfx12_opt_set_context_reg(R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
1211 SI_TRACKED_PA_SU_POLY_OFFSET_FRONT_OFFSET,
1212 state->pa_su_poly_offset_frontback_offset[db_format_index]);
1213 gfx12_opt_set_context_reg(R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
1214 SI_TRACKED_PA_SU_POLY_OFFSET_BACK_SCALE,
1215 state->pa_su_poly_offset_frontback_scale);
1216 gfx12_opt_set_context_reg(R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
1217 SI_TRACKED_PA_SU_POLY_OFFSET_BACK_OFFSET,
1218 state->pa_su_poly_offset_frontback_offset[db_format_index]);
1219 }
1220 gfx12_end_context_regs();
1221 radeon_end(); /* don't track context rolls on GFX12 */
1222 } else if (sctx->screen->info.has_set_context_pairs_packed) {
1223 radeon_begin(&sctx->gfx_cs);
1224 gfx11_begin_packed_context_regs();
1225 gfx11_opt_set_context_reg(R_0286D4_SPI_INTERP_CONTROL_0, SI_TRACKED_SPI_INTERP_CONTROL_0,
1226 state->spi_interp_control_0);
1227 gfx11_opt_set_context_reg(R_028A00_PA_SU_POINT_SIZE, SI_TRACKED_PA_SU_POINT_SIZE,
1228 state->pa_su_point_size);
1229 gfx11_opt_set_context_reg(R_028A04_PA_SU_POINT_MINMAX, SI_TRACKED_PA_SU_POINT_MINMAX,
1230 state->pa_su_point_minmax);
1231 gfx11_opt_set_context_reg(R_028A08_PA_SU_LINE_CNTL, SI_TRACKED_PA_SU_LINE_CNTL,
1232 state->pa_su_line_cntl);
1233 gfx11_opt_set_context_reg(R_028A48_PA_SC_MODE_CNTL_0, SI_TRACKED_PA_SC_MODE_CNTL_0,
1234 state->pa_sc_mode_cntl_0);
1235 gfx11_opt_set_context_reg(R_028814_PA_SU_SC_MODE_CNTL, SI_TRACKED_PA_SU_SC_MODE_CNTL,
1236 state->pa_su_sc_mode_cntl);
1237 gfx11_opt_set_context_reg(R_028838_PA_CL_NGG_CNTL, SI_TRACKED_PA_CL_NGG_CNTL,
1238 state->pa_cl_ngg_cntl);
1239 gfx11_opt_set_context_reg(R_028230_PA_SC_EDGERULE, SI_TRACKED_PA_SC_EDGERULE,
1240 state->pa_sc_edgerule);
1241
1242 if (state->uses_poly_offset && sctx->framebuffer.state.zsbuf) {
1243 unsigned db_format_index =
1244 ((struct si_surface *)sctx->framebuffer.state.zsbuf)->db_format_index;
1245
1246 gfx11_opt_set_context_reg(R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1247 SI_TRACKED_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1248 state->pa_su_poly_offset_db_fmt_cntl[db_format_index]);
1249 gfx11_opt_set_context_reg(R_028B7C_PA_SU_POLY_OFFSET_CLAMP,
1250 SI_TRACKED_PA_SU_POLY_OFFSET_CLAMP,
1251 state->pa_su_poly_offset_clamp);
1252 gfx11_opt_set_context_reg(R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
1253 SI_TRACKED_PA_SU_POLY_OFFSET_FRONT_SCALE,
1254 state->pa_su_poly_offset_frontback_scale);
1255 gfx11_opt_set_context_reg(R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
1256 SI_TRACKED_PA_SU_POLY_OFFSET_FRONT_OFFSET,
1257 state->pa_su_poly_offset_frontback_offset[db_format_index]);
1258 gfx11_opt_set_context_reg(R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
1259 SI_TRACKED_PA_SU_POLY_OFFSET_BACK_SCALE,
1260 state->pa_su_poly_offset_frontback_scale);
1261 gfx11_opt_set_context_reg(R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
1262 SI_TRACKED_PA_SU_POLY_OFFSET_BACK_OFFSET,
1263 state->pa_su_poly_offset_frontback_offset[db_format_index]);
1264 }
1265 gfx11_end_packed_context_regs();
1266 radeon_end(); /* don't track context rolls on GFX11 */
1267 } else {
1268 radeon_begin(&sctx->gfx_cs);
1269 radeon_opt_set_context_reg(R_0286D4_SPI_INTERP_CONTROL_0,
1270 SI_TRACKED_SPI_INTERP_CONTROL_0,
1271 state->spi_interp_control_0);
1272 radeon_opt_set_context_reg(R_028A00_PA_SU_POINT_SIZE, SI_TRACKED_PA_SU_POINT_SIZE,
1273 state->pa_su_point_size);
1274 radeon_opt_set_context_reg(R_028A04_PA_SU_POINT_MINMAX, SI_TRACKED_PA_SU_POINT_MINMAX,
1275 state->pa_su_point_minmax);
1276 radeon_opt_set_context_reg(R_028A08_PA_SU_LINE_CNTL, SI_TRACKED_PA_SU_LINE_CNTL,
1277 state->pa_su_line_cntl);
1278 radeon_opt_set_context_reg(R_028A48_PA_SC_MODE_CNTL_0, SI_TRACKED_PA_SC_MODE_CNTL_0,
1279 state->pa_sc_mode_cntl_0);
1280 radeon_opt_set_context_reg(R_028814_PA_SU_SC_MODE_CNTL,
1281 SI_TRACKED_PA_SU_SC_MODE_CNTL, state->pa_su_sc_mode_cntl);
1282 if (sctx->gfx_level >= GFX10) {
1283 radeon_opt_set_context_reg(R_028838_PA_CL_NGG_CNTL, SI_TRACKED_PA_CL_NGG_CNTL,
1284 state->pa_cl_ngg_cntl);
1285 }
1286 radeon_opt_set_context_reg(R_028230_PA_SC_EDGERULE, SI_TRACKED_PA_SC_EDGERULE,
1287 state->pa_sc_edgerule);
1288
1289 if (state->uses_poly_offset && sctx->framebuffer.state.zsbuf) {
1290 unsigned db_format_index =
1291 ((struct si_surface *)sctx->framebuffer.state.zsbuf)->db_format_index;
1292
1293 radeon_opt_set_context_reg6(R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1294 SI_TRACKED_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1295 state->pa_su_poly_offset_db_fmt_cntl[db_format_index],
1296 state->pa_su_poly_offset_clamp,
1297 state->pa_su_poly_offset_frontback_scale,
1298 state->pa_su_poly_offset_frontback_offset[db_format_index],
1299 state->pa_su_poly_offset_frontback_scale,
1300 state->pa_su_poly_offset_frontback_offset[db_format_index]);
1301 }
1302 radeon_end_update_context_roll();
1303 }
1304
1305 sctx->emitted.named.rasterizer = state;
1306 }
1307
si_bind_rs_state(struct pipe_context * ctx,void * state)1308 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
1309 {
1310 struct si_context *sctx = (struct si_context *)ctx;
1311 struct si_state_rasterizer *old_rs = (struct si_state_rasterizer *)sctx->queued.named.rasterizer;
1312 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1313
1314 if (!rs)
1315 rs = (struct si_state_rasterizer *)sctx->discard_rasterizer_state;
1316
1317 if (old_rs->multisample_enable != rs->multisample_enable) {
1318 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1319
1320 /* Update the small primitive filter workaround if necessary. */
1321 if (sctx->screen->info.has_small_prim_filter_sample_loc_bug && sctx->framebuffer.nr_samples > 1)
1322 si_mark_atom_dirty(sctx, &sctx->atoms.s.sample_locations);
1323
1324 /* NGG cull state uses multisample_enable. */
1325 if (sctx->screen->use_ngg_culling)
1326 si_mark_atom_dirty(sctx, &sctx->atoms.s.ngg_cull_state);
1327 }
1328
1329 if (old_rs->perpendicular_end_caps != rs->perpendicular_end_caps)
1330 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1331
1332 if (sctx->screen->use_ngg_culling &&
1333 (old_rs->half_pixel_center != rs->half_pixel_center ||
1334 old_rs->line_width != rs->line_width))
1335 si_mark_atom_dirty(sctx, &sctx->atoms.s.ngg_cull_state);
1336
1337 SET_FIELD(sctx->current_vs_state, VS_STATE_CLAMP_VERTEX_COLOR, rs->clamp_vertex_color);
1338
1339 si_pm4_bind_state(sctx, rasterizer, rs);
1340
1341 if (old_rs->scissor_enable != rs->scissor_enable)
1342 si_mark_atom_dirty(sctx, &sctx->atoms.s.scissors);
1343
1344 /* This never changes for OpenGL. */
1345 if (old_rs->half_pixel_center != rs->half_pixel_center)
1346 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1347
1348 if (util_prim_is_lines(sctx->current_rast_prim))
1349 si_set_clip_discard_distance(sctx, rs->line_width);
1350 else if (sctx->current_rast_prim == MESA_PRIM_POINTS)
1351 si_set_clip_discard_distance(sctx, rs->max_point_size);
1352
1353 if (old_rs->clip_halfz != rs->clip_halfz)
1354 si_mark_atom_dirty(sctx, &sctx->atoms.s.viewports);
1355
1356 if (old_rs->clip_plane_enable != rs->clip_plane_enable ||
1357 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
1358 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
1359
1360 if (old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
1361 old_rs->flatshade != rs->flatshade)
1362 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
1363
1364 if (sctx->screen->dpbb_allowed && (old_rs->bottom_edge_rule != rs->bottom_edge_rule))
1365 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
1366
1367 if (old_rs->multisample_enable != rs->multisample_enable)
1368 si_ps_key_update_framebuffer_blend_rasterizer(sctx);
1369
1370 if (old_rs->flatshade != rs->flatshade ||
1371 old_rs->clamp_fragment_color != rs->clamp_fragment_color)
1372 si_ps_key_update_rasterizer(sctx);
1373
1374 if (old_rs->flatshade != rs->flatshade ||
1375 old_rs->force_persample_interp != rs->force_persample_interp ||
1376 old_rs->multisample_enable != rs->multisample_enable)
1377 si_ps_key_update_framebuffer_rasterizer_sample_shading(sctx);
1378
1379 if (old_rs->rasterizer_discard != rs->rasterizer_discard ||
1380 old_rs->two_side != rs->two_side ||
1381 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
1382 old_rs->point_smooth != rs->point_smooth)
1383 si_update_ps_inputs_read_or_disabled(sctx);
1384
1385 if (old_rs->point_smooth != rs->point_smooth ||
1386 old_rs->line_smooth != rs->line_smooth ||
1387 old_rs->poly_smooth != rs->poly_smooth ||
1388 old_rs->polygon_mode_is_points != rs->polygon_mode_is_points ||
1389 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
1390 old_rs->two_side != rs->two_side ||
1391 old_rs->force_front_face_input != rs->force_front_face_input)
1392 si_vs_ps_key_update_rast_prim_smooth_stipple(sctx);
1393
1394 /* Used by si_get_vs_key_outputs in si_update_shaders: */
1395 if (old_rs->clip_plane_enable != rs->clip_plane_enable)
1396 sctx->do_update_shaders = true;
1397
1398 if (old_rs->line_smooth != rs->line_smooth ||
1399 old_rs->poly_smooth != rs->poly_smooth ||
1400 old_rs->point_smooth != rs->point_smooth ||
1401 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
1402 old_rs->flatshade != rs->flatshade)
1403 si_update_vrs_flat_shading(sctx);
1404
1405 if (old_rs->flatshade_first != rs->flatshade_first)
1406 si_update_ngg_sgpr_state_provoking_vtx(sctx, si_get_vs(sctx)->current, sctx->ngg);
1407 }
1408
si_delete_rs_state(struct pipe_context * ctx,void * state)1409 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1410 {
1411 struct si_context *sctx = (struct si_context *)ctx;
1412 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1413
1414 if (sctx->queued.named.rasterizer == state)
1415 si_bind_rs_state(ctx, sctx->discard_rasterizer_state);
1416
1417 si_pm4_free_state(sctx, &rs->pm4, SI_STATE_IDX(rasterizer));
1418 }
1419
1420 /*
1421 * inferred state between dsa and stencil ref
1422 */
si_emit_stencil_ref(struct si_context * sctx,unsigned index)1423 static void si_emit_stencil_ref(struct si_context *sctx, unsigned index)
1424 {
1425 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1426
1427 if (sctx->gfx_level >= GFX12) {
1428 radeon_begin(&sctx->gfx_cs);
1429 radeon_set_context_reg(R_028088_DB_STENCIL_REF,
1430 S_028088_TESTVAL(ref->ref_value[0]) |
1431 S_028088_TESTVAL_BF(ref->ref_value[1]));
1432 radeon_end();
1433 } else {
1434 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1435
1436 radeon_begin(&sctx->gfx_cs);
1437 radeon_set_context_reg_seq(R_028430_DB_STENCILREFMASK, 2);
1438 radeon_emit(S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1439 S_028430_STENCILMASK(dsa->valuemask[0]) |
1440 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1441 S_028430_STENCILOPVAL(1));
1442 radeon_emit(S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1443 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1444 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1445 S_028434_STENCILOPVAL_BF(1));
1446 radeon_end();
1447 }
1448 }
1449
si_set_stencil_ref(struct pipe_context * ctx,const struct pipe_stencil_ref state)1450 static void si_set_stencil_ref(struct pipe_context *ctx, const struct pipe_stencil_ref state)
1451 {
1452 struct si_context *sctx = (struct si_context *)ctx;
1453
1454 if (memcmp(&sctx->stencil_ref.state, &state, sizeof(state)) == 0)
1455 return;
1456
1457 sctx->stencil_ref.state = state;
1458 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1459 }
1460
1461 /*
1462 * DSA
1463 */
1464
si_translate_stencil_op(int s_op)1465 static uint32_t si_translate_stencil_op(int s_op)
1466 {
1467 switch (s_op) {
1468 case PIPE_STENCIL_OP_KEEP:
1469 return V_02842C_STENCIL_KEEP;
1470 case PIPE_STENCIL_OP_ZERO:
1471 return V_02842C_STENCIL_ZERO;
1472 case PIPE_STENCIL_OP_REPLACE:
1473 return V_02842C_STENCIL_REPLACE_TEST;
1474 case PIPE_STENCIL_OP_INCR:
1475 return V_02842C_STENCIL_ADD_CLAMP;
1476 case PIPE_STENCIL_OP_DECR:
1477 return V_02842C_STENCIL_SUB_CLAMP;
1478 case PIPE_STENCIL_OP_INCR_WRAP:
1479 return V_02842C_STENCIL_ADD_WRAP;
1480 case PIPE_STENCIL_OP_DECR_WRAP:
1481 return V_02842C_STENCIL_SUB_WRAP;
1482 case PIPE_STENCIL_OP_INVERT:
1483 return V_02842C_STENCIL_INVERT;
1484 default:
1485 PRINT_ERR("Unknown stencil op %d", s_op);
1486 assert(0);
1487 break;
1488 }
1489 return 0;
1490 }
1491
si_order_invariant_stencil_op(enum pipe_stencil_op op)1492 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op)
1493 {
1494 /* REPLACE is normally order invariant, except when the stencil
1495 * reference value is written by the fragment shader. Tracking this
1496 * interaction does not seem worth the effort, so be conservative. */
1497 return op != PIPE_STENCIL_OP_INCR && op != PIPE_STENCIL_OP_DECR && op != PIPE_STENCIL_OP_REPLACE;
1498 }
1499
1500 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1501 * invariant in the sense that the set of passing fragments as well as the
1502 * final stencil buffer result does not depend on the order of fragments. */
si_order_invariant_stencil_state(const struct pipe_stencil_state * state)1503 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state *state)
1504 {
1505 return !state->enabled || !state->writemask ||
1506 /* The following assumes that Z writes are disabled. */
1507 (state->func == PIPE_FUNC_ALWAYS && si_order_invariant_stencil_op(state->zpass_op) &&
1508 si_order_invariant_stencil_op(state->zfail_op)) ||
1509 (state->func == PIPE_FUNC_NEVER && si_order_invariant_stencil_op(state->fail_op));
1510 }
1511
si_create_dsa_state(struct pipe_context * ctx,const struct pipe_depth_stencil_alpha_state * state)1512 static void *si_create_dsa_state(struct pipe_context *ctx,
1513 const struct pipe_depth_stencil_alpha_state *state)
1514 {
1515 struct si_context *sctx = (struct si_context *)ctx;
1516 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1517 if (!dsa) {
1518 return NULL;
1519 }
1520
1521 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1522 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1523 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1524 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1525
1526 dsa->db_depth_control =
1527 S_028800_Z_ENABLE(state->depth_enabled) | S_028800_Z_WRITE_ENABLE(state->depth_writemask) |
1528 S_028800_ZFUNC(state->depth_func) | S_028800_DEPTH_BOUNDS_ENABLE(state->depth_bounds_test);
1529
1530 /* stencil */
1531 if (state->stencil[0].enabled) {
1532 dsa->db_depth_control |= S_028800_STENCIL_ENABLE(1);
1533 dsa->db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1534 dsa->db_stencil_control |=
1535 S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1536 dsa->db_stencil_control |=
1537 S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1538 dsa->db_stencil_control |=
1539 S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1540
1541 if (state->stencil[1].enabled) {
1542 dsa->db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1543 dsa->db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1544 dsa->db_stencil_control |=
1545 S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1546 dsa->db_stencil_control |=
1547 S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1548 dsa->db_stencil_control |=
1549 S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1550 }
1551 }
1552
1553 dsa->db_depth_bounds_min = fui(state->depth_bounds_min);
1554 dsa->db_depth_bounds_max = fui(state->depth_bounds_max);
1555
1556 /* alpha */
1557 if (state->alpha_enabled) {
1558 dsa->alpha_func = state->alpha_func;
1559 dsa->spi_shader_user_data_ps_alpha_ref = fui(state->alpha_ref_value);
1560 } else {
1561 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1562 }
1563
1564 dsa->depth_enabled = state->depth_enabled;
1565 dsa->depth_write_enabled = state->depth_enabled && state->depth_writemask;
1566 dsa->stencil_enabled = state->stencil[0].enabled;
1567 dsa->stencil_write_enabled =
1568 (util_writes_stencil(&state->stencil[0]) || util_writes_stencil(&state->stencil[1]));
1569 dsa->db_can_write = dsa->depth_write_enabled || dsa->stencil_write_enabled;
1570 dsa->depth_bounds_enabled = state->depth_bounds_test;
1571
1572 if (sctx->gfx_level >= GFX12) {
1573 dsa->db_stencil_read_mask = S_028090_TESTMASK(state->stencil[0].valuemask) |
1574 S_028090_TESTMASK_BF(state->stencil[1].valuemask);
1575 dsa->db_stencil_write_mask = S_028094_WRITEMASK(state->stencil[0].writemask) |
1576 S_028094_WRITEMASK_BF(state->stencil[1].writemask);
1577 }
1578
1579 bool zfunc_is_ordered =
1580 state->depth_func == PIPE_FUNC_NEVER || state->depth_func == PIPE_FUNC_LESS ||
1581 state->depth_func == PIPE_FUNC_LEQUAL || state->depth_func == PIPE_FUNC_GREATER ||
1582 state->depth_func == PIPE_FUNC_GEQUAL;
1583
1584 bool nozwrite_and_order_invariant_stencil =
1585 !dsa->db_can_write ||
1586 (!dsa->depth_write_enabled && si_order_invariant_stencil_state(&state->stencil[0]) &&
1587 si_order_invariant_stencil_state(&state->stencil[1]));
1588
1589 dsa->order_invariance[1].zs =
1590 nozwrite_and_order_invariant_stencil || (!dsa->stencil_write_enabled && zfunc_is_ordered);
1591 dsa->order_invariance[0].zs = !dsa->depth_write_enabled || zfunc_is_ordered;
1592
1593 dsa->order_invariance[1].pass_set =
1594 nozwrite_and_order_invariant_stencil ||
1595 (!dsa->stencil_write_enabled &&
1596 (state->depth_func == PIPE_FUNC_ALWAYS || state->depth_func == PIPE_FUNC_NEVER));
1597 dsa->order_invariance[0].pass_set =
1598 !dsa->depth_write_enabled ||
1599 (state->depth_func == PIPE_FUNC_ALWAYS || state->depth_func == PIPE_FUNC_NEVER);
1600
1601 return dsa;
1602 }
1603
si_pm4_emit_dsa(struct si_context * sctx,unsigned index)1604 static void si_pm4_emit_dsa(struct si_context *sctx, unsigned index)
1605 {
1606 struct si_state_dsa *state = sctx->queued.named.dsa;
1607 assert(state && state != sctx->emitted.named.dsa);
1608
1609 if (sctx->gfx_level >= GFX12) {
1610 radeon_begin(&sctx->gfx_cs);
1611 gfx12_begin_context_regs();
1612 gfx12_opt_set_context_reg(R_028070_DB_DEPTH_CONTROL, SI_TRACKED_DB_DEPTH_CONTROL,
1613 state->db_depth_control);
1614 if (state->stencil_enabled) {
1615 gfx12_opt_set_context_reg(R_028074_DB_STENCIL_CONTROL, SI_TRACKED_DB_STENCIL_CONTROL,
1616 state->db_stencil_control);
1617 gfx12_opt_set_context_reg(R_028090_DB_STENCIL_READ_MASK, SI_TRACKED_DB_STENCIL_READ_MASK,
1618 state->db_stencil_read_mask);
1619 gfx12_opt_set_context_reg(R_028094_DB_STENCIL_WRITE_MASK, SI_TRACKED_DB_STENCIL_WRITE_MASK,
1620 state->db_stencil_write_mask);
1621 }
1622 if (state->depth_bounds_enabled) {
1623 gfx12_opt_set_context_reg(R_028050_DB_DEPTH_BOUNDS_MIN, SI_TRACKED_DB_DEPTH_BOUNDS_MIN,
1624 state->db_depth_bounds_min);
1625 gfx12_opt_set_context_reg(R_028054_DB_DEPTH_BOUNDS_MAX, SI_TRACKED_DB_DEPTH_BOUNDS_MAX,
1626 state->db_depth_bounds_max);
1627 }
1628 gfx12_end_context_regs();
1629 radeon_end(); /* don't track context rolls on GFX12 */
1630
1631 gfx12_opt_push_gfx_sh_reg(R_00B030_SPI_SHADER_USER_DATA_PS_0 + SI_SGPR_ALPHA_REF * 4,
1632 SI_TRACKED_SPI_SHADER_USER_DATA_PS__ALPHA_REF,
1633 state->spi_shader_user_data_ps_alpha_ref);
1634 } else if (sctx->screen->info.has_set_context_pairs_packed) {
1635 radeon_begin(&sctx->gfx_cs);
1636 gfx11_begin_packed_context_regs();
1637 gfx11_opt_set_context_reg(R_028800_DB_DEPTH_CONTROL, SI_TRACKED_DB_DEPTH_CONTROL,
1638 state->db_depth_control);
1639 if (state->stencil_enabled) {
1640 gfx11_opt_set_context_reg(R_02842C_DB_STENCIL_CONTROL, SI_TRACKED_DB_STENCIL_CONTROL,
1641 state->db_stencil_control);
1642 }
1643 if (state->depth_bounds_enabled) {
1644 gfx11_opt_set_context_reg(R_028020_DB_DEPTH_BOUNDS_MIN, SI_TRACKED_DB_DEPTH_BOUNDS_MIN,
1645 state->db_depth_bounds_min);
1646 gfx11_opt_set_context_reg(R_028024_DB_DEPTH_BOUNDS_MAX, SI_TRACKED_DB_DEPTH_BOUNDS_MAX,
1647 state->db_depth_bounds_max);
1648 }
1649 gfx11_end_packed_context_regs();
1650
1651 if (state->alpha_func != PIPE_FUNC_ALWAYS) {
1652 if (sctx->screen->info.has_set_sh_pairs_packed) {
1653 gfx11_opt_push_gfx_sh_reg(R_00B030_SPI_SHADER_USER_DATA_PS_0 + SI_SGPR_ALPHA_REF * 4,
1654 SI_TRACKED_SPI_SHADER_USER_DATA_PS__ALPHA_REF,
1655 state->spi_shader_user_data_ps_alpha_ref);
1656 } else {
1657 radeon_opt_set_sh_reg(R_00B030_SPI_SHADER_USER_DATA_PS_0 + SI_SGPR_ALPHA_REF * 4,
1658 SI_TRACKED_SPI_SHADER_USER_DATA_PS__ALPHA_REF,
1659 state->spi_shader_user_data_ps_alpha_ref);
1660 }
1661 }
1662 radeon_end(); /* don't track context rolls on GFX11 */
1663 } else {
1664 radeon_begin(&sctx->gfx_cs);
1665 radeon_opt_set_context_reg(R_028800_DB_DEPTH_CONTROL, SI_TRACKED_DB_DEPTH_CONTROL,
1666 state->db_depth_control);
1667 if (state->stencil_enabled) {
1668 radeon_opt_set_context_reg(R_02842C_DB_STENCIL_CONTROL, SI_TRACKED_DB_STENCIL_CONTROL,
1669 state->db_stencil_control);
1670 }
1671 if (state->depth_bounds_enabled) {
1672 radeon_opt_set_context_reg2(R_028020_DB_DEPTH_BOUNDS_MIN,
1673 SI_TRACKED_DB_DEPTH_BOUNDS_MIN,
1674 state->db_depth_bounds_min,
1675 state->db_depth_bounds_max);
1676 }
1677 radeon_end_update_context_roll();
1678
1679 if (state->alpha_func != PIPE_FUNC_ALWAYS) {
1680 radeon_begin(&sctx->gfx_cs);
1681 radeon_opt_set_sh_reg(R_00B030_SPI_SHADER_USER_DATA_PS_0 + SI_SGPR_ALPHA_REF * 4,
1682 SI_TRACKED_SPI_SHADER_USER_DATA_PS__ALPHA_REF,
1683 state->spi_shader_user_data_ps_alpha_ref);
1684 radeon_end();
1685 }
1686 }
1687
1688 sctx->emitted.named.dsa = state;
1689 }
1690
si_bind_dsa_state(struct pipe_context * ctx,void * state)1691 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1692 {
1693 struct si_context *sctx = (struct si_context *)ctx;
1694 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1695 struct si_state_dsa *dsa = state;
1696
1697 if (!dsa)
1698 dsa = (struct si_state_dsa *)sctx->noop_dsa;
1699
1700 si_pm4_bind_state(sctx, dsa, dsa);
1701
1702 /* Gfx12 doesn't need to combine a DSA state with a stencil ref state. */
1703 if (sctx->gfx_level < GFX12 &&
1704 memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1705 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1706 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1707 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1708 }
1709
1710 if (old_dsa->alpha_func != dsa->alpha_func) {
1711 si_ps_key_update_dsa(sctx);
1712 si_update_ps_inputs_read_or_disabled(sctx);
1713 sctx->do_update_shaders = true;
1714 }
1715
1716 if (sctx->occlusion_query_mode == SI_OCCLUSION_QUERY_MODE_PRECISE_BOOLEAN &&
1717 (old_dsa->depth_enabled != dsa->depth_enabled ||
1718 old_dsa->depth_write_enabled != dsa->depth_write_enabled))
1719 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1720
1721 if (sctx->screen->dpbb_allowed && ((old_dsa->depth_enabled != dsa->depth_enabled ||
1722 old_dsa->stencil_enabled != dsa->stencil_enabled ||
1723 old_dsa->db_can_write != dsa->db_can_write)))
1724 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
1725
1726 if (sctx->screen->info.has_out_of_order_rast &&
1727 (memcmp(old_dsa->order_invariance, dsa->order_invariance,
1728 sizeof(old_dsa->order_invariance))))
1729 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1730 }
1731
si_delete_dsa_state(struct pipe_context * ctx,void * state)1732 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1733 {
1734 struct si_context *sctx = (struct si_context *)ctx;
1735
1736 if (sctx->queued.named.dsa == state)
1737 si_bind_dsa_state(ctx, sctx->noop_dsa);
1738
1739 si_pm4_free_state(sctx, (struct si_pm4_state*)state, SI_STATE_IDX(dsa));
1740 }
1741
si_create_db_flush_dsa(struct si_context * sctx)1742 static void *si_create_db_flush_dsa(struct si_context *sctx)
1743 {
1744 struct pipe_depth_stencil_alpha_state dsa = {};
1745
1746 return sctx->b.create_depth_stencil_alpha_state(&sctx->b, &dsa);
1747 }
1748
1749 /* DB RENDER STATE */
1750
si_set_active_query_state(struct pipe_context * ctx,bool enable)1751 static void si_set_active_query_state(struct pipe_context *ctx, bool enable)
1752 {
1753 struct si_context *sctx = (struct si_context *)ctx;
1754
1755 /* Pipeline stat & streamout queries. */
1756 if (enable) {
1757 /* Disable pipeline stats if there are no active queries. */
1758 if (sctx->num_hw_pipestat_streamout_queries) {
1759 sctx->barrier_flags &= ~SI_BARRIER_EVENT_PIPELINESTAT_STOP;
1760 sctx->barrier_flags |= SI_BARRIER_EVENT_PIPELINESTAT_START;
1761 si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
1762 }
1763 } else {
1764 if (sctx->num_hw_pipestat_streamout_queries) {
1765 sctx->barrier_flags &= ~SI_BARRIER_EVENT_PIPELINESTAT_START;
1766 sctx->barrier_flags |= SI_BARRIER_EVENT_PIPELINESTAT_STOP;
1767 si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
1768 }
1769 }
1770
1771 /* Occlusion queries. */
1772 if (sctx->occlusion_queries_disabled != !enable) {
1773 sctx->occlusion_queries_disabled = !enable;
1774 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1775 }
1776 }
1777
si_save_qbo_state(struct si_context * sctx,struct si_qbo_state * st)1778 void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1779 {
1780 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1781 }
1782
si_restore_qbo_state(struct si_context * sctx,struct si_qbo_state * st)1783 void si_restore_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1784 {
1785 sctx->b.set_constant_buffer(&sctx->b, PIPE_SHADER_COMPUTE, 0, true, &st->saved_const0);
1786 }
1787
si_emit_db_render_state(struct si_context * sctx,unsigned index)1788 static void si_emit_db_render_state(struct si_context *sctx, unsigned index)
1789 {
1790 unsigned db_shader_control = 0, db_render_control = 0, db_count_control = 0, vrs_override_cntl = 0;
1791
1792 /* DB_RENDER_CONTROL */
1793 /* Program OREO_MODE optimally for GFX11+. */
1794 if (sctx->gfx_level >= GFX11) {
1795 bool z_export = G_02880C_Z_EXPORT_ENABLE(sctx->ps_db_shader_control);
1796 db_render_control |= S_028000_OREO_MODE(z_export ? V_028000_OMODE_BLEND : V_028000_OMODE_O_THEN_B);
1797 }
1798
1799 if (sctx->gfx_level >= GFX12) {
1800 assert(!sctx->dbcb_depth_copy_enabled && !sctx->dbcb_stencil_copy_enabled);
1801 assert(!sctx->db_flush_depth_inplace && !sctx->db_flush_stencil_inplace);
1802 assert(!sctx->db_depth_clear && !sctx->db_stencil_clear);
1803 } else {
1804 if (sctx->dbcb_depth_copy_enabled || sctx->dbcb_stencil_copy_enabled) {
1805 db_render_control |= S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1806 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1807 S_028000_COPY_CENTROID(1) | S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample);
1808 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1809 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1810 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace);
1811 } else {
1812 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1813 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear);
1814 }
1815
1816 if (sctx->gfx_level >= GFX11) {
1817 unsigned max_allowed_tiles_in_wave;
1818
1819 if (sctx->screen->info.has_dedicated_vram) {
1820 if (sctx->framebuffer.nr_samples == 8)
1821 max_allowed_tiles_in_wave = 6;
1822 else if (sctx->framebuffer.nr_samples == 4)
1823 max_allowed_tiles_in_wave = 13;
1824 else
1825 max_allowed_tiles_in_wave = 0;
1826 } else {
1827 if (sctx->framebuffer.nr_samples == 8)
1828 max_allowed_tiles_in_wave = 7;
1829 else if (sctx->framebuffer.nr_samples == 4)
1830 max_allowed_tiles_in_wave = 15;
1831 else
1832 max_allowed_tiles_in_wave = 0;
1833 }
1834
1835 db_render_control |= S_028000_MAX_ALLOWED_TILES_IN_WAVE(max_allowed_tiles_in_wave);
1836 }
1837 }
1838
1839 /* DB_COUNT_CONTROL (occlusion queries) */
1840 if (sctx->occlusion_query_mode == SI_OCCLUSION_QUERY_MODE_DISABLE ||
1841 sctx->occlusion_queries_disabled) {
1842 /* Occlusion queries disabled. */
1843 if (sctx->gfx_level >= GFX7)
1844 db_count_control |= S_028004_ZPASS_ENABLE(0);
1845 else
1846 db_count_control |= S_028004_ZPASS_INCREMENT_DISABLE(1);
1847 } else {
1848 /* Occlusion queries enabled. */
1849 if (sctx->gfx_level < GFX12)
1850 db_count_control |= S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples);
1851
1852 if (sctx->gfx_level >= GFX7) {
1853 db_count_control |= S_028004_ZPASS_ENABLE(1) |
1854 S_028004_SLICE_EVEN_ENABLE(1) |
1855 S_028004_SLICE_ODD_ENABLE(1);
1856 }
1857
1858 if (sctx->occlusion_query_mode == SI_OCCLUSION_QUERY_MODE_PRECISE_INTEGER ||
1859 /* Boolean occlusion queries must set PERFECT_ZPASS_COUNTS for depth-only rendering
1860 * without depth writes or when depth testing is disabled. */
1861 (sctx->occlusion_query_mode == SI_OCCLUSION_QUERY_MODE_PRECISE_BOOLEAN &&
1862 (!sctx->queued.named.dsa->depth_enabled ||
1863 (!sctx->queued.named.blend->cb_target_mask &&
1864 !sctx->queued.named.dsa->depth_write_enabled))))
1865 db_count_control |= S_028004_PERFECT_ZPASS_COUNTS(1);
1866
1867 if (sctx->gfx_level >= GFX10 &&
1868 sctx->occlusion_query_mode != SI_OCCLUSION_QUERY_MODE_CONSERVATIVE_BOOLEAN)
1869 db_count_control |= S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(1);
1870 }
1871
1872 /* This should always be set on GFX11. */
1873 if (sctx->gfx_level >= GFX11)
1874 db_count_control |= S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(1);
1875
1876 db_shader_control |= sctx->ps_db_shader_control;
1877
1878 if (sctx->screen->info.has_export_conflict_bug &&
1879 sctx->queued.named.blend->blend_enable_4bit &&
1880 si_get_num_coverage_samples(sctx) == 1) {
1881 db_shader_control |= S_02880C_OVERRIDE_INTRINSIC_RATE_ENABLE(1) |
1882 S_02880C_OVERRIDE_INTRINSIC_RATE(2);
1883 }
1884
1885 if (sctx->gfx_level >= GFX10_3) {
1886 /* Variable rate shading. */
1887 unsigned mode, log_rate_x, log_rate_y;
1888
1889 if (sctx->allow_flat_shading) {
1890 mode = V_028064_SC_VRS_COMB_MODE_OVERRIDE;
1891 log_rate_x = log_rate_y = 1; /* 2x2 VRS (log2(2) == 1) */
1892 } else {
1893 /* If the shader is using discard, turn off coarse shading because discarding at 2x2 pixel
1894 * granularity degrades quality too much.
1895 *
1896 * The shader writes the VRS rate and we either pass it through or do MIN(shader, 1x1)
1897 * to disable coarse shading.
1898 */
1899 mode = sctx->screen->options.vrs2x2 && G_02880C_KILL_ENABLE(db_shader_control) ?
1900 V_028064_SC_VRS_COMB_MODE_MIN : V_028064_SC_VRS_COMB_MODE_PASSTHRU;
1901 log_rate_x = log_rate_y = 0; /* 1x1 VRS (log2(1) == 0) */
1902 }
1903
1904 if (sctx->gfx_level >= GFX11) {
1905 vrs_override_cntl = S_0283D0_VRS_OVERRIDE_RATE_COMBINER_MODE(mode) |
1906 S_0283D0_VRS_RATE(log_rate_x * 4 + log_rate_y);
1907 } else {
1908 vrs_override_cntl = S_028064_VRS_OVERRIDE_RATE_COMBINER_MODE(mode) |
1909 S_028064_VRS_OVERRIDE_RATE_X(log_rate_x) |
1910 S_028064_VRS_OVERRIDE_RATE_Y(log_rate_y);
1911 }
1912 }
1913
1914 unsigned db_render_override2 =
1915 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1916 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1917 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4) |
1918 S_028010_CENTROID_COMPUTATION_MODE(sctx->gfx_level >= GFX10_3 ? 1 : 0);
1919
1920 if (sctx->gfx_level >= GFX12) {
1921 radeon_begin(&sctx->gfx_cs);
1922 gfx12_begin_context_regs();
1923 gfx12_opt_set_context_reg(R_028000_DB_RENDER_CONTROL, SI_TRACKED_DB_RENDER_CONTROL,
1924 db_render_control);
1925 gfx12_opt_set_context_reg(R_028010_DB_RENDER_OVERRIDE2, SI_TRACKED_DB_RENDER_OVERRIDE2,
1926 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4) |
1927 S_028010_CENTROID_COMPUTATION_MODE(1));
1928 gfx12_opt_set_context_reg(R_028060_DB_COUNT_CONTROL, SI_TRACKED_DB_COUNT_CONTROL,
1929 db_count_control);
1930 gfx12_opt_set_context_reg(R_02806C_DB_SHADER_CONTROL, SI_TRACKED_DB_SHADER_CONTROL,
1931 db_shader_control);
1932 gfx12_opt_set_context_reg(R_0283D0_PA_SC_VRS_OVERRIDE_CNTL,
1933 SI_TRACKED_DB_PA_SC_VRS_OVERRIDE_CNTL, vrs_override_cntl);
1934 gfx12_end_context_regs();
1935 radeon_end(); /* don't track context rolls on GFX12 */
1936 } else if (sctx->screen->info.has_set_context_pairs_packed) {
1937 radeon_begin(&sctx->gfx_cs);
1938 gfx11_begin_packed_context_regs();
1939 gfx11_opt_set_context_reg(R_028000_DB_RENDER_CONTROL, SI_TRACKED_DB_RENDER_CONTROL,
1940 db_render_control);
1941 gfx11_opt_set_context_reg(R_028004_DB_COUNT_CONTROL, SI_TRACKED_DB_COUNT_CONTROL,
1942 db_count_control);
1943 gfx11_opt_set_context_reg(R_028010_DB_RENDER_OVERRIDE2, SI_TRACKED_DB_RENDER_OVERRIDE2,
1944 db_render_override2);
1945 gfx11_opt_set_context_reg(R_02880C_DB_SHADER_CONTROL, SI_TRACKED_DB_SHADER_CONTROL,
1946 db_shader_control);
1947 gfx11_opt_set_context_reg(R_0283D0_PA_SC_VRS_OVERRIDE_CNTL,
1948 SI_TRACKED_DB_PA_SC_VRS_OVERRIDE_CNTL, vrs_override_cntl);
1949 gfx11_end_packed_context_regs();
1950 radeon_end(); /* don't track context rolls on GFX11 */
1951 } else {
1952 radeon_begin(&sctx->gfx_cs);
1953 radeon_opt_set_context_reg2(R_028000_DB_RENDER_CONTROL, SI_TRACKED_DB_RENDER_CONTROL,
1954 db_render_control, db_count_control);
1955 radeon_opt_set_context_reg(R_028010_DB_RENDER_OVERRIDE2,
1956 SI_TRACKED_DB_RENDER_OVERRIDE2, db_render_override2);
1957 radeon_opt_set_context_reg(R_02880C_DB_SHADER_CONTROL, SI_TRACKED_DB_SHADER_CONTROL,
1958 db_shader_control);
1959
1960 if (sctx->gfx_level >= GFX11) {
1961 radeon_opt_set_context_reg(R_0283D0_PA_SC_VRS_OVERRIDE_CNTL,
1962 SI_TRACKED_DB_PA_SC_VRS_OVERRIDE_CNTL, vrs_override_cntl);
1963 } else if (sctx->gfx_level >= GFX10_3) {
1964 radeon_opt_set_context_reg(R_028064_DB_VRS_OVERRIDE_CNTL,
1965 SI_TRACKED_DB_PA_SC_VRS_OVERRIDE_CNTL, vrs_override_cntl);
1966 }
1967 radeon_end_update_context_roll();
1968 }
1969 }
1970
1971 /*
1972 * Texture translation
1973 */
1974
si_translate_texformat(struct pipe_screen * screen,enum pipe_format format,const struct util_format_description * desc,int first_non_void)1975 static uint32_t si_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
1976 const struct util_format_description *desc,
1977 int first_non_void)
1978 {
1979 struct si_screen *sscreen = (struct si_screen *)screen;
1980
1981 assert(sscreen->info.gfx_level <= GFX9);
1982
1983 return ac_translate_tex_dataformat(&sscreen->info, desc, first_non_void);
1984 }
1985
is_wrap_mode_legal(struct si_screen * screen,unsigned wrap)1986 static unsigned is_wrap_mode_legal(struct si_screen *screen, unsigned wrap)
1987 {
1988 if (!screen->info.has_3d_cube_border_color_mipmap) {
1989 switch (wrap) {
1990 case PIPE_TEX_WRAP_CLAMP:
1991 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1992 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1993 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1994 return false;
1995 }
1996 }
1997 return true;
1998 }
1999
si_tex_wrap(unsigned wrap)2000 static unsigned si_tex_wrap(unsigned wrap)
2001 {
2002 switch (wrap) {
2003 default:
2004 case PIPE_TEX_WRAP_REPEAT:
2005 return V_008F30_SQ_TEX_WRAP;
2006 case PIPE_TEX_WRAP_CLAMP:
2007 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
2008 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
2009 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
2010 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
2011 return V_008F30_SQ_TEX_CLAMP_BORDER;
2012 case PIPE_TEX_WRAP_MIRROR_REPEAT:
2013 return V_008F30_SQ_TEX_MIRROR;
2014 case PIPE_TEX_WRAP_MIRROR_CLAMP:
2015 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
2016 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
2017 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
2018 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
2019 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
2020 }
2021 }
2022
si_tex_mipfilter(unsigned filter)2023 static unsigned si_tex_mipfilter(unsigned filter)
2024 {
2025 switch (filter) {
2026 case PIPE_TEX_MIPFILTER_NEAREST:
2027 return V_008F38_SQ_TEX_Z_FILTER_POINT;
2028 case PIPE_TEX_MIPFILTER_LINEAR:
2029 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
2030 default:
2031 case PIPE_TEX_MIPFILTER_NONE:
2032 return V_008F38_SQ_TEX_Z_FILTER_NONE;
2033 }
2034 }
2035
si_tex_compare(unsigned mode,unsigned compare)2036 static unsigned si_tex_compare(unsigned mode, unsigned compare)
2037 {
2038 if (mode == PIPE_TEX_COMPARE_NONE)
2039 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
2040
2041 switch (compare) {
2042 default:
2043 case PIPE_FUNC_NEVER:
2044 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
2045 case PIPE_FUNC_LESS:
2046 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
2047 case PIPE_FUNC_EQUAL:
2048 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
2049 case PIPE_FUNC_LEQUAL:
2050 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
2051 case PIPE_FUNC_GREATER:
2052 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
2053 case PIPE_FUNC_NOTEQUAL:
2054 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
2055 case PIPE_FUNC_GEQUAL:
2056 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
2057 case PIPE_FUNC_ALWAYS:
2058 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
2059 }
2060 }
2061
si_tex_dim(struct si_screen * sscreen,struct si_texture * tex,unsigned view_target,unsigned nr_samples)2062 static unsigned si_tex_dim(struct si_screen *sscreen, struct si_texture *tex, unsigned view_target,
2063 unsigned nr_samples)
2064 {
2065 unsigned res_target = tex->buffer.b.b.target;
2066
2067 if (view_target == PIPE_TEXTURE_CUBE || view_target == PIPE_TEXTURE_CUBE_ARRAY)
2068 res_target = view_target;
2069 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
2070 else if (res_target == PIPE_TEXTURE_CUBE || res_target == PIPE_TEXTURE_CUBE_ARRAY)
2071 res_target = PIPE_TEXTURE_2D_ARRAY;
2072
2073 /* GFX9 allocates 1D textures as 2D. */
2074 if ((res_target == PIPE_TEXTURE_1D || res_target == PIPE_TEXTURE_1D_ARRAY) &&
2075 sscreen->info.gfx_level == GFX9 &&
2076 tex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
2077 if (res_target == PIPE_TEXTURE_1D)
2078 res_target = PIPE_TEXTURE_2D;
2079 else
2080 res_target = PIPE_TEXTURE_2D_ARRAY;
2081 }
2082
2083 switch (res_target) {
2084 default:
2085 case PIPE_TEXTURE_1D:
2086 return V_008F1C_SQ_RSRC_IMG_1D;
2087 case PIPE_TEXTURE_1D_ARRAY:
2088 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
2089 case PIPE_TEXTURE_2D:
2090 case PIPE_TEXTURE_RECT:
2091 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA : V_008F1C_SQ_RSRC_IMG_2D;
2092 case PIPE_TEXTURE_2D_ARRAY:
2093 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
2094 case PIPE_TEXTURE_3D:
2095 return V_008F1C_SQ_RSRC_IMG_3D;
2096 case PIPE_TEXTURE_CUBE:
2097 case PIPE_TEXTURE_CUBE_ARRAY:
2098 return V_008F1C_SQ_RSRC_IMG_CUBE;
2099 }
2100 }
2101
2102 /*
2103 * Format support testing
2104 */
2105
si_is_sampler_format_supported(struct pipe_screen * screen,enum pipe_format format)2106 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
2107 {
2108 struct si_screen *sscreen = (struct si_screen *)screen;
2109 const struct util_format_description *desc = util_format_description(format);
2110
2111 /* Samplers don't support 64 bits per channel. */
2112 if (desc->layout == UTIL_FORMAT_LAYOUT_PLAIN &&
2113 desc->channel[0].size == 64)
2114 return false;
2115
2116 if (sscreen->info.gfx_level >= GFX10) {
2117 const struct gfx10_format *fmt = &ac_get_gfx10_format_table(sscreen->info.gfx_level)[format];
2118 if (!fmt->img_format || fmt->buffers_only)
2119 return false;
2120 return true;
2121 }
2122
2123 const int first_non_void = util_format_get_first_non_void_channel(format);
2124
2125 if (si_translate_texformat(screen, format, desc, first_non_void) == ~0U)
2126 return false;
2127
2128 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB &&
2129 desc->nr_channels != 4 && desc->nr_channels != 1)
2130 return false;
2131
2132 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC && !sscreen->info.has_etc_support)
2133 return false;
2134
2135 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED &&
2136 (desc->format == PIPE_FORMAT_G8B8_G8R8_UNORM ||
2137 desc->format == PIPE_FORMAT_B8G8_R8G8_UNORM))
2138 return false;
2139
2140 /* Other "OTHER" layouts are unsupported. */
2141 if (desc->layout == UTIL_FORMAT_LAYOUT_OTHER &&
2142 desc->format != PIPE_FORMAT_R11G11B10_FLOAT &&
2143 desc->format != PIPE_FORMAT_R9G9B9E5_FLOAT)
2144 return false;
2145
2146 /* This must be before using first_non_void. */
2147 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
2148 return true;
2149
2150 if (first_non_void < 0 || first_non_void > 3)
2151 return false;
2152
2153 /* Reject SCALED formats because we don't implement them for CB and do the same for texturing. */
2154 if ((desc->channel[first_non_void].type == UTIL_FORMAT_TYPE_UNSIGNED ||
2155 desc->channel[first_non_void].type == UTIL_FORMAT_TYPE_SIGNED) &&
2156 !desc->channel[first_non_void].normalized &&
2157 !desc->channel[first_non_void].pure_integer)
2158 return false;
2159
2160 /* Reject unsupported 32_*NORM and FIXED formats. */
2161 if (desc->channel[first_non_void].size == 32 &&
2162 (desc->channel[first_non_void].normalized ||
2163 desc->channel[first_non_void].type == UTIL_FORMAT_TYPE_FIXED))
2164 return false;
2165
2166 /* This format fails on Gfx8/Carrizo´. */
2167 if (sscreen->info.family == CHIP_CARRIZO && format == PIPE_FORMAT_A8R8_UNORM)
2168 return false;
2169
2170 /* Reject unsupported 3x 32-bit formats for CB. */
2171 if (desc->nr_channels == 3 && desc->channel[0].size == 32 && desc->channel[1].size == 32 &&
2172 desc->channel[2].size == 32)
2173 return false;
2174
2175 /* Reject all 64-bit formats. */
2176 if (desc->channel[first_non_void].size == 64)
2177 return false;
2178
2179 return true;
2180 }
2181
si_translate_buffer_dataformat(struct pipe_screen * screen,const struct util_format_description * desc,int first_non_void)2182 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
2183 const struct util_format_description *desc,
2184 int first_non_void)
2185 {
2186 assert(((struct si_screen *)screen)->info.gfx_level <= GFX9);
2187
2188 return ac_translate_buffer_dataformat(desc, first_non_void);
2189 }
2190
si_translate_buffer_numformat(struct pipe_screen * screen,const struct util_format_description * desc,int first_non_void)2191 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
2192 const struct util_format_description *desc,
2193 int first_non_void)
2194 {
2195 assert(((struct si_screen *)screen)->info.gfx_level <= GFX9);
2196
2197 return ac_translate_buffer_numformat(desc, first_non_void);
2198 }
2199
si_is_vertex_format_supported(struct pipe_screen * screen,enum pipe_format format,unsigned usage)2200 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format,
2201 unsigned usage)
2202 {
2203 struct si_screen *sscreen = (struct si_screen *)screen;
2204 const struct util_format_description *desc;
2205 int first_non_void;
2206 unsigned data_format;
2207
2208 assert((usage & ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_VERTEX_BUFFER)) ==
2209 0);
2210
2211 desc = util_format_description(format);
2212
2213 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2214 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2215 * for read-only access (with caveats surrounding bounds checks), but
2216 * obviously fails for write access which we have to implement for
2217 * shader images. Luckily, OpenGL doesn't expect this to be supported
2218 * anyway, and so the only impact is on PBO uploads / downloads, which
2219 * shouldn't be expected to be fast for GL_RGB anyway.
2220 */
2221 if (desc->block.bits == 3 * 8 || desc->block.bits == 3 * 16) {
2222 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
2223 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
2224 if (!usage)
2225 return 0;
2226 }
2227 }
2228
2229 if (sscreen->info.gfx_level >= GFX10) {
2230 const struct gfx10_format *fmt = &ac_get_gfx10_format_table(sscreen->info.gfx_level)[format];
2231 unsigned first_image_only_format = sscreen->info.gfx_level >= GFX11 ? 64 : 128;
2232
2233 if (!fmt->img_format || fmt->img_format >= first_image_only_format)
2234 return 0;
2235 return usage;
2236 }
2237
2238 first_non_void = util_format_get_first_non_void_channel(format);
2239 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
2240 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
2241 return 0;
2242
2243 return usage;
2244 }
2245
si_is_zs_format_supported(enum pipe_format format)2246 static bool si_is_zs_format_supported(enum pipe_format format)
2247 {
2248 if (format == PIPE_FORMAT_Z16_UNORM_S8_UINT)
2249 return false;
2250
2251 return ac_is_zs_format_supported(format);
2252 }
2253
si_is_reduction_mode_supported(struct pipe_screen * screen,enum pipe_format format)2254 static bool si_is_reduction_mode_supported(struct pipe_screen *screen, enum pipe_format format)
2255 {
2256 struct si_screen *sscreen = (struct si_screen *)screen;
2257
2258 return ac_is_reduction_mode_supported(&sscreen->info, format, true);
2259 }
2260
si_is_format_supported(struct pipe_screen * screen,enum pipe_format format,enum pipe_texture_target target,unsigned sample_count,unsigned storage_sample_count,unsigned usage)2261 static bool si_is_format_supported(struct pipe_screen *screen, enum pipe_format format,
2262 enum pipe_texture_target target, unsigned sample_count,
2263 unsigned storage_sample_count, unsigned usage)
2264 {
2265 struct si_screen *sscreen = (struct si_screen *)screen;
2266 unsigned retval = 0;
2267
2268 if (target >= PIPE_MAX_TEXTURE_TYPES) {
2269 PRINT_ERR("radeonsi: unsupported texture type %d\n", target);
2270 return false;
2271 }
2272
2273 /* Require PIPE_BIND_SAMPLER_VIEW support when PIPE_BIND_RENDER_TARGET
2274 * is requested.
2275 */
2276 if (usage & PIPE_BIND_RENDER_TARGET)
2277 usage |= PIPE_BIND_SAMPLER_VIEW;
2278
2279 if ((target == PIPE_TEXTURE_3D || target == PIPE_TEXTURE_CUBE) &&
2280 !sscreen->info.has_3d_cube_border_color_mipmap)
2281 return false;
2282
2283 if (util_format_get_num_planes(format) >= 2)
2284 return false;
2285
2286 if (MAX2(1, sample_count) < MAX2(1, storage_sample_count))
2287 return false;
2288
2289 if (sample_count > 1) {
2290 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
2291 return false;
2292
2293 /* Only power-of-two sample counts are supported. */
2294 if (!util_is_power_of_two_or_zero(sample_count) ||
2295 !util_is_power_of_two_or_zero(storage_sample_count))
2296 return false;
2297
2298 /* Chips with 1 RB don't increment occlusion queries at 16x MSAA sample rate,
2299 * so don't expose 16 samples there.
2300 *
2301 * EQAA also uses max 8 samples because our FMASK fetches only load 32 bits and
2302 * would need to be changed to 64 bits for 16 samples.
2303 */
2304 const unsigned max_samples = 8;
2305
2306 /* MSAA support without framebuffer attachments. */
2307 if (format == PIPE_FORMAT_NONE && sample_count <= max_samples)
2308 return true;
2309
2310 if (!sscreen->info.has_eqaa_surface_allocator || util_format_is_depth_or_stencil(format)) {
2311 /* Color without EQAA or depth/stencil. */
2312 if (sample_count > max_samples || sample_count != storage_sample_count)
2313 return false;
2314 } else {
2315 /* Color with EQAA. */
2316 if (sample_count > max_samples || storage_sample_count > max_samples)
2317 return false;
2318 }
2319 }
2320
2321 if (usage & (PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_SHADER_IMAGE)) {
2322 if (target == PIPE_BUFFER) {
2323 retval |= si_is_vertex_format_supported(
2324 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_SHADER_IMAGE));
2325 } else {
2326 if (si_is_sampler_format_supported(screen, format))
2327 retval |= usage & (PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_SHADER_IMAGE);
2328 }
2329 }
2330
2331 if ((usage & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT |
2332 PIPE_BIND_SHARED | PIPE_BIND_BLENDABLE)) &&
2333 ac_is_colorbuffer_format_supported(sscreen->info.gfx_level, format)) {
2334 retval |= usage & (PIPE_BIND_RENDER_TARGET | PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT |
2335 PIPE_BIND_SHARED);
2336 if (!util_format_is_pure_integer(format) && !util_format_is_depth_or_stencil(format))
2337 retval |= usage & PIPE_BIND_BLENDABLE;
2338 }
2339
2340 if ((usage & PIPE_BIND_DEPTH_STENCIL) && si_is_zs_format_supported(format)) {
2341 retval |= PIPE_BIND_DEPTH_STENCIL;
2342 }
2343
2344 if (usage & PIPE_BIND_VERTEX_BUFFER) {
2345 retval |= si_is_vertex_format_supported(screen, format, PIPE_BIND_VERTEX_BUFFER);
2346 }
2347
2348 if (usage & PIPE_BIND_INDEX_BUFFER) {
2349 if (format == PIPE_FORMAT_R8_UINT ||
2350 format == PIPE_FORMAT_R16_UINT ||
2351 format == PIPE_FORMAT_R32_UINT)
2352 retval |= PIPE_BIND_INDEX_BUFFER;
2353 }
2354
2355 if ((usage & PIPE_BIND_LINEAR) && !util_format_is_compressed(format) &&
2356 !(usage & PIPE_BIND_DEPTH_STENCIL))
2357 retval |= PIPE_BIND_LINEAR;
2358
2359 if ((usage & PIPE_BIND_SAMPLER_REDUCTION_MINMAX) &&
2360 screen->get_param(screen, PIPE_CAP_SAMPLER_REDUCTION_MINMAX) &&
2361 si_is_reduction_mode_supported(screen, format))
2362 retval |= PIPE_BIND_SAMPLER_REDUCTION_MINMAX;
2363
2364 return retval == usage;
2365 }
2366
2367 /*
2368 * framebuffer handling
2369 */
2370
si_choose_spi_color_formats(struct si_surface * surf,unsigned format,unsigned swap,unsigned ntype,bool is_depth)2371 static void si_choose_spi_color_formats(struct si_surface *surf, unsigned format, unsigned swap,
2372 unsigned ntype, bool is_depth)
2373 {
2374 struct ac_spi_color_formats formats = {};
2375
2376 ac_choose_spi_color_formats(format, swap, ntype, is_depth, true, &formats);
2377
2378 surf->spi_shader_col_format = formats.normal;
2379 surf->spi_shader_col_format_alpha = formats.alpha;
2380 surf->spi_shader_col_format_blend = formats.blend;
2381 surf->spi_shader_col_format_blend_alpha = formats.blend_alpha;
2382 }
2383
si_initialize_color_surface(struct si_context * sctx,struct si_surface * surf)2384 static void si_initialize_color_surface(struct si_context *sctx, struct si_surface *surf)
2385 {
2386 struct si_texture *tex = (struct si_texture *)surf->base.texture;
2387 unsigned format, swap, ntype;//, endian;
2388
2389 ntype = ac_get_cb_number_type(surf->base.format);
2390 format = ac_get_cb_format(sctx->gfx_level, surf->base.format);
2391
2392 if (format == V_028C70_COLOR_INVALID) {
2393 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2394 }
2395 assert(format != V_028C70_COLOR_INVALID);
2396 swap = ac_translate_colorswap(sctx->gfx_level, surf->base.format, false);
2397
2398 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2399 if (format == V_028C70_COLOR_8 || format == V_028C70_COLOR_8_8 ||
2400 format == V_028C70_COLOR_8_8_8_8)
2401 surf->color_is_int8 = true;
2402 else if (format == V_028C70_COLOR_10_10_10_2 || format == V_028C70_COLOR_2_10_10_10)
2403 surf->color_is_int10 = true;
2404 }
2405
2406 const struct ac_cb_state cb_state = {
2407 .surf = &tex->surface,
2408 .format = surf->base.format,
2409 .width = surf->width0,
2410 .height = surf->height0,
2411 .first_layer = surf->base.u.tex.first_layer,
2412 .last_layer = surf->base.u.tex.last_layer,
2413 .num_layers = util_max_layer(&tex->buffer.b.b, 0),
2414 .num_samples = tex->buffer.b.b.nr_samples,
2415 .num_storage_samples = tex->buffer.b.b.nr_storage_samples,
2416 .base_level = surf->base.u.tex.level,
2417 .num_levels = tex->buffer.b.b.last_level + 1,
2418 };
2419
2420 ac_init_cb_surface(&sctx->screen->info, &cb_state, &surf->cb);
2421
2422 /* Determine pixel shader export format */
2423 si_choose_spi_color_formats(surf, format, swap, ntype, tex->is_depth);
2424
2425 surf->color_initialized = true;
2426 }
2427
si_init_depth_surface(struct si_context * sctx,struct si_surface * surf)2428 static void si_init_depth_surface(struct si_context *sctx, struct si_surface *surf)
2429 {
2430 struct si_texture *tex = (struct si_texture *)surf->base.texture;
2431 unsigned level = surf->base.u.tex.level;
2432 unsigned format;
2433
2434 format = ac_translate_dbformat(tex->db_render_format);
2435
2436 assert(format != V_028040_Z_24 || sctx->gfx_level < GFX12);
2437 assert(format != V_028040_Z_INVALID);
2438
2439 if (format == V_028040_Z_INVALID)
2440 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", tex->buffer.b.b.format);
2441
2442 /* Use the original Z format, not db_render_format, so that the polygon offset behaves as
2443 * expected by applications.
2444 */
2445 switch (tex->buffer.b.b.format) {
2446 case PIPE_FORMAT_Z16_UNORM:
2447 surf->db_format_index = 0;
2448 break;
2449 default: /* 24-bit */
2450 surf->db_format_index = 1;
2451 break;
2452 case PIPE_FORMAT_Z32_FLOAT:
2453 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2454 surf->db_format_index = 2;
2455 break;
2456 }
2457
2458 const struct ac_ds_state ds_state = {
2459 .surf = &tex->surface,
2460 .va = tex->buffer.gpu_address,
2461 .format = tex->db_render_format,
2462 .width = tex->buffer.b.b.width0,
2463 .height = tex->buffer.b.b.height0,
2464 .level = level,
2465 .num_levels = tex->buffer.b.b.last_level + 1,
2466 .num_samples = tex->buffer.b.b.nr_samples,
2467 .first_layer = surf->base.u.tex.first_layer,
2468 .last_layer = surf->base.u.tex.last_layer,
2469 .allow_expclear = true,
2470 .htile_enabled = sctx->gfx_level < GFX12 && si_htile_enabled(tex, level, PIPE_MASK_ZS),
2471 .htile_stencil_disabled = tex->htile_stencil_disabled,
2472 };
2473
2474 ac_init_ds_surface(&sctx->screen->info, &ds_state, &surf->ds);
2475
2476 surf->depth_initialized = true;
2477 }
2478
si_dec_framebuffer_counters(const struct pipe_framebuffer_state * state)2479 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2480 {
2481 for (int i = 0; i < state->nr_cbufs; ++i) {
2482 struct si_surface *surf = NULL;
2483 struct si_texture *tex;
2484
2485 if (!state->cbufs[i])
2486 continue;
2487 surf = (struct si_surface *)state->cbufs[i];
2488 tex = (struct si_texture *)surf->base.texture;
2489
2490 p_atomic_dec(&tex->framebuffers_bound);
2491 }
2492 }
2493
si_mark_display_dcc_dirty(struct si_context * sctx,struct si_texture * tex)2494 void si_mark_display_dcc_dirty(struct si_context *sctx, struct si_texture *tex)
2495 {
2496 assert(sctx->gfx_level < GFX12);
2497
2498 if (!tex->surface.display_dcc_offset || tex->displayable_dcc_dirty)
2499 return;
2500
2501 if (!(tex->buffer.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH)) {
2502 struct hash_entry *entry = _mesa_hash_table_search(sctx->dirty_implicit_resources, tex);
2503 if (!entry) {
2504 struct pipe_resource *dummy = NULL;
2505 pipe_resource_reference(&dummy, &tex->buffer.b.b);
2506 _mesa_hash_table_insert(sctx->dirty_implicit_resources, tex, tex);
2507 }
2508 }
2509 tex->displayable_dcc_dirty = true;
2510 }
2511
si_update_display_dcc_dirty(struct si_context * sctx)2512 static void si_update_display_dcc_dirty(struct si_context *sctx)
2513 {
2514 const struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2515
2516 for (unsigned i = 0; i < state->nr_cbufs; i++) {
2517 if (state->cbufs[i])
2518 si_mark_display_dcc_dirty(sctx, (struct si_texture *)state->cbufs[i]->texture);
2519 }
2520 }
2521
si_set_framebuffer_state(struct pipe_context * ctx,const struct pipe_framebuffer_state * state)2522 static void si_set_framebuffer_state(struct pipe_context *ctx,
2523 const struct pipe_framebuffer_state *state)
2524 {
2525 struct si_context *sctx = (struct si_context *)ctx;
2526 struct si_surface *surf = NULL;
2527 struct si_texture *tex;
2528 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2529 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2530 unsigned old_colorbuf_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit;
2531 bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf;
2532 bool old_has_stencil =
2533 old_has_zsbuf &&
2534 ((struct si_texture *)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
2535 uint8_t old_db_format_index =
2536 old_has_zsbuf ?
2537 ((struct si_surface *)sctx->framebuffer.state.zsbuf)->db_format_index : -1;
2538 bool old_has_hiz_his = sctx->framebuffer.has_hiz_his;
2539 int i;
2540
2541 /* Reject zero-sized framebuffers due to a hw bug on GFX6 that occurs
2542 * when PA_SU_HARDWARE_SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
2543 * We could implement the full workaround here, but it's a useless case.
2544 */
2545 if ((!state->width || !state->height) && (state->nr_cbufs || state->zsbuf)) {
2546 unreachable("the framebuffer shouldn't have zero area");
2547 return;
2548 }
2549
2550 si_fb_barrier_after_rendering(sctx, SI_FB_BARRIER_SYNC_ALL);
2551
2552 /* Disable DCC if the formats are incompatible. */
2553 if (sctx->gfx_level >= GFX8 && sctx->gfx_level < GFX11) {
2554 for (i = 0; i < state->nr_cbufs; i++) {
2555 if (!state->cbufs[i])
2556 continue;
2557
2558 surf = (struct si_surface *)state->cbufs[i];
2559 tex = (struct si_texture *)surf->base.texture;
2560
2561 if (!surf->dcc_incompatible)
2562 continue;
2563
2564 if (vi_dcc_enabled(tex, surf->base.u.tex.level))
2565 if (!si_texture_disable_dcc(sctx, tex))
2566 si_decompress_dcc(sctx, tex);
2567
2568 surf->dcc_incompatible = false;
2569 }
2570 }
2571
2572 /* Take the maximum of the old and new count. If the new count is lower,
2573 * dirtying is needed to disable the unbound colorbuffers.
2574 */
2575 sctx->framebuffer.dirty_cbufs |=
2576 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2577 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2578
2579 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2580 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2581
2582 /* The framebuffer state must be set before the barrier. */
2583 si_fb_barrier_before_rendering(sctx);
2584
2585 /* Recompute layers because frontends and utils might not set it. */
2586 sctx->framebuffer.state.layers = util_framebuffer_get_num_layers(state);
2587
2588 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2589 sctx->framebuffer.spi_shader_col_format = 0;
2590 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2591 sctx->framebuffer.spi_shader_col_format_blend = 0;
2592 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2593 sctx->framebuffer.color_is_int8 = 0;
2594 sctx->framebuffer.color_is_int10 = 0;
2595
2596 sctx->framebuffer.compressed_cb_mask = 0;
2597 sctx->framebuffer.uncompressed_cb_mask = 0;
2598 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2599 sctx->framebuffer.nr_color_samples = sctx->framebuffer.nr_samples;
2600 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2601 sctx->framebuffer.any_dst_linear = false;
2602 sctx->framebuffer.CB_has_shader_readable_metadata = false;
2603 sctx->framebuffer.DB_has_shader_readable_metadata = false;
2604 sctx->framebuffer.all_DCC_pipe_aligned = true;
2605 sctx->framebuffer.has_dcc_msaa = false;
2606 sctx->framebuffer.min_bytes_per_pixel = 0;
2607 sctx->framebuffer.disable_vrs_flat_shading = false;
2608 sctx->framebuffer.has_stencil = false;
2609 sctx->framebuffer.has_hiz_his = false;
2610
2611 for (i = 0; i < state->nr_cbufs; i++) {
2612 if (!state->cbufs[i])
2613 continue;
2614
2615 surf = (struct si_surface *)state->cbufs[i];
2616 tex = (struct si_texture *)surf->base.texture;
2617
2618 if (!surf->color_initialized) {
2619 si_initialize_color_surface(sctx, surf);
2620 }
2621
2622 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2623 sctx->framebuffer.spi_shader_col_format |= surf->spi_shader_col_format << (i * 4);
2624 sctx->framebuffer.spi_shader_col_format_alpha |= surf->spi_shader_col_format_alpha << (i * 4);
2625 sctx->framebuffer.spi_shader_col_format_blend |= surf->spi_shader_col_format_blend << (i * 4);
2626 sctx->framebuffer.spi_shader_col_format_blend_alpha |= surf->spi_shader_col_format_blend_alpha
2627 << (i * 4);
2628
2629 if (surf->color_is_int8)
2630 sctx->framebuffer.color_is_int8 |= 1 << i;
2631 if (surf->color_is_int10)
2632 sctx->framebuffer.color_is_int10 |= 1 << i;
2633
2634 if (tex->surface.fmask_offset)
2635 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2636 else
2637 sctx->framebuffer.uncompressed_cb_mask |= 1 << i;
2638
2639 /* Don't update nr_color_samples for non-AA buffers.
2640 * (e.g. destination of MSAA resolve)
2641 */
2642 if (tex->buffer.b.b.nr_samples >= 2 &&
2643 tex->buffer.b.b.nr_storage_samples < tex->buffer.b.b.nr_samples) {
2644 sctx->framebuffer.nr_color_samples =
2645 MIN2(sctx->framebuffer.nr_color_samples, tex->buffer.b.b.nr_storage_samples);
2646 sctx->framebuffer.nr_color_samples = MAX2(1, sctx->framebuffer.nr_color_samples);
2647 }
2648
2649 if (tex->surface.is_linear)
2650 sctx->framebuffer.any_dst_linear = true;
2651
2652 if (vi_dcc_enabled(tex, surf->base.u.tex.level)) {
2653 sctx->framebuffer.CB_has_shader_readable_metadata = true;
2654
2655 if (sctx->gfx_level >= GFX9 && sctx->gfx_level < GFX12 &&
2656 !tex->surface.u.gfx9.color.dcc.pipe_aligned)
2657 sctx->framebuffer.all_DCC_pipe_aligned = false;
2658
2659 if (tex->buffer.b.b.nr_storage_samples >= 2)
2660 sctx->framebuffer.has_dcc_msaa = true;
2661 }
2662
2663 p_atomic_inc(&tex->framebuffers_bound);
2664
2665 /* Update the minimum but don't keep 0. */
2666 if (!sctx->framebuffer.min_bytes_per_pixel ||
2667 tex->surface.bpe < sctx->framebuffer.min_bytes_per_pixel)
2668 sctx->framebuffer.min_bytes_per_pixel = tex->surface.bpe;
2669
2670 /* Disable VRS flat shading where it decreases performance.
2671 * This gives the best results for slow clears for AMD_TEST=blitperf on Navi31.
2672 */
2673 if ((sctx->framebuffer.nr_samples == 8 && tex->surface.bpe != 2) ||
2674 (tex->surface.thick_tiling && tex->surface.bpe == 4 &&
2675 util_format_get_nr_components(surf->base.format) == 4))
2676 sctx->framebuffer.disable_vrs_flat_shading = true;
2677 }
2678
2679 struct si_texture *zstex = NULL;
2680
2681 if (state->zsbuf) {
2682 surf = (struct si_surface *)state->zsbuf;
2683 zstex = (struct si_texture *)surf->base.texture;
2684
2685 if (!surf->depth_initialized) {
2686 si_init_depth_surface(sctx, surf);
2687 }
2688
2689 if (sctx->gfx_level < GFX12 &&
2690 vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level, PIPE_MASK_ZS))
2691 sctx->framebuffer.DB_has_shader_readable_metadata = true;
2692
2693 /* Update the minimum but don't keep 0. */
2694 if (!sctx->framebuffer.min_bytes_per_pixel ||
2695 zstex->surface.bpe < sctx->framebuffer.min_bytes_per_pixel)
2696 sctx->framebuffer.min_bytes_per_pixel = zstex->surface.bpe;
2697
2698 /* Update polygon offset based on the Z format. */
2699 if (sctx->queued.named.rasterizer->uses_poly_offset &&
2700 surf->db_format_index != old_db_format_index)
2701 sctx->dirty_atoms |= SI_STATE_BIT(rasterizer);
2702
2703 if (util_format_has_stencil(util_format_description(zstex->buffer.b.b.format)))
2704 sctx->framebuffer.has_stencil = true;
2705
2706 if (sctx->gfx_level >= GFX12) {
2707 sctx->framebuffer.has_hiz_his = zstex->surface.u.gfx9.zs.hiz.offset ||
2708 zstex->surface.u.gfx9.zs.his.offset;
2709 }
2710 }
2711
2712 si_update_ps_colorbuf0_slot(sctx);
2713 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
2714 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
2715
2716 /* NGG cull state uses the sample count. */
2717 if (sctx->screen->use_ngg_culling)
2718 si_mark_atom_dirty(sctx, &sctx->atoms.s.ngg_cull_state);
2719
2720 if (sctx->screen->dpbb_allowed)
2721 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
2722
2723 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear ||
2724 sctx->framebuffer.has_hiz_his != old_has_hiz_his)
2725 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2726
2727 if (sctx->screen->info.has_out_of_order_rast &&
2728 (sctx->framebuffer.colorbuf_enabled_4bit != old_colorbuf_enabled_4bit ||
2729 !!sctx->framebuffer.state.zsbuf != old_has_zsbuf ||
2730 (zstex && zstex->surface.has_stencil != old_has_stencil)))
2731 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2732
2733 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2734 struct pipe_constant_buffer constbuf = {0};
2735
2736 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2737 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
2738
2739 if (!sctx->sample_pos_buffer) {
2740 sctx->sample_pos_buffer = pipe_buffer_create_with_data(&sctx->b, 0, PIPE_USAGE_DEFAULT,
2741 sizeof(sctx->sample_positions),
2742 &sctx->sample_positions);
2743 }
2744 constbuf.buffer = sctx->sample_pos_buffer;
2745
2746 /* Set sample locations as fragment shader constants. */
2747 switch (sctx->framebuffer.nr_samples) {
2748 case 1:
2749 constbuf.buffer_offset = 0;
2750 break;
2751 case 2:
2752 constbuf.buffer_offset =
2753 (uint8_t *)sctx->sample_positions.x2 - (uint8_t *)sctx->sample_positions.x1;
2754 break;
2755 case 4:
2756 constbuf.buffer_offset =
2757 (uint8_t *)sctx->sample_positions.x4 - (uint8_t *)sctx->sample_positions.x1;
2758 break;
2759 case 8:
2760 constbuf.buffer_offset =
2761 (uint8_t *)sctx->sample_positions.x8 - (uint8_t *)sctx->sample_positions.x1;
2762 break;
2763 case 16:
2764 constbuf.buffer_offset =
2765 (uint8_t *)sctx->sample_positions.x16 - (uint8_t *)sctx->sample_positions.x1;
2766 break;
2767 default:
2768 PRINT_ERR("Requested an invalid number of samples %i.\n", sctx->framebuffer.nr_samples);
2769 assert(0);
2770 }
2771 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2772 si_set_internal_const_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2773
2774 si_mark_atom_dirty(sctx, &sctx->atoms.s.sample_locations);
2775 }
2776
2777 si_ps_key_update_framebuffer(sctx);
2778 si_ps_key_update_framebuffer_blend_rasterizer(sctx);
2779 si_ps_key_update_framebuffer_rasterizer_sample_shading(sctx);
2780 si_vs_ps_key_update_rast_prim_smooth_stipple(sctx);
2781 si_update_ps_inputs_read_or_disabled(sctx);
2782 si_update_vrs_flat_shading(sctx);
2783 sctx->do_update_shaders = true;
2784
2785 if (sctx->gfx_level < GFX12 && !sctx->decompression_enabled) {
2786 /* Prevent textures decompression when the framebuffer state
2787 * changes come from the decompression passes themselves.
2788 */
2789 sctx->need_check_render_feedback = true;
2790 }
2791 }
2792
gfx6_emit_framebuffer_state(struct si_context * sctx,unsigned index)2793 static void gfx6_emit_framebuffer_state(struct si_context *sctx, unsigned index)
2794 {
2795 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
2796 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2797 unsigned i, nr_cbufs = state->nr_cbufs;
2798 struct si_texture *tex = NULL;
2799 struct si_surface *cb = NULL;
2800 bool is_msaa_resolve = state->nr_cbufs == 2 &&
2801 state->cbufs[0] && state->cbufs[0]->texture->nr_samples > 1 &&
2802 state->cbufs[1] && state->cbufs[1]->texture->nr_samples <= 1;
2803
2804 /* CB can't do MSAA resolve on gfx11. */
2805 assert(!is_msaa_resolve || sctx->gfx_level < GFX11);
2806
2807 radeon_begin(cs);
2808
2809 /* Colorbuffers. */
2810 for (i = 0; i < nr_cbufs; i++) {
2811 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2812 continue;
2813
2814 /* RB+ depth-only rendering. See the comment where we set rbplus_depth_only_opt for more
2815 * information.
2816 */
2817 if (i == 0 &&
2818 sctx->screen->info.rbplus_allowed &&
2819 !sctx->queued.named.blend->cb_target_mask) {
2820 radeon_set_context_reg(R_028C70_CB_COLOR0_INFO + i * 0x3C,
2821 (sctx->gfx_level >= GFX11 ?
2822 S_028C70_FORMAT_GFX11(V_028C70_COLOR_32) :
2823 S_028C70_FORMAT_GFX6(V_028C70_COLOR_32)) |
2824 S_028C70_NUMBER_TYPE(V_028C70_NUMBER_FLOAT));
2825 continue;
2826 }
2827
2828 cb = (struct si_surface *)state->cbufs[i];
2829 if (!cb) {
2830 radeon_set_context_reg(R_028C70_CB_COLOR0_INFO + i * 0x3C,
2831 sctx->gfx_level >= GFX11 ?
2832 S_028C70_FORMAT_GFX11(V_028C70_COLOR_INVALID) :
2833 S_028C70_FORMAT_GFX6(V_028C70_COLOR_INVALID));
2834 continue;
2835 }
2836
2837 tex = (struct si_texture *)cb->base.texture;
2838 radeon_add_to_buffer_list(
2839 sctx, &sctx->gfx_cs, &tex->buffer, RADEON_USAGE_READWRITE | RADEON_USAGE_CB_NEEDS_IMPLICIT_SYNC |
2840 (tex->buffer.b.b.nr_samples > 1 ? RADEON_PRIO_COLOR_BUFFER_MSAA : RADEON_PRIO_COLOR_BUFFER));
2841
2842 if (tex->cmask_buffer && tex->cmask_buffer != &tex->buffer) {
2843 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, tex->cmask_buffer,
2844 RADEON_USAGE_READWRITE | RADEON_USAGE_CB_NEEDS_IMPLICIT_SYNC |
2845 RADEON_PRIO_SEPARATE_META);
2846 }
2847
2848 /* Compute mutable surface parameters. */
2849 const struct ac_mutable_cb_state mutable_cb_state = {
2850 .surf = &tex->surface,
2851 .cb = &cb->cb,
2852 .va = tex->buffer.gpu_address,
2853 .base_level = cb->base.u.tex.level,
2854 .num_samples = cb->base.texture->nr_samples,
2855 .fmask_enabled = !!tex->surface.fmask_offset,
2856 /* CMASK and fast clears are configured elsewhere. */
2857 .cmask_enabled = false,
2858 .fast_clear_enabled = false,
2859 .dcc_enabled = vi_dcc_enabled(tex, cb->base.u.tex.level) &&
2860 (i != 1 || !is_msaa_resolve),
2861 };
2862 struct ac_cb_surface cb_surf;
2863
2864 ac_set_mutable_cb_surface_fields(&sctx->screen->info, &mutable_cb_state, &cb_surf);
2865
2866 cb_surf.cb_color_info |= tex->cb_color_info;
2867
2868 if (sctx->gfx_level < GFX11) {
2869 if (tex->swap_rgb_to_bgr) {
2870 /* Swap R and B channels. */
2871 static unsigned rgb_to_bgr[4] = {
2872 [V_028C70_SWAP_STD] = V_028C70_SWAP_ALT,
2873 [V_028C70_SWAP_ALT] = V_028C70_SWAP_STD,
2874 [V_028C70_SWAP_STD_REV] = V_028C70_SWAP_ALT_REV,
2875 [V_028C70_SWAP_ALT_REV] = V_028C70_SWAP_STD_REV,
2876 };
2877 unsigned swap = rgb_to_bgr[G_028C70_COMP_SWAP(cb_surf.cb_color_info)];
2878
2879 cb_surf.cb_color_info &= C_028C70_COMP_SWAP;
2880 cb_surf.cb_color_info |= S_028C70_COMP_SWAP(swap);
2881 }
2882
2883 if (cb->base.u.tex.level > 0)
2884 cb_surf.cb_color_info &= C_028C70_FAST_CLEAR;
2885 else
2886 cb_surf.cb_color_cmask = tex->cmask_base_address_reg;
2887 }
2888
2889 if (sctx->gfx_level >= GFX11) {
2890 radeon_set_context_reg(R_028C60_CB_COLOR0_BASE + i * 0x3C, cb_surf.cb_color_base);
2891
2892 radeon_set_context_reg_seq(R_028C6C_CB_COLOR0_VIEW + i * 0x3C, 4);
2893 radeon_emit(cb_surf.cb_color_view); /* CB_COLOR0_VIEW */
2894 radeon_emit(cb_surf.cb_color_info); /* CB_COLOR0_INFO */
2895 radeon_emit(cb_surf.cb_color_attrib); /* CB_COLOR0_ATTRIB */
2896 radeon_emit(cb_surf.cb_dcc_control); /* CB_COLOR0_FDCC_CONTROL */
2897
2898 radeon_set_context_reg(R_028C94_CB_COLOR0_DCC_BASE + i * 0x3C, cb_surf.cb_dcc_base);
2899 radeon_set_context_reg(R_028E40_CB_COLOR0_BASE_EXT + i * 4, cb_surf.cb_color_base >> 32);
2900 radeon_set_context_reg(R_028EA0_CB_COLOR0_DCC_BASE_EXT + i * 4, cb_surf.cb_dcc_base >> 32);
2901 radeon_set_context_reg(R_028EC0_CB_COLOR0_ATTRIB2 + i * 4, cb_surf.cb_color_attrib2);
2902 radeon_set_context_reg(R_028EE0_CB_COLOR0_ATTRIB3 + i * 4, cb_surf.cb_color_attrib3);
2903 } else if (sctx->gfx_level >= GFX10) {
2904 radeon_set_context_reg_seq(R_028C60_CB_COLOR0_BASE + i * 0x3C, 14);
2905 radeon_emit(cb_surf.cb_color_base); /* CB_COLOR0_BASE */
2906 radeon_emit(0); /* hole */
2907 radeon_emit(0); /* hole */
2908 radeon_emit(cb_surf.cb_color_view); /* CB_COLOR0_VIEW */
2909 radeon_emit(cb_surf.cb_color_info); /* CB_COLOR0_INFO */
2910 radeon_emit(cb_surf.cb_color_attrib); /* CB_COLOR0_ATTRIB */
2911 radeon_emit(cb_surf.cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
2912 radeon_emit(cb_surf.cb_color_cmask); /* CB_COLOR0_CMASK */
2913 radeon_emit(0); /* hole */
2914 radeon_emit(cb_surf.cb_color_fmask); /* CB_COLOR0_FMASK */
2915 radeon_emit(0); /* hole */
2916 radeon_emit(tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
2917 radeon_emit(tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
2918 radeon_emit(cb_surf.cb_dcc_base); /* CB_COLOR0_DCC_BASE */
2919
2920 radeon_set_context_reg(R_028E40_CB_COLOR0_BASE_EXT + i * 4, cb_surf.cb_color_base >> 32);
2921 radeon_set_context_reg(R_028E60_CB_COLOR0_CMASK_BASE_EXT + i * 4,
2922 cb_surf.cb_color_cmask >> 32);
2923 radeon_set_context_reg(R_028E80_CB_COLOR0_FMASK_BASE_EXT + i * 4,
2924 cb_surf.cb_color_fmask >> 32);
2925 radeon_set_context_reg(R_028EA0_CB_COLOR0_DCC_BASE_EXT + i * 4, cb_surf.cb_dcc_base >> 32);
2926 radeon_set_context_reg(R_028EC0_CB_COLOR0_ATTRIB2 + i * 4, cb_surf.cb_color_attrib2);
2927 radeon_set_context_reg(R_028EE0_CB_COLOR0_ATTRIB3 + i * 4, cb_surf.cb_color_attrib3);
2928 } else if (sctx->gfx_level == GFX9) {
2929 radeon_set_context_reg_seq(R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
2930 radeon_emit(cb_surf.cb_color_base); /* CB_COLOR0_BASE */
2931 radeon_emit(S_028C64_BASE_256B(cb_surf.cb_color_base >> 32)); /* CB_COLOR0_BASE_EXT */
2932 radeon_emit(cb_surf.cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
2933 radeon_emit(cb_surf.cb_color_view); /* CB_COLOR0_VIEW */
2934 radeon_emit(cb_surf.cb_color_info); /* CB_COLOR0_INFO */
2935 radeon_emit(cb_surf.cb_color_attrib); /* CB_COLOR0_ATTRIB */
2936 radeon_emit(cb_surf.cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
2937 radeon_emit(cb_surf.cb_color_cmask); /* CB_COLOR0_CMASK */
2938 radeon_emit(S_028C80_BASE_256B(cb_surf.cb_color_cmask >> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
2939 radeon_emit(cb_surf.cb_color_fmask); /* CB_COLOR0_FMASK */
2940 radeon_emit(S_028C88_BASE_256B(cb_surf.cb_color_fmask >> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
2941 radeon_emit(tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
2942 radeon_emit(tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
2943 radeon_emit(cb_surf.cb_dcc_base); /* CB_COLOR0_DCC_BASE */
2944 radeon_emit(S_028C98_BASE_256B(cb_surf.cb_dcc_base >> 32)); /* CB_COLOR0_DCC_BASE_EXT */
2945
2946 radeon_set_context_reg(R_0287A0_CB_MRT0_EPITCH + i * 4, cb_surf.cb_mrt_epitch);
2947 } else {
2948 /* GFX6-8 */
2949 radeon_set_context_reg_seq(R_028C60_CB_COLOR0_BASE + i * 0x3C,
2950 sctx->gfx_level >= GFX8 ? 14 : 13);
2951 radeon_emit(cb_surf.cb_color_base); /* CB_COLOR0_BASE */
2952 radeon_emit(cb_surf.cb_color_pitch); /* CB_COLOR0_PITCH */
2953 radeon_emit(cb_surf.cb_color_slice); /* CB_COLOR0_SLICE */
2954 radeon_emit(cb_surf.cb_color_view); /* CB_COLOR0_VIEW */
2955 radeon_emit(cb_surf.cb_color_info); /* CB_COLOR0_INFO */
2956 radeon_emit(cb_surf.cb_color_attrib); /* CB_COLOR0_ATTRIB */
2957 radeon_emit(cb_surf.cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
2958 radeon_emit(cb_surf.cb_color_cmask); /* CB_COLOR0_CMASK */
2959 radeon_emit(tex->surface.u.legacy.color.cmask_slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
2960 radeon_emit(cb_surf.cb_color_fmask); /* CB_COLOR0_FMASK */
2961 radeon_emit(cb_surf.cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
2962 radeon_emit(tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
2963 radeon_emit(tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
2964
2965 if (sctx->gfx_level >= GFX8) /* R_028C94_CB_COLOR0_DCC_BASE */
2966 radeon_emit(cb_surf.cb_dcc_base);
2967 }
2968 }
2969 for (; i < 8; i++)
2970 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2971 radeon_set_context_reg(R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2972
2973 /* ZS buffer. */
2974 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2975 struct si_surface *zb = (struct si_surface *)state->zsbuf;
2976 struct si_texture *tex = (struct si_texture *)zb->base.texture;
2977
2978 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, &tex->buffer, RADEON_USAGE_READWRITE |
2979 (zb->base.texture->nr_samples > 1 ? RADEON_PRIO_DEPTH_BUFFER_MSAA
2980 : RADEON_PRIO_DEPTH_BUFFER));
2981
2982 const unsigned level = zb->base.u.tex.level;
2983
2984 /* Set mutable fields. */
2985 const struct ac_mutable_ds_state mutable_ds_state = {
2986 .ds = &zb->ds,
2987 .format = tex->db_render_format,
2988 .tc_compat_htile_enabled = vi_tc_compat_htile_enabled(tex, level, PIPE_MASK_ZS),
2989 .zrange_precision = tex->depth_clear_value[level] != 0,
2990 };
2991 struct ac_ds_surface ds;
2992
2993 ac_set_mutable_ds_surface_fields(&sctx->screen->info, &mutable_ds_state, &ds);
2994
2995 if (sctx->gfx_level >= GFX10) {
2996 radeon_set_context_reg(R_028014_DB_HTILE_DATA_BASE, ds.u.gfx6.db_htile_data_base);
2997 radeon_set_context_reg(R_02801C_DB_DEPTH_SIZE_XY, ds.db_depth_size);
2998
2999 if (sctx->gfx_level >= GFX11) {
3000 radeon_set_context_reg_seq(R_028040_DB_Z_INFO, 6);
3001 } else {
3002 radeon_set_context_reg_seq(R_02803C_DB_DEPTH_INFO, 7);
3003 radeon_emit(S_02803C_RESOURCE_LEVEL(1)); /* DB_DEPTH_INFO */
3004 }
3005 radeon_emit(ds.db_z_info); /* DB_Z_INFO */
3006 radeon_emit(ds.db_stencil_info); /* DB_STENCIL_INFO */
3007 radeon_emit(ds.db_depth_base); /* DB_Z_READ_BASE */
3008 radeon_emit(ds.db_stencil_base); /* DB_STENCIL_READ_BASE */
3009 radeon_emit(ds.db_depth_base); /* DB_Z_WRITE_BASE */
3010 radeon_emit(ds.db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3011
3012 radeon_set_context_reg_seq(R_028068_DB_Z_READ_BASE_HI, 5);
3013 radeon_emit(ds.db_depth_base >> 32); /* DB_Z_READ_BASE_HI */
3014 radeon_emit(ds.db_stencil_base >> 32); /* DB_STENCIL_READ_BASE_HI */
3015 radeon_emit(ds.db_depth_base >> 32); /* DB_Z_WRITE_BASE_HI */
3016 radeon_emit(ds.db_stencil_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
3017 radeon_emit(ds.u.gfx6.db_htile_data_base >> 32); /* DB_HTILE_DATA_BASE_HI */
3018 } else if (sctx->gfx_level == GFX9) {
3019 radeon_set_context_reg_seq(R_028014_DB_HTILE_DATA_BASE, 3);
3020 radeon_emit(ds.u.gfx6.db_htile_data_base); /* DB_HTILE_DATA_BASE */
3021 radeon_emit(S_028018_BASE_HI(ds.u.gfx6.db_htile_data_base >> 32)); /* DB_HTILE_DATA_BASE_HI */
3022 radeon_emit(ds.db_depth_size); /* DB_DEPTH_SIZE */
3023
3024 radeon_set_context_reg_seq(R_028038_DB_Z_INFO, 10);
3025 radeon_emit(ds.db_z_info); /* DB_Z_INFO */
3026 radeon_emit(ds.db_stencil_info); /* DB_STENCIL_INFO */
3027 radeon_emit(ds.db_depth_base); /* DB_Z_READ_BASE */
3028 radeon_emit(S_028044_BASE_HI(ds.db_depth_base >> 32)); /* DB_Z_READ_BASE_HI */
3029 radeon_emit(ds.db_stencil_base); /* DB_STENCIL_READ_BASE */
3030 radeon_emit(S_02804C_BASE_HI(ds.db_stencil_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
3031 radeon_emit(ds.db_depth_base); /* DB_Z_WRITE_BASE */
3032 radeon_emit(S_028054_BASE_HI(ds.db_depth_base >> 32)); /* DB_Z_WRITE_BASE_HI */
3033 radeon_emit(ds.db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3034 radeon_emit(S_02805C_BASE_HI(ds.db_stencil_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3035
3036 radeon_set_context_reg_seq(R_028068_DB_Z_INFO2, 2);
3037 radeon_emit(ds.u.gfx6.db_z_info2); /* DB_Z_INFO2 */
3038 radeon_emit(ds.u.gfx6.db_stencil_info2); /* DB_STENCIL_INFO2 */
3039 } else {
3040 /* GFX6-GFX8 */
3041 radeon_set_context_reg(R_028014_DB_HTILE_DATA_BASE, ds.u.gfx6.db_htile_data_base);
3042
3043 radeon_set_context_reg_seq(R_02803C_DB_DEPTH_INFO, 9);
3044 radeon_emit(ds.u.gfx6.db_depth_info); /* DB_DEPTH_INFO */
3045 radeon_emit(ds.db_z_info); /* DB_Z_INFO */
3046 radeon_emit(ds.db_stencil_info); /* DB_STENCIL_INFO */
3047 radeon_emit(ds.db_depth_base); /* DB_Z_READ_BASE */
3048 radeon_emit(ds.db_stencil_base); /* DB_STENCIL_READ_BASE */
3049 radeon_emit(ds.db_depth_base); /* DB_Z_WRITE_BASE */
3050 radeon_emit(ds.db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3051 radeon_emit(ds.db_depth_size); /* DB_DEPTH_SIZE */
3052 radeon_emit(ds.u.gfx6.db_depth_slice); /* DB_DEPTH_SLICE */
3053 }
3054
3055 radeon_set_context_reg_seq(R_028028_DB_STENCIL_CLEAR, 2);
3056 radeon_emit(tex->stencil_clear_value[level]); /* R_028028_DB_STENCIL_CLEAR */
3057 radeon_emit(fui(tex->depth_clear_value[level])); /* R_02802C_DB_DEPTH_CLEAR */
3058
3059 radeon_set_context_reg(R_028008_DB_DEPTH_VIEW, ds.db_depth_view);
3060 radeon_set_context_reg(R_028ABC_DB_HTILE_SURFACE, ds.u.gfx6.db_htile_surface);
3061 } else if (sctx->framebuffer.dirty_zsbuf) {
3062 if (sctx->gfx_level == GFX9)
3063 radeon_set_context_reg_seq(R_028038_DB_Z_INFO, 2);
3064 else
3065 radeon_set_context_reg_seq(R_028040_DB_Z_INFO, 2);
3066
3067 /* Gfx11+: DB_Z_INFO.NUM_SAMPLES should match the framebuffer samples if no Z/S is bound.
3068 * It determines the sample count for VRS, primitive-ordered pixel shading, and occlusion
3069 * queries.
3070 */
3071 radeon_emit(S_028040_FORMAT(V_028040_Z_INVALID) | /* DB_Z_INFO */
3072 S_028040_NUM_SAMPLES(sctx->gfx_level >= GFX11 ? sctx->framebuffer.log_samples : 0));
3073 radeon_emit(S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
3074 }
3075
3076 /* Framebuffer dimensions. */
3077 /* PA_SC_WINDOW_SCISSOR_TL is set to 0,0 in gfx*_init_gfx_preamble_state */
3078 radeon_set_context_reg(R_028208_PA_SC_WINDOW_SCISSOR_BR,
3079 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
3080
3081 if (sctx->screen->dpbb_allowed &&
3082 sctx->screen->pbb_context_states_per_bin > 1)
3083 radeon_event_write(V_028A90_BREAK_BATCH);
3084
3085 radeon_end();
3086
3087 si_update_display_dcc_dirty(sctx);
3088
3089 sctx->framebuffer.dirty_cbufs = 0;
3090 sctx->framebuffer.dirty_zsbuf = false;
3091 }
3092
gfx11_dgpu_emit_framebuffer_state(struct si_context * sctx,unsigned index)3093 static void gfx11_dgpu_emit_framebuffer_state(struct si_context *sctx, unsigned index)
3094 {
3095 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
3096 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
3097 unsigned i, nr_cbufs = state->nr_cbufs;
3098 struct si_texture *tex = NULL;
3099 struct si_surface *cb = NULL;
3100 bool is_msaa_resolve = state->nr_cbufs == 2 &&
3101 state->cbufs[0] && state->cbufs[0]->texture->nr_samples > 1 &&
3102 state->cbufs[1] && state->cbufs[1]->texture->nr_samples <= 1;
3103
3104 /* CB can't do MSAA resolve on gfx11. */
3105 assert(!is_msaa_resolve);
3106
3107 radeon_begin(cs);
3108 gfx11_begin_packed_context_regs();
3109
3110 /* Colorbuffers. */
3111 for (i = 0; i < nr_cbufs; i++) {
3112 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
3113 continue;
3114
3115 /* RB+ depth-only rendering. See the comment where we set rbplus_depth_only_opt for more
3116 * information.
3117 */
3118 if (i == 0 &&
3119 sctx->screen->info.rbplus_allowed &&
3120 !sctx->queued.named.blend->cb_target_mask) {
3121 gfx11_set_context_reg(R_028C70_CB_COLOR0_INFO + i * 0x3C,
3122 S_028C70_FORMAT_GFX11(V_028C70_COLOR_32) |
3123 S_028C70_NUMBER_TYPE(V_028C70_NUMBER_FLOAT));
3124 continue;
3125 }
3126
3127 cb = (struct si_surface *)state->cbufs[i];
3128 if (!cb) {
3129 gfx11_set_context_reg(R_028C70_CB_COLOR0_INFO + i * 0x3C,
3130 S_028C70_FORMAT_GFX11(V_028C70_COLOR_INVALID));
3131 continue;
3132 }
3133
3134 tex = (struct si_texture *)cb->base.texture;
3135 radeon_add_to_buffer_list(
3136 sctx, &sctx->gfx_cs, &tex->buffer, RADEON_USAGE_READWRITE | RADEON_USAGE_CB_NEEDS_IMPLICIT_SYNC |
3137 (tex->buffer.b.b.nr_samples > 1 ? RADEON_PRIO_COLOR_BUFFER_MSAA : RADEON_PRIO_COLOR_BUFFER));
3138
3139 if (tex->cmask_buffer && tex->cmask_buffer != &tex->buffer) {
3140 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, tex->cmask_buffer,
3141 RADEON_USAGE_READWRITE | RADEON_USAGE_CB_NEEDS_IMPLICIT_SYNC |
3142 RADEON_PRIO_SEPARATE_META);
3143 }
3144
3145 /* Compute mutable surface parameters. */
3146 const struct ac_mutable_cb_state mutable_cb_state = {
3147 .surf = &tex->surface,
3148 .cb = &cb->cb,
3149 .va = tex->buffer.gpu_address,
3150 .num_samples = cb->base.texture->nr_samples,
3151 .dcc_enabled = vi_dcc_enabled(tex, cb->base.u.tex.level),
3152 };
3153 struct ac_cb_surface cb_surf;
3154
3155 ac_set_mutable_cb_surface_fields(&sctx->screen->info, &mutable_cb_state, &cb_surf);
3156
3157 cb_surf.cb_color_info |= tex->cb_color_info;
3158
3159 gfx11_set_context_reg(R_028C60_CB_COLOR0_BASE + i * 0x3C, cb_surf.cb_color_base);
3160 gfx11_set_context_reg(R_028C6C_CB_COLOR0_VIEW + i * 0x3C, cb_surf.cb_color_view);
3161 gfx11_set_context_reg(R_028C70_CB_COLOR0_INFO + i * 0x3C, cb_surf.cb_color_info);
3162 gfx11_set_context_reg(R_028C74_CB_COLOR0_ATTRIB + i * 0x3C, cb_surf.cb_color_attrib);
3163 gfx11_set_context_reg(R_028C78_CB_COLOR0_DCC_CONTROL + i * 0x3C, cb_surf.cb_dcc_control);
3164 gfx11_set_context_reg(R_028C94_CB_COLOR0_DCC_BASE + i * 0x3C, cb_surf.cb_dcc_base);
3165 gfx11_set_context_reg(R_028E40_CB_COLOR0_BASE_EXT + i * 4, cb_surf.cb_color_base >> 32);
3166 gfx11_set_context_reg(R_028EA0_CB_COLOR0_DCC_BASE_EXT + i * 4, cb_surf.cb_dcc_base >> 32);
3167 gfx11_set_context_reg(R_028EC0_CB_COLOR0_ATTRIB2 + i * 4, cb_surf.cb_color_attrib2);
3168 gfx11_set_context_reg(R_028EE0_CB_COLOR0_ATTRIB3 + i * 4, cb_surf.cb_color_attrib3);
3169 }
3170 for (; i < 8; i++)
3171 if (sctx->framebuffer.dirty_cbufs & (1 << i))
3172 gfx11_set_context_reg(R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
3173
3174 /* ZS buffer. */
3175 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
3176 struct si_surface *zb = (struct si_surface *)state->zsbuf;
3177 struct si_texture *tex = (struct si_texture *)zb->base.texture;
3178
3179 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, &tex->buffer, RADEON_USAGE_READWRITE |
3180 (zb->base.texture->nr_samples > 1 ? RADEON_PRIO_DEPTH_BUFFER_MSAA
3181 : RADEON_PRIO_DEPTH_BUFFER));
3182
3183 const unsigned level = zb->base.u.tex.level;
3184
3185 /* Set mutable fields. */
3186 const struct ac_mutable_ds_state mutable_ds_state = {
3187 .ds = &zb->ds,
3188 .format = tex->db_render_format,
3189 .tc_compat_htile_enabled = vi_tc_compat_htile_enabled(tex, level, PIPE_MASK_ZS),
3190 .zrange_precision = tex->depth_clear_value[level] != 0,
3191 };
3192 struct ac_ds_surface ds;
3193
3194 ac_set_mutable_ds_surface_fields(&sctx->screen->info, &mutable_ds_state, &ds);
3195
3196 gfx11_set_context_reg(R_028014_DB_HTILE_DATA_BASE, ds.u.gfx6.db_htile_data_base);
3197 gfx11_set_context_reg(R_02801C_DB_DEPTH_SIZE_XY, ds.db_depth_size);
3198 gfx11_set_context_reg(R_028040_DB_Z_INFO, ds.db_z_info);
3199 gfx11_set_context_reg(R_028044_DB_STENCIL_INFO, ds.db_stencil_info);
3200 gfx11_set_context_reg(R_028048_DB_Z_READ_BASE, ds.db_depth_base);
3201 gfx11_set_context_reg(R_02804C_DB_STENCIL_READ_BASE, ds.db_stencil_base);
3202 gfx11_set_context_reg(R_028050_DB_Z_WRITE_BASE, ds.db_depth_base);
3203 gfx11_set_context_reg(R_028054_DB_STENCIL_WRITE_BASE, ds.db_stencil_base);
3204 gfx11_set_context_reg(R_028068_DB_Z_READ_BASE_HI, ds.db_depth_base >> 32);
3205 gfx11_set_context_reg(R_02806C_DB_STENCIL_READ_BASE_HI, ds.db_stencil_base >> 32);
3206 gfx11_set_context_reg(R_028070_DB_Z_WRITE_BASE_HI, ds.db_depth_base >> 32);
3207 gfx11_set_context_reg(R_028074_DB_STENCIL_WRITE_BASE_HI, ds.db_stencil_base >> 32);
3208 gfx11_set_context_reg(R_028078_DB_HTILE_DATA_BASE_HI, ds.u.gfx6.db_htile_data_base >> 32);
3209 gfx11_set_context_reg(R_028028_DB_STENCIL_CLEAR, tex->stencil_clear_value[level]);
3210 gfx11_set_context_reg(R_02802C_DB_DEPTH_CLEAR, fui(tex->depth_clear_value[level]));
3211 gfx11_set_context_reg(R_028008_DB_DEPTH_VIEW, ds.db_depth_view);
3212 gfx11_set_context_reg(R_028ABC_DB_HTILE_SURFACE, ds.u.gfx6.db_htile_surface);
3213 } else if (sctx->framebuffer.dirty_zsbuf) {
3214 /* Gfx11+: DB_Z_INFO.NUM_SAMPLES should match the framebuffer samples if no Z/S is bound.
3215 * It determines the sample count for VRS, primitive-ordered pixel shading, and occlusion
3216 * queries.
3217 */
3218 gfx11_set_context_reg(R_028040_DB_Z_INFO,
3219 S_028040_FORMAT(V_028040_Z_INVALID) |
3220 S_028040_NUM_SAMPLES(sctx->framebuffer.log_samples));
3221 gfx11_set_context_reg(R_028044_DB_STENCIL_INFO, S_028044_FORMAT(V_028044_STENCIL_INVALID));
3222 }
3223
3224 /* Framebuffer dimensions. */
3225 /* PA_SC_WINDOW_SCISSOR_TL is set to 0,0 in gfx*_init_gfx_preamble_state */
3226 gfx11_set_context_reg(R_028208_PA_SC_WINDOW_SCISSOR_BR,
3227 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
3228 gfx11_end_packed_context_regs();
3229
3230 if (sctx->screen->dpbb_allowed &&
3231 sctx->screen->pbb_context_states_per_bin > 1)
3232 radeon_event_write(V_028A90_BREAK_BATCH);
3233
3234 radeon_end();
3235
3236 si_update_display_dcc_dirty(sctx);
3237
3238 sctx->framebuffer.dirty_cbufs = 0;
3239 sctx->framebuffer.dirty_zsbuf = false;
3240 }
3241
gfx12_emit_framebuffer_state(struct si_context * sctx,unsigned index)3242 static void gfx12_emit_framebuffer_state(struct si_context *sctx, unsigned index)
3243 {
3244 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
3245 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
3246 unsigned i, nr_cbufs = state->nr_cbufs;
3247 struct si_texture *tex = NULL;
3248 struct si_surface *cb = NULL;
3249 bool is_msaa_resolve = state->nr_cbufs == 2 &&
3250 state->cbufs[0] && state->cbufs[0]->texture->nr_samples > 1 &&
3251 state->cbufs[1] && state->cbufs[1]->texture->nr_samples <= 1;
3252
3253 /* CB can't do MSAA resolve. */
3254 assert(!is_msaa_resolve);
3255
3256 radeon_begin(cs);
3257 gfx12_begin_context_regs();
3258
3259 /* Colorbuffers. */
3260 for (i = 0; i < nr_cbufs; i++) {
3261 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
3262 continue;
3263
3264 /* RB+ depth-only rendering. See the comment where we set rbplus_depth_only_opt for more
3265 * information.
3266 */
3267 if (i == 0 &&
3268 sctx->screen->info.rbplus_allowed &&
3269 !sctx->queued.named.blend->cb_target_mask) {
3270 gfx12_set_context_reg(R_028EC0_CB_COLOR0_INFO + i * 4,
3271 S_028EC0_FORMAT(V_028C70_COLOR_32) |
3272 S_028EC0_NUMBER_TYPE(V_028C70_NUMBER_FLOAT));
3273 continue;
3274 }
3275
3276 cb = (struct si_surface *)state->cbufs[i];
3277 if (!cb) {
3278 gfx12_set_context_reg(R_028EC0_CB_COLOR0_INFO + i * 4,
3279 S_028EC0_FORMAT(V_028C70_COLOR_INVALID));
3280 continue;
3281 }
3282
3283 tex = (struct si_texture *)cb->base.texture;
3284 radeon_add_to_buffer_list(
3285 sctx, &sctx->gfx_cs, &tex->buffer, RADEON_USAGE_READWRITE | RADEON_USAGE_CB_NEEDS_IMPLICIT_SYNC |
3286 (tex->buffer.b.b.nr_samples > 1 ? RADEON_PRIO_COLOR_BUFFER_MSAA : RADEON_PRIO_COLOR_BUFFER));
3287
3288 /* Compute mutable surface parameters. */
3289 const struct ac_mutable_cb_state mutable_cb_state = {
3290 .surf = &tex->surface,
3291 .cb = &cb->cb,
3292 .va = tex->buffer.gpu_address,
3293 };
3294 struct ac_cb_surface cb_surf;
3295
3296 ac_set_mutable_cb_surface_fields(&sctx->screen->info, &mutable_cb_state, &cb_surf);
3297
3298 gfx12_set_context_reg(R_028C60_CB_COLOR0_BASE + i * 0x24, cb_surf.cb_color_base);
3299 gfx12_set_context_reg(R_028C64_CB_COLOR0_VIEW + i * 0x24, cb_surf.cb_color_view);
3300 gfx12_set_context_reg(R_028C68_CB_COLOR0_VIEW2 + i * 0x24, cb_surf.cb_color_view2);
3301 gfx12_set_context_reg(R_028C6C_CB_COLOR0_ATTRIB + i * 0x24, cb_surf.cb_color_attrib);
3302 gfx12_set_context_reg(R_028C70_CB_COLOR0_FDCC_CONTROL + i * 0x24, cb_surf.cb_dcc_control);
3303 gfx12_set_context_reg(R_028C78_CB_COLOR0_ATTRIB2 + i * 0x24, cb_surf.cb_color_attrib2);
3304 gfx12_set_context_reg(R_028C7C_CB_COLOR0_ATTRIB3 + i * 0x24, cb_surf.cb_color_attrib3);
3305 gfx12_set_context_reg(R_028E40_CB_COLOR0_BASE_EXT + i * 4, cb_surf.cb_color_base >> 32);
3306 gfx12_set_context_reg(R_028EC0_CB_COLOR0_INFO + i * 4, cb_surf.cb_color_info);
3307 }
3308 /* Set unbound colorbuffers. */
3309 for (; i < 8; i++)
3310 if (sctx->framebuffer.dirty_cbufs & (1 << i))
3311 gfx12_set_context_reg(R_028EC0_CB_COLOR0_INFO + i * 4, 0);
3312
3313 /* ZS buffer. */
3314 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
3315 struct si_surface *zb = (struct si_surface *)state->zsbuf;
3316 struct si_texture *tex = (struct si_texture *)zb->base.texture;
3317
3318 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, &tex->buffer,
3319 RADEON_USAGE_READWRITE | RADEON_USAGE_DB_NEEDS_IMPLICIT_SYNC |
3320 (zb->base.texture->nr_samples > 1 ? RADEON_PRIO_DEPTH_BUFFER_MSAA
3321 : RADEON_PRIO_DEPTH_BUFFER));
3322 gfx12_set_context_reg(R_028004_DB_DEPTH_VIEW, zb->ds.db_depth_view);
3323 gfx12_set_context_reg(R_028008_DB_DEPTH_VIEW1, zb->ds.u.gfx12.db_depth_view1);
3324 gfx12_set_context_reg(R_028014_DB_DEPTH_SIZE_XY, zb->ds.db_depth_size);
3325 gfx12_set_context_reg(R_028018_DB_Z_INFO, zb->ds.db_z_info);
3326 gfx12_set_context_reg(R_02801C_DB_STENCIL_INFO, zb->ds.db_stencil_info);
3327 gfx12_set_context_reg(R_028020_DB_Z_READ_BASE, zb->ds.db_depth_base);
3328 gfx12_set_context_reg(R_028024_DB_Z_READ_BASE_HI, zb->ds.db_depth_base >> 32);
3329 gfx12_set_context_reg(R_028028_DB_Z_WRITE_BASE, zb->ds.db_depth_base);
3330 gfx12_set_context_reg(R_02802C_DB_Z_WRITE_BASE_HI, zb->ds.db_depth_base >> 32);
3331 gfx12_set_context_reg(R_028030_DB_STENCIL_READ_BASE, zb->ds.db_stencil_base);
3332 gfx12_set_context_reg(R_028034_DB_STENCIL_READ_BASE_HI, zb->ds.db_stencil_base >> 32);
3333 gfx12_set_context_reg(R_028038_DB_STENCIL_WRITE_BASE, zb->ds.db_stencil_base);
3334 gfx12_set_context_reg(R_02803C_DB_STENCIL_WRITE_BASE_HI, zb->ds.db_stencil_base >> 32);
3335 gfx12_set_context_reg(R_028B94_PA_SC_HIZ_INFO, zb->ds.u.gfx12.hiz_info);
3336 gfx12_set_context_reg(R_028B98_PA_SC_HIS_INFO, zb->ds.u.gfx12.his_info);
3337
3338 if (zb->ds.u.gfx12.hiz_info) {
3339 gfx12_set_context_reg(R_028B9C_PA_SC_HIZ_BASE, zb->ds.u.gfx12.hiz_base);
3340 gfx12_set_context_reg(R_028BA0_PA_SC_HIZ_BASE_EXT, zb->ds.u.gfx12.hiz_base >> 32);
3341 gfx12_set_context_reg(R_028BA4_PA_SC_HIZ_SIZE_XY, zb->ds.u.gfx12.hiz_size_xy);
3342 }
3343 if (zb->ds.u.gfx12.his_info) {
3344 gfx12_set_context_reg(R_028BA8_PA_SC_HIS_BASE, zb->ds.u.gfx12.his_base);
3345 gfx12_set_context_reg(R_028BAC_PA_SC_HIS_BASE_EXT, zb->ds.u.gfx12.his_base >> 32);
3346 gfx12_set_context_reg(R_028BB0_PA_SC_HIS_SIZE_XY, zb->ds.u.gfx12.his_size_xy);
3347 }
3348 } else if (sctx->framebuffer.dirty_zsbuf) {
3349 gfx12_set_context_reg(R_028018_DB_Z_INFO,
3350 S_028040_FORMAT(V_028040_Z_INVALID) |
3351 S_028040_NUM_SAMPLES(sctx->framebuffer.log_samples));
3352 gfx12_set_context_reg(R_02801C_DB_STENCIL_INFO,
3353 S_028044_FORMAT(V_028044_STENCIL_INVALID)|
3354 S_028044_TILE_STENCIL_DISABLE(1));
3355 gfx12_set_context_reg(R_028B94_PA_SC_HIZ_INFO, S_028B94_SURFACE_ENABLE(0));
3356 gfx12_set_context_reg(R_028B98_PA_SC_HIS_INFO, S_028B98_SURFACE_ENABLE(0));
3357 }
3358
3359 /* Framebuffer dimensions. */
3360 /* PA_SC_WINDOW_SCISSOR_TL is set in gfx12_init_gfx_preamble_state */
3361 gfx12_set_context_reg(R_028208_PA_SC_WINDOW_SCISSOR_BR,
3362 S_028208_BR_X(state->width - 1) | /* inclusive */
3363 S_028208_BR_Y(state->height - 1)); /* inclusive */
3364 gfx12_end_context_regs();
3365
3366 if (sctx->screen->dpbb_allowed &&
3367 sctx->screen->pbb_context_states_per_bin > 1)
3368 radeon_event_write(V_028A90_BREAK_BATCH);
3369
3370 radeon_end();
3371
3372 sctx->framebuffer.dirty_cbufs = 0;
3373 sctx->framebuffer.dirty_zsbuf = false;
3374 }
3375
si_out_of_order_rasterization(struct si_context * sctx)3376 static bool si_out_of_order_rasterization(struct si_context *sctx)
3377 {
3378 struct si_state_blend *blend = sctx->queued.named.blend;
3379 struct si_state_dsa *dsa = sctx->queued.named.dsa;
3380
3381 if (!sctx->screen->info.has_out_of_order_rast)
3382 return false;
3383
3384 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit;
3385
3386 colormask &= blend->cb_target_enabled_4bit;
3387
3388 /* Conservative: No logic op. */
3389 if (colormask && blend->logicop_enable)
3390 return false;
3391
3392 struct si_dsa_order_invariance dsa_order_invariant = {.zs = true,
3393 .pass_set = true};
3394
3395 if (sctx->framebuffer.state.zsbuf) {
3396 struct si_texture *zstex = (struct si_texture *)sctx->framebuffer.state.zsbuf->texture;
3397 bool has_stencil = zstex->surface.has_stencil;
3398 dsa_order_invariant = dsa->order_invariance[has_stencil];
3399 if (!dsa_order_invariant.zs)
3400 return false;
3401
3402 /* The set of PS invocations is always order invariant,
3403 * except when early Z/S tests are requested. */
3404 if (sctx->shader.ps.cso && sctx->shader.ps.cso->info.base.writes_memory &&
3405 sctx->shader.ps.cso->info.base.fs.early_fragment_tests &&
3406 !dsa_order_invariant.pass_set)
3407 return false;
3408
3409 if (sctx->occlusion_query_mode == SI_OCCLUSION_QUERY_MODE_PRECISE_INTEGER &&
3410 !dsa_order_invariant.pass_set)
3411 return false;
3412 }
3413
3414 if (!colormask)
3415 return true;
3416
3417 unsigned blendmask = colormask & blend->blend_enable_4bit;
3418
3419 if (blendmask) {
3420 /* Only commutative blending. */
3421 if (blendmask & ~blend->commutative_4bit)
3422 return false;
3423
3424 if (!dsa_order_invariant.pass_set)
3425 return false;
3426 }
3427
3428 if (colormask & ~blendmask)
3429 return false;
3430
3431 return true;
3432 }
3433
si_emit_msaa_config(struct si_context * sctx,unsigned index)3434 static void si_emit_msaa_config(struct si_context *sctx, unsigned index)
3435 {
3436 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
3437 unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes;
3438 /* 33% faster rendering to linear color buffers */
3439 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
3440 bool out_of_order_rast = si_out_of_order_rasterization(sctx);
3441 unsigned sc_mode_cntl_1 =
3442 S_028A4C_WALK_SIZE(dst_is_linear) | S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
3443 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
3444 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
3445 S_028A4C_OUT_OF_ORDER_WATER_MARK(sctx->gfx_level >= GFX12 ? 0 : 0x7) |
3446 /* This should also be 0 when the VRS image is enabled. */
3447 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(!sctx->framebuffer.has_hiz_his) |
3448 /* always 1: */
3449 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3450 S_028A4C_TILE_WALK_ORDER_ENABLE(1) | S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3451 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) | S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3452 unsigned db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3453 S_028804_INCOHERENT_EQAA_READS(sctx->gfx_level < GFX12) |
3454 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
3455 unsigned coverage_samples, z_samples;
3456 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3457
3458 /* S: Coverage samples (up to 16x):
3459 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
3460 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
3461 *
3462 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
3463 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
3464 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
3465 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
3466 * # from the closest defined sample if Z is uncompressed (same quality as the number of
3467 * # Z samples).
3468 *
3469 * F: Color samples (up to 8x, must be <= coverage samples):
3470 * - CB color samples (CB_COLORi_ATTRIB.NUM_FRAGMENTS)
3471 * - PS iter samples (DB_EQAA.PS_ITER_SAMPLES)
3472 *
3473 * Can be anything between coverage and color samples:
3474 * - SampleMaskIn samples (PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES)
3475 * - SampleMaskOut samples (DB_EQAA.MASK_EXPORT_NUM_SAMPLES)
3476 * - Alpha-to-coverage samples (DB_EQAA.ALPHA_TO_MASK_NUM_SAMPLES)
3477 * - Occlusion query samples (DB_COUNT_CONTROL.SAMPLE_RATE)
3478 * # All are currently set the same as coverage samples.
3479 *
3480 * If color samples < coverage samples, FMASK has a higher bpp to store an "unknown"
3481 * flag for undefined color samples. A shader-based resolve must handle unknowns
3482 * or mask them out with AND. Unknowns can also be guessed from neighbors via
3483 * an edge-detect shader-based resolve, which is required to make "color samples = 1"
3484 * useful. The CB resolve always drops unknowns.
3485 *
3486 * Sensible AA configurations:
3487 * EQAA 16s 8z 8f - might look the same as 16x MSAA if Z is compressed
3488 * EQAA 16s 8z 4f - might look the same as 16x MSAA if Z is compressed
3489 * EQAA 16s 4z 4f - might look the same as 16x MSAA if Z is compressed
3490 * EQAA 8s 8z 8f = 8x MSAA
3491 * EQAA 8s 8z 4f - might look the same as 8x MSAA
3492 * EQAA 8s 8z 2f - might look the same as 8x MSAA with low-density geometry
3493 * EQAA 8s 4z 4f - might look the same as 8x MSAA if Z is compressed
3494 * EQAA 8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
3495 * EQAA 4s 4z 4f = 4x MSAA
3496 * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry
3497 * EQAA 2s 2z 2f = 2x MSAA
3498 */
3499 coverage_samples = si_get_num_coverage_samples(sctx);
3500
3501 /* DCC_DECOMPRESS and ELIMINATE_FAST_CLEAR require MSAA_NUM_SAMPLES=0. */
3502 if (sctx->gfx_level >= GFX11 && sctx->gfx11_force_msaa_num_samples_zero)
3503 coverage_samples = 1;
3504
3505 /* The DX10 diamond test is not required by GL and decreases line rasterization
3506 * performance, so don't use it.
3507 */
3508 unsigned sc_line_cntl = 0;
3509 unsigned sc_aa_config = 0;
3510
3511 if (coverage_samples > 1 && (rs->multisample_enable ||
3512 sctx->smoothing_enabled)) {
3513 unsigned log_samples = util_logbase2(coverage_samples);
3514
3515 sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1) |
3516 S_028BDC_PERPENDICULAR_ENDCAP_ENA(rs->perpendicular_end_caps) |
3517 S_028BDC_EXTRA_DX_DY_PRECISION(rs->perpendicular_end_caps &&
3518 (sctx->family == CHIP_VEGA20 ||
3519 sctx->gfx_level >= GFX10));
3520 sc_aa_config = S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
3521 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples);
3522
3523 if (sctx->gfx_level < GFX12) {
3524 sc_aa_config |= S_028BE0_MAX_SAMPLE_DIST(si_msaa_max_distance[log_samples]) |
3525 S_028BE0_COVERED_CENTROID_IS_CENTER(sctx->gfx_level >= GFX10_3);
3526 }
3527 }
3528
3529 if (sctx->framebuffer.nr_samples > 1 ||
3530 sctx->smoothing_enabled) {
3531 if (sctx->framebuffer.state.zsbuf) {
3532 z_samples = sctx->framebuffer.state.zsbuf->texture->nr_samples;
3533 z_samples = MAX2(1, z_samples);
3534 } else {
3535 z_samples = coverage_samples;
3536 }
3537 unsigned log_samples = util_logbase2(coverage_samples);
3538 unsigned log_z_samples = util_logbase2(z_samples);
3539 unsigned ps_iter_samples = si_get_ps_iter_samples(sctx);
3540 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
3541 if (sctx->framebuffer.nr_samples > 1) {
3542 if (sctx->gfx_level >= GFX12) {
3543 sc_aa_config |= S_028BE0_PS_ITER_SAMPLES(log_ps_iter_samples);
3544 db_eqaa |= S_028078_MASK_EXPORT_NUM_SAMPLES(log_samples) |
3545 S_028078_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
3546 } else {
3547 db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
3548 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
3549 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
3550 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
3551 }
3552 sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
3553 } else if (sctx->smoothing_enabled) {
3554 db_eqaa |= S_028804_OVERRASTERIZATION_AMOUNT(log_samples);
3555 }
3556 }
3557
3558 if (sctx->gfx_level >= GFX12) {
3559 radeon_begin(cs);
3560 gfx12_begin_context_regs();
3561 gfx12_opt_set_context_reg(R_028BDC_PA_SC_LINE_CNTL, SI_TRACKED_PA_SC_LINE_CNTL,
3562 sc_line_cntl);
3563 gfx12_opt_set_context_reg(R_028BE0_PA_SC_AA_CONFIG, SI_TRACKED_PA_SC_AA_CONFIG,
3564 sc_aa_config);
3565 gfx12_opt_set_context_reg(R_028078_DB_EQAA, SI_TRACKED_DB_EQAA, db_eqaa);
3566 gfx12_opt_set_context_reg(R_028A4C_PA_SC_MODE_CNTL_1, SI_TRACKED_PA_SC_MODE_CNTL_1,
3567 sc_mode_cntl_1);
3568 gfx12_end_context_regs();
3569 radeon_end(); /* don't track context rolls on GFX12 */
3570 } else if (sctx->screen->info.has_set_context_pairs_packed) {
3571 radeon_begin(cs);
3572 gfx11_begin_packed_context_regs();
3573 gfx11_opt_set_context_reg(R_028BDC_PA_SC_LINE_CNTL, SI_TRACKED_PA_SC_LINE_CNTL,
3574 sc_line_cntl);
3575 gfx11_opt_set_context_reg(R_028BE0_PA_SC_AA_CONFIG, SI_TRACKED_PA_SC_AA_CONFIG,
3576 sc_aa_config);
3577 gfx11_opt_set_context_reg(R_028804_DB_EQAA, SI_TRACKED_DB_EQAA, db_eqaa);
3578 gfx11_opt_set_context_reg(R_028A4C_PA_SC_MODE_CNTL_1, SI_TRACKED_PA_SC_MODE_CNTL_1,
3579 sc_mode_cntl_1);
3580 gfx11_end_packed_context_regs();
3581 radeon_end(); /* don't track context rolls on GFX11 */
3582 } else {
3583 radeon_begin(cs);
3584 radeon_opt_set_context_reg2(R_028BDC_PA_SC_LINE_CNTL, SI_TRACKED_PA_SC_LINE_CNTL,
3585 sc_line_cntl, sc_aa_config);
3586 radeon_opt_set_context_reg(R_028804_DB_EQAA, SI_TRACKED_DB_EQAA, db_eqaa);
3587 radeon_opt_set_context_reg(R_028A4C_PA_SC_MODE_CNTL_1, SI_TRACKED_PA_SC_MODE_CNTL_1,
3588 sc_mode_cntl_1);
3589 radeon_end_update_context_roll();
3590 }
3591 }
3592
si_update_ps_iter_samples(struct si_context * sctx)3593 void si_update_ps_iter_samples(struct si_context *sctx)
3594 {
3595 if (sctx->framebuffer.nr_samples > 1)
3596 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3597 if (sctx->screen->dpbb_allowed)
3598 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3599 }
3600
si_set_min_samples(struct pipe_context * ctx,unsigned min_samples)3601 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
3602 {
3603 struct si_context *sctx = (struct si_context *)ctx;
3604
3605 /* The hardware can only do sample shading with 2^n samples. */
3606 min_samples = util_next_power_of_two(min_samples);
3607
3608 if (sctx->ps_iter_samples == min_samples)
3609 return;
3610
3611 sctx->ps_iter_samples = min_samples;
3612
3613 si_ps_key_update_sample_shading(sctx);
3614 si_ps_key_update_framebuffer_rasterizer_sample_shading(sctx);
3615 sctx->do_update_shaders = true;
3616
3617 si_update_ps_iter_samples(sctx);
3618 }
3619
3620 /*
3621 * Samplers
3622 */
3623
3624 /**
3625 * Build the sampler view descriptor for a buffer texture.
3626 * @param state 256-bit descriptor; only the high 128 bits are filled in
3627 */
si_make_buffer_descriptor(struct si_screen * screen,struct si_resource * buf,enum pipe_format format,unsigned offset,unsigned num_elements,uint32_t * state)3628 void si_make_buffer_descriptor(struct si_screen *screen, struct si_resource *buf,
3629 enum pipe_format format, unsigned offset, unsigned num_elements,
3630 uint32_t *state)
3631 {
3632 const struct util_format_description *desc;
3633 unsigned stride;
3634 unsigned num_records;
3635
3636 desc = util_format_description(format);
3637 stride = desc->block.bits / 8;
3638
3639 num_records = num_elements;
3640 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3641
3642 /* The NUM_RECORDS field has a different meaning depending on the chip,
3643 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3644 *
3645 * GFX6-7,10:
3646 * - If STRIDE == 0, it's in byte units.
3647 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3648 *
3649 * GFX8:
3650 * - For SMEM and STRIDE == 0, it's in byte units.
3651 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3652 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3653 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3654 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3655 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3656 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3657 * That way the same descriptor can be used by both SMEM and VMEM.
3658 *
3659 * GFX9:
3660 * - For SMEM and STRIDE == 0, it's in byte units.
3661 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3662 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3663 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3664 */
3665 if (screen->info.gfx_level == GFX8)
3666 num_records *= stride;
3667
3668 const struct ac_buffer_state buffer_state = {
3669 .size = num_records,
3670 .format = format,
3671 .swizzle =
3672 {
3673 desc->swizzle[0],
3674 desc->swizzle[1],
3675 desc->swizzle[2],
3676 desc->swizzle[3],
3677 },
3678 .stride = stride,
3679 .gfx10_oob_select = V_008F0C_OOB_SELECT_STRUCTURED_WITH_OFFSET,
3680 };
3681
3682 ac_build_buffer_descriptor(screen->info.gfx_level, &buffer_state, &state[4]);
3683 }
3684
3685 /**
3686 * Translate the parameters to an image descriptor for CDNA image emulation.
3687 * In this function, we choose our own image descriptor format because we emulate image opcodes
3688 * using buffer opcodes.
3689 */
cdna_emu_make_image_descriptor(struct si_screen * screen,struct si_texture * tex,bool sampler,enum pipe_texture_target target,enum pipe_format pipe_format,const unsigned char state_swizzle[4],unsigned first_level,unsigned last_level,unsigned first_layer,unsigned last_layer,unsigned width,unsigned height,unsigned depth,uint32_t * state,uint32_t * fmask_state)3690 static void cdna_emu_make_image_descriptor(struct si_screen *screen, struct si_texture *tex,
3691 bool sampler, enum pipe_texture_target target,
3692 enum pipe_format pipe_format,
3693 const unsigned char state_swizzle[4], unsigned first_level,
3694 unsigned last_level, unsigned first_layer,
3695 unsigned last_layer, unsigned width, unsigned height,
3696 unsigned depth, uint32_t *state, uint32_t *fmask_state)
3697 {
3698 const struct util_format_description *desc = util_format_description(pipe_format);
3699
3700 /* We don't need support these. We only need enough to support VAAPI and OpenMAX. */
3701 if (target == PIPE_TEXTURE_CUBE ||
3702 target == PIPE_TEXTURE_CUBE_ARRAY ||
3703 tex->buffer.b.b.last_level > 0 ||
3704 tex->buffer.b.b.nr_samples >= 2 ||
3705 desc->colorspace != UTIL_FORMAT_COLORSPACE_RGB ||
3706 desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED ||
3707 util_format_is_compressed(pipe_format)) {
3708 assert(!"unexpected texture type");
3709 memset(state, 0, 8 * 4);
3710 return;
3711 }
3712
3713 /* Adjust the image parameters according to the texture type. */
3714 switch (target) {
3715 case PIPE_TEXTURE_1D:
3716 height = 1;
3717 FALLTHROUGH;
3718 case PIPE_TEXTURE_2D:
3719 case PIPE_TEXTURE_RECT:
3720 depth = 1;
3721 break;
3722
3723 case PIPE_TEXTURE_1D_ARRAY:
3724 height = 1;
3725 FALLTHROUGH;
3726 case PIPE_TEXTURE_2D_ARRAY:
3727 first_layer = MIN2(first_layer, tex->buffer.b.b.array_size - 1);
3728 last_layer = MIN2(last_layer, tex->buffer.b.b.array_size - 1);
3729 last_layer = MAX2(last_layer, first_layer);
3730 depth = last_layer - first_layer + 1;
3731 break;
3732
3733 case PIPE_TEXTURE_3D:
3734 first_layer = 0;
3735 break;
3736
3737 default:
3738 unreachable("invalid texture target");
3739 }
3740
3741 unsigned stride = desc->block.bits / 8;
3742 uint64_t num_records = tex->surface.surf_size / stride;
3743 assert(num_records <= UINT32_MAX);
3744
3745 /* Prepare the format fields. */
3746 unsigned char swizzle[4];
3747 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3748
3749 /* Buffer descriptor */
3750 const struct ac_buffer_state buffer_state = {
3751 .size = num_records,
3752 .format = pipe_format,
3753 .swizzle =
3754 {
3755 desc->swizzle[0],
3756 desc->swizzle[1],
3757 desc->swizzle[2],
3758 desc->swizzle[3],
3759 },
3760 .stride = stride,
3761 .gfx10_oob_select = V_008F0C_OOB_SELECT_STRUCTURED_WITH_OFFSET,
3762 };
3763
3764 ac_build_buffer_descriptor(screen->info.gfx_level, &buffer_state, &state[0]);
3765
3766 /* Additional fields used by image opcode emulation. */
3767 state[4] = width | (height << 16);
3768 state[5] = depth | (first_layer << 16);
3769 state[6] = tex->surface.u.gfx9.surf_pitch;
3770 state[7] = (uint32_t)tex->surface.u.gfx9.surf_pitch * tex->surface.u.gfx9.surf_height;
3771 }
3772
3773 /**
3774 * Build the sampler view descriptor for a texture.
3775 */
gfx10_make_texture_descriptor(struct si_screen * screen,struct si_texture * tex,bool sampler,enum pipe_texture_target target,enum pipe_format pipe_format,const unsigned char state_swizzle[4],unsigned first_level,unsigned last_level,unsigned first_layer,unsigned last_layer,unsigned width,unsigned height,unsigned depth,bool get_bo_metadata,uint32_t * state,uint32_t * fmask_state)3776 static void gfx10_make_texture_descriptor(
3777 struct si_screen *screen, struct si_texture *tex, bool sampler, enum pipe_texture_target target,
3778 enum pipe_format pipe_format, const unsigned char state_swizzle[4], unsigned first_level,
3779 unsigned last_level, unsigned first_layer, unsigned last_layer, unsigned width, unsigned height,
3780 unsigned depth, bool get_bo_metadata, uint32_t *state, uint32_t *fmask_state)
3781 {
3782 if (!screen->info.has_image_opcodes && !get_bo_metadata) {
3783 cdna_emu_make_image_descriptor(screen, tex, sampler, target, pipe_format, state_swizzle,
3784 first_level, last_level, first_layer, last_layer, width,
3785 height, depth, state, fmask_state);
3786 return;
3787 }
3788
3789 struct pipe_resource *res = &tex->buffer.b.b;
3790 const struct util_format_description *desc;
3791 unsigned char swizzle[4];
3792 unsigned type;
3793
3794 desc = util_format_description(pipe_format);
3795
3796 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3797 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3798 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3799 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3800
3801 switch (pipe_format) {
3802 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3803 case PIPE_FORMAT_X32_S8X24_UINT:
3804 case PIPE_FORMAT_X8Z24_UNORM:
3805 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3806 break;
3807 case PIPE_FORMAT_X24S8_UINT:
3808 /*
3809 * X24S8 is implemented as an 8_8_8_8 data format, to
3810 * fix texture gathers. This affects at least
3811 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
3812 */
3813 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3814 break;
3815 default:
3816 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3817 }
3818 } else {
3819 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3820 }
3821
3822 if (!sampler && (res->target == PIPE_TEXTURE_CUBE || res->target == PIPE_TEXTURE_CUBE_ARRAY)) {
3823 /* For the purpose of shader images, treat cube maps as 2D
3824 * arrays.
3825 */
3826 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3827 } else {
3828 type = si_tex_dim(screen, tex, target, res->nr_samples);
3829 }
3830
3831 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3832 height = 1;
3833 depth = res->array_size;
3834 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY || type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3835 if (sampler || res->target != PIPE_TEXTURE_3D)
3836 depth = res->array_size;
3837 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3838 depth = res->array_size / 6;
3839
3840 const struct ac_texture_state tex_state = {
3841 .surf = &tex->surface,
3842 .format = pipe_format,
3843 .img_format = res->format,
3844 .width = width,
3845 .height = height,
3846 .depth = (type == V_008F1C_SQ_RSRC_IMG_3D && sampler) ? depth - 1 : last_layer,
3847 .type = type,
3848 .swizzle =
3849 {
3850 swizzle[0],
3851 swizzle[1],
3852 swizzle[2],
3853 swizzle[3],
3854 },
3855 .num_samples = res->nr_samples,
3856 .num_storage_samples = res->nr_storage_samples,
3857 .first_level = first_level,
3858 .last_level = last_level,
3859 .num_levels = res->last_level + 1,
3860 .first_layer = first_layer,
3861 .last_layer = last_layer,
3862 .gfx10 = {
3863 .uav3d = !!(type == V_008F1C_SQ_RSRC_IMG_3D && !sampler),
3864 .upgraded_depth = tex->upgraded_depth,
3865 },
3866 .dcc_enabled = vi_dcc_enabled(tex, first_level),
3867 };
3868
3869 ac_build_texture_descriptor(&screen->info, &tex_state, &state[0]);
3870
3871 /* Initialize the sampler view for FMASK. */
3872 if (tex->surface.fmask_offset) {
3873 const struct ac_fmask_state ac_state = {
3874 .surf = &tex->surface,
3875 .va = tex->buffer.gpu_address,
3876 .width = width,
3877 .height = height,
3878 .depth = depth,
3879 .type = si_tex_dim(screen, tex, target, 0),
3880 .first_layer = first_layer,
3881 .last_layer = last_layer,
3882 .num_samples = res->nr_samples,
3883 .num_storage_samples = res->nr_storage_samples,
3884 };
3885
3886 ac_build_fmask_descriptor(screen->info.gfx_level, &ac_state, &fmask_state[0]);
3887 }
3888 }
3889
3890 /**
3891 * Build the sampler view descriptor for a texture (SI-GFX9).
3892 */
si_make_texture_descriptor(struct si_screen * screen,struct si_texture * tex,bool sampler,enum pipe_texture_target target,enum pipe_format pipe_format,const unsigned char state_swizzle[4],unsigned first_level,unsigned last_level,unsigned first_layer,unsigned last_layer,unsigned width,unsigned height,unsigned depth,bool get_bo_metadata,uint32_t * state,uint32_t * fmask_state)3893 static void si_make_texture_descriptor(struct si_screen *screen, struct si_texture *tex,
3894 bool sampler, enum pipe_texture_target target,
3895 enum pipe_format pipe_format,
3896 const unsigned char state_swizzle[4], unsigned first_level,
3897 unsigned last_level, unsigned first_layer,
3898 unsigned last_layer, unsigned width, unsigned height,
3899 unsigned depth, bool get_bo_metadata,
3900 uint32_t *state, uint32_t *fmask_state)
3901 {
3902 if (!screen->info.has_image_opcodes && !get_bo_metadata) {
3903 cdna_emu_make_image_descriptor(screen, tex, sampler, target, pipe_format, state_swizzle,
3904 first_level, last_level, first_layer, last_layer, width,
3905 height, depth, state, fmask_state);
3906 return;
3907 }
3908
3909 struct pipe_resource *res = &tex->buffer.b.b;
3910 const struct util_format_description *desc;
3911 unsigned char swizzle[4];
3912 unsigned type, num_samples;
3913
3914 desc = util_format_description(pipe_format);
3915
3916 num_samples = desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS ? MAX2(1, res->nr_samples)
3917 : MAX2(1, res->nr_storage_samples);
3918
3919 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3920 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3921 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3922 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3923
3924 switch (pipe_format) {
3925 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3926 case PIPE_FORMAT_X32_S8X24_UINT:
3927 case PIPE_FORMAT_X8Z24_UNORM:
3928 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3929 break;
3930 case PIPE_FORMAT_X24S8_UINT:
3931 /*
3932 * X24S8 is implemented as an 8_8_8_8 data format, to
3933 * fix texture gathers. This affects at least
3934 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
3935 */
3936 if (screen->info.gfx_level <= GFX8)
3937 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3938 else
3939 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3940 break;
3941 default:
3942 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3943 }
3944 } else {
3945 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3946 }
3947
3948 if (!sampler && (res->target == PIPE_TEXTURE_CUBE || res->target == PIPE_TEXTURE_CUBE_ARRAY ||
3949 (screen->info.gfx_level <= GFX8 && res->target == PIPE_TEXTURE_3D))) {
3950 /* For the purpose of shader images, treat cube maps and 3D
3951 * textures as 2D arrays. For 3D textures, the address
3952 * calculations for mipmaps are different, so we rely on the
3953 * caller to effectively disable mipmaps.
3954 */
3955 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3956
3957 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
3958 } else {
3959 type = si_tex_dim(screen, tex, target, num_samples);
3960 }
3961
3962 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3963 height = 1;
3964 depth = res->array_size;
3965 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY || type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3966 if (sampler || res->target != PIPE_TEXTURE_3D)
3967 depth = res->array_size;
3968 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3969 depth = res->array_size / 6;
3970
3971 const struct ac_texture_state tex_state = {
3972 .surf = &tex->surface,
3973 .format = pipe_format,
3974 .img_format = res->format,
3975 .width = width,
3976 .height = height,
3977 .depth = depth,
3978 .type = type,
3979 .swizzle =
3980 {
3981 swizzle[0],
3982 swizzle[1],
3983 swizzle[2],
3984 swizzle[3],
3985 },
3986 .num_samples = res->nr_samples,
3987 .num_storage_samples = res->nr_storage_samples,
3988 .first_level = first_level,
3989 .last_level = last_level,
3990 .num_levels = res->last_level + 1,
3991 .first_layer = first_layer,
3992 .last_layer = last_layer,
3993 .dcc_enabled = vi_dcc_enabled(tex, first_level),
3994 .tc_compat_htile_enabled = true,
3995 };
3996
3997 ac_build_texture_descriptor(&screen->info, &tex_state, &state[0]);
3998
3999 /* Initialize the sampler view for FMASK. */
4000 if (tex->surface.fmask_offset) {
4001 const struct ac_fmask_state ac_state = {
4002 .surf = &tex->surface,
4003 .va = tex->buffer.gpu_address,
4004 .width = width,
4005 .height = height,
4006 .depth = depth,
4007 .type = si_tex_dim(screen, tex, target, 0),
4008 .first_layer = first_layer,
4009 .last_layer = last_layer,
4010 .num_samples = res->nr_samples,
4011 .num_storage_samples = res->nr_storage_samples,
4012 };
4013
4014 ac_build_fmask_descriptor(screen->info.gfx_level, &ac_state, &fmask_state[0]);
4015 }
4016 }
4017
4018 /**
4019 * Create a sampler view.
4020 *
4021 * @param ctx context
4022 * @param texture texture
4023 * @param state sampler view template
4024 */
si_create_sampler_view(struct pipe_context * ctx,struct pipe_resource * texture,const struct pipe_sampler_view * state)4025 static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx,
4026 struct pipe_resource *texture,
4027 const struct pipe_sampler_view *state)
4028 {
4029 struct si_context *sctx = (struct si_context *)ctx;
4030 struct si_sampler_view *view = CALLOC_STRUCT_CL(si_sampler_view);
4031 struct si_texture *tex = (struct si_texture *)texture;
4032 unsigned char state_swizzle[4];
4033 unsigned last_layer = state->u.tex.last_layer;
4034 enum pipe_format pipe_format;
4035 const struct legacy_surf_level *surflevel;
4036
4037 if (!view)
4038 return NULL;
4039
4040 /* initialize base object */
4041 view->base = *state;
4042 view->base.texture = NULL;
4043 view->base.reference.count = 1;
4044 view->base.context = ctx;
4045
4046 assert(texture);
4047 pipe_resource_reference(&view->base.texture, texture);
4048
4049 if (state->format == PIPE_FORMAT_X24S8_UINT || state->format == PIPE_FORMAT_S8X24_UINT ||
4050 state->format == PIPE_FORMAT_X32_S8X24_UINT || state->format == PIPE_FORMAT_S8_UINT)
4051 view->is_stencil_sampler = true;
4052
4053 /* Buffer resource. */
4054 if (texture->target == PIPE_BUFFER) {
4055 uint32_t elements = si_clamp_texture_texel_count(sctx->screen->max_texel_buffer_elements,
4056 state->format, state->u.buf.size);
4057
4058 si_make_buffer_descriptor(sctx->screen, si_resource(texture), state->format,
4059 state->u.buf.offset, elements, view->state);
4060 return &view->base;
4061 }
4062
4063 state_swizzle[0] = state->swizzle_r;
4064 state_swizzle[1] = state->swizzle_g;
4065 state_swizzle[2] = state->swizzle_b;
4066 state_swizzle[3] = state->swizzle_a;
4067
4068 /* This is not needed if gallium frontends set last_layer correctly. */
4069 if (state->target == PIPE_TEXTURE_1D || state->target == PIPE_TEXTURE_2D ||
4070 state->target == PIPE_TEXTURE_RECT || state->target == PIPE_TEXTURE_CUBE)
4071 last_layer = state->u.tex.first_layer;
4072
4073 /* Texturing with separate depth and stencil. */
4074 pipe_format = state->format;
4075
4076 /* Depth/stencil texturing sometimes needs separate texture. */
4077 if (tex->is_depth && !si_can_sample_zs(tex, view->is_stencil_sampler)) {
4078 if (!tex->flushed_depth_texture && !si_init_flushed_depth_texture(ctx, texture)) {
4079 pipe_resource_reference(&view->base.texture, NULL);
4080 FREE(view);
4081 return NULL;
4082 }
4083
4084 assert(tex->flushed_depth_texture);
4085
4086 /* Override format for the case where the flushed texture
4087 * contains only Z or only S.
4088 */
4089 if (tex->flushed_depth_texture->buffer.b.b.format != tex->buffer.b.b.format)
4090 pipe_format = tex->flushed_depth_texture->buffer.b.b.format;
4091
4092 tex = tex->flushed_depth_texture;
4093 }
4094
4095 surflevel = tex->surface.u.legacy.level;
4096
4097 if (tex->db_compatible) {
4098 if (!view->is_stencil_sampler)
4099 pipe_format = tex->db_render_format;
4100
4101 switch (pipe_format) {
4102 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
4103 pipe_format = PIPE_FORMAT_Z32_FLOAT;
4104 break;
4105 case PIPE_FORMAT_X8Z24_UNORM:
4106 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4107 /* Z24 is always stored like this for DB
4108 * compatibility.
4109 */
4110 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
4111 break;
4112 case PIPE_FORMAT_X24S8_UINT:
4113 case PIPE_FORMAT_S8X24_UINT:
4114 case PIPE_FORMAT_X32_S8X24_UINT:
4115 pipe_format = PIPE_FORMAT_S8_UINT;
4116 surflevel = tex->surface.u.legacy.zs.stencil_level;
4117 break;
4118 default:;
4119 }
4120 }
4121
4122 view->dcc_incompatible =
4123 vi_dcc_formats_are_incompatible(texture, state->u.tex.first_level, state->format);
4124
4125 sctx->screen->make_texture_descriptor(
4126 sctx->screen, tex, true, state->target, pipe_format, state_swizzle,
4127 state->u.tex.first_level, state->u.tex.last_level,
4128 state->u.tex.first_layer, last_layer, texture->width0, texture->height0, texture->depth0,
4129 false, view->state, view->fmask_state);
4130
4131 view->base_level_info = &surflevel[0];
4132 view->block_width = util_format_get_blockwidth(pipe_format);
4133 return &view->base;
4134 }
4135
si_sampler_view_destroy(struct pipe_context * ctx,struct pipe_sampler_view * state)4136 static void si_sampler_view_destroy(struct pipe_context *ctx, struct pipe_sampler_view *state)
4137 {
4138 struct si_sampler_view *view = (struct si_sampler_view *)state;
4139
4140 pipe_resource_reference(&state->texture, NULL);
4141 FREE_CL(view);
4142 }
4143
wrap_mode_uses_border_color(unsigned wrap,bool linear_filter)4144 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
4145 {
4146 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER || wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
4147 (linear_filter && (wrap == PIPE_TEX_WRAP_CLAMP || wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
4148 }
4149
si_translate_border_color(struct si_context * sctx,const struct pipe_sampler_state * state,const union pipe_color_union * color,bool is_integer,uint32_t * border_color_ptr)4150 static uint32_t si_translate_border_color(struct si_context *sctx,
4151 const struct pipe_sampler_state *state,
4152 const union pipe_color_union *color, bool is_integer,
4153 uint32_t *border_color_ptr)
4154 {
4155 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
4156 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
4157
4158 if (!wrap_mode_uses_border_color(state->wrap_s, linear_filter) &&
4159 !wrap_mode_uses_border_color(state->wrap_t, linear_filter) &&
4160 !wrap_mode_uses_border_color(state->wrap_r, linear_filter))
4161 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4162
4163 #define simple_border_types(elt) \
4164 do { \
4165 if (color->elt[0] == 0 && color->elt[1] == 0 && color->elt[2] == 0 && color->elt[3] == 0) \
4166 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK; \
4167 if (color->elt[0] == 0 && color->elt[1] == 0 && color->elt[2] == 0 && color->elt[3] == 1) \
4168 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK; \
4169 if (color->elt[0] == 1 && color->elt[1] == 1 && color->elt[2] == 1 && color->elt[3] == 1) \
4170 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE; \
4171 } while (false)
4172
4173 if (is_integer)
4174 simple_border_types(ui);
4175 else
4176 simple_border_types(f);
4177
4178 #undef simple_border_types
4179
4180 int i;
4181
4182 /* Check if the border has been uploaded already. */
4183 for (i = 0; i < sctx->border_color_count; i++)
4184 if (memcmp(&sctx->border_color_table[i], color, sizeof(*color)) == 0)
4185 break;
4186
4187 if (i >= SI_MAX_BORDER_COLORS) {
4188 /* Getting 4096 unique border colors is very unlikely. */
4189 static bool printed;
4190 if (!printed) {
4191 fprintf(stderr, "radeonsi: The border color table is full. "
4192 "Any new border colors will be just black. "
4193 "This is a hardware limitation.\n");
4194 printed = true;
4195 }
4196 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4197 }
4198
4199 if (i == sctx->border_color_count) {
4200 /* Upload a new border color. */
4201 memcpy(&sctx->border_color_table[i], color, sizeof(*color));
4202 util_memcpy_cpu_to_le32(&sctx->border_color_map[i], color, sizeof(*color));
4203 sctx->border_color_count++;
4204 }
4205
4206 *border_color_ptr = i;
4207
4208 return V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
4209 }
4210
S_FIXED(float value,unsigned frac_bits)4211 static inline int S_FIXED(float value, unsigned frac_bits)
4212 {
4213 return value * (1 << frac_bits);
4214 }
4215
si_tex_filter(unsigned filter,unsigned max_aniso)4216 static inline unsigned si_tex_filter(unsigned filter, unsigned max_aniso)
4217 {
4218 if (filter == PIPE_TEX_FILTER_LINEAR)
4219 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4220 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
4221 else
4222 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4223 : V_008F38_SQ_TEX_XY_FILTER_POINT;
4224 }
4225
si_tex_aniso_filter(unsigned filter)4226 static inline unsigned si_tex_aniso_filter(unsigned filter)
4227 {
4228 if (filter < 2)
4229 return 0;
4230 if (filter < 4)
4231 return 1;
4232 if (filter < 8)
4233 return 2;
4234 if (filter < 16)
4235 return 3;
4236 return 4;
4237 }
4238
si_tex_filter_mode(unsigned mode)4239 static unsigned si_tex_filter_mode(unsigned mode)
4240 {
4241 switch (mode) {
4242 case PIPE_TEX_REDUCTION_WEIGHTED_AVERAGE:
4243 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4244 case PIPE_TEX_REDUCTION_MIN:
4245 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
4246 case PIPE_TEX_REDUCTION_MAX:
4247 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
4248 default:
4249 break;
4250 }
4251 return 0;
4252 }
4253
si_create_sampler_state(struct pipe_context * ctx,const struct pipe_sampler_state * state)4254 static void *si_create_sampler_state(struct pipe_context *ctx,
4255 const struct pipe_sampler_state *state)
4256 {
4257 struct si_context *sctx = (struct si_context *)ctx;
4258 struct si_screen *sscreen = sctx->screen;
4259 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
4260 unsigned max_aniso = sscreen->force_aniso >= 0 ? sscreen->force_aniso : state->max_anisotropy;
4261 unsigned max_aniso_ratio = si_tex_aniso_filter(max_aniso);
4262 unsigned filter_mode = si_tex_filter_mode(state->reduction_mode);
4263 bool trunc_coord = (state->min_img_filter == PIPE_TEX_FILTER_NEAREST &&
4264 state->mag_img_filter == PIPE_TEX_FILTER_NEAREST &&
4265 state->compare_mode == PIPE_TEX_COMPARE_NONE) ||
4266 sscreen->info.conformant_trunc_coord;
4267 union pipe_color_union clamped_border_color;
4268
4269 if (!rstate) {
4270 return NULL;
4271 }
4272
4273 /* Validate inputs. */
4274 if (!is_wrap_mode_legal(sscreen, state->wrap_s) ||
4275 !is_wrap_mode_legal(sscreen, state->wrap_t) ||
4276 !is_wrap_mode_legal(sscreen, state->wrap_r) ||
4277 (!sscreen->info.has_3d_cube_border_color_mipmap &&
4278 (state->min_mip_filter != PIPE_TEX_MIPFILTER_NONE ||
4279 state->max_anisotropy > 0))) {
4280 assert(0);
4281 return NULL;
4282 }
4283
4284 #ifndef NDEBUG
4285 rstate->magic = SI_SAMPLER_STATE_MAGIC;
4286 #endif
4287
4288 unsigned border_color_ptr = 0;
4289 unsigned border_color_type =
4290 si_translate_border_color(sctx, state, &state->border_color,
4291 state->border_color_is_integer,
4292 &border_color_ptr);
4293
4294 struct ac_sampler_state ac_state = {
4295 .address_mode_u = si_tex_wrap(state->wrap_s),
4296 .address_mode_v = si_tex_wrap(state->wrap_t),
4297 .address_mode_w = si_tex_wrap(state->wrap_r),
4298 .max_aniso_ratio = max_aniso_ratio,
4299 .depth_compare_func = si_tex_compare(state->compare_mode, state->compare_func),
4300 .unnormalized_coords = state->unnormalized_coords,
4301 .cube_wrap = state->seamless_cube_map,
4302 .trunc_coord = trunc_coord,
4303 .filter_mode = filter_mode,
4304 .mag_filter = si_tex_filter(state->mag_img_filter, max_aniso),
4305 .min_filter = si_tex_filter(state->min_img_filter, max_aniso),
4306 .mip_filter = si_tex_mipfilter(state->min_mip_filter),
4307 .min_lod = state->min_lod,
4308 .max_lod = state->max_lod,
4309 .lod_bias = state->lod_bias,
4310 .border_color_type = border_color_type,
4311 .border_color_ptr = border_color_ptr,
4312 };
4313
4314 ac_build_sampler_descriptor(sscreen->info.gfx_level, &ac_state, rstate->val);
4315
4316 /* Create sampler resource for upgraded depth textures. */
4317 memcpy(rstate->upgraded_depth_val, rstate->val, sizeof(rstate->val));
4318
4319 for (unsigned i = 0; i < 4; ++i) {
4320 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4321 * when the border color is 1.0. */
4322 clamped_border_color.f[i] = CLAMP(state->border_color.f[0], 0, 1);
4323 }
4324
4325 if (memcmp(&state->border_color, &clamped_border_color, sizeof(clamped_border_color)) == 0) {
4326 if (sscreen->info.gfx_level <= GFX9)
4327 rstate->upgraded_depth_val[3] |= S_008F3C_UPGRADED_DEPTH(1);
4328 } else {
4329 border_color_ptr = 0;
4330 border_color_type = si_translate_border_color(sctx, state, &clamped_border_color, false, &border_color_ptr);
4331
4332 rstate->upgraded_depth_val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
4333
4334 if (sscreen->info.gfx_level >= GFX11) {
4335 rstate->upgraded_depth_val[3] |= S_008F3C_BORDER_COLOR_PTR_GFX11(border_color_ptr);
4336 } else {
4337 rstate->upgraded_depth_val[3] |= S_008F3C_BORDER_COLOR_PTR_GFX6(border_color_ptr);
4338 }
4339 }
4340
4341 return rstate;
4342 }
4343
si_set_sample_mask(struct pipe_context * ctx,unsigned sample_mask)4344 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
4345 {
4346 struct si_context *sctx = (struct si_context *)ctx;
4347
4348 if (sctx->sample_mask == (uint16_t)sample_mask)
4349 return;
4350
4351 sctx->sample_mask = sample_mask;
4352 si_mark_atom_dirty(sctx, &sctx->atoms.s.sample_mask);
4353 }
4354
si_emit_sample_mask(struct si_context * sctx,unsigned index)4355 static void si_emit_sample_mask(struct si_context *sctx, unsigned index)
4356 {
4357 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
4358 unsigned mask = sctx->sample_mask;
4359
4360 /* Needed for line and polygon smoothing as well as for the Polaris
4361 * small primitive filter. We expect the gallium frontend to take care of
4362 * this for us.
4363 */
4364 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
4365 (mask & 1 && sctx->blitter_running));
4366
4367 radeon_begin(cs);
4368 radeon_set_context_reg_seq(R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
4369 radeon_emit(mask | (mask << 16));
4370 radeon_emit(mask | (mask << 16));
4371 radeon_end();
4372 }
4373
si_delete_sampler_state(struct pipe_context * ctx,void * state)4374 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
4375 {
4376 #ifndef NDEBUG
4377 struct si_sampler_state *s = state;
4378
4379 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
4380 s->magic = 0;
4381 #endif
4382 free(state);
4383 }
4384
4385 /*
4386 * Vertex elements & buffers
4387 */
4388
si_compute_fast_udiv_info32(uint32_t D,unsigned num_bits)4389 struct si_fast_udiv_info32 si_compute_fast_udiv_info32(uint32_t D, unsigned num_bits)
4390 {
4391 struct util_fast_udiv_info info = util_compute_fast_udiv_info(D, num_bits, 32);
4392
4393 struct si_fast_udiv_info32 result = {
4394 info.multiplier,
4395 info.pre_shift,
4396 info.post_shift,
4397 info.increment,
4398 };
4399 return result;
4400 }
4401
si_create_vertex_elements(struct pipe_context * ctx,unsigned count,const struct pipe_vertex_element * elements)4402 static void *si_create_vertex_elements(struct pipe_context *ctx, unsigned count,
4403 const struct pipe_vertex_element *elements)
4404 {
4405 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
4406
4407 if (sscreen->debug_flags & DBG(VERTEX_ELEMENTS)) {
4408 for (int i = 0; i < count; ++i) {
4409 const struct pipe_vertex_element *e = elements + i;
4410 fprintf(stderr, "elements[%d]: offset %2d, buffer_index %d, dual_slot %d, format %3d, divisor %u\n",
4411 i, e->src_offset, e->vertex_buffer_index, e->dual_slot, e->src_format, e->instance_divisor);
4412 }
4413 }
4414
4415 struct si_vertex_elements *v = CALLOC_STRUCT(si_vertex_elements);
4416 struct si_fast_udiv_info32 divisor_factors[SI_MAX_ATTRIBS] = {};
4417 STATIC_ASSERT(sizeof(struct si_fast_udiv_info32) == 16);
4418 STATIC_ASSERT(sizeof(divisor_factors[0].multiplier) == 4);
4419 STATIC_ASSERT(sizeof(divisor_factors[0].pre_shift) == 4);
4420 STATIC_ASSERT(sizeof(divisor_factors[0].post_shift) == 4);
4421 STATIC_ASSERT(sizeof(divisor_factors[0].increment) == 4);
4422 int i;
4423
4424 assert(count <= SI_MAX_ATTRIBS);
4425 if (!v)
4426 return NULL;
4427
4428 v->count = count;
4429
4430 unsigned num_vbos_in_user_sgprs = si_num_vbos_in_user_sgprs(sscreen);
4431 unsigned alloc_count =
4432 count > num_vbos_in_user_sgprs ? count - num_vbos_in_user_sgprs : 0;
4433 v->vb_desc_list_alloc_size = align(alloc_count * 16, SI_CPDMA_ALIGNMENT);
4434
4435 for (i = 0; i < count; ++i) {
4436 const struct util_format_description *desc;
4437 const struct util_format_channel_description *channel;
4438 int first_non_void;
4439 unsigned vbo_index = elements[i].vertex_buffer_index;
4440
4441 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
4442 FREE(v);
4443 return NULL;
4444 }
4445
4446 unsigned instance_divisor = elements[i].instance_divisor;
4447 if (instance_divisor) {
4448 if (instance_divisor == 1) {
4449 v->instance_divisor_is_one |= 1u << i;
4450 } else {
4451 v->instance_divisor_is_fetched |= 1u << i;
4452 divisor_factors[i] = si_compute_fast_udiv_info32(instance_divisor, 32);
4453 }
4454 }
4455
4456 desc = util_format_description(elements[i].src_format);
4457 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
4458 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
4459
4460 v->elem[i].format_size = desc->block.bits / 8;
4461 v->elem[i].src_offset = elements[i].src_offset;
4462 v->elem[i].stride = elements[i].src_stride;
4463 v->vertex_buffer_index[i] = vbo_index;
4464
4465 bool always_fix = false;
4466 union si_vs_fix_fetch fix_fetch;
4467 unsigned log_hw_load_size; /* the load element size as seen by the hardware */
4468
4469 fix_fetch.bits = 0;
4470 log_hw_load_size = MIN2(2, util_logbase2(desc->block.bits) - 3);
4471
4472 if (channel) {
4473 switch (channel->type) {
4474 case UTIL_FORMAT_TYPE_FLOAT:
4475 fix_fetch.u.format = AC_FETCH_FORMAT_FLOAT;
4476 break;
4477 case UTIL_FORMAT_TYPE_FIXED:
4478 fix_fetch.u.format = AC_FETCH_FORMAT_FIXED;
4479 break;
4480 case UTIL_FORMAT_TYPE_SIGNED: {
4481 if (channel->pure_integer)
4482 fix_fetch.u.format = AC_FETCH_FORMAT_SINT;
4483 else if (channel->normalized)
4484 fix_fetch.u.format = AC_FETCH_FORMAT_SNORM;
4485 else
4486 fix_fetch.u.format = AC_FETCH_FORMAT_SSCALED;
4487 break;
4488 }
4489 case UTIL_FORMAT_TYPE_UNSIGNED: {
4490 if (channel->pure_integer)
4491 fix_fetch.u.format = AC_FETCH_FORMAT_UINT;
4492 else if (channel->normalized)
4493 fix_fetch.u.format = AC_FETCH_FORMAT_UNORM;
4494 else
4495 fix_fetch.u.format = AC_FETCH_FORMAT_USCALED;
4496 break;
4497 }
4498 default:
4499 unreachable("bad format type");
4500 }
4501 } else {
4502 switch (elements[i].src_format) {
4503 case PIPE_FORMAT_R11G11B10_FLOAT:
4504 fix_fetch.u.format = AC_FETCH_FORMAT_FLOAT;
4505 break;
4506 default:
4507 unreachable("bad other format");
4508 }
4509 }
4510
4511 if (desc->channel[0].size == 10) {
4512 fix_fetch.u.log_size = 3; /* special encoding for 2_10_10_10 */
4513 log_hw_load_size = 2;
4514
4515 /* The hardware always treats the 2-bit alpha channel as
4516 * unsigned, so a shader workaround is needed. The affected
4517 * chips are GFX8 and older except Stoney (GFX8.1).
4518 */
4519 always_fix = sscreen->info.gfx_level <= GFX8 && sscreen->info.family != CHIP_STONEY &&
4520 channel->type == UTIL_FORMAT_TYPE_SIGNED;
4521 } else if (elements[i].src_format == PIPE_FORMAT_R11G11B10_FLOAT) {
4522 fix_fetch.u.log_size = 3; /* special encoding */
4523 fix_fetch.u.format = AC_FETCH_FORMAT_FIXED;
4524 log_hw_load_size = 2;
4525 } else {
4526 fix_fetch.u.log_size = util_logbase2(channel->size) - 3;
4527 fix_fetch.u.num_channels_m1 = desc->nr_channels - 1;
4528
4529 /* Always fix up:
4530 * - doubles (multiple loads + truncate to float)
4531 * - 32-bit requiring a conversion
4532 */
4533 always_fix = (fix_fetch.u.log_size == 3) ||
4534 (fix_fetch.u.log_size == 2 && fix_fetch.u.format != AC_FETCH_FORMAT_FLOAT &&
4535 fix_fetch.u.format != AC_FETCH_FORMAT_UINT &&
4536 fix_fetch.u.format != AC_FETCH_FORMAT_SINT);
4537
4538 /* Also fixup 8_8_8 and 16_16_16. */
4539 if (desc->nr_channels == 3 && fix_fetch.u.log_size <= 1) {
4540 always_fix = true;
4541 log_hw_load_size = fix_fetch.u.log_size;
4542 }
4543 }
4544
4545 if (desc->swizzle[0] != PIPE_SWIZZLE_X) {
4546 assert(desc->swizzle[0] == PIPE_SWIZZLE_Z &&
4547 (desc->swizzle[2] == PIPE_SWIZZLE_X || desc->swizzle[2] == PIPE_SWIZZLE_0));
4548 fix_fetch.u.reverse = 1;
4549 }
4550
4551 /* Force the workaround for unaligned access here already if the
4552 * offset relative to the vertex buffer base is unaligned.
4553 *
4554 * There is a theoretical case in which this is too conservative:
4555 * if the vertex buffer's offset is also unaligned in just the
4556 * right way, we end up with an aligned address after all.
4557 * However, this case should be extremely rare in practice (it
4558 * won't happen in well-behaved applications), and taking it
4559 * into account would complicate the fast path (where everything
4560 * is nicely aligned).
4561 */
4562 bool check_alignment =
4563 log_hw_load_size >= 1 &&
4564 (sscreen->info.gfx_level == GFX6 || sscreen->info.gfx_level >= GFX10);
4565 bool opencode = sscreen->options.vs_fetch_always_opencode;
4566
4567 if (check_alignment && ((elements[i].src_offset & ((1 << log_hw_load_size) - 1)) != 0 ||
4568 elements[i].src_stride & 3))
4569 opencode = true;
4570
4571 if (always_fix || check_alignment || opencode)
4572 v->fix_fetch[i] = fix_fetch.bits;
4573
4574 if (opencode)
4575 v->fix_fetch_opencode |= 1 << i;
4576 if (opencode || always_fix)
4577 v->fix_fetch_always |= 1 << i;
4578
4579 if (check_alignment && !opencode) {
4580 assert(log_hw_load_size == 1 || log_hw_load_size == 2);
4581
4582 v->fix_fetch_unaligned |= 1 << i;
4583 v->hw_load_is_dword |= (log_hw_load_size - 1) << i;
4584 v->vb_alignment_check_mask |= 1 << vbo_index;
4585 }
4586
4587 const struct ac_buffer_state buffer_state = {
4588 .format = elements[i].src_format,
4589 .swizzle =
4590 {
4591 desc->swizzle[0],
4592 desc->swizzle[1],
4593 desc->swizzle[2],
4594 desc->swizzle[3],
4595 },
4596 /* OOB_SELECT chooses the out-of-bounds check:
4597 * - 1: index >= NUM_RECORDS (Structured)
4598 * - 3: offset >= NUM_RECORDS (Raw)
4599 */
4600 .gfx10_oob_select = v->elem[i].stride ? V_008F0C_OOB_SELECT_STRUCTURED
4601 : V_008F0C_OOB_SELECT_RAW,
4602 };
4603
4604 ac_set_buf_desc_word3(sscreen->info.gfx_level, &buffer_state, &v->elem[i].rsrc_word3);
4605 }
4606
4607 if (v->instance_divisor_is_fetched) {
4608 unsigned num_divisors = util_last_bit(v->instance_divisor_is_fetched);
4609
4610 v->instance_divisor_factor_buffer = (struct si_resource *)pipe_buffer_create(
4611 &sscreen->b, 0, PIPE_USAGE_DEFAULT, num_divisors * sizeof(divisor_factors[0]));
4612 if (!v->instance_divisor_factor_buffer) {
4613 FREE(v);
4614 return NULL;
4615 }
4616 void *map =
4617 sscreen->ws->buffer_map(sscreen->ws, v->instance_divisor_factor_buffer->buf, NULL, PIPE_MAP_WRITE);
4618 memcpy(map, divisor_factors, num_divisors * sizeof(divisor_factors[0]));
4619 }
4620 return v;
4621 }
4622
si_bind_vertex_elements(struct pipe_context * ctx,void * state)4623 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
4624 {
4625 struct si_context *sctx = (struct si_context *)ctx;
4626 struct si_vertex_elements *old = sctx->vertex_elements;
4627 struct si_vertex_elements *v = (struct si_vertex_elements *)state;
4628
4629 if (!v)
4630 v = sctx->no_velems_state;
4631
4632 sctx->vertex_elements = v;
4633 sctx->num_vertex_elements = v->count;
4634 sctx->vertex_buffers_dirty = sctx->num_vertex_elements > 0;
4635
4636 if (old->instance_divisor_is_one != v->instance_divisor_is_one ||
4637 old->instance_divisor_is_fetched != v->instance_divisor_is_fetched ||
4638 (old->vb_alignment_check_mask ^ v->vb_alignment_check_mask) &
4639 sctx->vertex_buffer_unaligned ||
4640 ((v->vb_alignment_check_mask & sctx->vertex_buffer_unaligned) &&
4641 memcmp(old->vertex_buffer_index, v->vertex_buffer_index,
4642 sizeof(v->vertex_buffer_index[0]) * MAX2(old->count, v->count))) ||
4643 /* fix_fetch_{always,opencode,unaligned} and hw_load_is_dword are
4644 * functions of fix_fetch and the src_offset alignment.
4645 * If they change and fix_fetch doesn't, it must be due to different
4646 * src_offset alignment, which is reflected in fix_fetch_opencode. */
4647 old->fix_fetch_opencode != v->fix_fetch_opencode ||
4648 memcmp(old->fix_fetch, v->fix_fetch, sizeof(v->fix_fetch[0]) *
4649 MAX2(old->count, v->count))) {
4650 si_vs_key_update_inputs(sctx);
4651 sctx->do_update_shaders = true;
4652 }
4653
4654 if (v->instance_divisor_is_fetched) {
4655 struct pipe_constant_buffer cb;
4656
4657 cb.buffer = &v->instance_divisor_factor_buffer->b.b;
4658 cb.user_buffer = NULL;
4659 cb.buffer_offset = 0;
4660 cb.buffer_size = 0xffffffff;
4661 si_set_internal_const_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb);
4662 }
4663 }
4664
si_delete_vertex_element(struct pipe_context * ctx,void * state)4665 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
4666 {
4667 struct si_context *sctx = (struct si_context *)ctx;
4668 struct si_vertex_elements *v = (struct si_vertex_elements *)state;
4669
4670 if (sctx->vertex_elements == state)
4671 si_bind_vertex_elements(ctx, sctx->no_velems_state);
4672
4673 si_resource_reference(&v->instance_divisor_factor_buffer, NULL);
4674 FREE(state);
4675 }
4676
si_set_vertex_buffers(struct pipe_context * ctx,unsigned count,const struct pipe_vertex_buffer * buffers)4677 static void si_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
4678 const struct pipe_vertex_buffer *buffers)
4679 {
4680 struct si_context *sctx = (struct si_context *)ctx;
4681 uint32_t unaligned = 0;
4682 unsigned i;
4683
4684 assert(count <= ARRAY_SIZE(sctx->vertex_buffer));
4685 assert(!count || buffers);
4686
4687 for (i = 0; i < count; i++) {
4688 const struct pipe_vertex_buffer *src = buffers + i;
4689 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + i;
4690 struct pipe_resource *buf = src->buffer.resource;
4691
4692 dst->buffer_offset = src->buffer_offset;
4693
4694 /* Only unreference bound vertex buffers. */
4695 pipe_resource_reference(&dst->buffer.resource, NULL);
4696 dst->buffer.resource = src->buffer.resource;
4697
4698 if (src->buffer_offset & 3)
4699 unaligned |= BITFIELD_BIT(i);
4700
4701 if (buf) {
4702 si_resource(buf)->bind_history |= SI_BIND_VERTEX_BUFFER;
4703 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(buf),
4704 RADEON_USAGE_READ | RADEON_PRIO_VERTEX_BUFFER);
4705 }
4706 }
4707
4708 unsigned last_count = sctx->num_vertex_buffers;
4709 for (; i < last_count; i++)
4710 pipe_resource_reference(&sctx->vertex_buffer[i].buffer.resource, NULL);
4711
4712 sctx->num_vertex_buffers = count;
4713 sctx->vertex_buffers_dirty = sctx->num_vertex_elements > 0;
4714 sctx->vertex_buffer_unaligned = unaligned;
4715
4716 /* Check whether alignment may have changed in a way that requires
4717 * shader changes. This check is conservative: a vertex buffer can only
4718 * trigger a shader change if the misalignment amount changes (e.g.
4719 * from byte-aligned to short-aligned), but we only keep track of
4720 * whether buffers are at least dword-aligned, since that should always
4721 * be the case in well-behaved applications anyway.
4722 */
4723 if (sctx->vertex_elements->vb_alignment_check_mask & unaligned) {
4724 si_vs_key_update_inputs(sctx);
4725 sctx->do_update_shaders = true;
4726 }
4727 }
4728
4729 static struct pipe_vertex_state *
si_create_vertex_state(struct pipe_screen * screen,struct pipe_vertex_buffer * buffer,const struct pipe_vertex_element * elements,unsigned num_elements,struct pipe_resource * indexbuf,uint32_t full_velem_mask)4730 si_create_vertex_state(struct pipe_screen *screen,
4731 struct pipe_vertex_buffer *buffer,
4732 const struct pipe_vertex_element *elements,
4733 unsigned num_elements,
4734 struct pipe_resource *indexbuf,
4735 uint32_t full_velem_mask)
4736 {
4737 struct si_screen *sscreen = (struct si_screen *)screen;
4738 struct si_vertex_state *state = CALLOC_STRUCT(si_vertex_state);
4739
4740 util_init_pipe_vertex_state(screen, buffer, elements, num_elements, indexbuf, full_velem_mask,
4741 &state->b);
4742
4743 /* Initialize the vertex element state in state->element.
4744 * Do it by creating a vertex element state object and copying it there.
4745 */
4746 struct si_context ctx = {};
4747 ctx.b.screen = screen;
4748 struct si_vertex_elements *velems = si_create_vertex_elements(&ctx.b, num_elements, elements);
4749 state->velems = *velems;
4750 si_delete_vertex_element(&ctx.b, velems);
4751
4752 assert(!state->velems.instance_divisor_is_one);
4753 assert(!state->velems.instance_divisor_is_fetched);
4754 assert(!state->velems.fix_fetch_always);
4755 assert(buffer->buffer_offset % 4 == 0);
4756 assert(!buffer->is_user_buffer);
4757 for (unsigned i = 0; i < num_elements; i++) {
4758 assert(elements[i].src_offset % 4 == 0);
4759 assert(!elements[i].dual_slot);
4760 assert(elements[i].src_stride % 4 == 0);
4761 }
4762
4763 for (unsigned i = 0; i < num_elements; i++) {
4764 si_set_vertex_buffer_descriptor(sscreen, &state->velems, &state->b.input.vbuffer, i,
4765 &state->descriptors[i * 4]);
4766 }
4767
4768 return &state->b;
4769 }
4770
si_vertex_state_destroy(struct pipe_screen * screen,struct pipe_vertex_state * state)4771 static void si_vertex_state_destroy(struct pipe_screen *screen,
4772 struct pipe_vertex_state *state)
4773 {
4774 pipe_vertex_buffer_unreference(&state->input.vbuffer);
4775 pipe_resource_reference(&state->input.indexbuf, NULL);
4776 FREE(state);
4777 }
4778
4779 static struct pipe_vertex_state *
si_pipe_create_vertex_state(struct pipe_screen * screen,struct pipe_vertex_buffer * buffer,const struct pipe_vertex_element * elements,unsigned num_elements,struct pipe_resource * indexbuf,uint32_t full_velem_mask)4780 si_pipe_create_vertex_state(struct pipe_screen *screen,
4781 struct pipe_vertex_buffer *buffer,
4782 const struct pipe_vertex_element *elements,
4783 unsigned num_elements,
4784 struct pipe_resource *indexbuf,
4785 uint32_t full_velem_mask)
4786 {
4787 struct si_screen *sscreen = (struct si_screen *)screen;
4788
4789 return util_vertex_state_cache_get(screen, buffer, elements, num_elements, indexbuf,
4790 full_velem_mask, &sscreen->vertex_state_cache);
4791 }
4792
si_pipe_vertex_state_destroy(struct pipe_screen * screen,struct pipe_vertex_state * state)4793 static void si_pipe_vertex_state_destroy(struct pipe_screen *screen,
4794 struct pipe_vertex_state *state)
4795 {
4796 struct si_screen *sscreen = (struct si_screen *)screen;
4797
4798 util_vertex_state_destroy(screen, &sscreen->vertex_state_cache, state);
4799 }
4800
4801 /*
4802 * Misc
4803 */
4804
si_set_tess_state(struct pipe_context * ctx,const float default_outer_level[4],const float default_inner_level[2])4805 static void si_set_tess_state(struct pipe_context *ctx, const float default_outer_level[4],
4806 const float default_inner_level[2])
4807 {
4808 struct si_context *sctx = (struct si_context *)ctx;
4809 struct pipe_constant_buffer cb;
4810 float array[8];
4811
4812 memcpy(array, default_outer_level, sizeof(float) * 4);
4813 memcpy(array + 4, default_inner_level, sizeof(float) * 2);
4814
4815 cb.buffer = NULL;
4816 cb.user_buffer = array;
4817 cb.buffer_offset = 0;
4818 cb.buffer_size = sizeof(array);
4819
4820 si_set_internal_const_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
4821 }
4822
si_create_blend_custom(struct si_context * sctx,unsigned mode)4823 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
4824 {
4825 struct pipe_blend_state blend;
4826
4827 memset(&blend, 0, sizeof(blend));
4828 blend.independent_blend_enable = true;
4829 blend.rt[0].colormask = 0xf;
4830 return si_create_blend_state_mode(&sctx->b, &blend, mode);
4831 }
4832
si_pm4_emit_sqtt_pipeline(struct si_context * sctx,unsigned index)4833 static void si_pm4_emit_sqtt_pipeline(struct si_context *sctx, unsigned index)
4834 {
4835 struct si_pm4_state *state = sctx->queued.array[index];
4836
4837 si_pm4_emit_state(sctx, index);
4838
4839 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, ((struct si_sqtt_fake_pipeline*)state)->bo,
4840 RADEON_USAGE_READ | RADEON_PRIO_SHADER_BINARY);
4841 }
4842
si_init_state_compute_functions(struct si_context * sctx)4843 void si_init_state_compute_functions(struct si_context *sctx)
4844 {
4845 sctx->b.create_sampler_state = si_create_sampler_state;
4846 sctx->b.delete_sampler_state = si_delete_sampler_state;
4847 sctx->b.create_sampler_view = si_create_sampler_view;
4848 sctx->b.sampler_view_destroy = si_sampler_view_destroy;
4849 }
4850
si_init_state_functions(struct si_context * sctx)4851 void si_init_state_functions(struct si_context *sctx)
4852 {
4853 sctx->atoms.s.pm4_states[SI_STATE_IDX(blend)].emit = si_pm4_emit_state;
4854 sctx->atoms.s.pm4_states[SI_STATE_IDX(rasterizer)].emit = si_pm4_emit_rasterizer;
4855 sctx->atoms.s.pm4_states[SI_STATE_IDX(dsa)].emit = si_pm4_emit_dsa;
4856 sctx->atoms.s.pm4_states[SI_STATE_IDX(sqtt_pipeline)].emit = si_pm4_emit_sqtt_pipeline;
4857 sctx->atoms.s.pm4_states[SI_STATE_IDX(ls)].emit = si_pm4_emit_shader;
4858 sctx->atoms.s.pm4_states[SI_STATE_IDX(hs)].emit = si_pm4_emit_shader;
4859 sctx->atoms.s.pm4_states[SI_STATE_IDX(es)].emit = si_pm4_emit_shader;
4860 sctx->atoms.s.pm4_states[SI_STATE_IDX(gs)].emit = si_pm4_emit_shader;
4861 sctx->atoms.s.pm4_states[SI_STATE_IDX(vs)].emit = si_pm4_emit_shader;
4862 sctx->atoms.s.pm4_states[SI_STATE_IDX(ps)].emit = si_pm4_emit_shader;
4863
4864 if (sctx->gfx_level >= GFX12)
4865 sctx->atoms.s.framebuffer.emit = gfx12_emit_framebuffer_state;
4866 else if (sctx->screen->info.has_set_context_pairs_packed)
4867 sctx->atoms.s.framebuffer.emit = gfx11_dgpu_emit_framebuffer_state;
4868 else
4869 sctx->atoms.s.framebuffer.emit = gfx6_emit_framebuffer_state;
4870
4871 sctx->atoms.s.db_render_state.emit = si_emit_db_render_state;
4872 sctx->atoms.s.dpbb_state.emit = si_emit_dpbb_state;
4873 sctx->atoms.s.msaa_config.emit = si_emit_msaa_config;
4874 sctx->atoms.s.sample_mask.emit = si_emit_sample_mask;
4875 sctx->atoms.s.cb_render_state.emit = si_emit_cb_render_state;
4876 sctx->atoms.s.blend_color.emit = si_emit_blend_color;
4877 sctx->atoms.s.clip_regs.emit = si_emit_clip_regs;
4878 sctx->atoms.s.clip_state.emit = si_emit_clip_state;
4879 sctx->atoms.s.stencil_ref.emit = si_emit_stencil_ref;
4880
4881 sctx->b.create_blend_state = si_create_blend_state;
4882 sctx->b.bind_blend_state = si_bind_blend_state;
4883 sctx->b.delete_blend_state = si_delete_blend_state;
4884 sctx->b.set_blend_color = si_set_blend_color;
4885
4886 sctx->b.create_rasterizer_state = si_create_rs_state;
4887 sctx->b.bind_rasterizer_state = si_bind_rs_state;
4888 sctx->b.delete_rasterizer_state = si_delete_rs_state;
4889
4890 sctx->b.create_depth_stencil_alpha_state = si_create_dsa_state;
4891 sctx->b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
4892 sctx->b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
4893
4894 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
4895
4896 if (sctx->gfx_level < GFX11) {
4897 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
4898 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
4899 sctx->custom_blend_eliminate_fastclear =
4900 si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
4901 }
4902
4903 sctx->custom_blend_dcc_decompress =
4904 si_create_blend_custom(sctx,
4905 sctx->gfx_level >= GFX12 ? V_028858_CB_DCC_DECOMPRESS :
4906 sctx->gfx_level >= GFX11 ? V_028808_CB_DCC_DECOMPRESS_GFX11 :
4907 V_028808_CB_DCC_DECOMPRESS_GFX8);
4908
4909 sctx->b.set_clip_state = si_set_clip_state;
4910 sctx->b.set_stencil_ref = si_set_stencil_ref;
4911
4912 sctx->b.set_framebuffer_state = si_set_framebuffer_state;
4913
4914 sctx->b.set_sample_mask = si_set_sample_mask;
4915
4916 sctx->b.create_vertex_elements_state = si_create_vertex_elements;
4917 sctx->b.bind_vertex_elements_state = si_bind_vertex_elements;
4918 sctx->b.delete_vertex_elements_state = si_delete_vertex_element;
4919 sctx->b.set_vertex_buffers = si_set_vertex_buffers;
4920
4921 sctx->b.set_min_samples = si_set_min_samples;
4922 sctx->b.set_tess_state = si_set_tess_state;
4923
4924 sctx->b.set_active_query_state = si_set_active_query_state;
4925 }
4926
si_init_screen_state_functions(struct si_screen * sscreen)4927 void si_init_screen_state_functions(struct si_screen *sscreen)
4928 {
4929 sscreen->b.is_format_supported = si_is_format_supported;
4930 sscreen->b.create_vertex_state = si_pipe_create_vertex_state;
4931 sscreen->b.vertex_state_destroy = si_pipe_vertex_state_destroy;
4932
4933 if (sscreen->info.gfx_level >= GFX10)
4934 sscreen->make_texture_descriptor = gfx10_make_texture_descriptor;
4935 else
4936 sscreen->make_texture_descriptor = si_make_texture_descriptor;
4937
4938 util_vertex_state_cache_init(&sscreen->vertex_state_cache,
4939 si_create_vertex_state, si_vertex_state_destroy);
4940 }
4941
si_set_grbm_gfx_index(struct si_context * sctx,struct si_pm4_state * pm4,unsigned value)4942 static void si_set_grbm_gfx_index(struct si_context *sctx, struct si_pm4_state *pm4, unsigned value)
4943 {
4944 unsigned reg = sctx->gfx_level >= GFX7 ? R_030800_GRBM_GFX_INDEX : R_00802C_GRBM_GFX_INDEX;
4945 ac_pm4_set_reg(&pm4->base, reg, value);
4946 }
4947
si_set_grbm_gfx_index_se(struct si_context * sctx,struct si_pm4_state * pm4,unsigned se)4948 static void si_set_grbm_gfx_index_se(struct si_context *sctx, struct si_pm4_state *pm4, unsigned se)
4949 {
4950 assert(se == ~0 || se < sctx->screen->info.max_se);
4951 si_set_grbm_gfx_index(sctx, pm4,
4952 (se == ~0 ? S_030800_SE_BROADCAST_WRITES(1) : S_030800_SE_INDEX(se)) |
4953 S_030800_SH_BROADCAST_WRITES(1) |
4954 S_030800_INSTANCE_BROADCAST_WRITES(1));
4955 }
4956
si_write_harvested_raster_configs(struct si_context * sctx,struct si_pm4_state * pm4,unsigned raster_config,unsigned raster_config_1)4957 static void si_write_harvested_raster_configs(struct si_context *sctx, struct si_pm4_state *pm4,
4958 unsigned raster_config, unsigned raster_config_1)
4959 {
4960 unsigned num_se = MAX2(sctx->screen->info.max_se, 1);
4961 unsigned raster_config_se[4];
4962 unsigned se;
4963
4964 ac_get_harvested_configs(&sctx->screen->info, raster_config, &raster_config_1, raster_config_se);
4965
4966 for (se = 0; se < num_se; se++) {
4967 si_set_grbm_gfx_index_se(sctx, pm4, se);
4968 ac_pm4_set_reg(&pm4->base, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
4969 }
4970 si_set_grbm_gfx_index(sctx, pm4, ~0);
4971
4972 if (sctx->gfx_level >= GFX7) {
4973 ac_pm4_set_reg(&pm4->base, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4974 }
4975 }
4976
si_set_raster_config(struct si_context * sctx,struct si_pm4_state * pm4)4977 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4)
4978 {
4979 struct si_screen *sscreen = sctx->screen;
4980 unsigned num_rb = MIN2(sscreen->info.max_render_backends, 16);
4981 uint64_t rb_mask = sscreen->info.enabled_rb_mask;
4982 unsigned raster_config = sscreen->pa_sc_raster_config;
4983 unsigned raster_config_1 = sscreen->pa_sc_raster_config_1;
4984
4985 if (!rb_mask || util_bitcount64(rb_mask) >= num_rb) {
4986 /* Always use the default config when all backends are enabled
4987 * (or when we failed to determine the enabled backends).
4988 */
4989 ac_pm4_set_reg(&pm4->base, R_028350_PA_SC_RASTER_CONFIG, raster_config);
4990 if (sctx->gfx_level >= GFX7)
4991 ac_pm4_set_reg(&pm4->base, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4992 } else {
4993 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4994 }
4995 }
4996
si_init_compute_preamble_state(struct si_context * sctx,struct si_pm4_state * pm4)4997 static void si_init_compute_preamble_state(struct si_context *sctx,
4998 struct si_pm4_state *pm4)
4999 {
5000 uint64_t border_color_va =
5001 sctx->border_color_buffer ? sctx->border_color_buffer->gpu_address : 0;
5002
5003 const struct ac_preamble_state preamble_state = {
5004 .border_color_va = border_color_va,
5005 .gfx11 = {
5006 .compute_dispatch_interleave = 256,
5007 },
5008 };
5009
5010 ac_init_compute_preamble_state(&preamble_state, &pm4->base);
5011
5012 if (sctx->gfx_level == GFX10 || sctx->gfx_level == GFX10_3)
5013 ac_pm4_set_reg(&pm4->base, R_00B8A0_COMPUTE_PGM_RSRC3, 0);
5014 }
5015
5016
si_init_graphics_preamble_state(struct si_context * sctx,struct si_pm4_state * pm4)5017 static void si_init_graphics_preamble_state(struct si_context *sctx,
5018 struct si_pm4_state *pm4)
5019 {
5020 struct si_screen *sscreen = sctx->screen;
5021 uint64_t border_color_va =
5022 sctx->border_color_buffer ? sctx->border_color_buffer->gpu_address : 0;
5023
5024 const struct ac_preamble_state preamble_state = {
5025 .border_color_va = border_color_va,
5026 .gfx10.cache_rb_gl2 = sctx->gfx_level >= GFX10 && sscreen->options.cache_rb_gl2,
5027 };
5028
5029 ac_init_graphics_preamble_state(&preamble_state, &pm4->base);
5030 }
5031
gfx6_init_gfx_preamble_state(struct si_context * sctx)5032 static void gfx6_init_gfx_preamble_state(struct si_context *sctx)
5033 {
5034 struct si_screen *sscreen = sctx->screen;
5035 bool has_clear_state = sscreen->info.has_clear_state;
5036
5037 /* We need more space because the preamble is large. */
5038 struct si_pm4_state *pm4 = si_pm4_create_sized(sscreen, 214, sctx->has_graphics);
5039 if (!pm4)
5040 return;
5041
5042 if (sctx->has_graphics && !sctx->shadowing.registers) {
5043 ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
5044 ac_pm4_cmd_add(&pm4->base, CC0_UPDATE_LOAD_ENABLES(1));
5045 ac_pm4_cmd_add(&pm4->base, CC1_UPDATE_SHADOW_ENABLES(1));
5046
5047 if (sscreen->dpbb_allowed) {
5048 ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_EVENT_WRITE, 0, 0));
5049 ac_pm4_cmd_add(&pm4->base, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
5050 }
5051
5052 if (has_clear_state) {
5053 ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_CLEAR_STATE, 0, 0));
5054 ac_pm4_cmd_add(&pm4->base, 0);
5055 }
5056 }
5057
5058 si_init_compute_preamble_state(sctx, pm4);
5059
5060 if (!sctx->has_graphics)
5061 goto done;
5062
5063 /* Graphics registers. */
5064 si_init_graphics_preamble_state(sctx, pm4);
5065
5066 if (!has_clear_state)
5067 ac_pm4_set_reg(&pm4->base, R_02800C_DB_RENDER_OVERRIDE, 0);
5068
5069 if (sctx->family >= CHIP_POLARIS10 && !sctx->screen->info.has_small_prim_filter_sample_loc_bug) {
5070 /* Polaris10-12 should disable small line culling, but those also have the sample loc bug,
5071 * so they never enter this branch.
5072 */
5073 assert(sctx->family > CHIP_POLARIS12);
5074 ac_pm4_set_reg(&pm4->base, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
5075 S_028830_SMALL_PRIM_FILTER_ENABLE(1));
5076 }
5077
5078 if (sctx->gfx_level <= GFX7 || !has_clear_state) {
5079 ac_pm4_set_reg(&pm4->base, R_028034_PA_SC_SCREEN_SCISSOR_BR,
5080 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
5081 }
5082
5083 if (sctx->gfx_level == GFX9) {
5084 ac_pm4_set_reg(&pm4->base, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
5085 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5086 }
5087
5088 done:
5089 ac_pm4_finalize(&pm4->base);
5090 sctx->cs_preamble_state = pm4;
5091 sctx->cs_preamble_state_tmz = si_pm4_clone(sscreen, pm4); /* Make a copy of the preamble for TMZ. */
5092 }
5093
cdna_init_compute_preamble_state(struct si_context * sctx)5094 static void cdna_init_compute_preamble_state(struct si_context *sctx)
5095 {
5096 struct si_screen *sscreen = sctx->screen;
5097 uint64_t border_color_va =
5098 sctx->border_color_buffer ? sctx->border_color_buffer->gpu_address : 0;
5099 uint32_t compute_cu_en = S_00B858_SH0_CU_EN(sscreen->info.spi_cu_en) |
5100 S_00B858_SH1_CU_EN(sscreen->info.spi_cu_en);
5101
5102 struct si_pm4_state *pm4 = si_pm4_create_sized(sscreen, 48, true);
5103 if (!pm4)
5104 return;
5105
5106 /* Compute registers. */
5107 /* Disable profiling on compute chips. */
5108 ac_pm4_set_reg(&pm4->base, R_00B82C_COMPUTE_PERFCOUNT_ENABLE, 0);
5109 ac_pm4_set_reg(&pm4->base, R_00B834_COMPUTE_PGM_HI, S_00B834_DATA(sctx->screen->info.address32_hi >> 8));
5110 ac_pm4_set_reg(&pm4->base, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, compute_cu_en);
5111 ac_pm4_set_reg(&pm4->base, R_00B85C_COMPUTE_STATIC_THREAD_MGMT_SE1, compute_cu_en);
5112 ac_pm4_set_reg(&pm4->base, R_00B864_COMPUTE_STATIC_THREAD_MGMT_SE2, compute_cu_en);
5113 ac_pm4_set_reg(&pm4->base, R_00B868_COMPUTE_STATIC_THREAD_MGMT_SE3, compute_cu_en);
5114 ac_pm4_set_reg(&pm4->base, R_00B878_COMPUTE_THREAD_TRACE_ENABLE, 0);
5115
5116 if (sscreen->info.family >= CHIP_GFX940) {
5117 ac_pm4_set_reg(&pm4->base, R_00B89C_COMPUTE_TG_CHUNK_SIZE, 0);
5118 ac_pm4_set_reg(&pm4->base, R_00B8B4_COMPUTE_PGM_RSRC3, 0);
5119 } else {
5120 ac_pm4_set_reg(&pm4->base, R_00B894_COMPUTE_STATIC_THREAD_MGMT_SE4, compute_cu_en);
5121 ac_pm4_set_reg(&pm4->base, R_00B898_COMPUTE_STATIC_THREAD_MGMT_SE5, compute_cu_en);
5122 ac_pm4_set_reg(&pm4->base, R_00B89C_COMPUTE_STATIC_THREAD_MGMT_SE6, compute_cu_en);
5123 ac_pm4_set_reg(&pm4->base, R_00B8A0_COMPUTE_STATIC_THREAD_MGMT_SE7, compute_cu_en);
5124 }
5125
5126 ac_pm4_set_reg(&pm4->base, R_0301EC_CP_COHER_START_DELAY, 0);
5127
5128 /* Set the pointer to border colors. Only MI100 supports border colors. */
5129 if (sscreen->info.family == CHIP_MI100) {
5130 ac_pm4_set_reg(&pm4->base, R_030E00_TA_CS_BC_BASE_ADDR, border_color_va >> 8);
5131 ac_pm4_set_reg(&pm4->base, R_030E04_TA_CS_BC_BASE_ADDR_HI,
5132 S_030E04_ADDRESS(border_color_va >> 40));
5133 }
5134
5135 ac_pm4_finalize(&pm4->base);
5136 sctx->cs_preamble_state = pm4;
5137 sctx->cs_preamble_state_tmz = si_pm4_clone(sscreen, pm4); /* Make a copy of the preamble for TMZ. */
5138 }
5139
gfx10_init_gfx_preamble_state(struct si_context * sctx)5140 static void gfx10_init_gfx_preamble_state(struct si_context *sctx)
5141 {
5142 struct si_screen *sscreen = sctx->screen;
5143
5144 /* We need more space because the preamble is large. */
5145 struct si_pm4_state *pm4 = si_pm4_create_sized(sscreen, 214, sctx->has_graphics);
5146 if (!pm4)
5147 return;
5148
5149 if (sctx->has_graphics && !sctx->shadowing.registers) {
5150 ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
5151 ac_pm4_cmd_add(&pm4->base, CC0_UPDATE_LOAD_ENABLES(1));
5152 ac_pm4_cmd_add(&pm4->base, CC1_UPDATE_SHADOW_ENABLES(1));
5153
5154 if (sscreen->dpbb_allowed) {
5155 ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_EVENT_WRITE, 0, 0));
5156 ac_pm4_cmd_add(&pm4->base, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
5157 }
5158
5159 ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_CLEAR_STATE, 0, 0));
5160 ac_pm4_cmd_add(&pm4->base, 0);
5161 }
5162
5163 si_init_compute_preamble_state(sctx, pm4);
5164
5165 if (!sctx->has_graphics)
5166 goto done;
5167
5168 /* Graphics registers. */
5169 si_init_graphics_preamble_state(sctx, pm4);
5170
5171 ac_pm4_set_reg(&pm4->base, R_028708_SPI_SHADER_IDX_FORMAT,
5172 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP));
5173
5174 if (sctx->gfx_level >= GFX10_3) {
5175 /* The rate combiners have no effect if they are disabled like this:
5176 * VERTEX_RATE: BYPASS_VTX_RATE_COMBINER = 1
5177 * PRIMITIVE_RATE: BYPASS_PRIM_RATE_COMBINER = 1
5178 * HTILE_RATE: VRS_HTILE_ENCODING = 0
5179 * SAMPLE_ITER: PS_ITER_SAMPLE = 0
5180 *
5181 * Use OVERRIDE, which will ignore results from previous combiners.
5182 * (e.g. enabled sample shading overrides the vertex rate)
5183 */
5184 ac_pm4_set_reg(&pm4->base, R_028848_PA_CL_VRS_CNTL,
5185 S_028848_VERTEX_RATE_COMBINER_MODE(V_028848_SC_VRS_COMB_MODE_OVERRIDE) |
5186 S_028848_SAMPLE_ITER_COMBINER_MODE(V_028848_SC_VRS_COMB_MODE_OVERRIDE));
5187 }
5188
5189 done:
5190 ac_pm4_finalize(&pm4->base);
5191 sctx->cs_preamble_state = pm4;
5192 sctx->cs_preamble_state_tmz = si_pm4_clone(sscreen, pm4); /* Make a copy of the preamble for TMZ. */
5193 }
5194
gfx12_init_gfx_preamble_state(struct si_context * sctx)5195 static void gfx12_init_gfx_preamble_state(struct si_context *sctx)
5196 {
5197 struct si_screen *sscreen = sctx->screen;
5198
5199 struct si_pm4_state *pm4 = si_pm4_create_sized(sscreen, 300, sctx->has_graphics);
5200 if (!pm4)
5201 return;
5202
5203 if (sctx->has_graphics && !sctx->shadowing.registers) {
5204 ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
5205 ac_pm4_cmd_add(&pm4->base, CC0_UPDATE_LOAD_ENABLES(1));
5206 ac_pm4_cmd_add(&pm4->base, CC1_UPDATE_SHADOW_ENABLES(1));
5207 }
5208
5209 if (sctx->has_graphics && sscreen->dpbb_allowed) {
5210 ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_EVENT_WRITE, 0, 0));
5211 ac_pm4_cmd_add(&pm4->base, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
5212 }
5213
5214 si_init_compute_preamble_state(sctx, pm4);
5215
5216 if (!sctx->has_graphics)
5217 goto done;
5218
5219 /* Graphics registers. */
5220 si_init_graphics_preamble_state(sctx, pm4);
5221
5222 ac_pm4_set_reg(&pm4->base, R_028648_SPI_SHADER_IDX_FORMAT,
5223 S_028648_IDX0_EXPORT_FORMAT(V_028648_SPI_SHADER_1COMP));
5224
5225 /* The rate combiners have no effect if they are disabled like this:
5226 * VERTEX_RATE: BYPASS_VTX_RATE_COMBINER = 1
5227 * PRIMITIVE_RATE: BYPASS_PRIM_RATE_COMBINER = 1
5228 * HTILE_RATE: VRS_HTILE_ENCODING = 0
5229 * SAMPLE_ITER: PS_ITER_SAMPLE = 0
5230 *
5231 * Use OVERRIDE, which will ignore results from previous combiners.
5232 * (e.g. enabled sample shading overrides the vertex rate)
5233 */
5234 ac_pm4_set_reg(&pm4->base, R_028848_PA_CL_VRS_CNTL,
5235 S_028848_VERTEX_RATE_COMBINER_MODE(V_028848_SC_VRS_COMB_MODE_OVERRIDE) |
5236 S_028848_SAMPLE_ITER_COMBINER_MODE(V_028848_SC_VRS_COMB_MODE_OVERRIDE));
5237
5238 ac_pm4_set_reg(&pm4->base, R_028C54_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
5239 S_028C54_NULL_SQUAD_AA_MASK_ENABLE(1));
5240
5241 done:
5242 sctx->cs_preamble_state = pm4;
5243 sctx->cs_preamble_state_tmz = si_pm4_clone(sscreen, pm4); /* Make a copy of the preamble for TMZ. */
5244 }
5245
si_init_gfx_preamble_state(struct si_context * sctx)5246 void si_init_gfx_preamble_state(struct si_context *sctx)
5247 {
5248 if (!sctx->screen->info.has_graphics)
5249 cdna_init_compute_preamble_state(sctx);
5250 else if (sctx->gfx_level >= GFX12)
5251 gfx12_init_gfx_preamble_state(sctx);
5252 else if (sctx->gfx_level >= GFX10)
5253 gfx10_init_gfx_preamble_state(sctx);
5254 else
5255 gfx6_init_gfx_preamble_state(sctx);
5256 }
5257