1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * SPDX-License-Identifier: MIT
5 */
6
7 #if AMD_LLVM_AVAILABLE
8 #include "ac_llvm_util.h"
9 #endif
10
11 #include "ac_nir.h"
12 #include "ac_shader_util.h"
13 #include "compiler/nir/nir_serialize.h"
14 #include "nir/tgsi_to_nir.h"
15 #include "si_build_pm4.h"
16 #include "sid.h"
17 #include "util/crc32.h"
18 #include "util/disk_cache.h"
19 #include "util/hash_table.h"
20 #include "util/mesa-sha1.h"
21 #include "util/u_async_debug.h"
22 #include "util/u_math.h"
23 #include "util/u_memory.h"
24 #include "util/u_prim.h"
25 #include "tgsi/tgsi_from_mesa.h"
26
27 static void si_update_tess_in_out_patch_vertices(struct si_context *sctx);
28
si_determine_wave_size(struct si_screen * sscreen,struct si_shader * shader)29 unsigned si_determine_wave_size(struct si_screen *sscreen, struct si_shader *shader)
30 {
31 struct si_shader_info *info = &shader->selector->info;
32 gl_shader_stage stage = shader->selector->stage;
33
34 struct si_shader_selector *prev_sel = NULL;
35 if (stage == MESA_SHADER_TESS_CTRL)
36 prev_sel = shader->key.ge.part.tcs.ls;
37 else if (stage == MESA_SHADER_GEOMETRY)
38 prev_sel = shader->key.ge.part.gs.es;
39
40 if (sscreen->info.gfx_level < GFX10)
41 return 64;
42
43 /* Legacy GS only supports Wave64. */
44 if ((stage == MESA_SHADER_VERTEX && shader->key.ge.as_es && !shader->key.ge.as_ngg) ||
45 (stage == MESA_SHADER_TESS_EVAL && shader->key.ge.as_es && !shader->key.ge.as_ngg) ||
46 (stage == MESA_SHADER_GEOMETRY && !shader->key.ge.as_ngg))
47 return 64;
48
49 /* For KHR_shader_subgroup which require a constant subgroup size known by user. */
50 if (info->base.subgroup_size == SUBGROUP_SIZE_API_CONSTANT ||
51 (prev_sel && prev_sel->info.base.subgroup_size == SUBGROUP_SIZE_API_CONSTANT))
52 return 64;
53
54 /* Workgroup sizes that are not divisible by 64 use Wave32. */
55 if (stage == MESA_SHADER_COMPUTE && !info->base.workgroup_size_variable &&
56 (info->base.workgroup_size[0] *
57 info->base.workgroup_size[1] *
58 info->base.workgroup_size[2]) % 64 != 0)
59 return 32;
60
61 /* AMD_DEBUG wave flags override everything else. */
62 if (sscreen->debug_flags &
63 (stage == MESA_SHADER_COMPUTE ? DBG(W32_CS) :
64 stage == MESA_SHADER_FRAGMENT ? DBG(W32_PS) : DBG(W32_GE)))
65 return 32;
66
67 if (sscreen->debug_flags &
68 (stage == MESA_SHADER_COMPUTE ? DBG(W64_CS) :
69 stage == MESA_SHADER_FRAGMENT ? DBG(W64_PS) : DBG(W64_GE)))
70 return 64;
71
72 /* Shader profiles. */
73 if (info->options & SI_PROFILE_WAVE32)
74 return 32;
75
76 if (info->options & SI_PROFILE_GFX10_WAVE64 &&
77 (sscreen->info.gfx_level == GFX10 || sscreen->info.gfx_level == GFX10_3))
78 return 64;
79
80 /* Gfx10: Pixel shaders without interp instructions don't suffer from reduced interpolation
81 * performance in Wave32, so use Wave32. This helps Piano and Voloplosion.
82 *
83 * Gfx11: Prefer Wave64 to take advantage of doubled VALU performance.
84 */
85 if (sscreen->info.gfx_level < GFX11 && stage == MESA_SHADER_FRAGMENT && !info->num_inputs)
86 return 32;
87
88 /* Gfx10: There are a few very rare cases where VS is better with Wave32, and there are no
89 * known cases where Wave64 is better.
90 *
91 * Wave32 is disabled for GFX10 when culling is active as a workaround for #6457. I don't
92 * know why this helps.
93 *
94 * Gfx11: Prefer Wave64 because it's slightly better than Wave32.
95 */
96 if (stage <= MESA_SHADER_GEOMETRY &&
97 (sscreen->info.gfx_level == GFX10 || sscreen->info.gfx_level == GFX10_3) &&
98 !(sscreen->info.gfx_level == GFX10 && shader->key.ge.opt.ngg_culling))
99 return 32;
100
101 /* Divergent loops in Wave64 can end up having too many iterations in one half of the wave
102 * while the other half is idling but occupying VGPRs, preventing other waves from launching.
103 * Wave32 eliminates the idling half to allow the next wave to start.
104 *
105 * Gfx11: Wave32 continues to be faster with divergent loops despite worse VALU performance.
106 */
107 if (info->has_divergent_loop ||
108 /* Merged shader has to use same wave size for two shader stages. */
109 (prev_sel && prev_sel->info.has_divergent_loop))
110 return 32;
111
112 return 64;
113 }
114
115 /* SHADER_CACHE */
116
117 /**
118 * Return the IR key for the shader cache.
119 */
si_get_ir_cache_key(struct si_shader_selector * sel,bool ngg,bool es,unsigned wave_size,unsigned char ir_sha1_cache_key[20])120 void si_get_ir_cache_key(struct si_shader_selector *sel, bool ngg, bool es,
121 unsigned wave_size, unsigned char ir_sha1_cache_key[20])
122 {
123 struct blob blob = {};
124 unsigned ir_size;
125 void *ir_binary;
126
127 if (sel->nir_binary) {
128 ir_binary = sel->nir_binary;
129 ir_size = sel->nir_size;
130 } else {
131 assert(sel->nir);
132
133 blob_init(&blob);
134 /* Keep debug info if NIR debug prints are in use. */
135 nir_serialize(&blob, sel->nir, NIR_DEBUG(PRINT) == 0);
136 ir_binary = blob.data;
137 ir_size = blob.size;
138 }
139
140 /* These settings affect the compilation, but they are not derived
141 * from the input shader IR.
142 */
143 unsigned shader_variant_flags = 0;
144
145 if (ngg)
146 shader_variant_flags |= 1 << 0;
147 /* bit gap */
148 if (wave_size == 32)
149 shader_variant_flags |= 1 << 2;
150 if (sel->screen->options.optimize_io)
151 shader_variant_flags |= 1 << 3;
152 /* use_ngg_culling disables NGG passthrough for non-culling shaders to reduce context
153 * rolls, which can be changed with AMD_DEBUG=nonggc or AMD_DEBUG=nggc.
154 */
155 if (sel->screen->use_ngg_culling)
156 shader_variant_flags |= 1 << 4;
157 if (sel->screen->record_llvm_ir)
158 shader_variant_flags |= 1 << 5;
159 if (sel->screen->info.has_image_opcodes)
160 shader_variant_flags |= 1 << 6;
161 if (sel->screen->options.no_infinite_interp)
162 shader_variant_flags |= 1 << 7;
163 if (sel->screen->options.clamp_div_by_zero)
164 shader_variant_flags |= 1 << 8;
165 if ((sel->stage == MESA_SHADER_VERTEX ||
166 sel->stage == MESA_SHADER_TESS_EVAL ||
167 sel->stage == MESA_SHADER_GEOMETRY) &&
168 !es &&
169 sel->screen->options.vrs2x2)
170 shader_variant_flags |= 1 << 10;
171 if (sel->screen->options.inline_uniforms)
172 shader_variant_flags |= 1 << 11;
173 if (sel->screen->options.clear_lds)
174 shader_variant_flags |= 1 << 12;
175
176 struct mesa_sha1 ctx;
177 _mesa_sha1_init(&ctx);
178 _mesa_sha1_update(&ctx, &shader_variant_flags, 4);
179 _mesa_sha1_update(&ctx, ir_binary, ir_size);
180 _mesa_sha1_final(&ctx, ir_sha1_cache_key);
181
182 if (ir_binary == blob.data)
183 blob_finish(&blob);
184 }
185
186 /** Copy "data" to "ptr" and return the next dword following copied data. */
write_data(uint32_t * ptr,const void * data,unsigned size)187 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
188 {
189 /* data may be NULL if size == 0 */
190 if (size)
191 memcpy(ptr, data, size);
192 ptr += DIV_ROUND_UP(size, 4);
193 return ptr;
194 }
195
196 /** Read data from "ptr". Return the next dword following the data. */
read_data(uint32_t * ptr,void * data,unsigned size)197 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
198 {
199 memcpy(data, ptr, size);
200 ptr += DIV_ROUND_UP(size, 4);
201 return ptr;
202 }
203
204 /**
205 * Write the size as uint followed by the data. Return the next dword
206 * following the copied data.
207 */
write_chunk(uint32_t * ptr,const void * data,unsigned size)208 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
209 {
210 *ptr++ = size;
211 return write_data(ptr, data, size);
212 }
213
214 /**
215 * Read the size as uint followed by the data. Return both via parameters.
216 * Return the next dword following the data.
217 */
read_chunk(uint32_t * ptr,void ** data,unsigned * size)218 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
219 {
220 *size = *ptr++;
221 assert(*data == NULL);
222 if (!*size)
223 return ptr;
224 *data = malloc(*size);
225 return read_data(ptr, *data, *size);
226 }
227
228 struct si_shader_blob_head {
229 uint32_t size;
230 uint32_t type;
231 uint32_t crc32;
232 };
233
234 /**
235 * Return the shader binary in a buffer.
236 */
si_get_shader_binary(struct si_shader * shader)237 static uint32_t *si_get_shader_binary(struct si_shader *shader)
238 {
239 /* There is always a size of data followed by the data itself. */
240 unsigned llvm_ir_size =
241 shader->binary.llvm_ir_string ? strlen(shader->binary.llvm_ir_string) + 1 : 0;
242
243 /* Refuse to allocate overly large buffers and guard against integer
244 * overflow. */
245 if (shader->binary.code_size > UINT_MAX / 4 || llvm_ir_size > UINT_MAX / 4 ||
246 shader->binary.num_symbols > UINT_MAX / 32)
247 return NULL;
248
249 unsigned size = sizeof(struct si_shader_blob_head) +
250 align(sizeof(shader->config), 4) +
251 align(sizeof(shader->info), 4) +
252 4 + 4 + align(shader->binary.code_size, 4) +
253 4 + shader->binary.num_symbols * 8 +
254 4 + align(llvm_ir_size, 4) +
255 4 + align(shader->binary.disasm_size, 4);
256 uint32_t *buffer = (uint32_t*)CALLOC(1, size);
257 if (!buffer)
258 return NULL;
259
260 struct si_shader_blob_head *head = (struct si_shader_blob_head *)buffer;
261 head->type = shader->binary.type;
262 head->size = size;
263
264 uint32_t *data = buffer + sizeof(*head) / 4;
265 uint32_t *ptr = data;
266
267 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
268 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
269 ptr = write_data(ptr, &shader->binary.exec_size, 4);
270 ptr = write_chunk(ptr, shader->binary.code_buffer, shader->binary.code_size);
271 ptr = write_chunk(ptr, shader->binary.symbols, shader->binary.num_symbols * 8);
272 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
273 ptr = write_chunk(ptr, shader->binary.disasm_string, shader->binary.disasm_size);
274 assert((char *)ptr - (char *)buffer == (ptrdiff_t)size);
275
276 /* Compute CRC32. */
277 head->crc32 = util_hash_crc32(data, size - sizeof(*head));
278
279 return buffer;
280 }
281
si_load_shader_binary(struct si_shader * shader,void * binary)282 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
283 {
284 struct si_shader_blob_head *head = (struct si_shader_blob_head *)binary;
285 unsigned chunk_size;
286 unsigned code_size;
287
288 uint32_t *ptr = (uint32_t *)binary + sizeof(*head) / 4;
289 if (util_hash_crc32(ptr, head->size - sizeof(*head)) != head->crc32) {
290 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
291 return false;
292 }
293
294 shader->binary.type = (enum si_shader_binary_type)head->type;
295 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
296 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
297 ptr = read_data(ptr, &shader->binary.exec_size, 4);
298 ptr = read_chunk(ptr, (void **)&shader->binary.code_buffer, &code_size);
299 shader->binary.code_size = code_size;
300 ptr = read_chunk(ptr, (void **)&shader->binary.symbols, &chunk_size);
301 shader->binary.num_symbols = chunk_size / 8;
302 ptr = read_chunk(ptr, (void **)&shader->binary.llvm_ir_string, &chunk_size);
303 ptr = read_chunk(ptr, (void **)&shader->binary.disasm_string, &chunk_size);
304 shader->binary.disasm_size = chunk_size;
305
306 if (!shader->is_gs_copy_shader &&
307 shader->selector->stage == MESA_SHADER_GEOMETRY && !shader->key.ge.as_ngg) {
308 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
309 if (!shader->gs_copy_shader)
310 return false;
311
312 shader->gs_copy_shader->is_gs_copy_shader = true;
313
314 if (!si_load_shader_binary(shader->gs_copy_shader, (uint8_t*)binary + head->size)) {
315 FREE(shader->gs_copy_shader);
316 shader->gs_copy_shader = NULL;
317 return false;
318 }
319
320 util_queue_fence_init(&shader->gs_copy_shader->ready);
321 shader->gs_copy_shader->selector = shader->selector;
322 shader->gs_copy_shader->is_gs_copy_shader = true;
323 shader->gs_copy_shader->wave_size =
324 si_determine_wave_size(shader->selector->screen, shader->gs_copy_shader);
325
326 si_shader_binary_upload(shader->selector->screen, shader->gs_copy_shader, 0);
327 }
328
329 return true;
330 }
331
332 /**
333 * Insert a shader into the cache. It's assumed the shader is not in the cache.
334 * Use si_shader_cache_load_shader before calling this.
335 */
si_shader_cache_insert_shader(struct si_screen * sscreen,unsigned char ir_sha1_cache_key[20],struct si_shader * shader,bool insert_into_disk_cache)336 void si_shader_cache_insert_shader(struct si_screen *sscreen, unsigned char ir_sha1_cache_key[20],
337 struct si_shader *shader, bool insert_into_disk_cache)
338 {
339 uint32_t *hw_binary;
340 struct hash_entry *entry;
341 uint8_t key[CACHE_KEY_SIZE];
342 bool memory_cache_full = sscreen->shader_cache_size >= sscreen->shader_cache_max_size;
343
344 if (!insert_into_disk_cache && memory_cache_full)
345 return;
346
347 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key);
348 if (entry)
349 return; /* already added */
350
351 hw_binary = si_get_shader_binary(shader);
352 if (!hw_binary)
353 return;
354
355 unsigned size = *hw_binary;
356
357 if (shader->selector->stage == MESA_SHADER_GEOMETRY && !shader->key.ge.as_ngg) {
358 uint32_t *gs_copy_binary = si_get_shader_binary(shader->gs_copy_shader);
359 if (!gs_copy_binary) {
360 FREE(hw_binary);
361 return;
362 }
363
364 /* Combine both binaries. */
365 size += *gs_copy_binary;
366 uint32_t *combined_binary = (uint32_t*)MALLOC(size);
367 if (!combined_binary) {
368 FREE(hw_binary);
369 FREE(gs_copy_binary);
370 return;
371 }
372
373 memcpy(combined_binary, hw_binary, *hw_binary);
374 memcpy(combined_binary + *hw_binary / 4, gs_copy_binary, *gs_copy_binary);
375 FREE(hw_binary);
376 FREE(gs_copy_binary);
377 hw_binary = combined_binary;
378 }
379
380 if (!memory_cache_full) {
381 if (_mesa_hash_table_insert(sscreen->shader_cache,
382 mem_dup(ir_sha1_cache_key, 20),
383 hw_binary) == NULL) {
384 FREE(hw_binary);
385 return;
386 }
387
388 sscreen->shader_cache_size += size;
389 }
390
391 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
392 disk_cache_compute_key(sscreen->disk_shader_cache, ir_sha1_cache_key, 20, key);
393 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary, size, NULL);
394 }
395
396 if (memory_cache_full)
397 FREE(hw_binary);
398 }
399
si_shader_cache_load_shader(struct si_screen * sscreen,unsigned char ir_sha1_cache_key[20],struct si_shader * shader)400 bool si_shader_cache_load_shader(struct si_screen *sscreen, unsigned char ir_sha1_cache_key[20],
401 struct si_shader *shader)
402 {
403 struct hash_entry *entry = _mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key);
404
405 if (entry) {
406 if (si_load_shader_binary(shader, entry->data)) {
407 p_atomic_inc(&sscreen->num_memory_shader_cache_hits);
408 return true;
409 }
410 }
411 p_atomic_inc(&sscreen->num_memory_shader_cache_misses);
412
413 if (!sscreen->disk_shader_cache)
414 return false;
415
416 unsigned char sha1[CACHE_KEY_SIZE];
417 disk_cache_compute_key(sscreen->disk_shader_cache, ir_sha1_cache_key, 20, sha1);
418
419 size_t total_size;
420 uint32_t *buffer = (uint32_t*)disk_cache_get(sscreen->disk_shader_cache, sha1, &total_size);
421 if (buffer) {
422 unsigned size = *buffer;
423 unsigned gs_copy_binary_size = 0;
424
425 /* The GS copy shader binary is after the GS binary. */
426 if (shader->selector->stage == MESA_SHADER_GEOMETRY && !shader->key.ge.as_ngg)
427 gs_copy_binary_size = buffer[size / 4];
428
429 if (total_size >= sizeof(uint32_t) && size + gs_copy_binary_size == total_size) {
430 if (si_load_shader_binary(shader, buffer)) {
431 free(buffer);
432 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key, shader, false);
433 p_atomic_inc(&sscreen->num_disk_shader_cache_hits);
434 return true;
435 }
436 } else {
437 /* Something has gone wrong discard the item from the cache and
438 * rebuild/link from source.
439 */
440 assert(!"Invalid radeonsi shader disk cache item!");
441 disk_cache_remove(sscreen->disk_shader_cache, sha1);
442 }
443 }
444
445 free(buffer);
446 p_atomic_inc(&sscreen->num_disk_shader_cache_misses);
447 return false;
448 }
449
si_shader_cache_key_hash(const void * key)450 static uint32_t si_shader_cache_key_hash(const void *key)
451 {
452 /* Take the first dword of SHA1. */
453 return *(uint32_t *)key;
454 }
455
si_shader_cache_key_equals(const void * a,const void * b)456 static bool si_shader_cache_key_equals(const void *a, const void *b)
457 {
458 /* Compare SHA1s. */
459 return memcmp(a, b, 20) == 0;
460 }
461
si_destroy_shader_cache_entry(struct hash_entry * entry)462 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
463 {
464 FREE((void *)entry->key);
465 FREE(entry->data);
466 }
467
si_init_shader_cache(struct si_screen * sscreen)468 bool si_init_shader_cache(struct si_screen *sscreen)
469 {
470 (void)simple_mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
471 sscreen->shader_cache =
472 _mesa_hash_table_create(NULL, si_shader_cache_key_hash, si_shader_cache_key_equals);
473 sscreen->shader_cache_size = 0;
474 /* Maximum size: 64MB on 32 bits, 1GB else */
475 sscreen->shader_cache_max_size = ((sizeof(void *) == 4) ? 64 : 1024) * 1024 * 1024;
476
477 return sscreen->shader_cache != NULL;
478 }
479
si_destroy_shader_cache(struct si_screen * sscreen)480 void si_destroy_shader_cache(struct si_screen *sscreen)
481 {
482 if (sscreen->shader_cache)
483 _mesa_hash_table_destroy(sscreen->shader_cache, si_destroy_shader_cache_entry);
484 simple_mtx_destroy(&sscreen->shader_cache_mutex);
485 }
486
487 /* SHADER STATES */
488
si_shader_encode_vgprs(struct si_shader * shader)489 unsigned si_shader_encode_vgprs(struct si_shader *shader)
490 {
491 assert(shader->selector->screen->info.gfx_level >= GFX10 || shader->wave_size == 64);
492 return shader->config.num_vgprs / (shader->wave_size == 32 ? 8 : 4) - 1;
493 }
494
si_shader_encode_sgprs(struct si_shader * shader)495 unsigned si_shader_encode_sgprs(struct si_shader *shader)
496 {
497 if (shader->selector->screen->info.gfx_level >= GFX10)
498 return 0; /* Gfx10+ don't have the SGPRS field and always allocate 128 SGPRs. */
499
500 return shader->config.num_sgprs / 8 - 1;
501 }
502
si_shader_mem_ordered(struct si_shader * shader)503 bool si_shader_mem_ordered(struct si_shader *shader)
504 {
505 struct si_screen *sscreen = shader->selector->screen;
506
507 if (sscreen->info.gfx_level < GFX10 || sscreen->info.gfx_level >= GFX12)
508 return false;
509
510 /* Return true if both types of VMEM that return something are used. */
511 return shader->info.uses_vmem_sampler_or_bvh &&
512 (shader->info.uses_vmem_load_other ||
513 shader->config.scratch_bytes_per_wave);
514 }
515
si_set_tesseval_regs(struct si_screen * sscreen,const struct si_shader_selector * tes,struct si_shader * shader)516 static void si_set_tesseval_regs(struct si_screen *sscreen, const struct si_shader_selector *tes,
517 struct si_shader *shader)
518 {
519 const struct si_shader_info *info = &tes->info;
520 enum tess_primitive_mode tes_prim_mode = info->base.tess._primitive_mode;
521 unsigned tes_spacing = info->base.tess.spacing;
522 bool tes_vertex_order_cw = !info->base.tess.ccw;
523 bool tes_point_mode = info->base.tess.point_mode;
524 unsigned type, partitioning, topology, distribution_mode;
525
526 switch (tes_prim_mode) {
527 case TESS_PRIMITIVE_ISOLINES:
528 type = V_028B6C_TESS_ISOLINE;
529 break;
530 case TESS_PRIMITIVE_TRIANGLES:
531 type = V_028B6C_TESS_TRIANGLE;
532 break;
533 case TESS_PRIMITIVE_QUADS:
534 type = V_028B6C_TESS_QUAD;
535 break;
536 default:
537 assert(0);
538 return;
539 }
540
541 switch (tes_spacing) {
542 case TESS_SPACING_FRACTIONAL_ODD:
543 partitioning = V_028B6C_PART_FRAC_ODD;
544 break;
545 case TESS_SPACING_FRACTIONAL_EVEN:
546 partitioning = V_028B6C_PART_FRAC_EVEN;
547 break;
548 case TESS_SPACING_EQUAL:
549 partitioning = V_028B6C_PART_INTEGER;
550 break;
551 default:
552 assert(0);
553 return;
554 }
555
556 if (tes_point_mode)
557 topology = V_028B6C_OUTPUT_POINT;
558 else if (tes_prim_mode == TESS_PRIMITIVE_ISOLINES)
559 topology = V_028B6C_OUTPUT_LINE;
560 else if (tes_vertex_order_cw)
561 /* for some reason, this must be the other way around */
562 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
563 else
564 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
565
566 if (sscreen->info.has_distributed_tess) {
567 if (sscreen->info.family == CHIP_FIJI || sscreen->info.family >= CHIP_POLARIS10)
568 distribution_mode = V_028B6C_TRAPEZOIDS;
569 else
570 distribution_mode = V_028B6C_DONUTS;
571 } else
572 distribution_mode = V_028B6C_NO_DIST;
573
574 shader->vgt_tf_param = S_028B6C_TYPE(type) | S_028B6C_PARTITIONING(partitioning) |
575 S_028B6C_TOPOLOGY(topology) |
576 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
577
578 if (sscreen->info.gfx_level >= GFX12)
579 shader->vgt_tf_param |= S_028AA4_TEMPORAL(gfx12_load_last_use_discard);
580 }
581
582 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
583 * whether the "fractional odd" tessellation spacing is used.
584 *
585 * Possible VGT configurations and which state should set the register:
586 *
587 * Reg set in | VGT shader configuration | Value
588 * ------------------------------------------------------
589 * VS as VS | VS | 30
590 * VS as ES | ES -> GS -> VS | 30
591 * TES as VS | LS -> HS -> VS | 14 or 30
592 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
593 */
polaris_set_vgt_vertex_reuse(struct si_screen * sscreen,struct si_shader_selector * sel,struct si_shader * shader)594 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen, struct si_shader_selector *sel,
595 struct si_shader *shader)
596 {
597 if (sscreen->info.family < CHIP_POLARIS10 || sscreen->info.gfx_level >= GFX10)
598 return;
599
600 /* VS as VS, or VS as ES: */
601 if ((sel->stage == MESA_SHADER_VERTEX &&
602 (!shader->key.ge.as_ls && !shader->is_gs_copy_shader)) ||
603 /* TES as VS, or TES as ES: */
604 sel->stage == MESA_SHADER_TESS_EVAL) {
605 unsigned vtx_reuse_depth = 30;
606
607 if (sel->stage == MESA_SHADER_TESS_EVAL &&
608 sel->info.base.tess.spacing == TESS_SPACING_FRACTIONAL_ODD)
609 vtx_reuse_depth = 14;
610
611 shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
612 }
613 }
614
615 static struct si_pm4_state *
si_get_shader_pm4_state(struct si_shader * shader,void (* emit_func)(struct si_context * ctx,unsigned index))616 si_get_shader_pm4_state(struct si_shader *shader,
617 void (*emit_func)(struct si_context *ctx, unsigned index))
618 {
619 si_pm4_clear_state(&shader->pm4, shader->selector->screen, false);
620 shader->pm4.atom.emit = emit_func;
621 return &shader->pm4;
622 }
623
si_get_num_vs_user_sgprs(struct si_shader * shader,unsigned num_always_on_user_sgprs)624 static unsigned si_get_num_vs_user_sgprs(struct si_shader *shader,
625 unsigned num_always_on_user_sgprs)
626 {
627 struct si_shader_selector *vs =
628 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
629 unsigned num_vbos_in_user_sgprs = vs->info.num_vbos_in_user_sgprs;
630
631 /* 1 SGPR is reserved for the vertex buffer pointer. */
632 assert(num_always_on_user_sgprs <= SI_SGPR_VS_VB_DESCRIPTOR_FIRST - 1);
633
634 if (num_vbos_in_user_sgprs)
635 return SI_SGPR_VS_VB_DESCRIPTOR_FIRST + num_vbos_in_user_sgprs * 4;
636
637 /* Add the pointer to VBO descriptors. */
638 return num_always_on_user_sgprs + 1;
639 }
640
641 /* Return VGPR_COMP_CNT for the API vertex shader. This can be hw LS, LSHS, ES, ESGS, VS. */
si_get_vs_vgpr_comp_cnt(struct si_screen * sscreen,struct si_shader * shader,bool legacy_vs_prim_id)642 static unsigned si_get_vs_vgpr_comp_cnt(struct si_screen *sscreen, struct si_shader *shader,
643 bool legacy_vs_prim_id)
644 {
645 assert(shader->selector->stage == MESA_SHADER_VERTEX ||
646 (shader->previous_stage_sel && shader->previous_stage_sel->stage == MESA_SHADER_VERTEX));
647
648 /* GFX6-9 LS (VertexID, RelAutoIndex, InstanceID / StepRate0, InstanceID)
649 * GFX6-9 ES,VS (VertexID, InstanceID / StepRate0, VSPrimID, InstanceID)
650 * GFX10-11 LS (VertexID, RelAutoIndex, UserVGPR1, UserVGPR2 or InstanceID)
651 * GFX10-11 ES,VS (VertexID, UserVGPR1, UserVGPR2 or VSPrimID, UserVGPR3 or InstanceID)
652 * GFX12 LS,ES (VertexID, InstanceID)
653 */
654 bool is_ls = shader->selector->stage == MESA_SHADER_TESS_CTRL || shader->key.ge.as_ls;
655 unsigned max = 0;
656
657 if (shader->info.uses_instanceid) {
658 if (sscreen->info.gfx_level >= GFX12)
659 max = MAX2(max, 1);
660 else if (sscreen->info.gfx_level >= GFX10)
661 max = MAX2(max, 3);
662 else if (is_ls)
663 max = MAX2(max, 2); /* use (InstanceID / StepRate0) because StepRate0 == 1 */
664 else
665 max = MAX2(max, 1); /* use (InstanceID / StepRate0) because StepRate0 == 1 */
666 }
667
668 if (legacy_vs_prim_id)
669 max = MAX2(max, 2); /* VSPrimID */
670
671 /* GFX11: We prefer to compute RelAutoIndex using (WaveID * WaveSize + ThreadID).
672 * Older chips didn't have WaveID in LS.
673 * GFX12 doesn't have RelAutoIndex.
674 */
675 if (is_ls && sscreen->info.gfx_level <= GFX10_3)
676 max = MAX2(max, 1); /* RelAutoIndex */
677
678 return max;
679 }
680
si_shader_ls(struct si_screen * sscreen,struct si_shader * shader)681 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
682 {
683 struct si_pm4_state *pm4;
684 uint64_t va;
685
686 assert(sscreen->info.gfx_level <= GFX8);
687
688 pm4 = si_get_shader_pm4_state(shader, NULL);
689 if (!pm4)
690 return;
691
692 va = shader->bo->gpu_address;
693 ac_pm4_set_reg(&pm4->base, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
694
695 shader->config.rsrc1 = S_00B528_VGPRS(si_shader_encode_vgprs(shader)) |
696 S_00B528_SGPRS(si_shader_encode_sgprs(shader)) |
697 S_00B528_VGPR_COMP_CNT(si_get_vs_vgpr_comp_cnt(sscreen, shader, false)) |
698 S_00B528_DX10_CLAMP(1) |
699 S_00B528_FLOAT_MODE(shader->config.float_mode);
700 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR)) |
701 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
702 ac_pm4_finalize(&pm4->base);
703 }
704
si_shader_hs(struct si_screen * sscreen,struct si_shader * shader)705 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
706 {
707 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader, NULL);
708 if (!pm4)
709 return;
710
711 uint64_t va = shader->bo->gpu_address;
712 unsigned num_user_sgprs = sscreen->info.gfx_level >= GFX9 ?
713 si_get_num_vs_user_sgprs(shader, GFX9_TCS_NUM_USER_SGPR) :
714 GFX6_TCS_NUM_USER_SGPR;
715
716 if (sscreen->info.gfx_level >= GFX12) {
717 ac_pm4_set_reg(&pm4->base, R_00B420_SPI_SHADER_PGM_RSRC4_HS,
718 S_00B420_WAVE_LIMIT(0x3ff) |
719 S_00B420_GLG_FORCE_DISABLE(1) |
720 S_00B420_INST_PREF_SIZE(si_get_shader_prefetch_size(shader)));
721
722 ac_pm4_set_reg(&pm4->base, R_00B424_SPI_SHADER_PGM_LO_LS, va >> 8);
723 } else if (sscreen->info.gfx_level >= GFX11) {
724 ac_pm4_set_reg_idx3(&pm4->base, R_00B404_SPI_SHADER_PGM_RSRC4_HS,
725 ac_apply_cu_en(S_00B404_INST_PREF_SIZE(si_get_shader_prefetch_size(shader)) |
726 S_00B404_CU_EN(0xffff),
727 C_00B404_CU_EN, 16, &sscreen->info));
728
729 ac_pm4_set_reg(&pm4->base, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
730 } else if (sscreen->info.gfx_level >= GFX10) {
731 ac_pm4_set_reg(&pm4->base, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
732 } else if (sscreen->info.gfx_level >= GFX9) {
733 ac_pm4_set_reg(&pm4->base, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
734 } else {
735 ac_pm4_set_reg(&pm4->base, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
736 ac_pm4_set_reg(&pm4->base, R_00B424_SPI_SHADER_PGM_HI_HS,
737 S_00B424_MEM_BASE(sscreen->info.address32_hi >> 8));
738 }
739
740 ac_pm4_set_reg(&pm4->base, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
741 S_00B428_VGPRS(si_shader_encode_vgprs(shader)) |
742 S_00B428_SGPRS(si_shader_encode_sgprs(shader)) |
743 S_00B428_DX10_CLAMP(sscreen->info.gfx_level < GFX12) |
744 S_00B428_MEM_ORDERED(si_shader_mem_ordered(shader)) |
745 S_00B428_FLOAT_MODE(shader->config.float_mode) |
746 S_00B428_LS_VGPR_COMP_CNT(sscreen->info.gfx_level >= GFX9 ?
747 si_get_vs_vgpr_comp_cnt(sscreen, shader, false) : 0));
748
749 shader->config.rsrc2 = S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
750 S_00B42C_USER_SGPR(num_user_sgprs);
751
752 if (sscreen->info.gfx_level >= GFX10)
753 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
754 else if (sscreen->info.gfx_level >= GFX9)
755 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
756 else
757 shader->config.rsrc2 |= S_00B42C_OC_LDS_EN(1);
758
759 if (sscreen->info.gfx_level <= GFX8)
760 ac_pm4_set_reg(&pm4->base, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, shader->config.rsrc2);
761
762 ac_pm4_finalize(&pm4->base);
763 }
764
si_emit_shader_es(struct si_context * sctx,unsigned index)765 static void si_emit_shader_es(struct si_context *sctx, unsigned index)
766 {
767 struct si_shader *shader = sctx->queued.named.es;
768
769 radeon_begin(&sctx->gfx_cs);
770 radeon_opt_set_context_reg(R_028AAC_VGT_ESGS_RING_ITEMSIZE,
771 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
772 shader->selector->info.esgs_vertex_stride / 4);
773
774 if (shader->selector->stage == MESA_SHADER_TESS_EVAL)
775 radeon_opt_set_context_reg(R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
776 shader->vgt_tf_param);
777
778 if (shader->vgt_vertex_reuse_block_cntl)
779 radeon_opt_set_context_reg(R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
780 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
781 shader->vgt_vertex_reuse_block_cntl);
782 radeon_end_update_context_roll();
783 }
784
si_shader_es(struct si_screen * sscreen,struct si_shader * shader)785 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
786 {
787 struct si_pm4_state *pm4;
788 unsigned num_user_sgprs;
789 unsigned vgpr_comp_cnt;
790 uint64_t va;
791 unsigned oc_lds_en;
792
793 assert(sscreen->info.gfx_level <= GFX8);
794
795 pm4 = si_get_shader_pm4_state(shader, si_emit_shader_es);
796 if (!pm4)
797 return;
798
799 va = shader->bo->gpu_address;
800
801 if (shader->selector->stage == MESA_SHADER_VERTEX) {
802 vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
803 num_user_sgprs = si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR);
804 } else if (shader->selector->stage == MESA_SHADER_TESS_EVAL) {
805 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
806 num_user_sgprs = SI_TES_NUM_USER_SGPR;
807 } else
808 unreachable("invalid shader selector type");
809
810 oc_lds_en = shader->selector->stage == MESA_SHADER_TESS_EVAL ? 1 : 0;
811
812 ac_pm4_set_reg(&pm4->base, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
813 ac_pm4_set_reg(&pm4->base, R_00B324_SPI_SHADER_PGM_HI_ES,
814 S_00B324_MEM_BASE(sscreen->info.address32_hi >> 8));
815 ac_pm4_set_reg(&pm4->base, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
816 S_00B328_VGPRS(si_shader_encode_vgprs(shader)) |
817 S_00B328_SGPRS(si_shader_encode_sgprs(shader)) |
818 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
819 S_00B328_DX10_CLAMP(1) |
820 S_00B328_FLOAT_MODE(shader->config.float_mode));
821 ac_pm4_set_reg(&pm4->base, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
822 S_00B32C_USER_SGPR(num_user_sgprs) | S_00B32C_OC_LDS_EN(oc_lds_en) |
823 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
824
825 if (shader->selector->stage == MESA_SHADER_TESS_EVAL)
826 si_set_tesseval_regs(sscreen, shader->selector, shader);
827
828 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader);
829 ac_pm4_finalize(&pm4->base);
830 }
831
gfx9_get_gs_info(struct si_shader_selector * es,struct si_shader_selector * gs,struct gfx9_gs_info * out)832 void gfx9_get_gs_info(struct si_shader_selector *es, struct si_shader_selector *gs,
833 struct gfx9_gs_info *out)
834 {
835 unsigned gs_num_invocations = MAX2(gs->info.base.gs.invocations, 1);
836 unsigned input_prim = gs->info.base.gs.input_primitive;
837 bool uses_adjacency =
838 input_prim >= MESA_PRIM_LINES_ADJACENCY && input_prim <= MESA_PRIM_TRIANGLE_STRIP_ADJACENCY;
839
840 /* All these are in dwords: */
841 /* We can't allow using the whole LDS, because GS waves compete with
842 * other shader stages for LDS space. */
843 const unsigned max_lds_size = 8 * 1024;
844 const unsigned esgs_itemsize = es->info.esgs_vertex_stride / 4;
845 unsigned esgs_lds_size;
846
847 /* All these are per subgroup: */
848 const unsigned max_out_prims = 32 * 1024;
849 const unsigned max_es_verts = 255;
850 const unsigned ideal_gs_prims = 64;
851 unsigned max_gs_prims, gs_prims;
852 unsigned min_es_verts, es_verts, worst_case_es_verts;
853
854 if (uses_adjacency || gs_num_invocations > 1)
855 max_gs_prims = 127 / gs_num_invocations;
856 else
857 max_gs_prims = 255;
858
859 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
860 * Make sure we don't go over the maximum value.
861 */
862 if (gs->info.base.gs.vertices_out > 0) {
863 max_gs_prims =
864 MIN2(max_gs_prims, max_out_prims / (gs->info.base.gs.vertices_out * gs_num_invocations));
865 }
866 assert(max_gs_prims > 0);
867
868 /* If the primitive has adjacency, halve the number of vertices
869 * that will be reused in multiple primitives.
870 */
871 min_es_verts = gs->info.gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
872
873 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
874 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
875
876 /* Compute ESGS LDS size based on the worst case number of ES vertices
877 * needed to create the target number of GS prims per subgroup.
878 */
879 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
880
881 /* If total LDS usage is too big, refactor partitions based on ratio
882 * of ESGS item sizes.
883 */
884 if (esgs_lds_size > max_lds_size) {
885 /* Our target GS Prims Per Subgroup was too large. Calculate
886 * the maximum number of GS Prims Per Subgroup that will fit
887 * into LDS, capped by the maximum that the hardware can support.
888 */
889 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)), max_gs_prims);
890 assert(gs_prims > 0);
891 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
892
893 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
894 assert(esgs_lds_size <= max_lds_size);
895 }
896
897 /* Now calculate remaining ESGS information. */
898 if (esgs_lds_size)
899 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
900 else
901 es_verts = max_es_verts;
902
903 /* Vertices for adjacency primitives are not always reused, so restore
904 * it for ES_VERTS_PER_SUBGRP.
905 */
906 min_es_verts = gs->info.gs_input_verts_per_prim;
907
908 /* For normal primitives, the VGT only checks if they are past the ES
909 * verts per subgroup after allocating a full GS primitive and if they
910 * are, kick off a new subgroup. But if those additional ES verts are
911 * unique (e.g. not reused) we need to make sure there is enough LDS
912 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
913 */
914 es_verts -= min_es_verts - 1;
915
916 out->es_verts_per_subgroup = es_verts;
917 out->gs_prims_per_subgroup = gs_prims;
918 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
919 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup * gs->info.base.gs.vertices_out;
920 out->esgs_ring_size = esgs_lds_size;
921
922 assert(out->max_prims_per_subgroup <= max_out_prims);
923 }
924
gfx9_set_gs_sgpr_num_es_outputs(struct si_context * sctx,unsigned esgs_vertex_stride)925 static void gfx9_set_gs_sgpr_num_es_outputs(struct si_context *sctx, unsigned esgs_vertex_stride)
926 {
927 /* The stride must always be odd (e.g. a multiple of 4 + 1) to reduce LDS bank conflicts. */
928 assert(esgs_vertex_stride % 4 == 1);
929 unsigned num_es_outputs = (esgs_vertex_stride - 1) / 4;
930
931 /* If there are no ES outputs, GS doesn't use this SGPR field, so only set it if the number
932 * is non-zero.
933 */
934 if (num_es_outputs)
935 SET_FIELD(sctx->current_gs_state, GS_STATE_NUM_ES_OUTPUTS, num_es_outputs);
936 }
937
si_emit_shader_gs(struct si_context * sctx,unsigned index)938 static void si_emit_shader_gs(struct si_context *sctx, unsigned index)
939 {
940 struct si_shader *shader = sctx->queued.named.gs;
941
942 if (sctx->gfx_level >= GFX9)
943 gfx9_set_gs_sgpr_num_es_outputs(sctx, shader->key.ge.part.gs.es->info.esgs_vertex_stride / 4);
944
945 radeon_begin(&sctx->gfx_cs);
946
947 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
948 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
949 radeon_opt_set_context_reg3(
950 R_028A60_VGT_GSVS_RING_OFFSET_1, SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
951 shader->gs.vgt_gsvs_ring_offset_1, shader->gs.vgt_gsvs_ring_offset_2,
952 shader->gs.vgt_gsvs_ring_offset_3);
953
954 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
955 radeon_opt_set_context_reg(R_028AB0_VGT_GSVS_RING_ITEMSIZE,
956 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
957 shader->gs.vgt_gsvs_ring_itemsize);
958
959 /* R_028B38_VGT_GS_MAX_VERT_OUT */
960 radeon_opt_set_context_reg(R_028B38_VGT_GS_MAX_VERT_OUT, SI_TRACKED_VGT_GS_MAX_VERT_OUT,
961 shader->gs.vgt_gs_max_vert_out);
962
963 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
964 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
965 radeon_opt_set_context_reg4(
966 R_028B5C_VGT_GS_VERT_ITEMSIZE, SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
967 shader->gs.vgt_gs_vert_itemsize, shader->gs.vgt_gs_vert_itemsize_1,
968 shader->gs.vgt_gs_vert_itemsize_2, shader->gs.vgt_gs_vert_itemsize_3);
969
970 /* R_028B90_VGT_GS_INSTANCE_CNT */
971 radeon_opt_set_context_reg(R_028B90_VGT_GS_INSTANCE_CNT, SI_TRACKED_VGT_GS_INSTANCE_CNT,
972 shader->gs.vgt_gs_instance_cnt);
973
974 if (sctx->gfx_level >= GFX9) {
975 /* R_028A44_VGT_GS_ONCHIP_CNTL */
976 radeon_opt_set_context_reg(R_028A44_VGT_GS_ONCHIP_CNTL, SI_TRACKED_VGT_GS_ONCHIP_CNTL,
977 shader->gs.vgt_gs_onchip_cntl);
978 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
979 if (sctx->gfx_level == GFX9) {
980 radeon_opt_set_context_reg(R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
981 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
982 shader->gs.vgt_gs_max_prims_per_subgroup);
983 }
984
985 if (shader->key.ge.part.gs.es->stage == MESA_SHADER_TESS_EVAL)
986 radeon_opt_set_context_reg(R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
987 shader->vgt_tf_param);
988 if (shader->vgt_vertex_reuse_block_cntl)
989 radeon_opt_set_context_reg(R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
990 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
991 shader->vgt_vertex_reuse_block_cntl);
992 }
993 radeon_end_update_context_roll();
994
995 /* These don't cause any context rolls. */
996 radeon_begin_again(&sctx->gfx_cs);
997 if (sctx->gfx_level >= GFX7) {
998 if (sctx->screen->info.uses_kernel_cu_mask) {
999 radeon_opt_set_sh_reg_idx(R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
1000 SI_TRACKED_SPI_SHADER_PGM_RSRC3_GS,
1001 3, shader->gs.spi_shader_pgm_rsrc3_gs);
1002 } else {
1003 radeon_opt_set_sh_reg(R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
1004 SI_TRACKED_SPI_SHADER_PGM_RSRC3_GS,
1005 shader->gs.spi_shader_pgm_rsrc3_gs);
1006 }
1007 }
1008 if (sctx->gfx_level >= GFX10) {
1009 if (sctx->screen->info.uses_kernel_cu_mask) {
1010 radeon_opt_set_sh_reg_idx(R_00B204_SPI_SHADER_PGM_RSRC4_GS,
1011 SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS,
1012 3, shader->gs.spi_shader_pgm_rsrc4_gs);
1013 } else {
1014 radeon_opt_set_sh_reg(R_00B204_SPI_SHADER_PGM_RSRC4_GS,
1015 SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS,
1016 shader->gs.spi_shader_pgm_rsrc4_gs);
1017 }
1018 }
1019 radeon_end();
1020 }
1021
si_shader_gs(struct si_screen * sscreen,struct si_shader * shader)1022 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
1023 {
1024 struct si_shader_selector *sel = shader->selector;
1025 const uint8_t *num_components = sel->info.num_stream_output_components;
1026 unsigned gs_num_invocations = sel->info.base.gs.invocations;
1027 struct si_pm4_state *pm4;
1028 uint64_t va;
1029 unsigned max_stream = util_last_bit(sel->info.base.gs.active_stream_mask);
1030 unsigned offset;
1031
1032 assert(sscreen->info.gfx_level < GFX11); /* gfx11 doesn't have the legacy pipeline */
1033
1034 pm4 = si_get_shader_pm4_state(shader, si_emit_shader_gs);
1035 if (!pm4)
1036 return;
1037
1038 offset = num_components[0] * sel->info.base.gs.vertices_out;
1039 shader->gs.vgt_gsvs_ring_offset_1 = offset;
1040
1041 if (max_stream >= 2)
1042 offset += num_components[1] * sel->info.base.gs.vertices_out;
1043 shader->gs.vgt_gsvs_ring_offset_2 = offset;
1044
1045 if (max_stream >= 3)
1046 offset += num_components[2] * sel->info.base.gs.vertices_out;
1047 shader->gs.vgt_gsvs_ring_offset_3 = offset;
1048
1049 if (max_stream >= 4)
1050 offset += num_components[3] * sel->info.base.gs.vertices_out;
1051 shader->gs.vgt_gsvs_ring_itemsize = offset;
1052
1053 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
1054 assert(offset < (1 << 15));
1055
1056 shader->gs.vgt_gs_max_vert_out = sel->info.base.gs.vertices_out;
1057
1058 shader->gs.vgt_gs_vert_itemsize = num_components[0];
1059 shader->gs.vgt_gs_vert_itemsize_1 = (max_stream >= 2) ? num_components[1] : 0;
1060 shader->gs.vgt_gs_vert_itemsize_2 = (max_stream >= 3) ? num_components[2] : 0;
1061 shader->gs.vgt_gs_vert_itemsize_3 = (max_stream >= 4) ? num_components[3] : 0;
1062
1063 shader->gs.vgt_gs_instance_cnt =
1064 S_028B90_CNT(MIN2(gs_num_invocations, 127)) | S_028B90_ENABLE(gs_num_invocations > 0);
1065
1066 /* Copy over fields from the GS copy shader to make them easily accessible from GS. */
1067 shader->pa_cl_vs_out_cntl = shader->gs_copy_shader->pa_cl_vs_out_cntl;
1068
1069 va = shader->bo->gpu_address;
1070
1071 if (sscreen->info.gfx_level >= GFX9) {
1072 unsigned input_prim = sel->info.base.gs.input_primitive;
1073 gl_shader_stage es_stage = shader->key.ge.part.gs.es->stage;
1074 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
1075
1076 if (es_stage == MESA_SHADER_VERTEX) {
1077 es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
1078 } else if (es_stage == MESA_SHADER_TESS_EVAL)
1079 es_vgpr_comp_cnt = shader->key.ge.part.gs.es->info.uses_primid ? 3 : 2;
1080 else
1081 unreachable("invalid shader selector type");
1082
1083 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1084 * VGPR[0:4] are always loaded.
1085 */
1086 if (sel->info.uses_invocationid)
1087 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
1088 else if (sel->info.uses_primid)
1089 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1090 else if (input_prim >= MESA_PRIM_TRIANGLES)
1091 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1092 else
1093 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1094
1095 unsigned num_user_sgprs;
1096 if (es_stage == MESA_SHADER_VERTEX)
1097 num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_GS_NUM_USER_SGPR);
1098 else
1099 num_user_sgprs = GFX9_GS_NUM_USER_SGPR;
1100
1101 if (sscreen->info.gfx_level >= GFX10) {
1102 ac_pm4_set_reg(&pm4->base, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
1103 } else {
1104 ac_pm4_set_reg(&pm4->base, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
1105 }
1106
1107 uint32_t rsrc1 = S_00B228_VGPRS(si_shader_encode_vgprs(shader)) |
1108 S_00B228_SGPRS(si_shader_encode_sgprs(shader)) |
1109 S_00B228_DX10_CLAMP(1) |
1110 S_00B228_MEM_ORDERED(si_shader_mem_ordered(shader)) |
1111 S_00B228_FLOAT_MODE(shader->config.float_mode) |
1112 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
1113 uint32_t rsrc2 = S_00B22C_USER_SGPR(num_user_sgprs) |
1114 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1115 S_00B22C_OC_LDS_EN(es_stage == MESA_SHADER_TESS_EVAL) |
1116 S_00B22C_LDS_SIZE(shader->config.lds_size) |
1117 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
1118
1119 if (sscreen->info.gfx_level >= GFX10) {
1120 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
1121 } else {
1122 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
1123 }
1124
1125 ac_pm4_set_reg(&pm4->base, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1);
1126 ac_pm4_set_reg(&pm4->base, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);
1127
1128 shader->gs.spi_shader_pgm_rsrc3_gs =
1129 ac_apply_cu_en(S_00B21C_CU_EN(0xffff) |
1130 S_00B21C_WAVE_LIMIT(0x3F),
1131 C_00B21C_CU_EN, 0, &sscreen->info);
1132 shader->gs.spi_shader_pgm_rsrc4_gs =
1133 ac_apply_cu_en(S_00B204_CU_EN_GFX10(0xffff) |
1134 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(0),
1135 C_00B204_CU_EN_GFX10, 16, &sscreen->info);
1136
1137 shader->gs.vgt_gs_onchip_cntl =
1138 S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) |
1139 S_028A44_GS_PRIMS_PER_SUBGRP(shader->gs_info.gs_prims_per_subgroup) |
1140 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->gs_info.gs_inst_prims_in_subgroup);
1141 shader->gs.vgt_gs_max_prims_per_subgroup =
1142 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader->gs_info.max_prims_per_subgroup);
1143 shader->gs.vgt_esgs_ring_itemsize = shader->key.ge.part.gs.es->info.esgs_vertex_stride / 4;
1144
1145 if (es_stage == MESA_SHADER_TESS_EVAL)
1146 si_set_tesseval_regs(sscreen, shader->key.ge.part.gs.es, shader);
1147
1148 polaris_set_vgt_vertex_reuse(sscreen, shader->key.ge.part.gs.es, shader);
1149 } else {
1150 shader->gs.spi_shader_pgm_rsrc3_gs =
1151 ac_apply_cu_en(S_00B21C_CU_EN(0xffff) |
1152 S_00B21C_WAVE_LIMIT(0x3F),
1153 C_00B21C_CU_EN, 0, &sscreen->info);
1154
1155 ac_pm4_set_reg(&pm4->base, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
1156 ac_pm4_set_reg(&pm4->base, R_00B224_SPI_SHADER_PGM_HI_GS,
1157 S_00B224_MEM_BASE(sscreen->info.address32_hi >> 8));
1158
1159 ac_pm4_set_reg(&pm4->base, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
1160 S_00B228_VGPRS(si_shader_encode_vgprs(shader)) |
1161 S_00B228_SGPRS(si_shader_encode_sgprs(shader)) |
1162 S_00B228_DX10_CLAMP(1) |
1163 S_00B228_FLOAT_MODE(shader->config.float_mode));
1164 ac_pm4_set_reg(&pm4->base, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
1165 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
1166 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1167 }
1168 ac_pm4_finalize(&pm4->base);
1169 }
1170
gfx10_is_ngg_passthrough(struct si_shader * shader)1171 bool gfx10_is_ngg_passthrough(struct si_shader *shader)
1172 {
1173 struct si_shader_selector *sel = shader->selector;
1174
1175 /* Never use NGG passthrough if culling is possible even when it's not used by this shader,
1176 * so that we don't get context rolls when enabling and disabling NGG passthrough.
1177 */
1178 if (sel->screen->use_ngg_culling)
1179 return false;
1180
1181 /* The definition of NGG passthrough is:
1182 * - user GS is turned off (no amplification, no GS instancing, and no culling)
1183 * - VGT_ESGS_RING_ITEMSIZE is ignored (behaving as if it was equal to 1)
1184 * - vertex indices are packed into 1 VGPR
1185 * - Navi23 and later chips can optionally skip the gs_alloc_req message
1186 *
1187 * NGG passthrough still allows the use of LDS.
1188 */
1189 return sel->stage != MESA_SHADER_GEOMETRY && !shader->key.ge.opt.ngg_culling;
1190 }
1191
1192 template <enum si_has_tess HAS_TESS>
gfx10_emit_shader_ngg(struct si_context * sctx,unsigned index)1193 static void gfx10_emit_shader_ngg(struct si_context *sctx, unsigned index)
1194 {
1195 struct si_shader *shader = sctx->queued.named.gs;
1196
1197 if (shader->selector->stage == MESA_SHADER_GEOMETRY)
1198 gfx9_set_gs_sgpr_num_es_outputs(sctx, shader->ngg.esgs_vertex_stride);
1199
1200 radeon_begin(&sctx->gfx_cs);
1201 if (HAS_TESS) {
1202 radeon_opt_set_context_reg(R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
1203 shader->vgt_tf_param);
1204 }
1205 radeon_opt_set_context_reg(R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
1206 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
1207 shader->ngg.ge_max_output_per_subgroup);
1208 radeon_opt_set_context_reg(R_028B4C_GE_NGG_SUBGRP_CNTL, SI_TRACKED_GE_NGG_SUBGRP_CNTL,
1209 shader->ngg.ge_ngg_subgrp_cntl);
1210 radeon_opt_set_context_reg(R_028A84_VGT_PRIMITIVEID_EN, SI_TRACKED_VGT_PRIMITIVEID_EN,
1211 shader->ngg.vgt_primitiveid_en);
1212 if (sctx->gfx_level < GFX11) {
1213 radeon_opt_set_context_reg(R_028A44_VGT_GS_ONCHIP_CNTL, SI_TRACKED_VGT_GS_ONCHIP_CNTL,
1214 shader->ngg.vgt_gs_onchip_cntl);
1215 }
1216 radeon_opt_set_context_reg(R_028B38_VGT_GS_MAX_VERT_OUT, SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1217 shader->ngg.vgt_gs_max_vert_out);
1218 radeon_opt_set_context_reg(R_028B90_VGT_GS_INSTANCE_CNT, SI_TRACKED_VGT_GS_INSTANCE_CNT,
1219 shader->ngg.vgt_gs_instance_cnt);
1220 radeon_opt_set_context_reg(R_0286C4_SPI_VS_OUT_CONFIG, SI_TRACKED_SPI_VS_OUT_CONFIG,
1221 shader->ngg.spi_vs_out_config);
1222 radeon_opt_set_context_reg(R_02870C_SPI_SHADER_POS_FORMAT,
1223 SI_TRACKED_SPI_SHADER_POS_FORMAT,
1224 shader->ngg.spi_shader_pos_format);
1225 radeon_opt_set_context_reg(R_028818_PA_CL_VTE_CNTL, SI_TRACKED_PA_CL_VTE_CNTL,
1226 shader->ngg.pa_cl_vte_cntl);
1227 radeon_end_update_context_roll();
1228
1229 /* These don't cause a context roll. */
1230 radeon_begin_again(&sctx->gfx_cs);
1231 if (sctx->screen->info.uses_kernel_cu_mask) {
1232 radeon_opt_set_sh_reg_idx(R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
1233 SI_TRACKED_SPI_SHADER_PGM_RSRC3_GS,
1234 3, shader->ngg.spi_shader_pgm_rsrc3_gs);
1235 radeon_opt_set_sh_reg_idx(R_00B204_SPI_SHADER_PGM_RSRC4_GS,
1236 SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS,
1237 3, shader->ngg.spi_shader_pgm_rsrc4_gs);
1238 } else {
1239 radeon_opt_set_sh_reg(R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
1240 SI_TRACKED_SPI_SHADER_PGM_RSRC3_GS,
1241 shader->ngg.spi_shader_pgm_rsrc3_gs);
1242 radeon_opt_set_sh_reg(R_00B204_SPI_SHADER_PGM_RSRC4_GS,
1243 SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS,
1244 shader->ngg.spi_shader_pgm_rsrc4_gs);
1245 }
1246 radeon_opt_set_uconfig_reg(R_030980_GE_PC_ALLOC, SI_TRACKED_GE_PC_ALLOC,
1247 shader->ngg.ge_pc_alloc);
1248 radeon_end();
1249 }
1250
1251 template <enum si_has_tess HAS_TESS>
gfx11_dgpu_emit_shader_ngg(struct si_context * sctx,unsigned index)1252 static void gfx11_dgpu_emit_shader_ngg(struct si_context *sctx, unsigned index)
1253 {
1254 struct si_shader *shader = sctx->queued.named.gs;
1255
1256 if (shader->selector->stage == MESA_SHADER_GEOMETRY)
1257 gfx9_set_gs_sgpr_num_es_outputs(sctx, shader->ngg.esgs_vertex_stride);
1258
1259 radeon_begin(&sctx->gfx_cs);
1260 gfx11_begin_packed_context_regs();
1261 if (HAS_TESS) {
1262 gfx11_opt_set_context_reg(R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
1263 shader->vgt_tf_param);
1264 }
1265 gfx11_opt_set_context_reg(R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
1266 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
1267 shader->ngg.ge_max_output_per_subgroup);
1268 gfx11_opt_set_context_reg(R_028B4C_GE_NGG_SUBGRP_CNTL, SI_TRACKED_GE_NGG_SUBGRP_CNTL,
1269 shader->ngg.ge_ngg_subgrp_cntl);
1270 gfx11_opt_set_context_reg(R_028A84_VGT_PRIMITIVEID_EN, SI_TRACKED_VGT_PRIMITIVEID_EN,
1271 shader->ngg.vgt_primitiveid_en);
1272 gfx11_opt_set_context_reg(R_028B38_VGT_GS_MAX_VERT_OUT, SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1273 shader->ngg.vgt_gs_max_vert_out);
1274 gfx11_opt_set_context_reg(R_028B90_VGT_GS_INSTANCE_CNT, SI_TRACKED_VGT_GS_INSTANCE_CNT,
1275 shader->ngg.vgt_gs_instance_cnt);
1276 gfx11_opt_set_context_reg(R_0286C4_SPI_VS_OUT_CONFIG, SI_TRACKED_SPI_VS_OUT_CONFIG,
1277 shader->ngg.spi_vs_out_config);
1278 gfx11_opt_set_context_reg(R_02870C_SPI_SHADER_POS_FORMAT, SI_TRACKED_SPI_SHADER_POS_FORMAT,
1279 shader->ngg.spi_shader_pos_format);
1280 gfx11_opt_set_context_reg(R_028818_PA_CL_VTE_CNTL, SI_TRACKED_PA_CL_VTE_CNTL,
1281 shader->ngg.pa_cl_vte_cntl);
1282 gfx11_end_packed_context_regs();
1283
1284 assert(!sctx->screen->info.uses_kernel_cu_mask);
1285 if (sctx->screen->info.has_set_sh_pairs_packed) {
1286 gfx11_opt_push_gfx_sh_reg(R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
1287 SI_TRACKED_SPI_SHADER_PGM_RSRC3_GS,
1288 shader->gs.spi_shader_pgm_rsrc3_gs);
1289 gfx11_opt_push_gfx_sh_reg(R_00B204_SPI_SHADER_PGM_RSRC4_GS,
1290 SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS,
1291 shader->gs.spi_shader_pgm_rsrc4_gs);
1292 } else {
1293 if (sctx->screen->info.uses_kernel_cu_mask) {
1294 radeon_opt_set_sh_reg_idx(R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
1295 SI_TRACKED_SPI_SHADER_PGM_RSRC3_GS,
1296 3, shader->ngg.spi_shader_pgm_rsrc3_gs);
1297 radeon_opt_set_sh_reg_idx(R_00B204_SPI_SHADER_PGM_RSRC4_GS,
1298 SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS,
1299 3, shader->ngg.spi_shader_pgm_rsrc4_gs);
1300 } else {
1301 radeon_opt_set_sh_reg(R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
1302 SI_TRACKED_SPI_SHADER_PGM_RSRC3_GS,
1303 shader->ngg.spi_shader_pgm_rsrc3_gs);
1304 radeon_opt_set_sh_reg(R_00B204_SPI_SHADER_PGM_RSRC4_GS,
1305 SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS,
1306 shader->ngg.spi_shader_pgm_rsrc4_gs);
1307 }
1308 }
1309
1310 radeon_opt_set_uconfig_reg(R_030980_GE_PC_ALLOC, SI_TRACKED_GE_PC_ALLOC,
1311 shader->ngg.ge_pc_alloc);
1312 radeon_end();
1313 }
1314
1315 template <enum si_has_tess HAS_TESS>
gfx12_emit_shader_ngg(struct si_context * sctx,unsigned index)1316 static void gfx12_emit_shader_ngg(struct si_context *sctx, unsigned index)
1317 {
1318 struct si_shader *shader = sctx->queued.named.gs;
1319
1320 if (shader->selector->stage == MESA_SHADER_GEOMETRY)
1321 gfx9_set_gs_sgpr_num_es_outputs(sctx, shader->ngg.esgs_vertex_stride);
1322
1323 radeon_begin(&sctx->gfx_cs);
1324 gfx12_begin_context_regs();
1325 if (HAS_TESS) {
1326 gfx12_opt_set_context_reg(R_028AA4_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
1327 shader->vgt_tf_param);
1328 }
1329 gfx12_opt_set_context_reg(R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
1330 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
1331 shader->ngg.ge_max_output_per_subgroup);
1332 gfx12_opt_set_context_reg(R_028B4C_GE_NGG_SUBGRP_CNTL, SI_TRACKED_GE_NGG_SUBGRP_CNTL,
1333 shader->ngg.ge_ngg_subgrp_cntl);
1334 gfx12_opt_set_context_reg(R_028B38_VGT_GS_MAX_VERT_OUT, SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1335 shader->ngg.vgt_gs_max_vert_out);
1336 gfx12_opt_set_context_reg(R_028B3C_VGT_GS_INSTANCE_CNT, SI_TRACKED_VGT_GS_INSTANCE_CNT,
1337 shader->ngg.vgt_gs_instance_cnt);
1338 gfx12_opt_set_context_reg(R_02864C_SPI_SHADER_POS_FORMAT, SI_TRACKED_SPI_SHADER_POS_FORMAT,
1339 shader->ngg.spi_shader_pos_format);
1340 gfx12_opt_set_context_reg(R_028814_PA_CL_VTE_CNTL, SI_TRACKED_PA_CL_VTE_CNTL,
1341 shader->ngg.pa_cl_vte_cntl);
1342 gfx12_end_context_regs();
1343
1344 radeon_opt_set_uconfig_reg(R_030988_VGT_PRIMITIVEID_EN,
1345 SI_TRACKED_VGT_PRIMITIVEID_EN_UCONFIG,
1346 shader->ngg.vgt_primitiveid_en);
1347 radeon_end(); /* don't track context rolls on GFX12 */
1348
1349 assert(!sctx->screen->info.uses_kernel_cu_mask);
1350 gfx12_opt_push_gfx_sh_reg(R_00B220_SPI_SHADER_PGM_RSRC4_GS,
1351 SI_TRACKED_SPI_SHADER_PGM_RSRC4_GS,
1352 shader->ngg.spi_shader_pgm_rsrc4_gs);
1353 }
1354
si_get_input_prim(const struct si_shader_selector * gs,const union si_shader_key * key)1355 unsigned si_get_input_prim(const struct si_shader_selector *gs, const union si_shader_key *key)
1356 {
1357 if (gs->stage == MESA_SHADER_GEOMETRY)
1358 return gs->info.base.gs.input_primitive;
1359
1360 if (gs->stage == MESA_SHADER_TESS_EVAL) {
1361 if (gs->info.base.tess.point_mode)
1362 return MESA_PRIM_POINTS;
1363 if (gs->info.base.tess._primitive_mode == TESS_PRIMITIVE_ISOLINES)
1364 return MESA_PRIM_LINES;
1365 return MESA_PRIM_TRIANGLES;
1366 }
1367
1368 if (key->ge.opt.ngg_culling & SI_NGG_CULL_LINES)
1369 return MESA_PRIM_LINES;
1370
1371 return MESA_PRIM_TRIANGLES; /* worst case for all callers */
1372 }
1373
si_get_vs_out_cntl(const struct si_shader_selector * sel,const struct si_shader * shader,bool ngg)1374 static unsigned si_get_vs_out_cntl(const struct si_shader_selector *sel,
1375 const struct si_shader *shader, bool ngg)
1376 {
1377 /* Clip distances can be killed, but cull distances can't. */
1378 unsigned clipcull_mask = (sel->info.clipdist_mask & ~shader->key.ge.opt.kill_clip_distances) |
1379 sel->info.culldist_mask;
1380 bool writes_psize = sel->info.writes_psize && !shader->key.ge.opt.kill_pointsize;
1381 bool writes_layer = sel->info.writes_layer && !shader->key.ge.opt.kill_layer;
1382 bool misc_vec_ena = writes_psize || (sel->info.writes_edgeflag && !ngg) ||
1383 writes_layer || sel->info.writes_viewport_index ||
1384 sel->screen->options.vrs2x2;
1385
1386 return S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipcull_mask & 0x0F) != 0) |
1387 S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipcull_mask & 0xF0) != 0) |
1388 S_02881C_USE_VTX_POINT_SIZE(writes_psize) |
1389 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag && !ngg) |
1390 S_02881C_USE_VTX_VRS_RATE(sel->screen->options.vrs2x2) |
1391 S_02881C_USE_VTX_RENDER_TARGET_INDX(writes_layer) |
1392 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
1393 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
1394 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena ||
1395 (sel->screen->info.gfx_level >= GFX10_3 &&
1396 shader->info.nr_pos_exports > 1));
1397 }
1398
1399 /* Return the number of allocated param exports. This can be more than the number of param
1400 * exports in the shader.
1401 */
si_shader_num_alloc_param_exports(struct si_shader * shader)1402 unsigned si_shader_num_alloc_param_exports(struct si_shader *shader)
1403 {
1404 unsigned num_params = shader->info.nr_param_exports;
1405
1406 /* Since there is no alloc/dealloc mechanism for the 12-bit ordered IDs on GFX12, they can wrap
1407 * around if there are more than 2^12 workgroups, causing 2 workgroups to get the same
1408 * ordered ID, which can deadlock the "ordered add" loop.
1409 *
1410 * The recommended solution is to use the alloc/dealloc mechanism of the attribute ring to limit
1411 * the number of workgroups in flight and thus the number of ordered IDs in flight.
1412 */
1413 if (shader->selector->screen->info.gfx_level >= GFX12 && si_shader_uses_streamout(shader))
1414 num_params = MAX2(num_params, 8);
1415
1416 return num_params;
1417 }
1418
1419 /**
1420 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1421 * in NGG mode.
1422 */
gfx10_shader_ngg(struct si_screen * sscreen,struct si_shader * shader)1423 static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader)
1424 {
1425 const struct si_shader_selector *gs_sel = shader->selector;
1426 const struct si_shader_info *gs_info = &gs_sel->info;
1427 const gl_shader_stage gs_stage = shader->selector->stage;
1428 const struct si_shader_selector *es_sel =
1429 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
1430 const struct si_shader_info *es_info = &es_sel->info;
1431 const gl_shader_stage es_stage = es_sel->stage;
1432 unsigned num_user_sgprs;
1433 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
1434 uint64_t va;
1435 bool window_space = gs_sel->stage == MESA_SHADER_VERTEX ?
1436 gs_info->base.vs.window_space_position : 0;
1437 bool es_enable_prim_id = shader->key.ge.mono.u.vs_export_prim_id || es_info->uses_primid;
1438 unsigned gs_num_invocations = gs_sel->stage == MESA_SHADER_GEOMETRY ?
1439 CLAMP(gs_info->base.gs.invocations, 1, 32) : 0;
1440 unsigned input_prim = si_get_input_prim(gs_sel, &shader->key);
1441 bool break_wave_at_eoi = false;
1442
1443 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader, NULL);
1444 if (!pm4)
1445 return;
1446
1447 if (sscreen->info.gfx_level >= GFX12) {
1448 if (es_stage == MESA_SHADER_TESS_EVAL)
1449 pm4->atom.emit = gfx12_emit_shader_ngg<TESS_ON>;
1450 else
1451 pm4->atom.emit = gfx12_emit_shader_ngg<TESS_OFF>;
1452 } else if (sscreen->info.has_set_context_pairs_packed) {
1453 if (es_stage == MESA_SHADER_TESS_EVAL)
1454 pm4->atom.emit = gfx11_dgpu_emit_shader_ngg<TESS_ON>;
1455 else
1456 pm4->atom.emit = gfx11_dgpu_emit_shader_ngg<TESS_OFF>;
1457 } else {
1458 if (es_stage == MESA_SHADER_TESS_EVAL)
1459 pm4->atom.emit = gfx10_emit_shader_ngg<TESS_ON>;
1460 else
1461 pm4->atom.emit = gfx10_emit_shader_ngg<TESS_OFF>;
1462 }
1463
1464 va = shader->bo->gpu_address;
1465
1466 if (es_stage == MESA_SHADER_VERTEX) {
1467 es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
1468
1469 if (es_info->base.vs.blit_sgprs_amd) {
1470 num_user_sgprs =
1471 SI_SGPR_VS_BLIT_DATA + es_info->base.vs.blit_sgprs_amd;
1472 } else {
1473 num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_GS_NUM_USER_SGPR);
1474 }
1475 } else {
1476 assert(es_stage == MESA_SHADER_TESS_EVAL);
1477 es_vgpr_comp_cnt = es_enable_prim_id ? 3 : 2;
1478 num_user_sgprs = GFX9_GS_NUM_USER_SGPR;
1479
1480 if (es_enable_prim_id || gs_info->uses_primid)
1481 break_wave_at_eoi = true;
1482 }
1483
1484 /* Primitives with adjancency can only occur without tessellation. */
1485 assert(gs_info->gs_input_verts_per_prim <= 3 || es_stage == MESA_SHADER_VERTEX);
1486
1487 if (sscreen->info.gfx_level >= GFX12) {
1488 if (gs_info->gs_input_verts_per_prim >= 4)
1489 gs_vgpr_comp_cnt = 2; /* VGPR2 contains offsets 3-5 */
1490 else if ((gs_stage == MESA_SHADER_GEOMETRY && gs_info->uses_primid) ||
1491 (gs_stage == MESA_SHADER_VERTEX && shader->key.ge.mono.u.vs_export_prim_id))
1492 gs_vgpr_comp_cnt = 1; /* VGPR1 contains PrimitiveID */
1493 else
1494 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0-2, edgeflags, GS invocation ID. */
1495 } else {
1496 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1497 * VGPR[0:4] are always loaded.
1498 *
1499 * Vertex shaders always need to load VGPR3, because they need to
1500 * pass edge flags for decomposed primitives (such as quads) to the PA
1501 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1502 */
1503 if (gs_info->uses_invocationid ||
1504 (gfx10_edgeflags_have_effect(shader) && !gfx10_is_ngg_passthrough(shader)))
1505 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID, edge flags. */
1506 else if ((gs_stage == MESA_SHADER_GEOMETRY && gs_info->uses_primid) ||
1507 (gs_stage == MESA_SHADER_VERTEX && shader->key.ge.mono.u.vs_export_prim_id))
1508 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1509 else if (input_prim >= MESA_PRIM_TRIANGLES && !gfx10_is_ngg_passthrough(shader))
1510 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1511 else
1512 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1513 }
1514
1515 if (sscreen->info.gfx_level >= GFX12) {
1516 ac_pm4_set_reg(&pm4->base, R_00B224_SPI_SHADER_PGM_LO_ES, va >> 8);
1517 } else {
1518 ac_pm4_set_reg(&pm4->base, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
1519 }
1520
1521 ac_pm4_set_reg(&pm4->base, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
1522 S_00B228_VGPRS(si_shader_encode_vgprs(shader)) |
1523 S_00B228_FLOAT_MODE(shader->config.float_mode) |
1524 S_00B228_DX10_CLAMP(sscreen->info.gfx_level < GFX12) |
1525 S_00B228_MEM_ORDERED(si_shader_mem_ordered(shader)) |
1526 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
1527 ac_pm4_set_reg(&pm4->base, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
1528 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
1529 S_00B22C_USER_SGPR(num_user_sgprs) |
1530 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1531 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5) |
1532 S_00B22C_OC_LDS_EN(es_stage == MESA_SHADER_TESS_EVAL) |
1533 S_00B22C_LDS_SIZE(shader->config.lds_size));
1534
1535 /* Set register values emitted conditionally in gfx10_emit_shader_ngg_*. */
1536 shader->ngg.spi_shader_pos_format =
1537 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1538 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ? V_02870C_SPI_SHADER_4COMP
1539 : V_02870C_SPI_SHADER_NONE) |
1540 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ? V_02870C_SPI_SHADER_4COMP
1541 : V_02870C_SPI_SHADER_NONE) |
1542 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ? V_02870C_SPI_SHADER_4COMP
1543 : V_02870C_SPI_SHADER_NONE);
1544 shader->ngg.ge_max_output_per_subgroup = S_0287FC_MAX_VERTS_PER_SUBGROUP(shader->ngg.max_out_verts);
1545 shader->ngg.vgt_gs_instance_cnt =
1546 S_028B90_ENABLE(gs_num_invocations > 1) |
1547 S_028B90_CNT(gs_num_invocations) |
1548 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(shader->ngg.max_vert_out_per_gs_instance);
1549 shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(shader->selector, shader, true);
1550
1551 if (gs_stage == MESA_SHADER_GEOMETRY) {
1552 shader->ngg.esgs_vertex_stride = es_sel->info.esgs_vertex_stride / 4;
1553 shader->ngg.vgt_gs_max_vert_out = gs_sel->info.base.gs.vertices_out;
1554 shader->ngg.ge_ngg_subgrp_cntl = S_028B4C_PRIM_AMP_FACTOR(gs_sel->info.base.gs.vertices_out);
1555 } else {
1556 shader->ngg.esgs_vertex_stride = 1;
1557 shader->ngg.vgt_gs_max_vert_out = 1;
1558 shader->ngg.ge_ngg_subgrp_cntl = S_028B4C_PRIM_AMP_FACTOR(1);
1559 }
1560
1561 if (es_stage == MESA_SHADER_TESS_EVAL)
1562 si_set_tesseval_regs(sscreen, es_sel, shader);
1563
1564 shader->ngg.vgt_primitiveid_en =
1565 S_028A84_NGG_DISABLE_PROVOK_REUSE(shader->key.ge.mono.u.vs_export_prim_id ||
1566 gs_sel->info.writes_primid);
1567
1568 if (sscreen->info.gfx_level >= GFX12) {
1569 unsigned num_params = si_shader_num_alloc_param_exports(shader);
1570
1571 shader->ngg.spi_shader_pgm_rsrc4_gs = S_00B220_SPI_SHADER_LATE_ALLOC_GS(127) |
1572 S_00B220_GLG_FORCE_DISABLE(1) |
1573 S_00B220_WAVE_LIMIT(0x3ff) |
1574 S_00B220_INST_PREF_SIZE(si_get_shader_prefetch_size(shader));
1575 shader->ngg.spi_vs_out_config = S_00B0C4_VS_EXPORT_COUNT(MAX2(num_params, 1) - 1) |
1576 S_00B0C4_NO_PC_EXPORT(num_params == 0);
1577 } else {
1578 unsigned late_alloc_wave64, cu_mask;
1579
1580 ac_compute_late_alloc(&sscreen->info, true, shader->key.ge.opt.ngg_culling,
1581 shader->config.scratch_bytes_per_wave > 0,
1582 &late_alloc_wave64, &cu_mask);
1583
1584 /* Oversubscribe PC. This improves performance when there are too many varyings. */
1585 unsigned oversub_pc_lines, oversub_pc_factor = 1;
1586
1587 if (shader->key.ge.opt.ngg_culling) {
1588 /* Be more aggressive with NGG culling. */
1589 if (shader->info.nr_param_exports > 4)
1590 oversub_pc_factor = 4;
1591 else if (shader->info.nr_param_exports > 2)
1592 oversub_pc_factor = 3;
1593 else
1594 oversub_pc_factor = 2;
1595 }
1596 oversub_pc_lines = late_alloc_wave64 ? (sscreen->info.pc_lines / 4) * oversub_pc_factor : 0;
1597 shader->ngg.ge_pc_alloc = S_030980_OVERSUB_EN(oversub_pc_lines > 0) |
1598 S_030980_NUM_PC_LINES(oversub_pc_lines - 1);
1599 shader->ngg.vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(es_enable_prim_id);
1600 shader->ngg.spi_shader_pgm_rsrc3_gs =
1601 ac_apply_cu_en(S_00B21C_CU_EN(cu_mask) |
1602 S_00B21C_WAVE_LIMIT(0x3F),
1603 C_00B21C_CU_EN, 0, &sscreen->info);
1604 shader->ngg.spi_shader_pgm_rsrc4_gs = S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_wave64);
1605 shader->ngg.spi_vs_out_config =
1606 S_0286C4_VS_EXPORT_COUNT(MAX2(shader->info.nr_param_exports, 1) - 1) |
1607 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1608
1609 if (sscreen->info.gfx_level >= GFX11) {
1610 shader->ngg.spi_shader_pgm_rsrc4_gs |=
1611 ac_apply_cu_en(S_00B204_CU_EN_GFX11(0x1) |
1612 S_00B204_INST_PREF_SIZE(si_get_shader_prefetch_size(shader)),
1613 C_00B204_CU_EN_GFX11, 16, &sscreen->info);
1614 } else {
1615 shader->ngg.spi_shader_pgm_rsrc4_gs |=
1616 ac_apply_cu_en(S_00B204_CU_EN_GFX10(0xffff),
1617 C_00B204_CU_EN_GFX10, 16, &sscreen->info);
1618 }
1619 }
1620
1621 if (sscreen->info.gfx_level >= GFX11) {
1622 /* This should be <= 252 for performance on Gfx11. 256 works too but is slower. */
1623 unsigned max_prim_grp_size = sscreen->info.gfx_level >= GFX12 ? 256 : 252;
1624 unsigned prim_amp_factor = gs_stage == MESA_SHADER_GEOMETRY ?
1625 gs_sel->info.base.gs.vertices_out : 1;
1626
1627 shader->ge_cntl = S_03096C_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) |
1628 S_03096C_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) |
1629 S_03096C_BREAK_PRIMGRP_AT_EOI(break_wave_at_eoi) |
1630 S_03096C_PRIM_GRP_SIZE_GFX11(
1631 CLAMP(max_prim_grp_size / MAX2(prim_amp_factor, 1), 1, 256));
1632 } else {
1633 shader->ge_cntl = S_03096C_PRIM_GRP_SIZE_GFX10(shader->ngg.max_gsprims) |
1634 S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts) |
1635 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
1636
1637 shader->ngg.vgt_gs_onchip_cntl =
1638 S_028A44_ES_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) |
1639 S_028A44_GS_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) |
1640 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->ngg.max_gsprims * gs_num_invocations);
1641
1642 /* On gfx10, the GE only checks against the maximum number of ES verts after
1643 * allocating a full GS primitive. So we need to ensure that whenever
1644 * this check passes, there is enough space for a full primitive without
1645 * vertex reuse. VERT_GRP_SIZE=256 doesn't need this. We should always get 256
1646 * if we have enough LDS.
1647 *
1648 * Tessellation is unaffected because it always sets GE_CNTL.VERT_GRP_SIZE = 0.
1649 */
1650 if ((sscreen->info.gfx_level == GFX10) &&
1651 (es_stage == MESA_SHADER_VERTEX || gs_stage == MESA_SHADER_VERTEX) && /* = no tess */
1652 shader->ngg.hw_max_esverts != 256 &&
1653 shader->ngg.hw_max_esverts > 5) {
1654 /* This could be based on the input primitive type. 5 is the worst case
1655 * for primitive types with adjacency.
1656 */
1657 shader->ge_cntl &= C_03096C_VERT_GRP_SIZE;
1658 shader->ge_cntl |= S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts - 5);
1659 }
1660 }
1661
1662 if (window_space) {
1663 shader->ngg.pa_cl_vte_cntl = S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1664 } else {
1665 shader->ngg.pa_cl_vte_cntl = S_028818_VTX_W0_FMT(1) |
1666 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1667 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1668 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1669 }
1670
1671 if (sscreen->info.gfx_level >= GFX12) {
1672 shader->ngg.vgt_shader_stages_en =
1673 S_028A98_GS_EN(gs_stage == MESA_SHADER_GEOMETRY) |
1674 S_028A98_PRIMGEN_PASSTHRU_NO_MSG(gfx10_is_ngg_passthrough(shader)) |
1675 S_028A98_GS_W32_EN(shader->wave_size == 32) |
1676 S_028A98_NGG_WAVE_ID_EN(si_shader_uses_streamout(shader));
1677 } else {
1678 shader->ngg.vgt_shader_stages_en =
1679 S_028B54_ES_EN(es_stage == MESA_SHADER_TESS_EVAL ?
1680 V_028B54_ES_STAGE_DS : V_028B54_ES_STAGE_REAL) |
1681 S_028B54_GS_EN(gs_stage == MESA_SHADER_GEOMETRY) |
1682 S_028B54_PRIMGEN_EN(1) |
1683 S_028B54_PRIMGEN_PASSTHRU_EN(gfx10_is_ngg_passthrough(shader)) |
1684 S_028B54_PRIMGEN_PASSTHRU_NO_MSG(gfx10_is_ngg_passthrough(shader) &&
1685 sscreen->info.family >= CHIP_NAVI23) |
1686 S_028B54_NGG_WAVE_ID_EN(si_shader_uses_streamout(shader)) |
1687 S_028B54_GS_W32_EN(shader->wave_size == 32) |
1688 S_028B54_MAX_PRIMGRP_IN_WAVE(2);
1689 }
1690
1691 ac_pm4_finalize(&pm4->base);
1692 }
1693
si_emit_shader_vs(struct si_context * sctx,unsigned index)1694 static void si_emit_shader_vs(struct si_context *sctx, unsigned index)
1695 {
1696 struct si_shader *shader = sctx->queued.named.vs;
1697
1698 radeon_begin(&sctx->gfx_cs);
1699 radeon_opt_set_context_reg(R_028A40_VGT_GS_MODE, SI_TRACKED_VGT_GS_MODE,
1700 shader->vs.vgt_gs_mode);
1701 radeon_opt_set_context_reg(R_028A84_VGT_PRIMITIVEID_EN, SI_TRACKED_VGT_PRIMITIVEID_EN,
1702 shader->vs.vgt_primitiveid_en);
1703
1704 if (sctx->gfx_level <= GFX8) {
1705 radeon_opt_set_context_reg(R_028AB4_VGT_REUSE_OFF, SI_TRACKED_VGT_REUSE_OFF,
1706 shader->vs.vgt_reuse_off);
1707 }
1708
1709 radeon_opt_set_context_reg(R_0286C4_SPI_VS_OUT_CONFIG, SI_TRACKED_SPI_VS_OUT_CONFIG,
1710 shader->vs.spi_vs_out_config);
1711
1712 radeon_opt_set_context_reg(R_02870C_SPI_SHADER_POS_FORMAT,
1713 SI_TRACKED_SPI_SHADER_POS_FORMAT,
1714 shader->vs.spi_shader_pos_format);
1715
1716 radeon_opt_set_context_reg(R_028818_PA_CL_VTE_CNTL, SI_TRACKED_PA_CL_VTE_CNTL,
1717 shader->vs.pa_cl_vte_cntl);
1718
1719 if (shader->selector->stage == MESA_SHADER_TESS_EVAL)
1720 radeon_opt_set_context_reg(R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
1721 shader->vgt_tf_param);
1722
1723 if (shader->vgt_vertex_reuse_block_cntl)
1724 radeon_opt_set_context_reg(R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1725 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
1726 shader->vgt_vertex_reuse_block_cntl);
1727
1728 /* Required programming for tessellation. (legacy pipeline only) */
1729 if (sctx->gfx_level >= GFX10 && shader->selector->stage == MESA_SHADER_TESS_EVAL) {
1730 radeon_opt_set_context_reg(R_028A44_VGT_GS_ONCHIP_CNTL,
1731 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
1732 S_028A44_ES_VERTS_PER_SUBGRP(250) |
1733 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
1734 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
1735 }
1736
1737 radeon_end_update_context_roll();
1738
1739 /* GE_PC_ALLOC is not a context register, so it doesn't cause a context roll. */
1740 if (sctx->gfx_level >= GFX10) {
1741 radeon_begin_again(&sctx->gfx_cs);
1742 radeon_opt_set_uconfig_reg(R_030980_GE_PC_ALLOC, SI_TRACKED_GE_PC_ALLOC,
1743 shader->vs.ge_pc_alloc);
1744 radeon_end();
1745 }
1746 }
1747
1748 /**
1749 * Compute the state for \p shader, which will run as a vertex shader on the
1750 * hardware.
1751 *
1752 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1753 * is the copy shader.
1754 */
si_shader_vs(struct si_screen * sscreen,struct si_shader * shader,struct si_shader_selector * gs)1755 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
1756 struct si_shader_selector *gs)
1757 {
1758 const struct si_shader_info *info = &shader->selector->info;
1759 struct si_pm4_state *pm4;
1760 unsigned num_user_sgprs, vgpr_comp_cnt;
1761 uint64_t va;
1762 unsigned nparams, oc_lds_en;
1763 bool window_space = shader->selector->stage == MESA_SHADER_VERTEX ?
1764 info->base.vs.window_space_position : 0;
1765 bool enable_prim_id = shader->key.ge.mono.u.vs_export_prim_id || info->uses_primid;
1766
1767 assert(sscreen->info.gfx_level < GFX11);
1768
1769 pm4 = si_get_shader_pm4_state(shader, si_emit_shader_vs);
1770 if (!pm4)
1771 return;
1772
1773 /* We always write VGT_GS_MODE in the VS state, because every switch
1774 * between different shader pipelines involving a different GS or no
1775 * GS at all involves a switch of the VS (different GS use different
1776 * copy shaders). On the other hand, when the API switches from a GS to
1777 * no GS and then back to the same GS used originally, the GS state is
1778 * not sent again.
1779 */
1780 if (!gs) {
1781 unsigned mode = V_028A40_GS_OFF;
1782
1783 /* PrimID needs GS scenario A. */
1784 if (enable_prim_id)
1785 mode = V_028A40_GS_SCENARIO_A;
1786
1787 shader->vs.vgt_gs_mode = S_028A40_MODE(mode);
1788 shader->vs.vgt_primitiveid_en = enable_prim_id;
1789 } else {
1790 shader->vs.vgt_gs_mode =
1791 ac_vgt_gs_mode(gs->info.base.gs.vertices_out, sscreen->info.gfx_level);
1792 shader->vs.vgt_primitiveid_en = 0;
1793 }
1794
1795 if (sscreen->info.gfx_level <= GFX8) {
1796 /* Reuse needs to be set off if we write oViewport. */
1797 shader->vs.vgt_reuse_off = S_028AB4_REUSE_OFF(info->writes_viewport_index);
1798 }
1799
1800 va = shader->bo->gpu_address;
1801
1802 if (gs) {
1803 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1804 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1805 } else if (shader->selector->stage == MESA_SHADER_VERTEX) {
1806 vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, enable_prim_id);
1807
1808 if (info->base.vs.blit_sgprs_amd) {
1809 num_user_sgprs = SI_SGPR_VS_BLIT_DATA + info->base.vs.blit_sgprs_amd;
1810 } else {
1811 num_user_sgprs = si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR);
1812 }
1813 } else if (shader->selector->stage == MESA_SHADER_TESS_EVAL) {
1814 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1815 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1816 } else
1817 unreachable("invalid shader selector type");
1818
1819 /* VS is required to export at least one param. */
1820 nparams = MAX2(shader->info.nr_param_exports, 1);
1821 shader->vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1822
1823 if (sscreen->info.gfx_level >= GFX10) {
1824 shader->vs.spi_vs_out_config |=
1825 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1826 }
1827
1828 shader->vs.spi_shader_pos_format =
1829 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1830 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ? V_02870C_SPI_SHADER_4COMP
1831 : V_02870C_SPI_SHADER_NONE) |
1832 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ? V_02870C_SPI_SHADER_4COMP
1833 : V_02870C_SPI_SHADER_NONE) |
1834 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ? V_02870C_SPI_SHADER_4COMP
1835 : V_02870C_SPI_SHADER_NONE);
1836 unsigned late_alloc_wave64, cu_mask;
1837 ac_compute_late_alloc(&sscreen->info, false, false,
1838 shader->config.scratch_bytes_per_wave > 0,
1839 &late_alloc_wave64, &cu_mask);
1840
1841 shader->vs.ge_pc_alloc = S_030980_OVERSUB_EN(late_alloc_wave64 > 0) |
1842 S_030980_NUM_PC_LINES(sscreen->info.pc_lines / 4 - 1);
1843 shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(shader->selector, shader, false);
1844
1845 oc_lds_en = shader->selector->stage == MESA_SHADER_TESS_EVAL ? 1 : 0;
1846
1847 if (sscreen->info.gfx_level >= GFX7) {
1848 ac_pm4_set_reg_idx3(&pm4->base, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
1849 ac_apply_cu_en(S_00B118_CU_EN(cu_mask) |
1850 S_00B118_WAVE_LIMIT(0x3F),
1851 C_00B118_CU_EN, 0, &sscreen->info));
1852 ac_pm4_set_reg(&pm4->base, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(late_alloc_wave64));
1853 }
1854
1855 ac_pm4_set_reg(&pm4->base, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1856 ac_pm4_set_reg(&pm4->base, R_00B124_SPI_SHADER_PGM_HI_VS,
1857 S_00B124_MEM_BASE(sscreen->info.address32_hi >> 8));
1858
1859 uint32_t rsrc1 =
1860 S_00B128_VGPRS(si_shader_encode_vgprs(shader)) |
1861 S_00B128_SGPRS(si_shader_encode_sgprs(shader)) |
1862 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
1863 S_00B128_DX10_CLAMP(1) |
1864 S_00B128_MEM_ORDERED(si_shader_mem_ordered(shader)) |
1865 S_00B128_FLOAT_MODE(shader->config.float_mode);
1866 uint32_t rsrc2 = S_00B12C_USER_SGPR(num_user_sgprs) | S_00B12C_OC_LDS_EN(oc_lds_en) |
1867 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
1868
1869 if (sscreen->info.gfx_level >= GFX10)
1870 rsrc2 |= S_00B12C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
1871 else if (sscreen->info.gfx_level == GFX9)
1872 rsrc2 |= S_00B12C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
1873
1874 if (si_shader_uses_streamout(shader)) {
1875 rsrc2 |= S_00B12C_SO_BASE0_EN(!!shader->selector->info.base.xfb_stride[0]) |
1876 S_00B12C_SO_BASE1_EN(!!shader->selector->info.base.xfb_stride[1]) |
1877 S_00B12C_SO_BASE2_EN(!!shader->selector->info.base.xfb_stride[2]) |
1878 S_00B12C_SO_BASE3_EN(!!shader->selector->info.base.xfb_stride[3]) |
1879 S_00B12C_SO_EN(1);
1880 }
1881
1882 ac_pm4_set_reg(&pm4->base, R_00B128_SPI_SHADER_PGM_RSRC1_VS, rsrc1);
1883 ac_pm4_set_reg(&pm4->base, R_00B12C_SPI_SHADER_PGM_RSRC2_VS, rsrc2);
1884
1885 if (window_space)
1886 shader->vs.pa_cl_vte_cntl = S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1887 else
1888 shader->vs.pa_cl_vte_cntl =
1889 S_028818_VTX_W0_FMT(1) | S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1890 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1891 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1892
1893 if (shader->selector->stage == MESA_SHADER_TESS_EVAL)
1894 si_set_tesseval_regs(sscreen, shader->selector, shader);
1895
1896 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader);
1897 ac_pm4_finalize(&pm4->base);
1898 }
1899
si_get_spi_shader_col_format(struct si_shader * shader)1900 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1901 {
1902 unsigned spi_shader_col_format = shader->key.ps.part.epilog.spi_shader_col_format;
1903 unsigned value = 0, num_mrts = 0;
1904 unsigned i, num_targets = (util_last_bit(spi_shader_col_format) + 3) / 4;
1905
1906 /* Remove holes in spi_shader_col_format. */
1907 for (i = 0; i < num_targets; i++) {
1908 unsigned spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
1909
1910 if (spi_format) {
1911 value |= spi_format << (num_mrts * 4);
1912 num_mrts++;
1913 }
1914 }
1915
1916 return value;
1917 }
1918
gfx6_emit_shader_ps(struct si_context * sctx,unsigned index)1919 static void gfx6_emit_shader_ps(struct si_context *sctx, unsigned index)
1920 {
1921 struct si_shader *shader = sctx->queued.named.ps;
1922
1923 radeon_begin(&sctx->gfx_cs);
1924 radeon_opt_set_context_reg2(R_0286CC_SPI_PS_INPUT_ENA, SI_TRACKED_SPI_PS_INPUT_ENA,
1925 shader->ps.spi_ps_input_ena,
1926 shader->ps.spi_ps_input_addr);
1927 radeon_opt_set_context_reg(R_0286E0_SPI_BARYC_CNTL, SI_TRACKED_SPI_BARYC_CNTL,
1928 shader->ps.spi_baryc_cntl);
1929 radeon_opt_set_context_reg(R_0286D8_SPI_PS_IN_CONTROL, SI_TRACKED_SPI_PS_IN_CONTROL,
1930 shader->ps.spi_ps_in_control);
1931 radeon_opt_set_context_reg2(R_028710_SPI_SHADER_Z_FORMAT, SI_TRACKED_SPI_SHADER_Z_FORMAT,
1932 shader->ps.spi_shader_z_format,
1933 shader->ps.spi_shader_col_format);
1934 radeon_opt_set_context_reg(R_02823C_CB_SHADER_MASK, SI_TRACKED_CB_SHADER_MASK,
1935 shader->ps.cb_shader_mask);
1936 radeon_end_update_context_roll();
1937 }
1938
gfx11_dgpu_emit_shader_ps(struct si_context * sctx,unsigned index)1939 static void gfx11_dgpu_emit_shader_ps(struct si_context *sctx, unsigned index)
1940 {
1941 struct si_shader *shader = sctx->queued.named.ps;
1942
1943 radeon_begin(&sctx->gfx_cs);
1944 gfx11_begin_packed_context_regs();
1945 gfx11_opt_set_context_reg(R_0286CC_SPI_PS_INPUT_ENA, SI_TRACKED_SPI_PS_INPUT_ENA,
1946 shader->ps.spi_ps_input_ena);
1947 gfx11_opt_set_context_reg(R_0286D0_SPI_PS_INPUT_ADDR, SI_TRACKED_SPI_PS_INPUT_ADDR,
1948 shader->ps.spi_ps_input_addr);
1949 gfx11_opt_set_context_reg(R_0286E0_SPI_BARYC_CNTL, SI_TRACKED_SPI_BARYC_CNTL,
1950 shader->ps.spi_baryc_cntl);
1951 gfx11_opt_set_context_reg(R_0286D8_SPI_PS_IN_CONTROL, SI_TRACKED_SPI_PS_IN_CONTROL,
1952 shader->ps.spi_ps_in_control);
1953 gfx11_opt_set_context_reg(R_028710_SPI_SHADER_Z_FORMAT, SI_TRACKED_SPI_SHADER_Z_FORMAT,
1954 shader->ps.spi_shader_z_format);
1955 gfx11_opt_set_context_reg(R_028714_SPI_SHADER_COL_FORMAT, SI_TRACKED_SPI_SHADER_COL_FORMAT,
1956 shader->ps.spi_shader_col_format);
1957 gfx11_opt_set_context_reg(R_02823C_CB_SHADER_MASK, SI_TRACKED_CB_SHADER_MASK,
1958 shader->ps.cb_shader_mask);
1959 gfx11_end_packed_context_regs();
1960 radeon_end(); /* don't track context rolls on GFX11 */
1961 }
1962
gfx12_emit_shader_ps(struct si_context * sctx,unsigned index)1963 static void gfx12_emit_shader_ps(struct si_context *sctx, unsigned index)
1964 {
1965 struct si_shader *shader = sctx->queued.named.ps;
1966
1967 radeon_begin(&sctx->gfx_cs);
1968 gfx12_begin_context_regs();
1969 gfx12_opt_set_context_reg(R_028640_SPI_PS_IN_CONTROL, SI_TRACKED_SPI_PS_IN_CONTROL,
1970 shader->ps.spi_ps_in_control);
1971 gfx12_opt_set_context_reg(R_028650_SPI_SHADER_Z_FORMAT, SI_TRACKED_SPI_SHADER_Z_FORMAT,
1972 shader->ps.spi_shader_z_format);
1973 gfx12_opt_set_context_reg(R_028654_SPI_SHADER_COL_FORMAT, SI_TRACKED_SPI_SHADER_COL_FORMAT,
1974 shader->ps.spi_shader_col_format);
1975 gfx12_opt_set_context_reg(R_028658_SPI_BARYC_CNTL, SI_TRACKED_SPI_BARYC_CNTL,
1976 shader->ps.spi_baryc_cntl);
1977 gfx12_opt_set_context_reg(R_02865C_SPI_PS_INPUT_ENA, SI_TRACKED_SPI_PS_INPUT_ENA,
1978 shader->ps.spi_ps_input_ena);
1979 gfx12_opt_set_context_reg(R_028660_SPI_PS_INPUT_ADDR, SI_TRACKED_SPI_PS_INPUT_ADDR,
1980 shader->ps.spi_ps_input_addr);
1981 gfx12_opt_set_context_reg(R_028854_CB_SHADER_MASK, SI_TRACKED_CB_SHADER_MASK,
1982 shader->ps.cb_shader_mask);
1983 gfx12_opt_set_context_reg(R_028BBC_PA_SC_HISZ_CONTROL, SI_TRACKED_PA_SC_HISZ_CONTROL,
1984 shader->ps.pa_sc_hisz_control);
1985 gfx12_end_context_regs();
1986 radeon_end(); /* don't track context rolls on GFX12 */
1987 }
1988
si_shader_ps(struct si_screen * sscreen,struct si_shader * shader)1989 static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
1990 {
1991 struct si_shader_info *info = &shader->selector->info;
1992 const unsigned input_ena = shader->config.spi_ps_input_ena;
1993
1994 /* we need to enable at least one of them, otherwise we hang the GPU */
1995 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) || G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1996 G_0286CC_PERSP_CENTROID_ENA(input_ena) || G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1997 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) || G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1998 G_0286CC_LINEAR_CENTROID_ENA(input_ena) || G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1999 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
2000 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) || G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
2001 G_0286CC_PERSP_CENTER_ENA(input_ena) || G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
2002 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
2003
2004 /* Validate interpolation optimization flags (read as implications). */
2005 assert(!shader->key.ps.part.prolog.bc_optimize_for_persp ||
2006 (G_0286CC_PERSP_CENTER_ENA(input_ena) && G_0286CC_PERSP_CENTROID_ENA(input_ena)));
2007 assert(!shader->key.ps.part.prolog.bc_optimize_for_linear ||
2008 (G_0286CC_LINEAR_CENTER_ENA(input_ena) && G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
2009 assert(!shader->key.ps.part.prolog.force_persp_center_interp ||
2010 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) && !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
2011 assert(!shader->key.ps.part.prolog.force_linear_center_interp ||
2012 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) && !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
2013 assert(!shader->key.ps.part.prolog.force_persp_sample_interp ||
2014 (!G_0286CC_PERSP_CENTER_ENA(input_ena) && !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
2015 assert(!shader->key.ps.part.prolog.force_linear_sample_interp ||
2016 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) && !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
2017
2018 /* color_two_side always enables FRONT_FACE. Since st/mesa disables two-side colors if the back
2019 * face is culled, the only case when both color_two_side and force_front_face_input can be set
2020 * is when the front face is culled (which means force_front_face_input == -1).
2021 */
2022 assert(!shader->key.ps.opt.force_front_face_input || !G_0286CC_FRONT_FACE_ENA(input_ena) ||
2023 (shader->key.ps.part.prolog.color_two_side &&
2024 shader->key.ps.opt.force_front_face_input == -1));
2025
2026 /* Validate cases when the optimizations are off (read as implications). */
2027 assert(shader->key.ps.part.prolog.bc_optimize_for_persp ||
2028 !G_0286CC_PERSP_CENTER_ENA(input_ena) || !G_0286CC_PERSP_CENTROID_ENA(input_ena));
2029 assert(shader->key.ps.part.prolog.bc_optimize_for_linear ||
2030 !G_0286CC_LINEAR_CENTER_ENA(input_ena) || !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
2031
2032 /* DB_SHADER_CONTROL */
2033 shader->ps.db_shader_control = S_02880C_Z_EXPORT_ENABLE(info->writes_z) |
2034 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(info->writes_stencil) |
2035 S_02880C_MASK_EXPORT_ENABLE(shader->ps.writes_samplemask) |
2036 S_02880C_KILL_ENABLE(si_shader_uses_discard(shader));
2037 if (sscreen->info.gfx_level >= GFX12)
2038 shader->ps.pa_sc_hisz_control = S_028BBC_ROUND(2); /* required minimum value */
2039
2040 switch (info->base.fs.depth_layout) {
2041 case FRAG_DEPTH_LAYOUT_GREATER:
2042 shader->ps.db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2043 if (sscreen->info.gfx_level >= GFX12)
2044 shader->ps.pa_sc_hisz_control |= S_028BBC_CONSERVATIVE_Z_EXPORT(V_028BBC_EXPORT_GREATER_THAN_Z);
2045 break;
2046 case FRAG_DEPTH_LAYOUT_LESS:
2047 shader->ps.db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2048 if (sscreen->info.gfx_level >= GFX12)
2049 shader->ps.pa_sc_hisz_control |= S_028BBC_CONSERVATIVE_Z_EXPORT(V_028BBC_EXPORT_LESS_THAN_Z);
2050 break;
2051 default:;
2052 }
2053
2054 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2055 *
2056 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2057 * --|-----------|------------|------------|--------------------|-------------------|-------------
2058 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2059 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2060 * 2 | false | true | n/a | LateZ | 1 | 0
2061 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2062 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2063 *
2064 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2065 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2066 *
2067 * Don't use ReZ without profiling !!!
2068 *
2069 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2070 * shaders.
2071 */
2072 if (info->base.fs.early_fragment_tests) {
2073 /* Cases 3, 4. */
2074 shader->ps.db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2075 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2076 S_02880C_EXEC_ON_NOOP(info->base.writes_memory);
2077 } else if (info->base.writes_memory) {
2078 /* Case 2. */
2079 shader->ps.db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2080 S_02880C_EXEC_ON_HIER_FAIL(1);
2081 } else {
2082 /* Case 1. */
2083 shader->ps.db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2084 }
2085
2086 if (info->base.fs.post_depth_coverage)
2087 shader->ps.db_shader_control |= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
2088
2089 /* Bug workaround for smoothing (overrasterization) on GFX6. */
2090 if (sscreen->info.gfx_level == GFX6 && shader->key.ps.mono.poly_line_smoothing) {
2091 shader->ps.db_shader_control &= C_02880C_Z_ORDER;
2092 shader->ps.db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
2093 }
2094
2095 if (sscreen->info.has_rbplus && !sscreen->info.rbplus_allowed)
2096 shader->ps.db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
2097
2098 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
2099 * Possible values:
2100 * 0 -> Position = pixel center
2101 * 1 -> Position = pixel centroid
2102 * 2 -> Position = at sample position
2103 *
2104 * From GLSL 4.5 specification, section 7.1:
2105 * "The variable gl_FragCoord is available as an input variable from
2106 * within fragment shaders and it holds the window relative coordinates
2107 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
2108 * value can be for any location within the pixel, or one of the
2109 * fragment samples. The use of centroid does not further restrict
2110 * this value to be inside the current primitive."
2111 *
2112 * Meaning that centroid has no effect and we can return anything within
2113 * the pixel. Thus, return the value at sample position, because that's
2114 * the most accurate one shaders can get.
2115 */
2116 shader->ps.spi_baryc_cntl = S_0286E0_POS_FLOAT_LOCATION(2) |
2117 S_0286E0_POS_FLOAT_ULC(info->base.fs.pixel_center_integer) |
2118 S_0286E0_FRONT_FACE_ALL_BITS(1);
2119 shader->ps.spi_shader_col_format = si_get_spi_shader_col_format(shader);
2120 shader->ps.cb_shader_mask = ac_get_cb_shader_mask(shader->key.ps.part.epilog.spi_shader_col_format);
2121 shader->ps.spi_ps_input_ena = shader->config.spi_ps_input_ena;
2122 shader->ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
2123 shader->ps.num_interp = si_get_ps_num_interp(shader);
2124 shader->ps.spi_shader_z_format =
2125 ac_get_spi_shader_z_format(info->writes_z, info->writes_stencil, shader->ps.writes_samplemask,
2126 shader->key.ps.part.epilog.alpha_to_coverage_via_mrtz);
2127
2128 /* Ensure that some export memory is always allocated, for two reasons:
2129 *
2130 * 1) Correctness: The hardware ignores the EXEC mask if no export
2131 * memory is allocated, so KILL and alpha test do not work correctly
2132 * without this.
2133 * 2) Performance: Every shader needs at least a NULL export, even when
2134 * it writes no color/depth output. The NULL export instruction
2135 * stalls without this setting.
2136 *
2137 * Don't add this to CB_SHADER_MASK.
2138 *
2139 * GFX10 supports pixel shaders without exports by setting both
2140 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
2141 * instructions if any are present.
2142 *
2143 * RB+ depth-only rendering requires SPI_SHADER_32_R.
2144 */
2145 bool has_mrtz = info->writes_z || info->writes_stencil || shader->ps.writes_samplemask;
2146
2147 if (!shader->ps.spi_shader_col_format) {
2148 if (shader->key.ps.part.epilog.rbplus_depth_only_opt) {
2149 shader->ps.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
2150 } else if (!has_mrtz) {
2151 if (sscreen->info.gfx_level >= GFX10) {
2152 if (G_02880C_KILL_ENABLE(shader->ps.db_shader_control))
2153 shader->ps.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
2154 } else {
2155 shader->ps.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
2156 }
2157 }
2158 }
2159
2160 if (sscreen->info.gfx_level >= GFX12) {
2161 shader->ps.spi_ps_in_control = S_028640_PARAM_GEN(shader->key.ps.mono.point_smoothing) |
2162 S_028640_PS_W32_EN(shader->wave_size == 32);
2163 shader->ps.spi_gs_out_config_ps = S_00B0C4_NUM_INTERP(shader->ps.num_interp);
2164 } else {
2165 /* Enable PARAM_GEN for point smoothing.
2166 * Gfx11 workaround when there are no PS inputs but LDS is used.
2167 */
2168 bool param_gen = shader->key.ps.mono.point_smoothing ||
2169 (sscreen->info.gfx_level == GFX11 && !shader->ps.num_interp &&
2170 shader->config.lds_size);
2171
2172 shader->ps.spi_ps_in_control = S_0286D8_NUM_INTERP(shader->ps.num_interp) |
2173 S_0286D8_PARAM_GEN(param_gen) |
2174 S_0286D8_PS_W32_EN(shader->wave_size == 32);
2175 }
2176
2177 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader, NULL);
2178 if (!pm4)
2179 return;
2180
2181 if (sscreen->info.gfx_level >= GFX12)
2182 pm4->atom.emit = gfx12_emit_shader_ps;
2183 else if (sscreen->info.has_set_context_pairs_packed)
2184 pm4->atom.emit = gfx11_dgpu_emit_shader_ps;
2185 else
2186 pm4->atom.emit = gfx6_emit_shader_ps;
2187
2188 /* If multiple state sets are allowed to be in a bin, break the batch on a new PS. */
2189 if (sscreen->dpbb_allowed &&
2190 (sscreen->pbb_context_states_per_bin > 1 ||
2191 sscreen->pbb_persistent_states_per_bin > 1)) {
2192 ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_EVENT_WRITE, 0, 0));
2193 ac_pm4_cmd_add(&pm4->base, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2194 }
2195
2196 if (sscreen->info.gfx_level >= GFX12) {
2197 ac_pm4_set_reg(&pm4->base, R_00B01C_SPI_SHADER_PGM_RSRC4_PS,
2198 S_00B01C_WAVE_LIMIT_GFX12(0x3FF) |
2199 S_00B01C_LDS_GROUP_SIZE_GFX12(1) |
2200 S_00B01C_INST_PREF_SIZE(si_get_shader_prefetch_size(shader)));
2201 } else if (sscreen->info.gfx_level >= GFX11) {
2202 unsigned cu_mask_ps = ac_gfx103_get_cu_mask_ps(&sscreen->info);
2203
2204 ac_pm4_set_reg_idx3(&pm4->base, R_00B004_SPI_SHADER_PGM_RSRC4_PS,
2205 ac_apply_cu_en(S_00B004_CU_EN(cu_mask_ps >> 16) |
2206 S_00B004_INST_PREF_SIZE(si_get_shader_prefetch_size(shader)),
2207 C_00B004_CU_EN, 16, &sscreen->info));
2208 }
2209
2210 uint64_t va = shader->bo->gpu_address;
2211 ac_pm4_set_reg(&pm4->base, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
2212 ac_pm4_set_reg(&pm4->base, R_00B024_SPI_SHADER_PGM_HI_PS,
2213 S_00B024_MEM_BASE(sscreen->info.address32_hi >> 8));
2214
2215 ac_pm4_set_reg(&pm4->base, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
2216 S_00B028_VGPRS(si_shader_encode_vgprs(shader)) |
2217 S_00B028_SGPRS(si_shader_encode_sgprs(shader)) |
2218 S_00B028_DX10_CLAMP(sscreen->info.gfx_level < GFX12) |
2219 S_00B028_MEM_ORDERED(si_shader_mem_ordered(shader)) |
2220 S_00B028_FLOAT_MODE(shader->config.float_mode));
2221 ac_pm4_set_reg(&pm4->base, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
2222 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
2223 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
2224 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
2225 ac_pm4_finalize(&pm4->base);
2226 }
2227
si_shader_init_pm4_state(struct si_screen * sscreen,struct si_shader * shader)2228 static void si_shader_init_pm4_state(struct si_screen *sscreen, struct si_shader *shader)
2229 {
2230 assert(shader->wave_size);
2231
2232 switch (shader->selector->stage) {
2233 case MESA_SHADER_VERTEX:
2234 if (shader->key.ge.as_ls)
2235 si_shader_ls(sscreen, shader);
2236 else if (shader->key.ge.as_es)
2237 si_shader_es(sscreen, shader);
2238 else if (shader->key.ge.as_ngg)
2239 gfx10_shader_ngg(sscreen, shader);
2240 else
2241 si_shader_vs(sscreen, shader, NULL);
2242 break;
2243 case MESA_SHADER_TESS_CTRL:
2244 si_shader_hs(sscreen, shader);
2245 break;
2246 case MESA_SHADER_TESS_EVAL:
2247 if (shader->key.ge.as_es)
2248 si_shader_es(sscreen, shader);
2249 else if (shader->key.ge.as_ngg)
2250 gfx10_shader_ngg(sscreen, shader);
2251 else
2252 si_shader_vs(sscreen, shader, NULL);
2253 break;
2254 case MESA_SHADER_GEOMETRY:
2255 if (shader->key.ge.as_ngg) {
2256 gfx10_shader_ngg(sscreen, shader);
2257 } else {
2258 /* VS must be initialized first because GS uses its fields. */
2259 si_shader_vs(sscreen, shader->gs_copy_shader, shader->selector);
2260 si_shader_gs(sscreen, shader);
2261 }
2262 break;
2263 case MESA_SHADER_FRAGMENT:
2264 si_shader_ps(sscreen, shader);
2265 break;
2266 default:
2267 assert(0);
2268 }
2269
2270 assert(!(sscreen->debug_flags & DBG(SQTT)) || shader->pm4.base.spi_shader_pgm_lo_reg != 0);
2271 }
2272
si_clear_vs_key_inputs(union si_shader_key * key)2273 static void si_clear_vs_key_inputs(union si_shader_key *key)
2274 {
2275 key->ge.mono.instance_divisor_is_one = 0;
2276 key->ge.mono.instance_divisor_is_fetched = 0;
2277 key->ge.mono.vs_fetch_opencode = 0;
2278 memset(key->ge.mono.vs_fix_fetch, 0, sizeof(key->ge.mono.vs_fix_fetch));
2279 }
2280
si_vs_key_update_inputs(struct si_context * sctx)2281 void si_vs_key_update_inputs(struct si_context *sctx)
2282 {
2283 struct si_shader_selector *vs = sctx->shader.vs.cso;
2284 struct si_vertex_elements *elts = sctx->vertex_elements;
2285 union si_shader_key *key = &sctx->shader.vs.key;
2286
2287 if (!vs)
2288 return;
2289
2290 if (vs->info.base.vs.blit_sgprs_amd) {
2291 si_clear_vs_key_inputs(key);
2292 key->ge.opt.prefer_mono = 0;
2293 sctx->uses_nontrivial_vs_inputs = false;
2294 return;
2295 }
2296
2297 bool uses_nontrivial_vs_inputs = false;
2298
2299 if (elts->instance_divisor_is_one || elts->instance_divisor_is_fetched)
2300 uses_nontrivial_vs_inputs = true;
2301
2302 key->ge.mono.instance_divisor_is_one = elts->instance_divisor_is_one;
2303 key->ge.mono.instance_divisor_is_fetched = elts->instance_divisor_is_fetched;
2304 key->ge.opt.prefer_mono = elts->instance_divisor_is_fetched;
2305
2306 unsigned count_mask = (1 << vs->info.num_inputs) - 1;
2307 unsigned fix = elts->fix_fetch_always & count_mask;
2308 unsigned opencode = elts->fix_fetch_opencode & count_mask;
2309
2310 if (sctx->vertex_buffer_unaligned & elts->vb_alignment_check_mask) {
2311 uint32_t mask = elts->fix_fetch_unaligned & count_mask;
2312 while (mask) {
2313 unsigned i = u_bit_scan(&mask);
2314 unsigned log_hw_load_size = 1 + ((elts->hw_load_is_dword >> i) & 1);
2315 unsigned vbidx = elts->vertex_buffer_index[i];
2316 const struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbidx];
2317 unsigned align_mask = (1 << log_hw_load_size) - 1;
2318 if (vb->buffer_offset & align_mask) {
2319 fix |= 1 << i;
2320 opencode |= 1 << i;
2321 }
2322 }
2323 }
2324
2325 memset(key->ge.mono.vs_fix_fetch, 0, sizeof(key->ge.mono.vs_fix_fetch));
2326
2327 while (fix) {
2328 unsigned i = u_bit_scan(&fix);
2329 uint8_t fix_fetch = elts->fix_fetch[i];
2330
2331 key->ge.mono.vs_fix_fetch[i].bits = fix_fetch;
2332 if (fix_fetch)
2333 uses_nontrivial_vs_inputs = true;
2334 }
2335 key->ge.mono.vs_fetch_opencode = opencode;
2336 if (opencode)
2337 uses_nontrivial_vs_inputs = true;
2338
2339 sctx->uses_nontrivial_vs_inputs = uses_nontrivial_vs_inputs;
2340
2341 /* draw_vertex_state (display lists) requires that all VS input lowering is disabled
2342 * because its vertex elements never need any lowering.
2343 *
2344 * We just computed the key because we needed to set uses_nontrivial_vs_inputs, so that we know
2345 * whether the VS should be updated when we switch from draw_vertex_state to draw_vbo. Now
2346 * clear the VS input bits for draw_vertex_state. This should happen rarely because VS inputs
2347 * don't usually need any lowering.
2348 */
2349 if (uses_nontrivial_vs_inputs && sctx->force_trivial_vs_inputs)
2350 si_clear_vs_key_inputs(key);
2351 }
2352
si_get_vs_key_inputs(struct si_context * sctx,union si_shader_key * key)2353 static void si_get_vs_key_inputs(struct si_context *sctx, union si_shader_key *key)
2354 {
2355 key->ge.mono.instance_divisor_is_one = sctx->shader.vs.key.ge.mono.instance_divisor_is_one;
2356 key->ge.mono.instance_divisor_is_fetched = sctx->shader.vs.key.ge.mono.instance_divisor_is_fetched;
2357 key->ge.mono.vs_fetch_opencode = sctx->shader.vs.key.ge.mono.vs_fetch_opencode;
2358 memcpy(key->ge.mono.vs_fix_fetch, sctx->shader.vs.key.ge.mono.vs_fix_fetch,
2359 sizeof(key->ge.mono.vs_fix_fetch));
2360 }
2361
si_update_ps_inputs_read_or_disabled(struct si_context * sctx)2362 void si_update_ps_inputs_read_or_disabled(struct si_context *sctx)
2363 {
2364 struct si_shader_selector *ps = sctx->shader.ps.cso;
2365
2366 /* Find out if PS is disabled. */
2367 bool ps_disabled = true;
2368 if (ps) {
2369 bool ps_modifies_zs = ps->info.base.fs.uses_discard ||
2370 ps->info.writes_z ||
2371 ps->info.writes_stencil ||
2372 ps->info.writes_samplemask ||
2373 sctx->queued.named.blend->alpha_to_coverage ||
2374 sctx->queued.named.dsa->alpha_func != PIPE_FUNC_ALWAYS ||
2375 sctx->queued.named.rasterizer->poly_stipple_enable ||
2376 sctx->queued.named.rasterizer->point_smooth;
2377
2378 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
2379 (!ps_modifies_zs && !ps->info.base.writes_memory &&
2380 !si_any_colorbuffer_written(sctx));
2381 }
2382
2383 uint64_t ps_inputs_read_or_disabled;
2384
2385 if (ps_disabled) {
2386 ps_inputs_read_or_disabled = 0;
2387 } else {
2388 uint64_t inputs_read = ps->info.inputs_read;
2389
2390 if (ps->info.colors_read && sctx->queued.named.rasterizer->two_side) {
2391 if (inputs_read & BITFIELD64_BIT(SI_UNIQUE_SLOT_COL0))
2392 inputs_read |= BITFIELD64_BIT(SI_UNIQUE_SLOT_BFC0);
2393
2394 if (inputs_read & BITFIELD64_BIT(SI_UNIQUE_SLOT_COL1))
2395 inputs_read |= BITFIELD64_BIT(SI_UNIQUE_SLOT_BFC1);
2396 }
2397
2398 ps_inputs_read_or_disabled = inputs_read;
2399 }
2400
2401 if (sctx->ps_inputs_read_or_disabled != ps_inputs_read_or_disabled) {
2402 sctx->ps_inputs_read_or_disabled = ps_inputs_read_or_disabled;
2403 sctx->do_update_shaders = true;
2404 }
2405 }
2406
si_vs_ps_key_update_rast_prim_smooth_stipple(struct si_context * sctx)2407 void si_vs_ps_key_update_rast_prim_smooth_stipple(struct si_context *sctx)
2408 {
2409 struct si_shader_ctx_state *hw_vs = si_get_vs(sctx);
2410 struct si_shader_selector *ps = sctx->shader.ps.cso;
2411
2412 if (!hw_vs->cso || !ps)
2413 return;
2414
2415 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2416 union si_shader_key *vs_key = &hw_vs->key; /* could also be TES or GS before PS */
2417 union si_shader_key *ps_key = &sctx->shader.ps.key;
2418
2419 bool old_kill_pointsize = vs_key->ge.opt.kill_pointsize;
2420 bool old_color_two_side = ps_key->ps.part.prolog.color_two_side;
2421 bool old_poly_stipple = ps_key->ps.part.prolog.poly_stipple;
2422 bool old_poly_line_smoothing = ps_key->ps.mono.poly_line_smoothing;
2423 bool old_point_smoothing = ps_key->ps.mono.point_smoothing;
2424 int old_force_front_face_input = ps_key->ps.opt.force_front_face_input;
2425
2426 if (sctx->current_rast_prim == MESA_PRIM_POINTS) {
2427 vs_key->ge.opt.kill_pointsize = 0;
2428 ps_key->ps.part.prolog.color_two_side = 0;
2429 ps_key->ps.part.prolog.poly_stipple = 0;
2430 ps_key->ps.mono.poly_line_smoothing = 0;
2431 ps_key->ps.mono.point_smoothing = rs->point_smooth;
2432 ps_key->ps.opt.force_front_face_input = ps->info.uses_frontface;
2433 } else if (util_prim_is_lines(sctx->current_rast_prim)) {
2434 vs_key->ge.opt.kill_pointsize = hw_vs->cso->info.writes_psize;
2435 ps_key->ps.part.prolog.color_two_side = 0;
2436 ps_key->ps.part.prolog.poly_stipple = 0;
2437 ps_key->ps.mono.poly_line_smoothing = rs->line_smooth && sctx->framebuffer.nr_samples <= 1;
2438 ps_key->ps.mono.point_smoothing = 0;
2439 ps_key->ps.opt.force_front_face_input = ps->info.uses_frontface;
2440 } else {
2441 /* Triangles. */
2442 vs_key->ge.opt.kill_pointsize = hw_vs->cso->info.writes_psize &&
2443 !rs->polygon_mode_is_points;
2444 ps_key->ps.part.prolog.color_two_side = rs->two_side && ps->info.colors_read;
2445 ps_key->ps.part.prolog.poly_stipple = rs->poly_stipple_enable;
2446 ps_key->ps.mono.poly_line_smoothing = rs->poly_smooth && sctx->framebuffer.nr_samples <= 1;
2447 ps_key->ps.mono.point_smoothing = 0;
2448 ps_key->ps.opt.force_front_face_input = rs->force_front_face_input &&
2449 ps->info.uses_frontface;
2450 }
2451
2452 if (vs_key->ge.opt.kill_pointsize != old_kill_pointsize ||
2453 ps_key->ps.part.prolog.color_two_side != old_color_two_side ||
2454 ps_key->ps.part.prolog.poly_stipple != old_poly_stipple ||
2455 ps_key->ps.mono.poly_line_smoothing != old_poly_line_smoothing ||
2456 ps_key->ps.mono.point_smoothing != old_point_smoothing ||
2457 ps_key->ps.opt.force_front_face_input != old_force_front_face_input)
2458 sctx->do_update_shaders = true;
2459 }
2460
si_get_vs_key_outputs(struct si_context * sctx,struct si_shader_selector * vs,union si_shader_key * key)2461 static void si_get_vs_key_outputs(struct si_context *sctx, struct si_shader_selector *vs,
2462 union si_shader_key *key)
2463 {
2464 key->ge.opt.kill_clip_distances = vs->info.clipdist_mask & ~sctx->queued.named.rasterizer->clip_plane_enable;
2465
2466 /* Find out which VS outputs aren't used by the PS. */
2467 uint64_t outputs_written = vs->info.outputs_written_before_ps;
2468 uint64_t linked = outputs_written & sctx->ps_inputs_read_or_disabled;
2469
2470 key->ge.opt.kill_layer = vs->info.writes_layer &&
2471 sctx->framebuffer.state.layers <= 1;
2472 key->ge.opt.kill_outputs = ~linked & outputs_written;
2473 key->ge.opt.ngg_culling = sctx->ngg_culling;
2474 key->ge.mono.u.vs_export_prim_id = vs->stage != MESA_SHADER_GEOMETRY &&
2475 sctx->shader.ps.cso && sctx->shader.ps.cso->info.uses_primid;
2476 key->ge.opt.remove_streamout = vs->info.enabled_streamout_buffer_mask &&
2477 !sctx->streamout.enabled_mask;
2478 if (sctx->gfx_level >= GFX12)
2479 key->ge.mono.remove_streamout = key->ge.opt.remove_streamout;
2480 }
2481
si_clear_vs_key_outputs(struct si_context * sctx,struct si_shader_selector * vs,union si_shader_key * key)2482 static void si_clear_vs_key_outputs(struct si_context *sctx, struct si_shader_selector *vs,
2483 union si_shader_key *key)
2484 {
2485 key->ge.opt.kill_clip_distances = 0;
2486 key->ge.opt.kill_outputs = 0;
2487 key->ge.opt.remove_streamout = 0;
2488 key->ge.opt.ngg_culling = 0;
2489 key->ge.mono.u.vs_export_prim_id = 0;
2490 key->ge.mono.remove_streamout = 0;
2491 }
2492
si_ps_key_update_framebuffer(struct si_context * sctx)2493 void si_ps_key_update_framebuffer(struct si_context *sctx)
2494 {
2495 struct si_shader_selector *sel = sctx->shader.ps.cso;
2496 union si_shader_key *key = &sctx->shader.ps.key;
2497
2498 if (!sel)
2499 return;
2500
2501 if (sel->info.color0_writes_all_cbufs &&
2502 sel->info.colors_written == 0x1)
2503 key->ps.part.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
2504 else
2505 key->ps.part.epilog.last_cbuf = 0;
2506
2507 /* ps_uses_fbfetch is true only if the color buffer is bound. */
2508 if (sctx->ps_uses_fbfetch) {
2509 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
2510 struct pipe_resource *tex = cb0->texture;
2511
2512 /* 1D textures are allocated and used as 2D on GFX9. */
2513 key->ps.mono.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
2514 key->ps.mono.fbfetch_is_1D =
2515 sctx->gfx_level != GFX9 &&
2516 (tex->target == PIPE_TEXTURE_1D || tex->target == PIPE_TEXTURE_1D_ARRAY);
2517 key->ps.mono.fbfetch_layered =
2518 tex->target == PIPE_TEXTURE_1D_ARRAY || tex->target == PIPE_TEXTURE_2D_ARRAY ||
2519 tex->target == PIPE_TEXTURE_CUBE || tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
2520 tex->target == PIPE_TEXTURE_3D;
2521 } else {
2522 key->ps.mono.fbfetch_msaa = 0;
2523 key->ps.mono.fbfetch_is_1D = 0;
2524 key->ps.mono.fbfetch_layered = 0;
2525 }
2526 }
2527
si_ps_key_update_framebuffer_blend_rasterizer(struct si_context * sctx)2528 void si_ps_key_update_framebuffer_blend_rasterizer(struct si_context *sctx)
2529 {
2530 struct si_shader_selector *sel = sctx->shader.ps.cso;
2531 if (!sel)
2532 return;
2533
2534 union si_shader_key *key = &sctx->shader.ps.key;
2535 struct si_state_blend *blend = sctx->queued.named.blend;
2536 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2537 bool alpha_to_coverage = blend->alpha_to_coverage && rs->multisample_enable &&
2538 sctx->framebuffer.nr_samples >= 2;
2539 unsigned need_src_alpha_4bit = blend->need_src_alpha_4bit;
2540
2541 /* Old key data for comparison. */
2542 struct si_ps_epilog_bits old_epilog;
2543 memcpy(&old_epilog, &key->ps.part.epilog, sizeof(old_epilog));
2544 bool old_prefer_mono = key->ps.opt.prefer_mono;
2545 #ifndef NDEBUG
2546 struct si_shader_key_ps old_key;
2547 memcpy(&old_key, &key->ps, sizeof(old_key));
2548 #endif
2549
2550 key->ps.part.epilog.alpha_to_one = blend->alpha_to_one && rs->multisample_enable;
2551 key->ps.part.epilog.alpha_to_coverage_via_mrtz =
2552 sctx->gfx_level >= GFX11 && alpha_to_coverage &&
2553 (sel->info.writes_z || sel->info.writes_stencil || sel->info.writes_samplemask);
2554
2555 /* Remove the gl_SampleMask fragment shader output if MSAA is disabled.
2556 * This is required for correctness and it's also an optimization.
2557 */
2558 key->ps.part.epilog.kill_samplemask = sel->info.writes_samplemask &&
2559 (sctx->framebuffer.nr_samples <= 1 ||
2560 !rs->multisample_enable);
2561
2562 /* If alpha-to-coverage isn't exported via MRTZ, set that we need to export alpha
2563 * through MRT0.
2564 */
2565 if (alpha_to_coverage && !key->ps.part.epilog.alpha_to_coverage_via_mrtz)
2566 need_src_alpha_4bit |= 0xf;
2567
2568 /* Select the shader color format based on whether
2569 * blending or alpha are needed.
2570 */
2571 key->ps.part.epilog.spi_shader_col_format =
2572 (blend->blend_enable_4bit & need_src_alpha_4bit &
2573 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
2574 (blend->blend_enable_4bit & ~need_src_alpha_4bit &
2575 sctx->framebuffer.spi_shader_col_format_blend) |
2576 (~blend->blend_enable_4bit & need_src_alpha_4bit &
2577 sctx->framebuffer.spi_shader_col_format_alpha) |
2578 (~blend->blend_enable_4bit & ~need_src_alpha_4bit &
2579 sctx->framebuffer.spi_shader_col_format);
2580 key->ps.part.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
2581
2582 key->ps.part.epilog.dual_src_blend_swizzle = sctx->gfx_level >= GFX11 &&
2583 blend->dual_src_blend &&
2584 (sel->info.colors_written_4bit & 0xff) == 0xff;
2585
2586 /* The output for dual source blending should have
2587 * the same format as the first output.
2588 */
2589 if (blend->dual_src_blend) {
2590 key->ps.part.epilog.spi_shader_col_format |=
2591 (key->ps.part.epilog.spi_shader_col_format & 0xf) << 4;
2592 }
2593
2594 /* If alpha-to-coverage is enabled, we have to export alpha
2595 * even if there is no color buffer.
2596 *
2597 * Gfx11 exports alpha-to-coverage via MRTZ if MRTZ is present.
2598 */
2599 if (!(key->ps.part.epilog.spi_shader_col_format & 0xf) && alpha_to_coverage &&
2600 !key->ps.part.epilog.alpha_to_coverage_via_mrtz)
2601 key->ps.part.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
2602
2603 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
2604 * to the range supported by the type if a channel has less
2605 * than 16 bits and the export format is 16_ABGR.
2606 */
2607 if (sctx->gfx_level <= GFX7 && sctx->family != CHIP_HAWAII) {
2608 key->ps.part.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
2609 key->ps.part.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
2610 }
2611
2612 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
2613 if (!key->ps.part.epilog.last_cbuf) {
2614 key->ps.part.epilog.spi_shader_col_format &= sel->info.colors_written_4bit;
2615 key->ps.part.epilog.color_is_int8 &= sel->info.colors_written;
2616 key->ps.part.epilog.color_is_int10 &= sel->info.colors_written;
2617 }
2618
2619 /* Enable RB+ for depth-only rendering. Registers must be programmed as follows:
2620 * CB_COLOR_CONTROL.MODE = CB_DISABLE
2621 * CB_COLOR0_INFO.FORMAT = COLOR_32
2622 * CB_COLOR0_INFO.NUMBER_TYPE = NUMBER_FLOAT
2623 * SPI_SHADER_COL_FORMAT.COL0_EXPORT_FORMAT = SPI_SHADER_32_R
2624 * SX_PS_DOWNCONVERT.MRT0 = SX_RT_EXPORT_32_R
2625 *
2626 * Also, the following conditions must be met.
2627 */
2628 key->ps.part.epilog.rbplus_depth_only_opt =
2629 sctx->screen->info.rbplus_allowed &&
2630 blend->cb_target_enabled_4bit == 0 && /* implies CB_DISABLE */
2631 !alpha_to_coverage &&
2632 !sel->info.base.writes_memory &&
2633 !key->ps.part.epilog.spi_shader_col_format;
2634
2635 /* Eliminate shader code computing output values that are unused.
2636 * This enables dead code elimination between shader parts.
2637 * Check if any output is eliminated.
2638 *
2639 * Dual source blending never has color buffer 1 enabled, so ignore it.
2640 *
2641 * On gfx11, pixel shaders that write memory should be compiled with an inlined epilog,
2642 * so that the compiler can see s_endpgm and deallocates VGPRs before memory stores return.
2643 */
2644 if (sel->info.colors_written_4bit &
2645 (blend->dual_src_blend ? 0xffffff0f : 0xffffffff) &
2646 ~(sctx->framebuffer.colorbuf_enabled_4bit & blend->cb_target_enabled_4bit))
2647 key->ps.opt.prefer_mono = 1;
2648 else if (sctx->gfx_level >= GFX11 && sel->info.base.writes_memory)
2649 key->ps.opt.prefer_mono = 1;
2650 else
2651 key->ps.opt.prefer_mono = 0;
2652
2653 /* Update shaders only if the key changed. */
2654 if (memcmp(&key->ps.part.epilog, &old_epilog, sizeof(old_epilog)) ||
2655 key->ps.opt.prefer_mono != old_prefer_mono) {
2656 sctx->do_update_shaders = true;
2657 } else {
2658 assert(memcmp(&key->ps, &old_key, sizeof(old_key)) == 0);
2659 }
2660 }
2661
si_ps_key_update_rasterizer(struct si_context * sctx)2662 void si_ps_key_update_rasterizer(struct si_context *sctx)
2663 {
2664 struct si_shader_selector *sel = sctx->shader.ps.cso;
2665 union si_shader_key *key = &sctx->shader.ps.key;
2666 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2667
2668 if (!sel)
2669 return;
2670
2671 bool old_flatshade_colors = key->ps.part.prolog.flatshade_colors;
2672 bool old_clamp_color = key->ps.part.epilog.clamp_color;
2673
2674 key->ps.part.prolog.flatshade_colors = rs->flatshade && sel->info.uses_interp_color;
2675 key->ps.part.epilog.clamp_color = rs->clamp_fragment_color;
2676
2677 if (key->ps.part.prolog.flatshade_colors != old_flatshade_colors ||
2678 key->ps.part.epilog.clamp_color != old_clamp_color)
2679 sctx->do_update_shaders = true;
2680 }
2681
si_ps_key_update_dsa(struct si_context * sctx)2682 void si_ps_key_update_dsa(struct si_context *sctx)
2683 {
2684 union si_shader_key *key = &sctx->shader.ps.key;
2685
2686 key->ps.part.epilog.alpha_func = sctx->queued.named.dsa->alpha_func;
2687 }
2688
si_ps_key_update_sample_shading(struct si_context * sctx)2689 void si_ps_key_update_sample_shading(struct si_context *sctx)
2690 {
2691 struct si_shader_selector *sel = sctx->shader.ps.cso;
2692 union si_shader_key *key = &sctx->shader.ps.key;
2693
2694 if (!sel)
2695 return;
2696
2697 if (sctx->ps_iter_samples > 1 && sel->info.reads_samplemask)
2698 key->ps.part.prolog.samplemask_log_ps_iter = util_logbase2(sctx->ps_iter_samples);
2699 else
2700 key->ps.part.prolog.samplemask_log_ps_iter = 0;
2701 }
2702
si_ps_key_update_framebuffer_rasterizer_sample_shading(struct si_context * sctx)2703 void si_ps_key_update_framebuffer_rasterizer_sample_shading(struct si_context *sctx)
2704 {
2705 struct si_shader_selector *sel = sctx->shader.ps.cso;
2706 union si_shader_key *key = &sctx->shader.ps.key;
2707 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2708
2709 if (!sel)
2710 return;
2711
2712 /* Old key data for comparison. */
2713 struct si_ps_prolog_bits old_prolog;
2714 memcpy(&old_prolog, &key->ps.part.prolog, sizeof(old_prolog));
2715 bool old_interpolate_at_sample_force_center = key->ps.mono.interpolate_at_sample_force_center;
2716
2717 bool uses_persp_center = sel->info.uses_persp_center ||
2718 (!rs->flatshade && sel->info.uses_persp_center_color);
2719 bool uses_persp_centroid = sel->info.uses_persp_centroid ||
2720 (!rs->flatshade && sel->info.uses_persp_centroid_color);
2721 bool uses_persp_sample = sel->info.uses_persp_sample ||
2722 (!rs->flatshade && sel->info.uses_persp_sample_color);
2723
2724 if (rs->force_persample_interp && rs->multisample_enable &&
2725 sctx->framebuffer.nr_samples > 1 && sctx->ps_iter_samples > 1) {
2726 key->ps.part.prolog.force_persp_sample_interp =
2727 uses_persp_center || uses_persp_centroid;
2728
2729 key->ps.part.prolog.force_linear_sample_interp =
2730 sel->info.uses_linear_center || sel->info.uses_linear_centroid;
2731
2732 key->ps.part.prolog.force_persp_center_interp = 0;
2733 key->ps.part.prolog.force_linear_center_interp = 0;
2734 key->ps.part.prolog.bc_optimize_for_persp = 0;
2735 key->ps.part.prolog.bc_optimize_for_linear = 0;
2736 key->ps.mono.interpolate_at_sample_force_center = 0;
2737 } else if (rs->multisample_enable && sctx->framebuffer.nr_samples > 1) {
2738 key->ps.part.prolog.force_persp_sample_interp = 0;
2739 key->ps.part.prolog.force_linear_sample_interp = 0;
2740 key->ps.part.prolog.force_persp_center_interp = 0;
2741 key->ps.part.prolog.force_linear_center_interp = 0;
2742 key->ps.part.prolog.bc_optimize_for_persp =
2743 uses_persp_center && uses_persp_centroid;
2744 key->ps.part.prolog.bc_optimize_for_linear =
2745 sel->info.uses_linear_center && sel->info.uses_linear_centroid;
2746 key->ps.mono.interpolate_at_sample_force_center = 0;
2747 } else {
2748 key->ps.part.prolog.force_persp_sample_interp = 0;
2749 key->ps.part.prolog.force_linear_sample_interp = 0;
2750
2751 /* Make sure SPI doesn't compute more than 1 pair
2752 * of (i,j), which is the optimization here. */
2753 key->ps.part.prolog.force_persp_center_interp = uses_persp_center +
2754 uses_persp_centroid +
2755 uses_persp_sample > 1;
2756
2757 key->ps.part.prolog.force_linear_center_interp = sel->info.uses_linear_center +
2758 sel->info.uses_linear_centroid +
2759 sel->info.uses_linear_sample > 1;
2760 key->ps.part.prolog.bc_optimize_for_persp = 0;
2761 key->ps.part.prolog.bc_optimize_for_linear = 0;
2762 key->ps.mono.interpolate_at_sample_force_center = sel->info.uses_interp_at_sample;
2763 }
2764
2765 /* Update shaders only if the key changed. */
2766 if (memcmp(&key->ps.part.prolog, &old_prolog, sizeof(old_prolog)) ||
2767 key->ps.mono.interpolate_at_sample_force_center != old_interpolate_at_sample_force_center)
2768 sctx->do_update_shaders = true;
2769 }
2770
2771 /* Compute the key for the hw shader variant */
si_shader_selector_key(struct pipe_context * ctx,struct si_shader_selector * sel,union si_shader_key * key)2772 static inline void si_shader_selector_key(struct pipe_context *ctx, struct si_shader_selector *sel,
2773 union si_shader_key *key)
2774 {
2775 struct si_context *sctx = (struct si_context *)ctx;
2776
2777 switch (sel->stage) {
2778 case MESA_SHADER_VERTEX:
2779 if (!sctx->shader.tes.cso && !sctx->shader.gs.cso)
2780 si_get_vs_key_outputs(sctx, sel, key);
2781 else
2782 si_clear_vs_key_outputs(sctx, sel, key);
2783 break;
2784 case MESA_SHADER_TESS_CTRL:
2785 if (sctx->gfx_level >= GFX9) {
2786 si_get_vs_key_inputs(sctx, key);
2787 key->ge.part.tcs.ls = sctx->shader.vs.cso;
2788 }
2789 break;
2790 case MESA_SHADER_TESS_EVAL:
2791 if (!sctx->shader.gs.cso)
2792 si_get_vs_key_outputs(sctx, sel, key);
2793 else
2794 si_clear_vs_key_outputs(sctx, sel, key);
2795 break;
2796 case MESA_SHADER_GEOMETRY:
2797 if (sctx->gfx_level >= GFX9) {
2798 if (sctx->shader.tes.cso) {
2799 si_clear_vs_key_inputs(key);
2800 key->ge.part.gs.es = sctx->shader.tes.cso;
2801 } else {
2802 si_get_vs_key_inputs(sctx, key);
2803 key->ge.part.gs.es = sctx->shader.vs.cso;
2804 }
2805
2806 /* Only NGG can eliminate GS outputs, because the code is shared with VS. */
2807 if (sctx->ngg)
2808 si_get_vs_key_outputs(sctx, sel, key);
2809 else
2810 si_clear_vs_key_outputs(sctx, sel, key);
2811 }
2812 break;
2813 case MESA_SHADER_FRAGMENT:
2814 break;
2815 default:
2816 assert(0);
2817 }
2818 }
2819
si_build_shader_variant(struct si_shader * shader,int thread_index,bool low_priority)2820 static void si_build_shader_variant(struct si_shader *shader, int thread_index, bool low_priority)
2821 {
2822 struct si_shader_selector *sel = shader->selector;
2823 struct si_screen *sscreen = sel->screen;
2824 struct ac_llvm_compiler **compiler;
2825 struct util_debug_callback *debug = &shader->compiler_ctx_state.debug;
2826
2827 if (thread_index >= 0) {
2828 if (low_priority) {
2829 assert(thread_index < (int)ARRAY_SIZE(sscreen->compiler_lowp));
2830 compiler = &sscreen->compiler_lowp[thread_index];
2831 } else {
2832 assert(thread_index < (int)ARRAY_SIZE(sscreen->compiler));
2833 compiler = &sscreen->compiler[thread_index];
2834 }
2835 if (!debug->async)
2836 debug = NULL;
2837 } else {
2838 assert(!low_priority);
2839 compiler = &shader->compiler_ctx_state.compiler;
2840 }
2841
2842 if (!sel->info.base.use_aco_amd && !*compiler)
2843 *compiler = si_create_llvm_compiler(sscreen);
2844
2845 if (unlikely(!si_create_shader_variant(sscreen, *compiler, shader, debug))) {
2846 PRINT_ERR("Failed to build shader variant (type=%u)\n", sel->stage);
2847 shader->compilation_failed = true;
2848 return;
2849 }
2850
2851 if (shader->compiler_ctx_state.is_debug_context) {
2852 FILE *f = open_memstream(&shader->shader_log, &shader->shader_log_size);
2853 if (f) {
2854 si_shader_dump(sscreen, shader, NULL, f, false);
2855 fclose(f);
2856 }
2857 }
2858
2859 si_shader_init_pm4_state(sscreen, shader);
2860 }
2861
si_build_shader_variant_low_priority(void * job,void * gdata,int thread_index)2862 static void si_build_shader_variant_low_priority(void *job, void *gdata, int thread_index)
2863 {
2864 struct si_shader *shader = (struct si_shader *)job;
2865
2866 assert(thread_index >= 0);
2867
2868 si_build_shader_variant(shader, thread_index, true);
2869 }
2870
2871 /* This should be const, but C++ doesn't allow implicit zero-initialization with const. */
2872 static union si_shader_key zeroed;
2873
si_check_missing_main_part(struct si_screen * sscreen,struct si_shader_selector * sel,struct si_compiler_ctx_state * compiler_state,const union si_shader_key * key,unsigned wave_size)2874 static bool si_check_missing_main_part(struct si_screen *sscreen, struct si_shader_selector *sel,
2875 struct si_compiler_ctx_state *compiler_state,
2876 const union si_shader_key *key, unsigned wave_size)
2877 {
2878 struct si_shader **mainp = si_get_main_shader_part(sel, key, wave_size);
2879
2880 if (!*mainp) {
2881 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
2882
2883 if (!main_part)
2884 return false;
2885
2886 /* We can leave the fence as permanently signaled because the
2887 * main part becomes visible globally only after it has been
2888 * compiled. */
2889 util_queue_fence_init(&main_part->ready);
2890
2891 main_part->selector = sel;
2892 if (sel->stage <= MESA_SHADER_GEOMETRY) {
2893 main_part->key.ge.as_es = key->ge.as_es;
2894 main_part->key.ge.as_ls = key->ge.as_ls;
2895 main_part->key.ge.as_ngg = key->ge.as_ngg;
2896 }
2897 main_part->is_monolithic = false;
2898 main_part->wave_size = wave_size;
2899
2900 if (!si_compile_shader(sscreen, compiler_state->compiler, main_part,
2901 &compiler_state->debug)) {
2902 FREE(main_part);
2903 return false;
2904 }
2905 *mainp = main_part;
2906 }
2907 return true;
2908 }
2909
2910 /* A helper to copy *key to *local_key and return local_key. */
2911 template<typename SHADER_KEY_TYPE>
2912 static ALWAYS_INLINE const SHADER_KEY_TYPE *
use_local_key_copy(const SHADER_KEY_TYPE * key,SHADER_KEY_TYPE * local_key,unsigned key_size)2913 use_local_key_copy(const SHADER_KEY_TYPE *key, SHADER_KEY_TYPE *local_key, unsigned key_size)
2914 {
2915 if (key != local_key)
2916 memcpy(local_key, key, key_size);
2917
2918 return local_key;
2919 }
2920
2921 #define NO_INLINE_UNIFORMS false
2922
2923 /**
2924 * Select a shader variant according to the shader key.
2925 *
2926 * This uses a C++ template to compute the optimal memcmp size at compile time, which is important
2927 * for getting inlined memcmp. The memcmp size depends on the shader key type and whether inlined
2928 * uniforms are enabled.
2929 */
2930 template<bool INLINE_UNIFORMS = true, typename SHADER_KEY_TYPE>
si_shader_select_with_key(struct si_context * sctx,struct si_shader_ctx_state * state,const SHADER_KEY_TYPE * key)2931 static int si_shader_select_with_key(struct si_context *sctx, struct si_shader_ctx_state *state,
2932 const SHADER_KEY_TYPE *key)
2933 {
2934 struct si_screen *sscreen = sctx->screen;
2935 struct si_shader_selector *sel = state->cso;
2936 struct si_shader_selector *previous_stage_sel = NULL;
2937 struct si_shader *current = state->current;
2938 struct si_shader *shader = NULL;
2939 const SHADER_KEY_TYPE *zeroed_key = (SHADER_KEY_TYPE*)&zeroed;
2940
2941 /* "opt" must be the last field and "inlined_uniform_values" must be the last field inside opt.
2942 * If there is padding, insert the padding manually before opt or inside opt.
2943 */
2944 STATIC_ASSERT(offsetof(SHADER_KEY_TYPE, opt) + sizeof(key->opt) == sizeof(*key));
2945 STATIC_ASSERT(offsetof(SHADER_KEY_TYPE, opt.inlined_uniform_values) +
2946 sizeof(key->opt.inlined_uniform_values) == sizeof(*key));
2947
2948 const unsigned key_size_no_uniforms = sizeof(*key) - sizeof(key->opt.inlined_uniform_values);
2949 /* Don't compare inlined_uniform_values if uniform inlining is disabled. */
2950 const unsigned key_size = INLINE_UNIFORMS ? sizeof(*key) : key_size_no_uniforms;
2951 const unsigned key_opt_size =
2952 INLINE_UNIFORMS ? sizeof(key->opt) :
2953 sizeof(key->opt) - sizeof(key->opt.inlined_uniform_values);
2954
2955 /* si_shader_select_with_key must not modify 'key' because it would affect future shaders.
2956 * If we need to modify it for this specific shader (eg: to disable optimizations), we
2957 * use a copy.
2958 */
2959 SHADER_KEY_TYPE local_key;
2960
2961 if (unlikely(sscreen->debug_flags & DBG(NO_OPT_VARIANT))) {
2962 /* Disable shader variant optimizations. */
2963 key = use_local_key_copy<SHADER_KEY_TYPE>(key, &local_key, key_size);
2964 memset(&local_key.opt, 0, key_opt_size);
2965 }
2966
2967 again:
2968 /* Check if we don't need to change anything.
2969 * This path is also used for most shaders that don't need multiple
2970 * variants, it will cost just a computation of the key and this
2971 * test. */
2972 if (likely(current && memcmp(¤t->key, key, key_size) == 0)) {
2973 if (unlikely(!util_queue_fence_is_signalled(¤t->ready))) {
2974 if (current->is_optimized) {
2975 key = use_local_key_copy(key, &local_key, key_size);
2976 memset(&local_key.opt, 0, key_opt_size);
2977 goto current_not_ready;
2978 }
2979
2980 util_queue_fence_wait(¤t->ready);
2981 }
2982
2983 return current->compilation_failed ? -1 : 0;
2984 }
2985 current_not_ready:
2986
2987 /* This must be done before the mutex is locked, because async GS
2988 * compilation calls this function too, and therefore must enter
2989 * the mutex first.
2990 */
2991 util_queue_fence_wait(&sel->ready);
2992
2993 simple_mtx_lock(&sel->mutex);
2994
2995 int variant_count = 0;
2996 const int max_inline_uniforms_variants = 5;
2997
2998 /* Find the shader variant. */
2999 const unsigned cnt = sel->variants_count;
3000 for (unsigned i = 0; i < cnt; i++) {
3001 const SHADER_KEY_TYPE *iter_key = (const SHADER_KEY_TYPE *)&sel->keys[i];
3002
3003 if (memcmp(iter_key, key, key_size_no_uniforms) == 0) {
3004 struct si_shader *iter = sel->variants[i];
3005
3006 /* Check the inlined uniform values separately, and count
3007 * the number of variants based on them.
3008 */
3009 if (key->opt.inline_uniforms &&
3010 memcmp(iter_key->opt.inlined_uniform_values,
3011 key->opt.inlined_uniform_values,
3012 MAX_INLINABLE_UNIFORMS * 4) != 0) {
3013 if (variant_count++ > max_inline_uniforms_variants) {
3014 key = use_local_key_copy(key, &local_key, key_size);
3015 /* Too many variants. Disable inlining for this shader. */
3016 local_key.opt.inline_uniforms = 0;
3017 memset(local_key.opt.inlined_uniform_values, 0, MAX_INLINABLE_UNIFORMS * 4);
3018 simple_mtx_unlock(&sel->mutex);
3019 goto again;
3020 }
3021 continue;
3022 }
3023
3024 simple_mtx_unlock(&sel->mutex);
3025
3026 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
3027 /* If it's an optimized shader and its compilation has
3028 * been started but isn't done, use the unoptimized
3029 * shader so as not to cause a stall due to compilation.
3030 */
3031 if (iter->is_optimized) {
3032 key = use_local_key_copy(key, &local_key, key_size);
3033 memset(&local_key.opt, 0, key_opt_size);
3034 goto again;
3035 }
3036
3037 util_queue_fence_wait(&iter->ready);
3038 }
3039
3040 if (iter->compilation_failed) {
3041 return -1; /* skip the draw call */
3042 }
3043
3044 state->current = sel->variants[i];
3045 return 0;
3046 }
3047 }
3048
3049 /* Build a new shader. */
3050 shader = CALLOC_STRUCT(si_shader);
3051 if (!shader) {
3052 simple_mtx_unlock(&sel->mutex);
3053 return -ENOMEM;
3054 }
3055
3056 util_queue_fence_init(&shader->ready);
3057
3058 if (!sel->info.base.use_aco_amd && !sctx->compiler)
3059 sctx->compiler = si_create_llvm_compiler(sctx->screen);
3060
3061 shader->selector = sel;
3062 *((SHADER_KEY_TYPE*)&shader->key) = *key;
3063 shader->wave_size = si_determine_wave_size(sscreen, shader);
3064 shader->compiler_ctx_state.compiler = sctx->compiler;
3065 shader->compiler_ctx_state.debug = sctx->debug;
3066 shader->compiler_ctx_state.is_debug_context = sctx->is_debug;
3067
3068 /* If this is a merged shader, get the first shader's selector. */
3069 if (sscreen->info.gfx_level >= GFX9) {
3070 if (sel->stage == MESA_SHADER_TESS_CTRL)
3071 previous_stage_sel = ((struct si_shader_key_ge*)key)->part.tcs.ls;
3072 else if (sel->stage == MESA_SHADER_GEOMETRY)
3073 previous_stage_sel = ((struct si_shader_key_ge*)key)->part.gs.es;
3074
3075 /* We need to wait for the previous shader. */
3076 if (previous_stage_sel)
3077 util_queue_fence_wait(&previous_stage_sel->ready);
3078 }
3079
3080 bool is_pure_monolithic =
3081 sscreen->use_monolithic_shaders || memcmp(&key->mono, &zeroed_key->mono, sizeof(key->mono)) != 0;
3082
3083 /* Compile the main shader part if it doesn't exist. This can happen
3084 * if the initial guess was wrong.
3085 */
3086 if (!is_pure_monolithic) {
3087 bool ok = true;
3088
3089 /* Make sure the main shader part is present. This is needed
3090 * for shaders that can be compiled as VS, LS, or ES, and only
3091 * one of them is compiled at creation.
3092 *
3093 * It is also needed for GS, which can be compiled as non-NGG
3094 * and NGG.
3095 *
3096 * For merged shaders, check that the starting shader's main
3097 * part is present.
3098 */
3099 if (previous_stage_sel) {
3100 union si_shader_key shader1_key = zeroed;
3101
3102 if (sel->stage == MESA_SHADER_TESS_CTRL) {
3103 shader1_key.ge.as_ls = 1;
3104 } else if (sel->stage == MESA_SHADER_GEOMETRY) {
3105 shader1_key.ge.as_es = 1;
3106 shader1_key.ge.as_ngg = ((struct si_shader_key_ge*)key)->as_ngg; /* for Wave32 vs Wave64 */
3107 } else {
3108 assert(0);
3109 }
3110
3111 simple_mtx_lock(&previous_stage_sel->mutex);
3112 ok = si_check_missing_main_part(sscreen, previous_stage_sel, &shader->compiler_ctx_state,
3113 &shader1_key, shader->wave_size);
3114 simple_mtx_unlock(&previous_stage_sel->mutex);
3115 }
3116
3117 if (ok) {
3118 ok = si_check_missing_main_part(sscreen, sel, &shader->compiler_ctx_state,
3119 (union si_shader_key*)key, shader->wave_size);
3120 }
3121
3122 if (!ok) {
3123 FREE(shader);
3124 simple_mtx_unlock(&sel->mutex);
3125 return -ENOMEM; /* skip the draw call */
3126 }
3127 }
3128
3129 if (sel->variants_count == sel->variants_max_count) {
3130 sel->variants_max_count += 2;
3131 sel->variants = (struct si_shader**)
3132 realloc(sel->variants, sel->variants_max_count * sizeof(struct si_shader*));
3133 sel->keys = (union si_shader_key*)
3134 realloc(sel->keys, sel->variants_max_count * sizeof(union si_shader_key));
3135 }
3136
3137 /* Keep the reference to the 1st shader of merged shaders, so that
3138 * Gallium can't destroy it before we destroy the 2nd shader.
3139 *
3140 * Set sctx = NULL, because it's unused if we're not releasing
3141 * the shader, and we don't have any sctx here.
3142 */
3143 si_shader_selector_reference(NULL, &shader->previous_stage_sel, previous_stage_sel);
3144
3145 /* Monolithic-only shaders don't make a distinction between optimized
3146 * and unoptimized. */
3147 shader->is_monolithic =
3148 is_pure_monolithic || memcmp(&key->opt, &zeroed_key->opt, key_opt_size) != 0;
3149
3150 shader->is_optimized = !is_pure_monolithic &&
3151 memcmp(&key->opt, &zeroed_key->opt, key_opt_size) != 0;
3152
3153 /* If it's an optimized shader, compile it asynchronously. */
3154 if (shader->is_optimized) {
3155 /* Compile it asynchronously. */
3156 util_queue_add_job(&sscreen->shader_compiler_queue_opt_variants, shader, &shader->ready,
3157 si_build_shader_variant_low_priority, NULL, 0);
3158
3159 /* Add only after the ready fence was reset, to guard against a
3160 * race with si_bind_XX_shader. */
3161 sel->variants[sel->variants_count] = shader;
3162 sel->keys[sel->variants_count] = shader->key;
3163 sel->variants_count++;
3164
3165 /* Use the default (unoptimized) shader for now. */
3166 key = use_local_key_copy(key, &local_key, key_size);
3167 memset(&local_key.opt, 0, key_opt_size);
3168 simple_mtx_unlock(&sel->mutex);
3169
3170 if (sscreen->options.sync_compile)
3171 util_queue_fence_wait(&shader->ready);
3172
3173 goto again;
3174 }
3175
3176 /* Reset the fence before adding to the variant list. */
3177 util_queue_fence_reset(&shader->ready);
3178
3179 sel->variants[sel->variants_count] = shader;
3180 sel->keys[sel->variants_count] = shader->key;
3181 sel->variants_count++;
3182
3183 simple_mtx_unlock(&sel->mutex);
3184
3185 assert(!shader->is_optimized);
3186 si_build_shader_variant(shader, -1, false);
3187
3188 util_queue_fence_signal(&shader->ready);
3189
3190 if (!shader->compilation_failed)
3191 state->current = shader;
3192
3193 return shader->compilation_failed ? -1 : 0;
3194 }
3195
si_shader_select(struct pipe_context * ctx,struct si_shader_ctx_state * state)3196 int si_shader_select(struct pipe_context *ctx, struct si_shader_ctx_state *state)
3197 {
3198 struct si_context *sctx = (struct si_context *)ctx;
3199
3200 si_shader_selector_key(ctx, state->cso, &state->key);
3201
3202 if (state->cso->stage == MESA_SHADER_FRAGMENT) {
3203 if (state->key.ps.opt.inline_uniforms)
3204 return si_shader_select_with_key(sctx, state, &state->key.ps);
3205 else
3206 return si_shader_select_with_key<NO_INLINE_UNIFORMS>(sctx, state, &state->key.ps);
3207 } else {
3208 if (state->key.ge.opt.inline_uniforms) {
3209 return si_shader_select_with_key(sctx, state, &state->key.ge);
3210 } else {
3211 return si_shader_select_with_key<NO_INLINE_UNIFORMS>(sctx, state, &state->key.ge);
3212 }
3213 }
3214 }
3215
si_parse_next_shader_property(const struct si_shader_info * info,union si_shader_key * key)3216 static void si_parse_next_shader_property(const struct si_shader_info *info,
3217 union si_shader_key *key)
3218 {
3219 gl_shader_stage next_shader = info->base.next_stage;
3220
3221 switch (info->base.stage) {
3222 case MESA_SHADER_VERTEX:
3223 switch (next_shader) {
3224 case MESA_SHADER_GEOMETRY:
3225 key->ge.as_es = 1;
3226 break;
3227 case MESA_SHADER_TESS_CTRL:
3228 case MESA_SHADER_TESS_EVAL:
3229 key->ge.as_ls = 1;
3230 break;
3231 default:
3232 /* If POSITION isn't written, it can only be a HW VS
3233 * if streamout is used. If streamout isn't used,
3234 * assume that it's a HW LS. (the next shader is TCS)
3235 * This heuristic is needed for separate shader objects.
3236 */
3237 if (!info->writes_position && !info->enabled_streamout_buffer_mask)
3238 key->ge.as_ls = 1;
3239 }
3240 break;
3241
3242 case MESA_SHADER_TESS_EVAL:
3243 if (next_shader == MESA_SHADER_GEOMETRY || !info->writes_position)
3244 key->ge.as_es = 1;
3245 break;
3246
3247 default:;
3248 }
3249 }
3250
3251 /**
3252 * Compile the main shader part or the monolithic shader as part of
3253 * si_shader_selector initialization. Since it can be done asynchronously,
3254 * there is no way to report compile failures to applications.
3255 */
si_init_shader_selector_async(void * job,void * gdata,int thread_index)3256 static void si_init_shader_selector_async(void *job, void *gdata, int thread_index)
3257 {
3258 struct si_shader_selector *sel = (struct si_shader_selector *)job;
3259 struct si_screen *sscreen = sel->screen;
3260 struct ac_llvm_compiler **compiler;
3261 struct util_debug_callback *debug = &sel->compiler_ctx_state.debug;
3262
3263 assert(!debug->debug_message || debug->async);
3264 assert(thread_index >= 0);
3265 assert(thread_index < (int)ARRAY_SIZE(sscreen->compiler));
3266 compiler = &sscreen->compiler[thread_index];
3267
3268 if (!sel->info.base.use_aco_amd && !*compiler)
3269 *compiler = si_create_llvm_compiler(sscreen);
3270
3271 /* Serialize NIR to save memory. Monolithic shader variants
3272 * have to deserialize NIR before compilation.
3273 */
3274 if (sel->nir) {
3275 struct blob blob;
3276 size_t size;
3277
3278 blob_init(&blob);
3279 /* true = remove optional debugging data to increase
3280 * the likehood of getting more shader cache hits.
3281 * It also drops variable names, so we'll save more memory.
3282 * If NIR debug prints are used we don't strip to get more
3283 * useful logs.
3284 */
3285 nir_serialize(&blob, sel->nir, NIR_DEBUG(PRINT) == 0);
3286 blob_finish_get_buffer(&blob, &sel->nir_binary, &size);
3287 sel->nir_size = size;
3288 }
3289
3290 /* Compile the main shader part for use with a prolog and/or epilog.
3291 * If this fails, the driver will try to compile a monolithic shader
3292 * on demand.
3293 */
3294 if (!sscreen->use_monolithic_shaders) {
3295 struct si_shader *shader = CALLOC_STRUCT(si_shader);
3296 unsigned char ir_sha1_cache_key[20];
3297
3298 if (!shader) {
3299 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
3300 return;
3301 }
3302
3303 /* We can leave the fence signaled because use of the default
3304 * main part is guarded by the selector's ready fence. */
3305 util_queue_fence_init(&shader->ready);
3306
3307 shader->selector = sel;
3308 shader->is_monolithic = false;
3309 si_parse_next_shader_property(&sel->info, &shader->key);
3310
3311 if (sel->stage <= MESA_SHADER_GEOMETRY &&
3312 sscreen->use_ngg && (!sel->info.enabled_streamout_buffer_mask ||
3313 sscreen->info.gfx_level >= GFX11) &&
3314 ((sel->stage == MESA_SHADER_VERTEX && !shader->key.ge.as_ls) ||
3315 sel->stage == MESA_SHADER_TESS_EVAL || sel->stage == MESA_SHADER_GEOMETRY))
3316 shader->key.ge.as_ngg = 1;
3317
3318 shader->wave_size = si_determine_wave_size(sscreen, shader);
3319
3320 if (sel->nir) {
3321 if (sel->stage <= MESA_SHADER_GEOMETRY) {
3322 si_get_ir_cache_key(sel, shader->key.ge.as_ngg, shader->key.ge.as_es,
3323 shader->wave_size, ir_sha1_cache_key);
3324 } else {
3325 si_get_ir_cache_key(sel, false, false, shader->wave_size, ir_sha1_cache_key);
3326 }
3327 }
3328
3329 /* Try to load the shader from the shader cache. */
3330 simple_mtx_lock(&sscreen->shader_cache_mutex);
3331
3332 if (si_shader_cache_load_shader(sscreen, ir_sha1_cache_key, shader)) {
3333 simple_mtx_unlock(&sscreen->shader_cache_mutex);
3334 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
3335 } else {
3336 simple_mtx_unlock(&sscreen->shader_cache_mutex);
3337
3338 /* Compile the shader if it hasn't been loaded from the cache. */
3339 if (!si_compile_shader(sscreen, *compiler, shader, debug)) {
3340 fprintf(stderr,
3341 "radeonsi: can't compile a main shader part (type: %s, name: %s).\n"
3342 "This is probably a driver bug, please report "
3343 "it to https://gitlab.freedesktop.org/mesa/mesa/-/issues.\n",
3344 gl_shader_stage_name(shader->selector->stage),
3345 shader->selector->info.base.name);
3346 FREE(shader);
3347 return;
3348 }
3349
3350 simple_mtx_lock(&sscreen->shader_cache_mutex);
3351 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key, shader, true);
3352 simple_mtx_unlock(&sscreen->shader_cache_mutex);
3353 }
3354
3355 *si_get_main_shader_part(sel, &shader->key, shader->wave_size) = shader;
3356
3357 /* Unset "outputs_written" flags for outputs converted to
3358 * DEFAULT_VAL, so that later inter-shader optimizations don't
3359 * try to eliminate outputs that don't exist in the final
3360 * shader.
3361 *
3362 * This is only done if non-monolithic shaders are enabled.
3363 */
3364 if ((sel->stage == MESA_SHADER_VERTEX ||
3365 sel->stage == MESA_SHADER_TESS_EVAL ||
3366 sel->stage == MESA_SHADER_GEOMETRY) &&
3367 !shader->key.ge.as_ls && !shader->key.ge.as_es) {
3368 unsigned i;
3369
3370 for (i = 0; i < sel->info.num_outputs; i++) {
3371 unsigned semantic = sel->info.output_semantic[i];
3372 unsigned ps_input_cntl = shader->info.vs_output_ps_input_cntl[semantic];
3373
3374 /* OFFSET=0x20 means DEFAULT_VAL, which means VS doesn't export it. */
3375 if (G_028644_OFFSET(ps_input_cntl) != 0x20)
3376 continue;
3377
3378 unsigned id;
3379
3380 /* Remove the output from the mask. */
3381 if ((semantic <= VARYING_SLOT_VAR31 || semantic >= VARYING_SLOT_VAR0_16BIT) &&
3382 semantic != VARYING_SLOT_POS &&
3383 semantic != VARYING_SLOT_PSIZ &&
3384 semantic != VARYING_SLOT_CLIP_VERTEX &&
3385 semantic != VARYING_SLOT_EDGE &&
3386 semantic != VARYING_SLOT_LAYER) {
3387 id = si_shader_io_get_unique_index(semantic);
3388 sel->info.outputs_written_before_ps &= ~(1ull << id);
3389 }
3390 }
3391 }
3392 }
3393
3394 /* Free NIR. We only keep serialized NIR after this point. */
3395 if (sel->nir) {
3396 ralloc_free(sel->nir);
3397 sel->nir = NULL;
3398 }
3399 }
3400
si_schedule_initial_compile(struct si_context * sctx,gl_shader_stage stage,struct util_queue_fence * ready_fence,struct si_compiler_ctx_state * compiler_ctx_state,void * job,util_queue_execute_func execute)3401 void si_schedule_initial_compile(struct si_context *sctx, gl_shader_stage stage,
3402 struct util_queue_fence *ready_fence,
3403 struct si_compiler_ctx_state *compiler_ctx_state, void *job,
3404 util_queue_execute_func execute)
3405 {
3406 util_queue_fence_init(ready_fence);
3407
3408 struct util_async_debug_callback async_debug;
3409 bool debug = (sctx->debug.debug_message && !sctx->debug.async) || sctx->is_debug ||
3410 si_can_dump_shader(sctx->screen, stage, SI_DUMP_ALWAYS);
3411
3412 if (debug) {
3413 u_async_debug_init(&async_debug);
3414 compiler_ctx_state->debug = async_debug.base;
3415 }
3416
3417 util_queue_add_job(&sctx->screen->shader_compiler_queue, job, ready_fence, execute, NULL, 0);
3418
3419 if (debug) {
3420 util_queue_fence_wait(ready_fence);
3421 u_async_debug_drain(&async_debug, &sctx->debug);
3422 u_async_debug_cleanup(&async_debug);
3423 }
3424
3425 if (sctx->screen->options.sync_compile)
3426 util_queue_fence_wait(ready_fence);
3427 }
3428
3429 /* Return descriptor slot usage masks from the given shader info. */
si_get_active_slot_masks(struct si_screen * sscreen,const struct si_shader_info * info,uint64_t * const_and_shader_buffers,uint64_t * samplers_and_images)3430 void si_get_active_slot_masks(struct si_screen *sscreen, const struct si_shader_info *info,
3431 uint64_t *const_and_shader_buffers, uint64_t *samplers_and_images)
3432 {
3433 unsigned start, num_shaderbufs, num_constbufs, num_images, num_msaa_images, num_samplers;
3434
3435 num_shaderbufs = info->base.num_ssbos;
3436 num_constbufs = info->base.num_ubos;
3437 /* two 8-byte images share one 16-byte slot */
3438 num_images = align(info->base.num_images, 2);
3439 num_msaa_images = align(BITSET_LAST_BIT(info->base.msaa_images), 2);
3440 num_samplers = BITSET_LAST_BIT(info->base.textures_used);
3441
3442 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
3443 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
3444 *const_and_shader_buffers = u_bit_consecutive64(start, num_shaderbufs + num_constbufs);
3445
3446 /* The layout is:
3447 * - fmask[last] ... fmask[0] go to [15-last .. 15]
3448 * - image[last] ... image[0] go to [31-last .. 31]
3449 * - sampler[0] ... sampler[last] go to [32 .. 32+last*2]
3450 *
3451 * FMASKs for images are placed separately, because MSAA images are rare,
3452 * and so we can benefit from a better cache hit rate if we keep image
3453 * descriptors together.
3454 */
3455 if (sscreen->info.gfx_level < GFX11 && num_msaa_images)
3456 num_images = SI_NUM_IMAGES + num_msaa_images; /* add FMASK descriptors */
3457
3458 start = si_get_image_slot(num_images - 1) / 2;
3459 *samplers_and_images = u_bit_consecutive64(start, num_images / 2 + num_samplers);
3460 }
3461
si_create_shader_selector(struct pipe_context * ctx,const struct pipe_shader_state * state)3462 static void *si_create_shader_selector(struct pipe_context *ctx,
3463 const struct pipe_shader_state *state)
3464 {
3465 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
3466 struct si_context *sctx = (struct si_context *)ctx;
3467 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
3468
3469 if (!sel)
3470 return NULL;
3471
3472 sel->screen = sscreen;
3473 sel->compiler_ctx_state.debug = sctx->debug;
3474 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
3475 sel->variants_max_count = 2;
3476 sel->keys = (union si_shader_key *)
3477 realloc(NULL, sel->variants_max_count * sizeof(union si_shader_key));
3478 sel->variants = (struct si_shader **)
3479 realloc(NULL, sel->variants_max_count * sizeof(struct si_shader *));
3480
3481 if (state->type == PIPE_SHADER_IR_TGSI) {
3482 sel->nir = tgsi_to_nir(state->tokens, ctx->screen, true);
3483 } else {
3484 assert(state->type == PIPE_SHADER_IR_NIR);
3485 sel->nir = (nir_shader*)state->ir.nir;
3486 }
3487
3488 si_nir_scan_shader(sscreen, sel->nir, &sel->info);
3489
3490 sel->stage = sel->nir->info.stage;
3491 const enum pipe_shader_type type = pipe_shader_type_from_mesa(sel->stage);
3492 sel->pipe_shader_type = type;
3493 sel->const_and_shader_buf_descriptors_index =
3494 si_const_and_shader_buffer_descriptors_idx(type);
3495 sel->sampler_and_images_descriptors_index =
3496 si_sampler_and_image_descriptors_idx(type);
3497
3498 if (si_can_dump_shader(sscreen, sel->stage, SI_DUMP_INIT_NIR))
3499 nir_print_shader(sel->nir, stderr);
3500
3501 p_atomic_inc(&sscreen->num_shaders_created);
3502 si_get_active_slot_masks(sscreen, &sel->info, &sel->active_const_and_shader_buffers,
3503 &sel->active_samplers_and_images);
3504
3505 switch (sel->stage) {
3506 case MESA_SHADER_GEOMETRY:
3507 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
3508 sel->rast_prim = (enum mesa_prim)sel->info.base.gs.output_primitive;
3509 if (util_rast_prim_is_triangles(sel->rast_prim))
3510 sel->rast_prim = MESA_PRIM_TRIANGLES;
3511
3512 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tessellation so
3513 * we can't split workgroups. Disable ngg if any of the following conditions is true:
3514 * - num_invocations * gs.vertices_out > 256
3515 * - LDS usage is too high
3516 */
3517 sel->tess_turns_off_ngg = sscreen->info.gfx_level >= GFX10 &&
3518 sscreen->info.gfx_level <= GFX10_3 &&
3519 (sel->info.base.gs.invocations * sel->info.base.gs.vertices_out > 256 ||
3520 sel->info.base.gs.invocations * sel->info.base.gs.vertices_out *
3521 (sel->info.num_outputs * 4 + 1) > 6500 /* max dw per GS primitive */);
3522 break;
3523
3524 case MESA_SHADER_VERTEX:
3525 case MESA_SHADER_TESS_EVAL:
3526 if (sel->stage == MESA_SHADER_TESS_EVAL) {
3527 if (sel->info.base.tess.point_mode)
3528 sel->rast_prim = MESA_PRIM_POINTS;
3529 else if (sel->info.base.tess._primitive_mode == TESS_PRIMITIVE_ISOLINES)
3530 sel->rast_prim = MESA_PRIM_LINE_STRIP;
3531 else
3532 sel->rast_prim = MESA_PRIM_TRIANGLES;
3533 } else {
3534 sel->rast_prim = MESA_PRIM_TRIANGLES;
3535 }
3536 break;
3537 default:;
3538 }
3539
3540 bool ngg_culling_allowed =
3541 sscreen->info.gfx_level >= GFX10 &&
3542 sscreen->use_ngg_culling &&
3543 sel->info.writes_position &&
3544 !sel->info.writes_viewport_index && /* cull only against viewport 0 */
3545 !sel->info.base.writes_memory &&
3546 /* NGG GS supports culling with streamout because it culls after streamout. */
3547 (sel->stage == MESA_SHADER_GEOMETRY || !sel->info.enabled_streamout_buffer_mask) &&
3548 (sel->stage != MESA_SHADER_GEOMETRY || sel->info.num_stream_output_components[0]) &&
3549 (sel->stage != MESA_SHADER_VERTEX ||
3550 (!sel->info.base.vs.blit_sgprs_amd &&
3551 !sel->info.base.vs.window_space_position));
3552
3553 sel->ngg_cull_vert_threshold = UINT_MAX; /* disabled (changed below) */
3554
3555 if (ngg_culling_allowed) {
3556 if (sel->stage == MESA_SHADER_VERTEX) {
3557 if (sscreen->debug_flags & DBG(ALWAYS_NGG_CULLING_ALL))
3558 sel->ngg_cull_vert_threshold = 0; /* always enabled */
3559 else
3560 sel->ngg_cull_vert_threshold = 128;
3561 } else if (sel->stage == MESA_SHADER_TESS_EVAL ||
3562 sel->stage == MESA_SHADER_GEOMETRY) {
3563 if (sel->rast_prim != MESA_PRIM_POINTS)
3564 sel->ngg_cull_vert_threshold = 0; /* always enabled */
3565 }
3566 }
3567
3568 (void)simple_mtx_init(&sel->mutex, mtx_plain);
3569
3570 si_schedule_initial_compile(sctx, sel->stage, &sel->ready, &sel->compiler_ctx_state,
3571 sel, si_init_shader_selector_async);
3572 return sel;
3573 }
3574
si_create_shader(struct pipe_context * ctx,const struct pipe_shader_state * state)3575 static void *si_create_shader(struct pipe_context *ctx, const struct pipe_shader_state *state)
3576 {
3577 struct si_context *sctx = (struct si_context *)ctx;
3578 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
3579 bool cache_hit;
3580 struct si_shader_selector *sel = (struct si_shader_selector *)util_live_shader_cache_get(
3581 ctx, &sscreen->live_shader_cache, state, &cache_hit);
3582
3583 if (sel && cache_hit && sctx->debug.debug_message) {
3584 for (unsigned i = 0; i < 2; i++) {
3585 if (sel->main_shader_part[i])
3586 si_shader_dump_stats_for_shader_db(sscreen, sel->main_shader_part[i], &sctx->debug);
3587 if (sel->main_shader_part_ls[i])
3588 si_shader_dump_stats_for_shader_db(sscreen, sel->main_shader_part_ls[i], &sctx->debug);
3589 if (sel->main_shader_part_ngg[i])
3590 si_shader_dump_stats_for_shader_db(sscreen, sel->main_shader_part_ngg[i], &sctx->debug);
3591 if (sel->main_shader_part_ngg_es[i])
3592 si_shader_dump_stats_for_shader_db(sscreen, sel->main_shader_part_ngg_es[i], &sctx->debug);
3593 }
3594
3595 if (sel->main_shader_part_es)
3596 si_shader_dump_stats_for_shader_db(sscreen, sel->main_shader_part_es, &sctx->debug);
3597 }
3598 return sel;
3599 }
3600
si_update_streamout_state(struct si_context * sctx)3601 static void si_update_streamout_state(struct si_context *sctx)
3602 {
3603 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
3604
3605 if (!shader_with_so)
3606 return;
3607
3608 sctx->streamout.enabled_stream_buffers_mask = shader_with_so->info.enabled_streamout_buffer_mask;
3609 sctx->streamout.stride_in_dw = shader_with_so->info.base.xfb_stride;
3610
3611 /* GDS must be allocated when any GDS instructions are used, otherwise it hangs. */
3612 if (sctx->gfx_level >= GFX11 && sctx->gfx_level < GFX12 &&
3613 shader_with_so->info.enabled_streamout_buffer_mask && !sctx->screen->gds_oa) {
3614 /* Gfx11 only uses GDS OA, not GDS memory. */
3615 simple_mtx_lock(&sctx->screen->gds_mutex);
3616 if (!sctx->screen->gds_oa) {
3617 sctx->screen->gds_oa = sctx->ws->buffer_create(sctx->ws, 1, 1, RADEON_DOMAIN_OA,
3618 RADEON_FLAG_DRIVER_INTERNAL);
3619 assert(sctx->screen->gds_oa);
3620 }
3621 simple_mtx_unlock(&sctx->screen->gds_mutex);
3622
3623 if (sctx->screen->gds_oa)
3624 sctx->ws->cs_add_buffer(&sctx->gfx_cs, sctx->screen->gds_oa, RADEON_USAGE_READWRITE,
3625 (enum radeon_bo_domain)0);
3626 }
3627 }
3628
si_update_clip_regs(struct si_context * sctx,struct si_shader_selector * old_hw_vs,struct si_shader * old_hw_vs_variant,struct si_shader_selector * next_hw_vs,struct si_shader * next_hw_vs_variant)3629 static void si_update_clip_regs(struct si_context *sctx, struct si_shader_selector *old_hw_vs,
3630 struct si_shader *old_hw_vs_variant,
3631 struct si_shader_selector *next_hw_vs,
3632 struct si_shader *next_hw_vs_variant)
3633 {
3634 if (next_hw_vs &&
3635 (!old_hw_vs ||
3636 (old_hw_vs->stage == MESA_SHADER_VERTEX && old_hw_vs->info.base.vs.window_space_position) !=
3637 (next_hw_vs->stage == MESA_SHADER_VERTEX && next_hw_vs->info.base.vs.window_space_position) ||
3638 old_hw_vs->info.clipdist_mask != next_hw_vs->info.clipdist_mask ||
3639 old_hw_vs->info.culldist_mask != next_hw_vs->info.culldist_mask || !old_hw_vs_variant ||
3640 !next_hw_vs_variant ||
3641 old_hw_vs_variant->pa_cl_vs_out_cntl != next_hw_vs_variant->pa_cl_vs_out_cntl))
3642 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
3643 }
3644
si_update_rasterized_prim(struct si_context * sctx)3645 static void si_update_rasterized_prim(struct si_context *sctx)
3646 {
3647 struct si_shader *hw_vs = si_get_vs(sctx)->current;
3648
3649 if (sctx->shader.gs.cso) {
3650 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
3651 si_set_rasterized_prim(sctx, sctx->shader.gs.cso->rast_prim, hw_vs, sctx->ngg);
3652 } else if (sctx->shader.tes.cso) {
3653 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
3654 si_set_rasterized_prim(sctx, sctx->shader.tes.cso->rast_prim, hw_vs, sctx->ngg);
3655 } else {
3656 /* The rasterized prim is determined by draw calls. */
3657 }
3658
3659 /* This must be done unconditionally because it also depends on si_shader fields. */
3660 si_update_ngg_sgpr_state_out_prim(sctx, hw_vs, sctx->ngg);
3661 }
3662
si_update_common_shader_state(struct si_context * sctx,struct si_shader_selector * sel,enum pipe_shader_type type)3663 static void si_update_common_shader_state(struct si_context *sctx, struct si_shader_selector *sel,
3664 enum pipe_shader_type type)
3665 {
3666 si_set_active_descriptors_for_shader(sctx, sel);
3667
3668 sctx->uses_bindless_samplers = si_shader_uses_bindless_samplers(sctx->shader.vs.cso) ||
3669 si_shader_uses_bindless_samplers(sctx->shader.gs.cso) ||
3670 si_shader_uses_bindless_samplers(sctx->shader.ps.cso) ||
3671 si_shader_uses_bindless_samplers(sctx->shader.tcs.cso) ||
3672 si_shader_uses_bindless_samplers(sctx->shader.tes.cso);
3673 sctx->uses_bindless_images = si_shader_uses_bindless_images(sctx->shader.vs.cso) ||
3674 si_shader_uses_bindless_images(sctx->shader.gs.cso) ||
3675 si_shader_uses_bindless_images(sctx->shader.ps.cso) ||
3676 si_shader_uses_bindless_images(sctx->shader.tcs.cso) ||
3677 si_shader_uses_bindless_images(sctx->shader.tes.cso);
3678
3679 if (type == PIPE_SHADER_VERTEX || type == PIPE_SHADER_TESS_EVAL || type == PIPE_SHADER_GEOMETRY)
3680 sctx->ngg_culling = 0; /* this will be enabled on the first draw if needed */
3681
3682 si_invalidate_inlinable_uniforms(sctx, type);
3683 sctx->do_update_shaders = true;
3684 }
3685
si_update_last_vgt_stage_state(struct si_context * sctx,struct si_shader_selector * old_hw_vs,struct si_shader * old_hw_vs_variant)3686 static void si_update_last_vgt_stage_state(struct si_context *sctx,
3687 /* hw_vs refers to the last VGT stage */
3688 struct si_shader_selector *old_hw_vs,
3689 struct si_shader *old_hw_vs_variant)
3690 {
3691 struct si_shader_ctx_state *hw_vs = si_get_vs(sctx);
3692
3693 si_update_vs_viewport_state(sctx);
3694 si_update_streamout_state(sctx);
3695 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant, hw_vs->cso, hw_vs->current);
3696 si_update_rasterized_prim(sctx);
3697
3698 /* Clear kill_pointsize because we only want it to be set in the last shader before PS. */
3699 sctx->shader.vs.key.ge.opt.kill_pointsize = 0;
3700 sctx->shader.tes.key.ge.opt.kill_pointsize = 0;
3701 sctx->shader.gs.key.ge.opt.kill_pointsize = 0;
3702 si_vs_ps_key_update_rast_prim_smooth_stipple(sctx);
3703 }
3704
si_bind_vs_shader(struct pipe_context * ctx,void * state)3705 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
3706 {
3707 struct si_context *sctx = (struct si_context *)ctx;
3708 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3709 struct si_shader *old_hw_vs_variant = si_get_vs(sctx)->current;
3710 struct si_shader_selector *sel = (struct si_shader_selector*)state;
3711
3712 if (sctx->shader.vs.cso == sel)
3713 return;
3714
3715 sctx->shader.vs.cso = sel;
3716 sctx->shader.vs.current = (sel && sel->variants_count) ? sel->variants[0] : NULL;
3717 sctx->num_vs_blit_sgprs = sel ? sel->info.base.vs.blit_sgprs_amd : 0;
3718 sctx->vs_uses_draw_id = sel ? sel->info.uses_drawid : false;
3719
3720 if (si_update_ngg(sctx))
3721 si_shader_change_notify(sctx);
3722
3723 si_update_common_shader_state(sctx, sel, PIPE_SHADER_VERTEX);
3724 si_select_draw_vbo(sctx);
3725 si_update_last_vgt_stage_state(sctx, old_hw_vs, old_hw_vs_variant);
3726 si_vs_key_update_inputs(sctx);
3727
3728 if (sctx->screen->dpbb_allowed) {
3729 bool force_off = sel && sel->info.options & SI_PROFILE_VS_NO_BINNING;
3730
3731 if (force_off != sctx->dpbb_force_off_profile_vs) {
3732 sctx->dpbb_force_off_profile_vs = force_off;
3733 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3734 }
3735 }
3736 }
3737
si_update_tess_uses_prim_id(struct si_context * sctx)3738 static void si_update_tess_uses_prim_id(struct si_context *sctx)
3739 {
3740 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
3741 (sctx->shader.tes.cso && sctx->shader.tes.cso->info.uses_primid) ||
3742 (sctx->shader.tcs.cso && sctx->shader.tcs.cso->info.uses_primid) ||
3743 (sctx->shader.gs.cso && sctx->shader.gs.cso->info.uses_primid) ||
3744 (sctx->shader.ps.cso && !sctx->shader.gs.cso && sctx->shader.ps.cso->info.uses_primid);
3745 }
3746
si_update_ngg(struct si_context * sctx)3747 bool si_update_ngg(struct si_context *sctx)
3748 {
3749 if (!sctx->screen->use_ngg) {
3750 assert(!sctx->ngg);
3751 return false;
3752 }
3753
3754 bool new_ngg = true;
3755
3756 if (sctx->shader.gs.cso && sctx->shader.tes.cso && sctx->shader.gs.cso->tess_turns_off_ngg) {
3757 new_ngg = false;
3758 } else if (sctx->gfx_level < GFX11) {
3759 struct si_shader_selector *last = si_get_vs(sctx)->cso;
3760
3761 if ((last && last->info.enabled_streamout_buffer_mask) ||
3762 sctx->streamout.prims_gen_query_enabled)
3763 new_ngg = false;
3764 }
3765
3766 if (new_ngg != sctx->ngg) {
3767 /* Transitioning from NGG to legacy GS requires VGT_FLUSH on Navi10-14.
3768 * VGT_FLUSH is also emitted at the beginning of IBs when legacy GS ring
3769 * pointers are set.
3770 */
3771 if (sctx->screen->info.has_vgt_flush_ngg_legacy_bug && !new_ngg) {
3772 sctx->barrier_flags |= SI_BARRIER_EVENT_VGT_FLUSH;
3773 si_mark_atom_dirty(sctx, &sctx->atoms.s.barrier);
3774
3775 if (sctx->gfx_level == GFX10) {
3776 /* Workaround for https://gitlab.freedesktop.org/mesa/mesa/-/issues/2941 */
3777 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3778 }
3779 }
3780
3781 sctx->ngg = new_ngg;
3782 si_select_draw_vbo(sctx);
3783 return true;
3784 }
3785 return false;
3786 }
3787
si_bind_gs_shader(struct pipe_context * ctx,void * state)3788 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
3789 {
3790 struct si_context *sctx = (struct si_context *)ctx;
3791 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3792 struct si_shader *old_hw_vs_variant = si_get_vs(sctx)->current;
3793 struct si_shader_selector *sel = (struct si_shader_selector*)state;
3794 bool enable_changed = !!sctx->shader.gs.cso != !!sel;
3795 bool ngg_changed;
3796
3797 if (sctx->shader.gs.cso == sel)
3798 return;
3799
3800 sctx->shader.gs.cso = sel;
3801 sctx->shader.gs.current = (sel && sel->variants_count) ? sel->variants[0] : NULL;
3802 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
3803
3804 si_update_common_shader_state(sctx, sel, PIPE_SHADER_GEOMETRY);
3805 si_select_draw_vbo(sctx);
3806
3807 ngg_changed = si_update_ngg(sctx);
3808 if (ngg_changed || enable_changed)
3809 si_shader_change_notify(sctx);
3810 if (enable_changed) {
3811 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3812 si_update_tess_uses_prim_id(sctx);
3813 }
3814 si_update_last_vgt_stage_state(sctx, old_hw_vs, old_hw_vs_variant);
3815 }
3816
si_bind_tcs_shader(struct pipe_context * ctx,void * state)3817 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
3818 {
3819 struct si_context *sctx = (struct si_context *)ctx;
3820 struct si_shader_selector *sel = (struct si_shader_selector*)state;
3821 bool enable_changed = !!sctx->shader.tcs.cso != !!sel;
3822
3823 /* Note it could happen that user shader sel is same as fixed function shader,
3824 * so we should update this field even sctx->shader.tcs.cso == sel.
3825 */
3826 sctx->is_user_tcs = !!sel;
3827
3828 if (sctx->shader.tcs.cso == sel)
3829 return;
3830
3831 sctx->shader.tcs.cso = sel;
3832 sctx->shader.tcs.current = (sel && sel->variants_count) ? sel->variants[0] : NULL;
3833 si_update_tess_uses_prim_id(sctx);
3834 si_update_tess_in_out_patch_vertices(sctx);
3835
3836 si_update_common_shader_state(sctx, sel, PIPE_SHADER_TESS_CTRL);
3837
3838 if (enable_changed)
3839 sctx->last_tcs = NULL; /* invalidate derived tess state */
3840 }
3841
si_bind_tes_shader(struct pipe_context * ctx,void * state)3842 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
3843 {
3844 struct si_context *sctx = (struct si_context *)ctx;
3845 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3846 struct si_shader *old_hw_vs_variant = si_get_vs(sctx)->current;
3847 struct si_shader_selector *sel = (struct si_shader_selector*)state;
3848 bool enable_changed = !!sctx->shader.tes.cso != !!sel;
3849
3850 if (sctx->shader.tes.cso == sel)
3851 return;
3852
3853 sctx->shader.tes.cso = sel;
3854 sctx->shader.tes.current = (sel && sel->variants_count) ? sel->variants[0] : NULL;
3855 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
3856 si_update_tess_uses_prim_id(sctx);
3857
3858 sctx->shader.tcs.key.ge.opt.tes_prim_mode =
3859 sel ? sel->info.base.tess._primitive_mode : 0;
3860
3861 sctx->shader.tcs.key.ge.opt.tes_reads_tess_factors =
3862 sel ? sel->info.reads_tess_factors : 0;
3863
3864 if (sel) {
3865 sctx->tcs_offchip_layout &= 0x1fffffff;
3866 sctx->tcs_offchip_layout |=
3867 (sel->info.base.tess._primitive_mode << 29) |
3868 (sel->info.reads_tess_factors << 31);
3869
3870 si_mark_atom_dirty(sctx, &sctx->atoms.s.tess_io_layout);
3871 }
3872
3873 si_update_common_shader_state(sctx, sel, PIPE_SHADER_TESS_EVAL);
3874 si_select_draw_vbo(sctx);
3875
3876 bool ngg_changed = si_update_ngg(sctx);
3877 if (ngg_changed || enable_changed)
3878 si_shader_change_notify(sctx);
3879 if (enable_changed)
3880 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
3881 si_update_last_vgt_stage_state(sctx, old_hw_vs, old_hw_vs_variant);
3882 }
3883
si_update_vrs_flat_shading(struct si_context * sctx)3884 void si_update_vrs_flat_shading(struct si_context *sctx)
3885 {
3886 if (sctx->gfx_level >= GFX10_3 && sctx->shader.ps.cso) {
3887 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3888 struct si_shader_info *info = &sctx->shader.ps.cso->info;
3889 bool allow_flat_shading =
3890 info->allow_flat_shading && !sctx->framebuffer.disable_vrs_flat_shading &&
3891 !rs->line_smooth && !rs->poly_smooth && !rs->poly_stipple_enable &&
3892 !rs->point_smooth && (rs->flatshade || !info->uses_interp_color);
3893
3894 if (sctx->allow_flat_shading != allow_flat_shading) {
3895 sctx->allow_flat_shading = allow_flat_shading;
3896 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3897 }
3898 }
3899 }
3900
si_bind_ps_shader(struct pipe_context * ctx,void * state)3901 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
3902 {
3903 struct si_context *sctx = (struct si_context *)ctx;
3904 struct si_shader_selector *old_sel = sctx->shader.ps.cso;
3905 struct si_shader_selector *sel = (struct si_shader_selector*)state;
3906
3907 /* skip if supplied shader is one already in use */
3908 if (old_sel == sel)
3909 return;
3910
3911 sctx->shader.ps.cso = sel;
3912 sctx->shader.ps.current = (sel && sel->variants_count) ? sel->variants[0] : NULL;
3913
3914 si_update_common_shader_state(sctx, sel, PIPE_SHADER_FRAGMENT);
3915 if (sel) {
3916 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3917 si_update_tess_uses_prim_id(sctx);
3918
3919 if (!old_sel || old_sel->info.colors_written != sel->info.colors_written)
3920 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3921
3922 if (sctx->screen->info.has_out_of_order_rast &&
3923 (!old_sel || old_sel->info.base.writes_memory != sel->info.base.writes_memory ||
3924 old_sel->info.base.fs.early_fragment_tests !=
3925 sel->info.base.fs.early_fragment_tests))
3926 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3927 }
3928 si_update_ps_colorbuf0_slot(sctx);
3929
3930 si_ps_key_update_framebuffer(sctx);
3931 si_ps_key_update_framebuffer_blend_rasterizer(sctx);
3932 si_ps_key_update_rasterizer(sctx);
3933 si_ps_key_update_dsa(sctx);
3934 si_ps_key_update_sample_shading(sctx);
3935 si_ps_key_update_framebuffer_rasterizer_sample_shading(sctx);
3936 si_update_ps_inputs_read_or_disabled(sctx);
3937 si_update_vrs_flat_shading(sctx);
3938
3939 if (sctx->screen->dpbb_allowed) {
3940 bool force_off = sel && sel->info.options & SI_PROFILE_GFX9_GFX10_PS_NO_BINNING &&
3941 (sctx->gfx_level >= GFX9 && sctx->gfx_level <= GFX10_3);
3942
3943 if (force_off != sctx->dpbb_force_off_profile_ps) {
3944 sctx->dpbb_force_off_profile_ps = force_off;
3945 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3946 }
3947 }
3948 }
3949
si_delete_shader(struct si_context * sctx,struct si_shader * shader)3950 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
3951 {
3952 if (shader->is_optimized) {
3953 util_queue_drop_job(&sctx->screen->shader_compiler_queue_opt_variants, &shader->ready);
3954 }
3955
3956 util_queue_fence_destroy(&shader->ready);
3957
3958 /* If destroyed shaders were not unbound, the next compiled
3959 * shader variant could get the same pointer address and so
3960 * binding it to the same shader stage would be considered
3961 * a no-op, causing random behavior.
3962 */
3963 int state_index = -1;
3964
3965 switch (shader->selector->stage) {
3966 case MESA_SHADER_VERTEX:
3967 if (shader->key.ge.as_ls) {
3968 if (sctx->gfx_level <= GFX8)
3969 state_index = SI_STATE_IDX(ls);
3970 } else if (shader->key.ge.as_es) {
3971 if (sctx->gfx_level <= GFX8)
3972 state_index = SI_STATE_IDX(es);
3973 } else if (shader->key.ge.as_ngg) {
3974 state_index = SI_STATE_IDX(gs);
3975 } else {
3976 state_index = SI_STATE_IDX(vs);
3977 }
3978 break;
3979 case MESA_SHADER_TESS_CTRL:
3980 state_index = SI_STATE_IDX(hs);
3981 break;
3982 case MESA_SHADER_TESS_EVAL:
3983 if (shader->key.ge.as_es) {
3984 if (sctx->gfx_level <= GFX8)
3985 state_index = SI_STATE_IDX(es);
3986 } else if (shader->key.ge.as_ngg) {
3987 state_index = SI_STATE_IDX(gs);
3988 } else {
3989 state_index = SI_STATE_IDX(vs);
3990 }
3991 break;
3992 case MESA_SHADER_GEOMETRY:
3993 if (shader->is_gs_copy_shader)
3994 state_index = SI_STATE_IDX(vs);
3995 else
3996 state_index = SI_STATE_IDX(gs);
3997 break;
3998 case MESA_SHADER_FRAGMENT:
3999 state_index = SI_STATE_IDX(ps);
4000 break;
4001 default:;
4002 }
4003
4004 if (shader->gs_copy_shader)
4005 si_delete_shader(sctx, shader->gs_copy_shader);
4006
4007 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
4008 si_shader_destroy(shader);
4009 si_pm4_free_state(sctx, &shader->pm4, state_index);
4010 }
4011
si_destroy_shader_selector(struct pipe_context * ctx,void * cso)4012 static void si_destroy_shader_selector(struct pipe_context *ctx, void *cso)
4013 {
4014 struct si_context *sctx = (struct si_context *)ctx;
4015 struct si_shader_selector *sel = (struct si_shader_selector *)cso;
4016 enum pipe_shader_type type = pipe_shader_type_from_mesa(sel->stage);
4017
4018 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
4019
4020 if (sctx->shaders[type].cso == sel) {
4021 sctx->shaders[type].cso = NULL;
4022 sctx->shaders[type].current = NULL;
4023 }
4024
4025 for (unsigned i = 0; i < sel->variants_count; i++) {
4026 si_delete_shader(sctx, sel->variants[i]);
4027 }
4028
4029 for (unsigned i = 0; i < 2; i++) {
4030 if (sel->main_shader_part[i])
4031 si_delete_shader(sctx, sel->main_shader_part[i]);
4032 if (sel->main_shader_part_ls[i])
4033 si_delete_shader(sctx, sel->main_shader_part_ls[i]);
4034 if (sel->main_shader_part_ngg[i])
4035 si_delete_shader(sctx, sel->main_shader_part_ngg[i]);
4036 if (sel->main_shader_part_ngg_es[i])
4037 si_delete_shader(sctx, sel->main_shader_part_ngg_es[i]);
4038 }
4039
4040 if (sel->main_shader_part_es)
4041 si_delete_shader(sctx, sel->main_shader_part_es);
4042
4043 free(sel->keys);
4044 free(sel->variants);
4045
4046 util_queue_fence_destroy(&sel->ready);
4047 simple_mtx_destroy(&sel->mutex);
4048 ralloc_free(sel->nir);
4049 free(sel->nir_binary);
4050 free(sel);
4051 }
4052
si_delete_shader_selector(struct pipe_context * ctx,void * state)4053 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
4054 {
4055 struct si_context *sctx = (struct si_context *)ctx;
4056 struct si_shader_selector *sel = (struct si_shader_selector *)state;
4057
4058 si_shader_selector_reference(sctx, &sel, NULL);
4059 }
4060
4061 /**
4062 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
4063 */
si_cs_preamble_add_vgt_flush(struct si_context * sctx,bool tmz)4064 static void si_cs_preamble_add_vgt_flush(struct si_context *sctx, bool tmz)
4065 {
4066 struct si_pm4_state *pm4 = tmz ? sctx->cs_preamble_state_tmz : sctx->cs_preamble_state;
4067 bool *has_vgt_flush = tmz ? &sctx->cs_preamble_has_vgt_flush_tmz :
4068 &sctx->cs_preamble_has_vgt_flush;
4069
4070 /* We shouldn't get here if registers are shadowed. */
4071 assert(!sctx->shadowing.registers);
4072
4073 if (*has_vgt_flush)
4074 return;
4075
4076 /* Done by Vulkan before VGT_FLUSH. */
4077 ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_EVENT_WRITE, 0, 0));
4078 ac_pm4_cmd_add(&pm4->base, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
4079
4080 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
4081 ac_pm4_cmd_add(&pm4->base, PKT3(PKT3_EVENT_WRITE, 0, 0));
4082 ac_pm4_cmd_add(&pm4->base, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
4083 ac_pm4_finalize(&pm4->base);
4084
4085 *has_vgt_flush = true;
4086 }
4087
4088 /**
4089 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
4090 */
si_emit_vgt_flush(struct radeon_cmdbuf * cs)4091 static void si_emit_vgt_flush(struct radeon_cmdbuf *cs)
4092 {
4093 radeon_begin(cs);
4094
4095 /* This is required before VGT_FLUSH. */
4096 radeon_event_write(V_028A90_VS_PARTIAL_FLUSH);
4097
4098 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
4099 radeon_event_write(V_028A90_VGT_FLUSH);
4100 radeon_end();
4101 }
4102
4103 /* Initialize state related to ESGS / GSVS ring buffers */
si_update_gs_ring_buffers(struct si_context * sctx)4104 bool si_update_gs_ring_buffers(struct si_context *sctx)
4105 {
4106 assert(sctx->gfx_level < GFX11);
4107
4108 struct si_shader_selector *es =
4109 sctx->shader.tes.cso ? sctx->shader.tes.cso : sctx->shader.vs.cso;
4110 struct si_shader_selector *gs = sctx->shader.gs.cso;
4111
4112 /* Chip constants. */
4113 unsigned num_se = sctx->screen->info.max_se;
4114 unsigned wave_size = 64;
4115 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
4116 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
4117 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
4118 */
4119 unsigned gs_vertex_reuse = (sctx->gfx_level >= GFX8 ? 32 : 16) * num_se;
4120 unsigned alignment = 256 * num_se;
4121 /* The maximum size is 63.999 MB per SE. */
4122 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
4123
4124 /* Calculate the minimum size. */
4125 unsigned min_esgs_ring_size = align(es->info.esgs_vertex_stride * gs_vertex_reuse * wave_size, alignment);
4126
4127 /* These are recommended sizes, not minimum sizes. */
4128 unsigned esgs_ring_size =
4129 max_gs_waves * 2 * wave_size * es->info.esgs_vertex_stride * gs->info.gs_input_verts_per_prim;
4130 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size * gs->info.max_gsvs_emit_size;
4131
4132 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
4133 esgs_ring_size = align(esgs_ring_size, alignment);
4134 gsvs_ring_size = align(gsvs_ring_size, alignment);
4135
4136 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
4137 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
4138
4139 /* Some rings don't have to be allocated if shaders don't use them.
4140 * (e.g. no varyings between ES and GS or GS and VS)
4141 *
4142 * GFX9 doesn't have the ESGS ring.
4143 */
4144 bool update_esgs = sctx->gfx_level <= GFX8 && esgs_ring_size &&
4145 (!sctx->esgs_ring || sctx->esgs_ring->width0 < esgs_ring_size);
4146 bool update_gsvs =
4147 gsvs_ring_size && (!sctx->gsvs_ring || sctx->gsvs_ring->width0 < gsvs_ring_size);
4148
4149 if (!update_esgs && !update_gsvs)
4150 return true;
4151
4152 if (update_esgs) {
4153 pipe_resource_reference(&sctx->esgs_ring, NULL);
4154 sctx->esgs_ring =
4155 pipe_aligned_buffer_create(sctx->b.screen,
4156 PIPE_RESOURCE_FLAG_UNMAPPABLE | SI_RESOURCE_FLAG_DRIVER_INTERNAL |
4157 SI_RESOURCE_FLAG_DISCARDABLE,
4158 PIPE_USAGE_DEFAULT,
4159 esgs_ring_size, sctx->screen->info.pte_fragment_size);
4160 if (!sctx->esgs_ring)
4161 return false;
4162 }
4163
4164 if (update_gsvs) {
4165 pipe_resource_reference(&sctx->gsvs_ring, NULL);
4166 sctx->gsvs_ring =
4167 pipe_aligned_buffer_create(sctx->b.screen,
4168 PIPE_RESOURCE_FLAG_UNMAPPABLE | SI_RESOURCE_FLAG_DRIVER_INTERNAL |
4169 SI_RESOURCE_FLAG_DISCARDABLE,
4170 PIPE_USAGE_DEFAULT,
4171 gsvs_ring_size, sctx->screen->info.pte_fragment_size);
4172 if (!sctx->gsvs_ring)
4173 return false;
4174 }
4175
4176 /* Set ring bindings. */
4177 if (sctx->esgs_ring) {
4178 assert(sctx->gfx_level <= GFX8);
4179 si_set_ring_buffer(sctx, SI_RING_ESGS, sctx->esgs_ring, 0, sctx->esgs_ring->width0, false,
4180 false, 0, 0, 0);
4181 }
4182 if (sctx->gsvs_ring) {
4183 si_set_ring_buffer(sctx, SI_RING_GSVS, sctx->gsvs_ring, 0, sctx->gsvs_ring->width0, false,
4184 false, 0, 0, 0);
4185 }
4186
4187 if (sctx->shadowing.registers) {
4188 /* These registers will be shadowed, so set them only once. */
4189 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
4190
4191 assert(sctx->gfx_level >= GFX7);
4192
4193 si_emit_vgt_flush(cs);
4194
4195 radeon_begin(cs);
4196
4197 /* Set the GS registers. */
4198 if (sctx->esgs_ring) {
4199 assert(sctx->gfx_level <= GFX8);
4200 radeon_set_uconfig_reg(R_030900_VGT_ESGS_RING_SIZE,
4201 sctx->esgs_ring->width0 / 256);
4202 }
4203 if (sctx->gsvs_ring) {
4204 radeon_set_uconfig_reg(R_030904_VGT_GSVS_RING_SIZE,
4205 sctx->gsvs_ring->width0 / 256);
4206 }
4207 radeon_end();
4208 return true;
4209 }
4210
4211 /* The codepath without register shadowing. */
4212 for (unsigned tmz = 0; tmz <= 1; tmz++) {
4213 struct si_pm4_state *pm4 = tmz ? sctx->cs_preamble_state_tmz : sctx->cs_preamble_state;
4214 uint16_t *gs_ring_state_dw_offset = tmz ? &sctx->gs_ring_state_dw_offset_tmz :
4215 &sctx->gs_ring_state_dw_offset;
4216 unsigned old_ndw = 0;
4217
4218 si_cs_preamble_add_vgt_flush(sctx, tmz);
4219
4220 if (!*gs_ring_state_dw_offset) {
4221 /* We are here for the first time. The packets will be added. */
4222 *gs_ring_state_dw_offset = pm4->base.ndw;
4223 } else {
4224 /* We have been here before. Overwrite the previous packets. */
4225 old_ndw = pm4->base.ndw;
4226 pm4->base.ndw = *gs_ring_state_dw_offset;
4227 }
4228
4229 /* Unallocated rings are written to reserve the space in the pm4
4230 * (to be able to overwrite them later). */
4231 if (sctx->gfx_level >= GFX7) {
4232 if (sctx->gfx_level <= GFX8)
4233 ac_pm4_set_reg(&pm4->base, R_030900_VGT_ESGS_RING_SIZE,
4234 sctx->esgs_ring ? sctx->esgs_ring->width0 / 256 : 0);
4235 ac_pm4_set_reg(&pm4->base, R_030904_VGT_GSVS_RING_SIZE,
4236 sctx->gsvs_ring ? sctx->gsvs_ring->width0 / 256 : 0);
4237 } else {
4238 ac_pm4_set_reg(&pm4->base, R_0088C8_VGT_ESGS_RING_SIZE,
4239 sctx->esgs_ring ? sctx->esgs_ring->width0 / 256 : 0);
4240 ac_pm4_set_reg(&pm4->base, R_0088CC_VGT_GSVS_RING_SIZE,
4241 sctx->gsvs_ring ? sctx->gsvs_ring->width0 / 256 : 0);
4242 }
4243 ac_pm4_finalize(&pm4->base);
4244
4245 if (old_ndw) {
4246 pm4->base.ndw = old_ndw;
4247 pm4->base.last_opcode = 255; /* invalid opcode (we don't save the last opcode) */
4248 }
4249 }
4250
4251 /* Flush the context to re-emit both cs_preamble states. */
4252 sctx->initial_gfx_cs_size = 0; /* force flush */
4253 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
4254
4255 return true;
4256 }
4257
si_shader_lock(struct si_shader * shader)4258 static void si_shader_lock(struct si_shader *shader)
4259 {
4260 simple_mtx_lock(&shader->selector->mutex);
4261 if (shader->previous_stage_sel) {
4262 assert(shader->previous_stage_sel != shader->selector);
4263 simple_mtx_lock(&shader->previous_stage_sel->mutex);
4264 }
4265 }
4266
si_shader_unlock(struct si_shader * shader)4267 static void si_shader_unlock(struct si_shader *shader)
4268 {
4269 if (shader->previous_stage_sel)
4270 simple_mtx_unlock(&shader->previous_stage_sel->mutex);
4271 simple_mtx_unlock(&shader->selector->mutex);
4272 }
4273
4274 /**
4275 * @returns 1 if \p sel has been updated to use a new scratch buffer
4276 * 0 if not
4277 * < 0 if there was a failure
4278 */
si_update_scratch_buffer(struct si_context * sctx,struct si_shader * shader)4279 static int si_update_scratch_buffer(struct si_context *sctx, struct si_shader *shader)
4280 {
4281 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
4282
4283 if (!shader)
4284 return 0;
4285
4286 /* This shader doesn't need a scratch buffer */
4287 if (shader->config.scratch_bytes_per_wave == 0)
4288 return 0;
4289
4290 /* Prevent race conditions when updating:
4291 * - si_shader::scratch_va
4292 * - si_shader::binary::code
4293 * - si_shader::previous_stage::binary::code.
4294 */
4295 si_shader_lock(shader);
4296
4297 /* This shader is already configured to use the current
4298 * scratch buffer. */
4299 if (shader->scratch_va == scratch_va) {
4300 si_shader_unlock(shader);
4301 return 0;
4302 }
4303
4304 assert(sctx->scratch_buffer);
4305
4306 /* Replace the shader bo with a new bo that has the relocs applied. */
4307 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va)) {
4308 si_shader_unlock(shader);
4309 return -1;
4310 }
4311
4312 /* Update the shader state to use the new shader bo. */
4313 si_shader_init_pm4_state(sctx->screen, shader);
4314 shader->scratch_va = scratch_va;
4315
4316 si_shader_unlock(shader);
4317 return 1;
4318 }
4319
si_update_scratch_relocs(struct si_context * sctx)4320 static bool si_update_scratch_relocs(struct si_context *sctx)
4321 {
4322 int r;
4323
4324 /* Update the shaders, so that they are using the latest scratch.
4325 * The scratch buffer may have been changed since these shaders were
4326 * last used, so we still need to try to update them, even if they
4327 * require scratch buffers smaller than the current size.
4328 */
4329 r = si_update_scratch_buffer(sctx, sctx->shader.ps.current);
4330 if (r < 0)
4331 return false;
4332 if (r == 1)
4333 si_pm4_bind_state(sctx, ps, sctx->shader.ps.current);
4334
4335 r = si_update_scratch_buffer(sctx, sctx->shader.gs.current);
4336 if (r < 0)
4337 return false;
4338 if (r == 1)
4339 si_pm4_bind_state(sctx, gs, sctx->shader.gs.current);
4340
4341 r = si_update_scratch_buffer(sctx, sctx->shader.tcs.current);
4342 if (r < 0)
4343 return false;
4344 if (r == 1)
4345 si_pm4_bind_state(sctx, hs, sctx->shader.tcs.current);
4346
4347 /* VS can be bound as LS, ES, or VS. */
4348 r = si_update_scratch_buffer(sctx, sctx->shader.vs.current);
4349 if (r < 0)
4350 return false;
4351 if (r == 1) {
4352 if (sctx->shader.vs.current->key.ge.as_ls)
4353 si_pm4_bind_state(sctx, ls, sctx->shader.vs.current);
4354 else if (sctx->shader.vs.current->key.ge.as_es)
4355 si_pm4_bind_state(sctx, es, sctx->shader.vs.current);
4356 else if (sctx->shader.vs.current->key.ge.as_ngg)
4357 si_pm4_bind_state(sctx, gs, sctx->shader.vs.current);
4358 else
4359 si_pm4_bind_state(sctx, vs, sctx->shader.vs.current);
4360 }
4361
4362 /* TES can be bound as ES or VS. */
4363 r = si_update_scratch_buffer(sctx, sctx->shader.tes.current);
4364 if (r < 0)
4365 return false;
4366 if (r == 1) {
4367 if (sctx->shader.tes.current->key.ge.as_es)
4368 si_pm4_bind_state(sctx, es, sctx->shader.tes.current);
4369 else if (sctx->shader.tes.current->key.ge.as_ngg)
4370 si_pm4_bind_state(sctx, gs, sctx->shader.tes.current);
4371 else
4372 si_pm4_bind_state(sctx, vs, sctx->shader.tes.current);
4373 }
4374
4375 return true;
4376 }
4377
si_update_spi_tmpring_size(struct si_context * sctx,unsigned bytes)4378 bool si_update_spi_tmpring_size(struct si_context *sctx, unsigned bytes)
4379 {
4380 unsigned spi_tmpring_size;
4381 ac_get_scratch_tmpring_size(&sctx->screen->info, bytes,
4382 &sctx->max_seen_scratch_bytes_per_wave, &spi_tmpring_size);
4383
4384 unsigned scratch_needed_size = sctx->max_seen_scratch_bytes_per_wave *
4385 sctx->screen->info.max_scratch_waves;
4386
4387 if (scratch_needed_size > 0) {
4388 if (!sctx->scratch_buffer || scratch_needed_size > sctx->scratch_buffer->b.b.width0) {
4389 /* Create a bigger scratch buffer */
4390 si_resource_reference(&sctx->scratch_buffer, NULL);
4391
4392 sctx->scratch_buffer = si_aligned_buffer_create(
4393 &sctx->screen->b,
4394 PIPE_RESOURCE_FLAG_UNMAPPABLE | SI_RESOURCE_FLAG_DRIVER_INTERNAL |
4395 SI_RESOURCE_FLAG_DISCARDABLE,
4396 PIPE_USAGE_DEFAULT, scratch_needed_size,
4397 sctx->screen->info.pte_fragment_size);
4398 if (!sctx->scratch_buffer)
4399 return false;
4400 }
4401
4402 if (!sctx->screen->info.has_scratch_base_registers && !si_update_scratch_relocs(sctx))
4403 return false;
4404 }
4405
4406 if (spi_tmpring_size != sctx->spi_tmpring_size) {
4407 sctx->spi_tmpring_size = spi_tmpring_size;
4408 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
4409 }
4410 return true;
4411 }
4412
si_init_tess_factor_ring(struct si_context * sctx)4413 void si_init_tess_factor_ring(struct si_context *sctx)
4414 {
4415 struct si_screen *sscreen = sctx->screen;
4416 assert(!sctx->has_tessellation);
4417
4418 if (sctx->has_tessellation)
4419 return;
4420
4421 simple_mtx_lock(&sscreen->tess_ring_lock);
4422
4423 if (!sscreen->tess_rings) {
4424 /* The address must be aligned to 2^19, because the shader only
4425 * receives the high 13 bits. Align it to 2MB to match the GPU page size.
4426 */
4427 sscreen->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
4428 PIPE_RESOURCE_FLAG_UNMAPPABLE |
4429 SI_RESOURCE_FLAG_32BIT |
4430 SI_RESOURCE_FLAG_DRIVER_INTERNAL |
4431 SI_RESOURCE_FLAG_DISCARDABLE,
4432 PIPE_USAGE_DEFAULT,
4433 sscreen->hs.tess_offchip_ring_size +
4434 sscreen->hs.tess_factor_ring_size,
4435 2 * 1024 * 1024);
4436 if (!sscreen->tess_rings) {
4437 simple_mtx_unlock(&sscreen->tess_ring_lock);
4438 return;
4439 }
4440
4441 if (sscreen->info.has_tmz_support) {
4442 sscreen->tess_rings_tmz = pipe_aligned_buffer_create(sctx->b.screen,
4443 PIPE_RESOURCE_FLAG_UNMAPPABLE |
4444 PIPE_RESOURCE_FLAG_ENCRYPTED |
4445 SI_RESOURCE_FLAG_32BIT |
4446 SI_RESOURCE_FLAG_DRIVER_INTERNAL |
4447 SI_RESOURCE_FLAG_DISCARDABLE,
4448 PIPE_USAGE_DEFAULT,
4449 sscreen->hs.tess_offchip_ring_size +
4450 sscreen->hs.tess_factor_ring_size,
4451 2 * 1024 * 1024);
4452 }
4453 }
4454
4455 simple_mtx_unlock(&sscreen->tess_ring_lock);
4456 sctx->has_tessellation = true;
4457
4458 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_ge_ring_state);
4459 }
4460
si_emit_vgt_pipeline_state(struct si_context * sctx,unsigned index)4461 static void si_emit_vgt_pipeline_state(struct si_context *sctx, unsigned index)
4462 {
4463 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
4464
4465 radeon_begin(cs);
4466 radeon_opt_set_context_reg(sctx->gfx_level >= GFX12 ?
4467 R_028A98_VGT_SHADER_STAGES_EN :
4468 R_028B54_VGT_SHADER_STAGES_EN,
4469 SI_TRACKED_VGT_SHADER_STAGES_EN, sctx->vgt_shader_stages_en);
4470 if (sctx->gfx_level == GFX10_3) {
4471 /* Legacy Tess+GS should disable reuse to prevent hangs on GFX10.3. */
4472 bool has_legacy_tess_gs = G_028B54_HS_EN(sctx->vgt_shader_stages_en) &&
4473 G_028B54_GS_EN(sctx->vgt_shader_stages_en) &&
4474 !G_028B54_PRIMGEN_EN(sctx->vgt_shader_stages_en); /* !NGG */
4475
4476 radeon_opt_set_context_reg(R_028AB4_VGT_REUSE_OFF, SI_TRACKED_VGT_REUSE_OFF,
4477 S_028AB4_REUSE_OFF(has_legacy_tess_gs));
4478 }
4479 radeon_end_update_context_roll();
4480
4481 if (sctx->gfx_level >= GFX10) {
4482 uint32_t ge_cntl = sctx->ge_cntl;
4483
4484 if (sctx->gfx_level < GFX11 && sctx->shader.tes.cso) {
4485 /* This must be a multiple of VGT_LS_HS_CONFIG.NUM_PATCHES. */
4486 ge_cntl |= S_03096C_PRIM_GRP_SIZE_GFX10(sctx->num_patches_per_workgroup);
4487 }
4488
4489 radeon_begin_again(cs);
4490 radeon_opt_set_uconfig_reg(R_03096C_GE_CNTL, SI_TRACKED_GE_CNTL, ge_cntl);
4491 radeon_end();
4492 }
4493 }
4494
si_emit_scratch_state(struct si_context * sctx,unsigned index)4495 static void si_emit_scratch_state(struct si_context *sctx, unsigned index)
4496 {
4497 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
4498
4499 radeon_begin(cs);
4500 if (sctx->gfx_level >= GFX11) {
4501 radeon_set_context_reg_seq(R_0286E8_SPI_TMPRING_SIZE, 3);
4502 radeon_emit(sctx->spi_tmpring_size); /* SPI_TMPRING_SIZE */
4503 radeon_emit(sctx->scratch_buffer->gpu_address >> 8); /* SPI_GFX_SCRATCH_BASE_LO */
4504 radeon_emit(sctx->scratch_buffer->gpu_address >> 40); /* SPI_GFX_SCRATCH_BASE_HI */
4505 } else {
4506 radeon_set_context_reg(R_0286E8_SPI_TMPRING_SIZE, sctx->spi_tmpring_size);
4507 }
4508 radeon_end();
4509
4510 if (sctx->scratch_buffer) {
4511 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, sctx->scratch_buffer,
4512 RADEON_USAGE_READWRITE | RADEON_PRIO_SCRATCH_BUFFER);
4513 }
4514 }
4515
4516 struct si_fixed_func_tcs_shader_key {
4517 uint64_t outputs_written;
4518 uint8_t vertices_out;
4519 };
4520
4521 DERIVE_HASH_TABLE(si_fixed_func_tcs_shader_key);
4522
si_set_tcs_to_fixed_func_shader(struct si_context * sctx)4523 bool si_set_tcs_to_fixed_func_shader(struct si_context *sctx)
4524 {
4525 if (!sctx->fixed_func_tcs_shader_cache) {
4526 sctx->fixed_func_tcs_shader_cache = si_fixed_func_tcs_shader_key_table_create(NULL);
4527 }
4528
4529 struct si_fixed_func_tcs_shader_key key;
4530 key.outputs_written = sctx->shader.vs.cso->info.outputs_written_before_tes_gs;
4531 key.vertices_out = sctx->patch_vertices;
4532
4533 struct hash_entry *entry = _mesa_hash_table_search(
4534 sctx->fixed_func_tcs_shader_cache, &key);
4535
4536 struct si_shader_selector *tcs;
4537 if (entry)
4538 tcs = (struct si_shader_selector *)entry->data;
4539 else {
4540 tcs = (struct si_shader_selector *)si_create_passthrough_tcs(sctx);
4541 if (!tcs)
4542 return false;
4543 _mesa_hash_table_insert(sctx->fixed_func_tcs_shader_cache, &key, (void *)tcs);
4544 }
4545
4546 sctx->shader.tcs.cso = tcs;
4547 return true;
4548 }
4549
si_update_tess_in_out_patch_vertices(struct si_context * sctx)4550 static void si_update_tess_in_out_patch_vertices(struct si_context *sctx)
4551 {
4552 if (sctx->is_user_tcs) {
4553 struct si_shader_selector *tcs = sctx->shader.tcs.cso;
4554
4555 bool same_patch_vertices =
4556 sctx->gfx_level >= GFX9 &&
4557 sctx->patch_vertices == tcs->info.base.tess.tcs_vertices_out;
4558
4559 if (sctx->shader.tcs.key.ge.opt.same_patch_vertices != same_patch_vertices) {
4560 sctx->shader.tcs.key.ge.opt.same_patch_vertices = same_patch_vertices;
4561 sctx->do_update_shaders = true;
4562 }
4563 } else {
4564 /* These fields are static for fixed function TCS. So no need to set
4565 * do_update_shaders between fixed-TCS draws. As fixed-TCS to user-TCS
4566 * or opposite, do_update_shaders should already be set by bind state.
4567 */
4568 sctx->shader.tcs.key.ge.opt.same_patch_vertices = sctx->gfx_level >= GFX9;
4569
4570 /* User may only change patch vertices, needs to update fixed func TCS. */
4571 if (sctx->shader.tcs.cso &&
4572 sctx->shader.tcs.cso->info.base.tess.tcs_vertices_out != sctx->patch_vertices)
4573 sctx->do_update_shaders = true;
4574 }
4575 }
4576
si_set_patch_vertices(struct pipe_context * ctx,uint8_t patch_vertices)4577 static void si_set_patch_vertices(struct pipe_context *ctx, uint8_t patch_vertices)
4578 {
4579 struct si_context *sctx = (struct si_context *)ctx;
4580
4581 if (sctx->patch_vertices != patch_vertices) {
4582 sctx->patch_vertices = patch_vertices;
4583 si_update_tess_in_out_patch_vertices(sctx);
4584 if (sctx->shader.tcs.current) {
4585 /* Update the io layout now if possible,
4586 * otherwise make sure it's done by si_update_shaders.
4587 */
4588 if (sctx->has_tessellation)
4589 si_update_tess_io_layout_state(sctx);
4590 else
4591 sctx->do_update_shaders = true;
4592 }
4593
4594 /* Gfx12 programs patch_vertices in VGT_PRIMITIVE_TYPE.NUM_INPUT_CP. Make sure
4595 * the register is updated.
4596 */
4597 if (sctx->gfx_level >= GFX12 && sctx->last_prim == MESA_PRIM_PATCHES)
4598 sctx->last_prim = -1;
4599 }
4600 }
4601
si_shader_lshs_vertex_stride(struct si_shader * ls)4602 unsigned si_shader_lshs_vertex_stride(struct si_shader *ls)
4603 {
4604 unsigned num_slots;
4605
4606 if (ls->selector->stage == MESA_SHADER_VERTEX && !ls->next_shader) {
4607 assert(ls->key.ge.as_ls);
4608 assert(ls->selector->screen->info.gfx_level <= GFX8 || !ls->is_monolithic);
4609 num_slots = util_last_bit64(ls->selector->info.outputs_written_before_tes_gs);
4610 } else {
4611 struct si_shader *tcs = ls->next_shader ? ls->next_shader : ls;
4612
4613 assert(tcs->selector->stage == MESA_SHADER_TESS_CTRL);
4614 assert(tcs->selector->screen->info.gfx_level >= GFX9);
4615
4616 if (tcs->is_monolithic) {
4617 uint64_t lds_inputs_read = tcs->selector->info.base.inputs_read;
4618
4619 /* Don't allocate LDS for inputs passed via VGPRs. */
4620 if (tcs->key.ge.opt.same_patch_vertices)
4621 lds_inputs_read &= ~tcs->selector->info.tcs_vgpr_only_inputs;
4622
4623 /* NIR lowering passes pack LS outputs/HS inputs if the usage masks of both are known. */
4624 num_slots = util_bitcount64(lds_inputs_read);
4625 } else {
4626 num_slots = util_last_bit64(tcs->previous_stage_sel->info.outputs_written_before_tes_gs);
4627 }
4628 }
4629
4630 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex starts on a different LDS
4631 * bank.
4632 */
4633 return num_slots ? num_slots * 16 + 4 : 0;
4634 }
4635
4636 /**
4637 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
4638 * LS.LDS_SIZE is shared by all 3 shader stages.
4639 *
4640 * The information about LDS and other non-compile-time parameters is then
4641 * written to userdata SGPRs.
4642 *
4643 * This depends on:
4644 * - patch_vertices
4645 * - VS and the currently selected shader variant (called by si_update_shaders)
4646 * - TCS and the currently selected shader variant (called by si_update_shaders)
4647 * - tess_uses_prim_id (called by si_update_shaders)
4648 * - sh_base[TESS_EVAL] depending on GS on/off (called by si_update_shaders)
4649 */
si_update_tess_io_layout_state(struct si_context * sctx)4650 void si_update_tess_io_layout_state(struct si_context *sctx)
4651 {
4652 struct si_shader *ls_current;
4653 struct si_shader_selector *tcs = sctx->shader.tcs.cso;
4654 unsigned tess_uses_primid = sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id;
4655 bool has_primid_instancing_bug = sctx->gfx_level == GFX6 && sctx->screen->info.max_se == 1;
4656 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL];
4657 uint8_t num_tcs_input_cp = sctx->patch_vertices;
4658
4659 assert(sctx->shader.tcs.current);
4660
4661 /* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. */
4662 if (sctx->gfx_level >= GFX9) {
4663 ls_current = sctx->shader.tcs.current;
4664 } else {
4665 ls_current = sctx->shader.vs.current;
4666
4667 if (!ls_current) {
4668 sctx->do_update_shaders = true;
4669 return;
4670 }
4671 }
4672
4673 if (sctx->last_ls == ls_current && sctx->last_tcs == tcs &&
4674 sctx->last_tes_sh_base == tes_sh_base && sctx->last_num_tcs_input_cp == num_tcs_input_cp &&
4675 (!has_primid_instancing_bug || (sctx->last_tess_uses_primid == tess_uses_primid)))
4676 return;
4677
4678 sctx->last_ls = ls_current;
4679 sctx->last_tcs = tcs;
4680 sctx->last_tes_sh_base = tes_sh_base;
4681 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
4682 sctx->last_tess_uses_primid = tess_uses_primid;
4683
4684 /* This calculates how shader inputs and outputs among VS, TCS, and TES
4685 * are laid out in LDS. */
4686 unsigned num_tcs_outputs = util_last_bit64(tcs->info.outputs_written_before_tes_gs);
4687 unsigned num_tcs_output_cp = tcs->info.base.tess.tcs_vertices_out;
4688 unsigned num_tcs_patch_outputs = util_last_bit64(tcs->info.patch_outputs_written);
4689
4690 unsigned input_vertex_size = si_shader_lshs_vertex_stride(ls_current);
4691 unsigned num_vs_outputs = input_vertex_size / 16;
4692 unsigned output_vertex_size = num_tcs_outputs * 16;
4693 unsigned input_patch_size = num_tcs_input_cp * input_vertex_size;
4694
4695 unsigned pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
4696 unsigned output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
4697 unsigned lds_per_patch;
4698
4699 /* Compute the LDS size per patch.
4700 *
4701 * LDS is used to store TCS outputs if they are read, and to store tess
4702 * factors if they are not defined in all invocations.
4703 */
4704 if (tcs->info.base.outputs_read ||
4705 tcs->info.base.patch_outputs_read ||
4706 !tcs->info.tessfactors_are_def_in_all_invocs) {
4707 lds_per_patch = input_patch_size + output_patch_size;
4708 } else {
4709 /* LDS will only store TCS inputs. The offchip buffer will only store TCS outputs. */
4710 lds_per_patch = MAX2(input_patch_size, output_patch_size);
4711 }
4712
4713 unsigned num_patches =
4714 ac_compute_num_tess_patches(&sctx->screen->info, num_tcs_input_cp,
4715 num_tcs_output_cp, output_patch_size,
4716 lds_per_patch, ls_current->wave_size,
4717 tess_uses_primid);
4718
4719 if (sctx->num_patches_per_workgroup != num_patches) {
4720 sctx->num_patches_per_workgroup = num_patches;
4721 si_mark_atom_dirty(sctx, &sctx->atoms.s.vgt_pipeline_state);
4722 }
4723
4724 /* Compute userdata SGPRs. */
4725 assert(num_tcs_input_cp <= 32);
4726 assert(num_tcs_output_cp <= 32);
4727 assert(num_patches <= 128);
4728 assert(num_vs_outputs <= 63);
4729 assert(num_tcs_outputs <= 63);
4730
4731 uint64_t ring_va =
4732 sctx->ws->cs_is_secure(&sctx->gfx_cs) ?
4733 si_resource(sctx->screen->tess_rings_tmz)->gpu_address :
4734 si_resource(sctx->screen->tess_rings)->gpu_address;
4735 assert((ring_va & u_bit_consecutive(0, 19)) == 0);
4736
4737 sctx->tes_offchip_ring_va_sgpr = ring_va;
4738 sctx->tcs_offchip_layout &= 0xe0000000;
4739 sctx->tcs_offchip_layout |=
4740 (num_patches - 1) | ((num_tcs_output_cp - 1) << 7) | ((num_tcs_input_cp - 1) << 12) |
4741 (num_vs_outputs << 17) | (num_tcs_outputs << 23);
4742
4743 /* Compute the LDS size. */
4744 unsigned lds_size = ac_compute_tess_lds_size(&sctx->screen->info, lds_per_patch, num_patches);
4745
4746 /* We should be able to support in-shader LDS use with LLVM >= 9
4747 * by just adding the lds_sizes together, but it has never
4748 * been tested. */
4749 assert(ls_current->config.lds_size == 0);
4750
4751 unsigned ls_hs_rsrc2;
4752
4753 if (sctx->gfx_level >= GFX9) {
4754 ls_hs_rsrc2 = sctx->shader.tcs.current->config.rsrc2;
4755
4756 if (sctx->gfx_level >= GFX10)
4757 ls_hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(lds_size);
4758 else
4759 ls_hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(lds_size);
4760 } else {
4761 ls_hs_rsrc2 = sctx->shader.vs.current->config.rsrc2;
4762
4763 si_multiwave_lds_size_workaround(sctx->screen, &lds_size);
4764 ls_hs_rsrc2 |= S_00B52C_LDS_SIZE(lds_size);
4765 }
4766
4767 sctx->ls_hs_rsrc2 = ls_hs_rsrc2;
4768 sctx->ls_hs_config =
4769 S_028B58_NUM_PATCHES(sctx->num_patches_per_workgroup) |
4770 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
4771
4772 if (sctx->gfx_level < GFX12)
4773 sctx->ls_hs_config |= S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp);
4774
4775 si_mark_atom_dirty(sctx, &sctx->atoms.s.tess_io_layout);
4776 }
4777
gfx6_emit_tess_io_layout_state(struct si_context * sctx,unsigned index)4778 static void gfx6_emit_tess_io_layout_state(struct si_context *sctx, unsigned index)
4779 {
4780 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
4781
4782 if (!sctx->shader.tes.cso || !sctx->shader.tcs.current)
4783 return;
4784
4785 radeon_begin(cs);
4786 if (sctx->gfx_level >= GFX12) {
4787 gfx12_opt_push_gfx_sh_reg(R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
4788 SI_TRACKED_SPI_SHADER_PGM_RSRC2_HS, sctx->ls_hs_rsrc2);
4789
4790 /* Set userdata SGPRs for merged LS-HS. */
4791 gfx12_opt_push_gfx_sh_reg(R_00B430_SPI_SHADER_USER_DATA_HS_0 +
4792 GFX9_SGPR_TCS_OFFCHIP_LAYOUT * 4,
4793 SI_TRACKED_SPI_SHADER_USER_DATA_HS__TCS_OFFCHIP_LAYOUT,
4794 sctx->tcs_offchip_layout);
4795 gfx12_opt_push_gfx_sh_reg(R_00B430_SPI_SHADER_USER_DATA_HS_0 +
4796 GFX9_SGPR_TCS_OFFCHIP_ADDR * 4,
4797 SI_TRACKED_SPI_SHADER_USER_DATA_HS__TCS_OFFCHIP_ADDR,
4798 sctx->tes_offchip_ring_va_sgpr);
4799 } else if (sctx->screen->info.has_set_sh_pairs_packed) {
4800 gfx11_opt_push_gfx_sh_reg(R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
4801 SI_TRACKED_SPI_SHADER_PGM_RSRC2_HS, sctx->ls_hs_rsrc2);
4802
4803 /* Set userdata SGPRs for merged LS-HS. */
4804 gfx11_opt_push_gfx_sh_reg(R_00B430_SPI_SHADER_USER_DATA_HS_0 +
4805 GFX9_SGPR_TCS_OFFCHIP_LAYOUT * 4,
4806 SI_TRACKED_SPI_SHADER_USER_DATA_HS__TCS_OFFCHIP_LAYOUT,
4807 sctx->tcs_offchip_layout);
4808 gfx11_opt_push_gfx_sh_reg(R_00B430_SPI_SHADER_USER_DATA_HS_0 +
4809 GFX9_SGPR_TCS_OFFCHIP_ADDR * 4,
4810 SI_TRACKED_SPI_SHADER_USER_DATA_HS__TCS_OFFCHIP_ADDR,
4811 sctx->tes_offchip_ring_va_sgpr);
4812 } else if (sctx->gfx_level >= GFX9) {
4813 radeon_opt_set_sh_reg(R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
4814 SI_TRACKED_SPI_SHADER_PGM_RSRC2_HS, sctx->ls_hs_rsrc2);
4815
4816 /* Set userdata SGPRs for merged LS-HS. */
4817 radeon_opt_set_sh_reg2(R_00B430_SPI_SHADER_USER_DATA_HS_0 +
4818 GFX9_SGPR_TCS_OFFCHIP_LAYOUT * 4,
4819 SI_TRACKED_SPI_SHADER_USER_DATA_HS__TCS_OFFCHIP_LAYOUT,
4820 sctx->tcs_offchip_layout, sctx->tes_offchip_ring_va_sgpr);
4821 } else {
4822 /* Due to a hw bug, RSRC2_LS must be written twice with another
4823 * LS register written in between. */
4824 if (sctx->gfx_level == GFX7 && sctx->family != CHIP_HAWAII)
4825 radeon_set_sh_reg(R_00B52C_SPI_SHADER_PGM_RSRC2_LS, sctx->ls_hs_rsrc2);
4826 radeon_set_sh_reg_seq(R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
4827 radeon_emit(sctx->shader.vs.current->config.rsrc1);
4828 radeon_emit(sctx->ls_hs_rsrc2);
4829
4830 /* Set userdata SGPRs for TCS. */
4831 radeon_opt_set_sh_reg3(R_00B430_SPI_SHADER_USER_DATA_HS_0 +
4832 GFX6_SGPR_TCS_OFFCHIP_LAYOUT * 4,
4833 SI_TRACKED_SPI_SHADER_USER_DATA_HS__TCS_OFFCHIP_LAYOUT,
4834 sctx->tcs_offchip_layout, sctx->tes_offchip_ring_va_sgpr,
4835 sctx->current_vs_state);
4836 }
4837
4838 /* Set userdata SGPRs for TES. */
4839 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL];
4840 assert(tes_sh_base);
4841
4842 /* TES (as ES or VS) reuses the BaseVertex and DrawID user SGPRs that are used when
4843 * tessellation is disabled. We can do that because those user SGPRs are only set in LS
4844 * for tessellation and are unused in TES.
4845 */
4846 if (sctx->screen->info.has_set_sh_pairs_packed) {
4847 gfx11_opt_push_gfx_sh_reg(tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4,
4848 SI_TRACKED_SPI_SHADER_USER_DATA_ES__BASE_VERTEX,
4849 sctx->tcs_offchip_layout);
4850 gfx11_opt_push_gfx_sh_reg(tes_sh_base + SI_SGPR_TES_OFFCHIP_ADDR * 4,
4851 SI_TRACKED_SPI_SHADER_USER_DATA_ES__DRAWID,
4852 sctx->tes_offchip_ring_va_sgpr);
4853 } else {
4854 bool has_gs = sctx->ngg || sctx->shader.gs.cso;
4855
4856 radeon_opt_set_sh_reg2(tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4,
4857 has_gs ? SI_TRACKED_SPI_SHADER_USER_DATA_ES__BASE_VERTEX
4858 : SI_TRACKED_SPI_SHADER_USER_DATA_VS__BASE_VERTEX,
4859 sctx->tcs_offchip_layout, sctx->tes_offchip_ring_va_sgpr);
4860 }
4861 radeon_end();
4862
4863 radeon_begin_again(cs);
4864 if (sctx->gfx_level >= GFX7) {
4865 radeon_opt_set_context_reg_idx(R_028B58_VGT_LS_HS_CONFIG,
4866 SI_TRACKED_VGT_LS_HS_CONFIG, 2, sctx->ls_hs_config);
4867 } else {
4868 radeon_opt_set_context_reg(R_028B58_VGT_LS_HS_CONFIG,
4869 SI_TRACKED_VGT_LS_HS_CONFIG, sctx->ls_hs_config);
4870 }
4871 radeon_end_update_context_roll();
4872 }
4873
gfx12_emit_tess_io_layout_state(struct si_context * sctx,unsigned index)4874 static void gfx12_emit_tess_io_layout_state(struct si_context *sctx, unsigned index)
4875 {
4876 struct radeon_cmdbuf *cs = &sctx->gfx_cs;
4877
4878 if (!sctx->shader.tes.cso || !sctx->shader.tcs.current)
4879 return;
4880
4881 gfx12_opt_push_gfx_sh_reg(R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
4882 SI_TRACKED_SPI_SHADER_PGM_RSRC2_HS, sctx->ls_hs_rsrc2);
4883 /* Set userdata SGPRs for merged LS-HS. */
4884 gfx12_opt_push_gfx_sh_reg(R_00B430_SPI_SHADER_USER_DATA_HS_0 +
4885 GFX9_SGPR_TCS_OFFCHIP_LAYOUT * 4,
4886 SI_TRACKED_SPI_SHADER_USER_DATA_HS__TCS_OFFCHIP_LAYOUT,
4887 sctx->tcs_offchip_layout);
4888 gfx12_opt_push_gfx_sh_reg(R_00B430_SPI_SHADER_USER_DATA_HS_0 +
4889 GFX9_SGPR_TCS_OFFCHIP_ADDR * 4,
4890 SI_TRACKED_SPI_SHADER_USER_DATA_HS__TCS_OFFCHIP_ADDR,
4891 sctx->tes_offchip_ring_va_sgpr);
4892
4893 /* Set userdata SGPRs for TES. */
4894 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL];
4895 assert(tes_sh_base);
4896
4897 /* TES (as ES or VS) reuses the BaseVertex and DrawID user SGPRs that are used when
4898 * tessellation is disabled. We can do that because those user SGPRs are only set in LS
4899 * for tessellation and are unused in TES.
4900 */
4901 gfx12_opt_push_gfx_sh_reg(tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4,
4902 SI_TRACKED_SPI_SHADER_USER_DATA_ES__BASE_VERTEX,
4903 sctx->tcs_offchip_layout);
4904 gfx12_opt_push_gfx_sh_reg(tes_sh_base + SI_SGPR_TES_OFFCHIP_ADDR * 4,
4905 SI_TRACKED_SPI_SHADER_USER_DATA_ES__DRAWID,
4906 sctx->tes_offchip_ring_va_sgpr);
4907
4908 radeon_begin(cs);
4909 radeon_opt_set_context_reg_idx(R_028B58_VGT_LS_HS_CONFIG,
4910 SI_TRACKED_VGT_LS_HS_CONFIG, 2, sctx->ls_hs_config);
4911 radeon_end(); /* don't track context rolls on GFX12 */
4912 }
4913
si_init_screen_live_shader_cache(struct si_screen * sscreen)4914 void si_init_screen_live_shader_cache(struct si_screen *sscreen)
4915 {
4916 util_live_shader_cache_init(&sscreen->live_shader_cache, si_create_shader_selector,
4917 si_destroy_shader_selector);
4918 }
4919
4920 template<int NUM_INTERP>
si_emit_spi_map(struct si_context * sctx,unsigned index)4921 static void si_emit_spi_map(struct si_context *sctx, unsigned index)
4922 {
4923 struct si_shader *ps = sctx->shader.ps.current;
4924 struct si_shader *vs = si_get_vs(sctx)->current;
4925 unsigned spi_ps_input_cntl[NUM_INTERP];
4926
4927 STATIC_ASSERT(NUM_INTERP >= 0 && NUM_INTERP <= 32);
4928
4929 if (sctx->gfx_level >= GFX12) {
4930 gfx12_opt_push_gfx_sh_reg(R_00B0C4_SPI_SHADER_GS_OUT_CONFIG_PS,
4931 SI_TRACKED_SPI_SHADER_GS_OUT_CONFIG_PS,
4932 vs->ngg.spi_vs_out_config | ps->ps.spi_gs_out_config_ps);
4933 }
4934
4935 if (!NUM_INTERP)
4936 return;
4937
4938 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
4939
4940 for (unsigned i = 0; i < NUM_INTERP; i++) {
4941 union si_input_info input = ps->info.ps_inputs[i];
4942 unsigned ps_input_cntl = vs->info.vs_output_ps_input_cntl[input.semantic];
4943 bool non_default_val = G_028644_OFFSET(ps_input_cntl) != 0x20;
4944
4945 if (non_default_val) {
4946 if (input.interpolate == INTERP_MODE_FLAT ||
4947 (input.interpolate == INTERP_MODE_COLOR && rs->flatshade))
4948 ps_input_cntl |= S_028644_FLAT_SHADE(1);
4949
4950 if (input.fp16_lo_hi_valid) {
4951 ps_input_cntl |= S_028644_FP16_INTERP_MODE(1) |
4952 S_028644_ATTR0_VALID(1) | /* this must be set if FP16_INTERP_MODE is set */
4953 S_028644_ATTR1_VALID(!!(input.fp16_lo_hi_valid & 0x2));
4954 }
4955 }
4956
4957 if (input.semantic == VARYING_SLOT_PNTC ||
4958 (input.semantic >= VARYING_SLOT_TEX0 && input.semantic <= VARYING_SLOT_TEX7 &&
4959 rs->sprite_coord_enable & (1 << (input.semantic - VARYING_SLOT_TEX0)))) {
4960 /* Overwrite the whole value (except OFFSET) for sprite coordinates. */
4961 ps_input_cntl &= ~C_028644_OFFSET;
4962 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
4963 if (input.fp16_lo_hi_valid & 0x1) {
4964 ps_input_cntl |= S_028644_FP16_INTERP_MODE(1) |
4965 S_028644_ATTR0_VALID(1);
4966 }
4967 }
4968
4969 spi_ps_input_cntl[i] = ps_input_cntl;
4970 }
4971
4972 /* Performance notes:
4973 * Dota 2: Only ~16% of SPI map updates set different values.
4974 * Talos: Only ~9% of SPI map updates set different values.
4975 */
4976 if (sctx->gfx_level >= GFX12) {
4977 radeon_begin(&sctx->gfx_cs);
4978 radeon_opt_set_context_regn(R_028664_SPI_PS_INPUT_CNTL_0, spi_ps_input_cntl,
4979 sctx->tracked_regs.spi_ps_input_cntl, NUM_INTERP);
4980 radeon_end(); /* don't track context rolls on GFX12 */
4981 } else {
4982 radeon_begin(&sctx->gfx_cs);
4983 radeon_opt_set_context_regn(R_028644_SPI_PS_INPUT_CNTL_0, spi_ps_input_cntl,
4984 sctx->tracked_regs.spi_ps_input_cntl, NUM_INTERP);
4985 radeon_end_update_context_roll();
4986 }
4987 }
4988
si_emit_spi_ge_ring_state(struct si_context * sctx,unsigned index)4989 static void si_emit_spi_ge_ring_state(struct si_context *sctx, unsigned index)
4990 {
4991 struct si_screen *sscreen = sctx->screen;
4992
4993 if (sctx->has_tessellation) {
4994 struct pipe_resource *tf_ring =
4995 sctx->ws->cs_is_secure(&sctx->gfx_cs) ? sscreen->tess_rings_tmz : sscreen->tess_rings;
4996 uint64_t factor_va = si_resource(tf_ring)->gpu_address +
4997 sscreen->hs.tess_offchip_ring_size;
4998
4999 unsigned tf_ring_size_field = sscreen->hs.tess_factor_ring_size / 4;
5000 if (sctx->gfx_level >= GFX11)
5001 tf_ring_size_field /= sscreen->info.max_se;
5002
5003 assert((tf_ring_size_field & C_030938_SIZE) == 0);
5004
5005 radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, si_resource(tf_ring),
5006 RADEON_USAGE_READWRITE | RADEON_PRIO_SHADER_RINGS);
5007
5008 radeon_begin(&sctx->gfx_cs);
5009 /* Required before writing tessellation config registers. */
5010 radeon_event_write(V_028A90_VS_PARTIAL_FLUSH);
5011 radeon_event_write(V_028A90_VGT_FLUSH);
5012
5013 if (sctx->gfx_level >= GFX7) {
5014 radeon_set_uconfig_reg_seq(R_030938_VGT_TF_RING_SIZE, 3);
5015 radeon_emit(S_030938_SIZE(tf_ring_size_field)); /* R_030938_VGT_TF_RING_SIZE */
5016 radeon_emit(sscreen->hs.hs_offchip_param); /* R_03093C_VGT_HS_OFFCHIP_PARAM */
5017 radeon_emit(factor_va >> 8); /* R_030940_VGT_TF_MEMORY_BASE */
5018
5019 if (sctx->gfx_level >= GFX12)
5020 radeon_set_uconfig_reg(R_03099C_VGT_TF_MEMORY_BASE_HI, S_03099C_BASE_HI(factor_va >> 40));
5021 else if (sctx->gfx_level >= GFX10)
5022 radeon_set_uconfig_reg(R_030984_VGT_TF_MEMORY_BASE_HI, S_030984_BASE_HI(factor_va >> 40));
5023 else if (sctx->gfx_level == GFX9)
5024 radeon_set_uconfig_reg(R_030944_VGT_TF_MEMORY_BASE_HI, S_030944_BASE_HI(factor_va >> 40));
5025 } else {
5026 radeon_set_config_reg(R_008988_VGT_TF_RING_SIZE, S_008988_SIZE(tf_ring_size_field));
5027 radeon_set_config_reg(R_0089B8_VGT_TF_MEMORY_BASE, factor_va >> 8);
5028 radeon_set_config_reg(R_0089B0_VGT_HS_OFFCHIP_PARAM, sscreen->hs.hs_offchip_param);
5029 }
5030 radeon_end();
5031 }
5032
5033 if (sctx->gfx_level >= GFX11) {
5034 /* We must wait for idle using an EOP event before changing the attribute ring registers.
5035 * Use the bottom-of-pipe EOP event, but use the PWS TS counter instead of the counter
5036 * in memory.
5037 */
5038 si_cp_release_acquire_mem_pws(sctx, &sctx->gfx_cs, V_028A90_BOTTOM_OF_PIPE_TS, 0,
5039 V_580_CP_ME, 0);
5040
5041 uint64_t attr_address = sscreen->attribute_pos_prim_ring->gpu_address;
5042 assert((attr_address >> 32) == sscreen->info.address32_hi);
5043
5044 radeon_begin(&sctx->gfx_cs);
5045 radeon_set_uconfig_reg_seq(R_031110_SPI_GS_THROTTLE_CNTL1, 4);
5046 radeon_emit(0x12355123); /* SPI_GS_THROTTLE_CNTL1 */
5047 radeon_emit(0x1544D); /* SPI_GS_THROTTLE_CNTL2 */
5048 radeon_emit(attr_address >> 16); /* SPI_ATTRIBUTE_RING_BASE */
5049 radeon_emit(S_03111C_MEM_SIZE((sscreen->info.attribute_ring_size_per_se >> 16) - 1) |
5050 S_03111C_BIG_PAGE(sscreen->info.discardable_allows_big_page) |
5051 S_03111C_L1_POLICY(1)); /* SPI_ATTRIBUTE_RING_SIZE */
5052
5053 if (sctx->gfx_level >= GFX12) {
5054 uint64_t pos_address = attr_address + sscreen->info.pos_ring_offset;
5055 uint64_t prim_address = attr_address + sscreen->info.prim_ring_offset;
5056
5057 /* When one of these 4 registers is updated, all 4 must be updated. */
5058 radeon_set_uconfig_reg_seq(R_0309A0_GE_POS_RING_BASE, 4);
5059 radeon_emit(pos_address >> 16); /* R_0309A0_GE_POS_RING_BASE */
5060 radeon_emit(S_0309A4_MEM_SIZE(sscreen->info.pos_ring_size_per_se >> 5)); /* R_0309A4_GE_POS_RING_SIZE */
5061 radeon_emit(prim_address >> 16); /* R_0309A8_GE_PRIM_RING_BASE */
5062 radeon_emit(S_0309AC_MEM_SIZE(sscreen->info.prim_ring_size_per_se >> 5) |
5063 S_0309AC_SCOPE(gfx12_scope_device) |
5064 S_0309AC_PAF_TEMPORAL(gfx12_store_high_temporal_stay_dirty) |
5065 S_0309AC_PAB_TEMPORAL(gfx12_load_last_use_discard) |
5066 S_0309AC_SPEC_DATA_READ(gfx12_spec_read_auto) |
5067 S_0309AC_FORCE_SE_SCOPE(1) |
5068 S_0309AC_PAB_NOFILL(1)); /* R_0309AC_GE_PRIM_RING_SIZE */
5069 }
5070 radeon_end();
5071 }
5072 }
5073
si_init_shader_functions(struct si_context * sctx)5074 void si_init_shader_functions(struct si_context *sctx)
5075 {
5076 sctx->atoms.s.vgt_pipeline_state.emit = si_emit_vgt_pipeline_state;
5077 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
5078 sctx->atoms.s.spi_ge_ring_state.emit = si_emit_spi_ge_ring_state;
5079
5080 if (sctx->gfx_level >= GFX12)
5081 sctx->atoms.s.tess_io_layout.emit = gfx12_emit_tess_io_layout_state;
5082 else
5083 sctx->atoms.s.tess_io_layout.emit = gfx6_emit_tess_io_layout_state;
5084
5085 sctx->b.create_vs_state = si_create_shader;
5086 sctx->b.create_tcs_state = si_create_shader;
5087 sctx->b.create_tes_state = si_create_shader;
5088 sctx->b.create_gs_state = si_create_shader;
5089 sctx->b.create_fs_state = si_create_shader;
5090
5091 sctx->b.bind_vs_state = si_bind_vs_shader;
5092 sctx->b.bind_tcs_state = si_bind_tcs_shader;
5093 sctx->b.bind_tes_state = si_bind_tes_shader;
5094 sctx->b.bind_gs_state = si_bind_gs_shader;
5095 sctx->b.bind_fs_state = si_bind_ps_shader;
5096
5097 sctx->b.delete_vs_state = si_delete_shader_selector;
5098 sctx->b.delete_tcs_state = si_delete_shader_selector;
5099 sctx->b.delete_tes_state = si_delete_shader_selector;
5100 sctx->b.delete_gs_state = si_delete_shader_selector;
5101 sctx->b.delete_fs_state = si_delete_shader_selector;
5102
5103 sctx->b.set_patch_vertices = si_set_patch_vertices;
5104
5105 /* This unrolls the loops in si_emit_spi_map and inlines memcmp and memcpys.
5106 * It improves performance for viewperf/snx.
5107 */
5108 sctx->emit_spi_map[0] = si_emit_spi_map<0>;
5109 sctx->emit_spi_map[1] = si_emit_spi_map<1>;
5110 sctx->emit_spi_map[2] = si_emit_spi_map<2>;
5111 sctx->emit_spi_map[3] = si_emit_spi_map<3>;
5112 sctx->emit_spi_map[4] = si_emit_spi_map<4>;
5113 sctx->emit_spi_map[5] = si_emit_spi_map<5>;
5114 sctx->emit_spi_map[6] = si_emit_spi_map<6>;
5115 sctx->emit_spi_map[7] = si_emit_spi_map<7>;
5116 sctx->emit_spi_map[8] = si_emit_spi_map<8>;
5117 sctx->emit_spi_map[9] = si_emit_spi_map<9>;
5118 sctx->emit_spi_map[10] = si_emit_spi_map<10>;
5119 sctx->emit_spi_map[11] = si_emit_spi_map<11>;
5120 sctx->emit_spi_map[12] = si_emit_spi_map<12>;
5121 sctx->emit_spi_map[13] = si_emit_spi_map<13>;
5122 sctx->emit_spi_map[14] = si_emit_spi_map<14>;
5123 sctx->emit_spi_map[15] = si_emit_spi_map<15>;
5124 sctx->emit_spi_map[16] = si_emit_spi_map<16>;
5125 sctx->emit_spi_map[17] = si_emit_spi_map<17>;
5126 sctx->emit_spi_map[18] = si_emit_spi_map<18>;
5127 sctx->emit_spi_map[19] = si_emit_spi_map<19>;
5128 sctx->emit_spi_map[20] = si_emit_spi_map<20>;
5129 sctx->emit_spi_map[21] = si_emit_spi_map<21>;
5130 sctx->emit_spi_map[22] = si_emit_spi_map<22>;
5131 sctx->emit_spi_map[23] = si_emit_spi_map<23>;
5132 sctx->emit_spi_map[24] = si_emit_spi_map<24>;
5133 sctx->emit_spi_map[25] = si_emit_spi_map<25>;
5134 sctx->emit_spi_map[26] = si_emit_spi_map<26>;
5135 sctx->emit_spi_map[27] = si_emit_spi_map<27>;
5136 sctx->emit_spi_map[28] = si_emit_spi_map<28>;
5137 sctx->emit_spi_map[29] = si_emit_spi_map<29>;
5138 sctx->emit_spi_map[30] = si_emit_spi_map<30>;
5139 sctx->emit_spi_map[31] = si_emit_spi_map<31>;
5140 sctx->emit_spi_map[32] = si_emit_spi_map<32>;
5141 }
5142