1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef SOC_MEDIATEK_COMMON_CLKBUF_H 4 #define SOC_MEDIATEK_COMMON_CLKBUF_H 5 6 #include <device/mmio.h> 7 8 enum { 9 PMIC_RG_DCXO_CW00 = 0x0788, 10 PMIC_RG_DCXO_CW02 = 0x0790, 11 PMIC_RG_DCXO_CW08 = 0x079C, 12 PMIC_RG_DCXO_CW09 = 0x079E, 13 PMIC_RG_DCXO_CW09_CLR = 0x07A2, 14 PMIC_RG_DCXO_CW10 = 0x07A4, 15 PMIC_RG_DCXO_CW12 = 0x07A8, 16 PMIC_RG_DCXO_CW13 = 0x07AA, 17 PMIC_RG_DCXO_CW15 = 0x07AE, 18 PMIC_RG_DCXO_CW19 = 0x07B6, 19 }; 20 21 enum { 22 PMIC_TOP_TMA_KEY = 0x3A8, 23 PMIC_RG_TOP_SPI_CON1 = 0x458, 24 }; 25 26 enum { 27 PMIC_TOP_TMA_KEY_UNLOCK = 0x9CA6, 28 }; 29 30 enum { 31 PMIC_RG_LDO_VRFCK_ELR = 0x1B40, 32 PMIC_RG_LDO_VRFCK_CON0 = 0x1D1C, 33 PMIC_RG_LDO_VRFCK_OP_EN = 0x1D22, 34 PMIC_RG_LDO_VRFCK_OP_EN_SET = 0x1D24, 35 PMIC_RG_LDO_VBBCK_CON0 = 0x1D2E, 36 PMIC_RG_LDO_VBBCK_OP_EN = 0x1D34, 37 PMIC_RG_LDO_VBBCK_OP_EN_SET = 0x1D36, 38 }; 39 40 enum { 41 PMIC_RG_DCXO_ADLDO_BIAS_ELR_0 = 0x209C, 42 PMIC_RG_DCXO_ADLDO_BIAS_ELR_1 = 0x209E, 43 }; 44 45 enum { 46 PMIC_RG_XO_BUF_CTL0 = 0x54C, 47 PMIC_RG_XO_BUF_CTL1 = 0x54E, 48 PMIC_RG_XO_BUF_CTL2 = 0x550, 49 PMIC_RG_XO_BUF_CTL3 = 0x552, 50 PMIC_RG_XO_BUF_CTL4 = 0x554, 51 PMIC_RG_XO_CONN_BT0 = 0x556, 52 }; 53 54 DEFINE_BITFIELD(PMIC_REG_COMMON, 15, 0) 55 DEFINE_BIT(PMIC_RG_VRFCK_HV_EN, 9) 56 DEFINE_BIT(PMIC_RG_LDO_VRFCK_EN, 0) 57 DEFINE_BIT(PMIC_RG_LDO_VRFCK_ANA_SEL, 0) 58 DEFINE_BIT(PMIC_RG_LDO_VBBCK_EN, 0) 59 DEFINE_BIT(PMIC_RG_VRFCK_NDIS_EN, 11) 60 DEFINE_BIT(PMIC_RG_VRFCK_1_NDIS_EN, 0) 61 DEFINE_BIT(PMIC_RG_LDO_VRFCK_HW14_OP_EN, 14) 62 DEFINE_BIT(PMIC_RG_LDO_VBBCK_HW14_OP_EN, 14) 63 DEFINE_BIT(PMIC_RG_SRCLKEN_IN3_EN, 0) 64 DEFINE_BIT(PMIC_RG_XO_PMIC_TOP_DIG_SW, 2) 65 DEFINE_BITFIELD(PMIC_RG_XO_VOTE, 10, 0) 66 67 int clk_buf_init(void); 68 69 #endif /* SOC_MEDIATEK_COMMON_CLKBUF_H */ 70