1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef MTK_COMMON_I2C_H 4 #define MTK_COMMON_I2C_H 5 6 #include <commonlib/bsd/helpers.h> 7 #include <device/i2c.h> 8 9 /* I2C DMA Registers */ 10 struct mt_i2c_dma_regs { 11 uint32_t dma_int_flag; 12 uint32_t dma_int_en; 13 uint32_t dma_en; 14 uint32_t dma_rst; 15 uint32_t reserved1; 16 uint32_t dma_flush; 17 uint32_t dma_con; 18 uint32_t dma_tx_mem_addr; 19 uint32_t dma_rx_mem_addr; 20 uint32_t dma_tx_len; 21 uint32_t dma_rx_len; 22 }; 23 24 check_member(mt_i2c_dma_regs, dma_tx_len, 0x24); 25 26 /* I2C Configuration */ 27 enum { 28 I2C_HS_DEFAULT_VALUE = 0x0102, 29 }; 30 31 enum i2c_modes { 32 I2C_WRITE_MODE = 0, 33 I2C_READ_MODE = 1, 34 I2C_WRITE_READ_MODE = 2, 35 }; 36 37 enum { 38 I2C_DMA_CON_TX = 0x0, 39 I2C_DMA_CON_RX = 0x1, 40 I2C_DMA_START_EN = 0x1, 41 I2C_DMA_INT_FLAG_NONE = 0x0, 42 I2C_DMA_CLR_FLAG = 0x0, 43 I2C_DMA_FLUSH_FLAG = 0x1, 44 I2C_DMA_ASYNC_MODE = 0x0004, 45 I2C_DMA_SKIP_CONFIG = 0x0010, 46 I2C_DMA_DIR_CHANGE = 0x0200, 47 I2C_DMA_WARM_RST = 0x1, 48 I2C_DMA_HARD_RST = 0x2, 49 I2C_DMA_HANDSHAKE_RST = 0x4, 50 }; 51 52 enum { 53 I2C_TRANS_LEN_MASK = (0xff), 54 I2C_TRANS_AUX_LEN_MASK = (0x1f << 8), 55 I2C_CONTROL_MASK = (0x3f << 1) 56 }; 57 58 enum { 59 I2C_APDMA_NOASYNC = 0, 60 I2C_APDMA_ASYNC = 1, 61 }; 62 63 /* Register mask */ 64 enum { 65 I2C_HS_NACKERR = (1 << 2), 66 I2C_ACKERR = (1 << 1), 67 I2C_TRANSAC_COMP = (1 << 0), 68 }; 69 70 /* reset bits */ 71 enum { 72 I2C_CLR_FLAG = 0x0, 73 I2C_SOFT_RST = 0x1, 74 I2C_HANDSHAKE_RST = 0x20, 75 }; 76 77 /* i2c control bits */ 78 enum { 79 ASYNC_MODE = (1 << 9), 80 DMAACK_EN = (1 << 8), 81 ACK_ERR_DET_EN = (1 << 5), 82 DIR_CHG = (1 << 4), 83 CLK_EXT = (1 << 3), 84 DMA_EN = (1 << 2), 85 REPEATED_START_FLAG = (1 << 1), 86 STOP_FLAG = (0 << 1) 87 }; 88 89 /* I2C Status Code */ 90 enum { 91 I2C_OK = 0x0000, 92 I2C_SET_SPEED_FAIL_OVER_SPEED = -0xA001, 93 I2C_TRANSFER_INVALID_LENGTH = -0xA002, 94 I2C_TRANSFER_FAIL_HS_NACKERR = -0xA003, 95 I2C_TRANSFER_FAIL_ACKERR = -0xA004, 96 I2C_TRANSFER_FAIL_TIMEOUT = -0xA005, 97 I2C_TRANSFER_INVALID_ARGUMENT = -0xA006, 98 }; 99 100 struct mtk_i2c_ac_timing { 101 u16 htiming; 102 u16 ltiming; 103 u16 hs; 104 u16 ext; 105 u16 inter_clk_div; 106 u16 scl_hl_ratio; 107 u16 hs_scl_hl_ratio; 108 u16 sta_stop; 109 u16 hs_sta_stop; 110 u16 sda_timing; 111 }; 112 113 struct mtk_i2c { 114 struct mt_i2c_regs *i2c_regs; 115 struct mt_i2c_dma_regs *i2c_dma_regs; 116 struct mtk_i2c_ac_timing ac_timing; 117 uint32_t mt_i2c_flag; 118 }; 119 120 #define I2C_TIME_CLR_VALUE 0x0000 121 #define MAX_SAMPLE_CNT_DIV 8 122 #define MAX_STEP_CNT_DIV 64 123 #define MAX_HS_STEP_CNT_DIV 8 124 #define I2C_TIME_DEFAULT_VALUE 0x0083 125 #define I2C_STANDARD_MODE_BUFFER (1000 / 3) 126 #define I2C_FAST_MODE_BUFFER (300 / 3) 127 #define I2C_FAST_MODE_PLUS_BUFFER (20 / 3) 128 129 /* 130 * struct i2c_spec_values: 131 * @min_low_ns: min LOW period of the SCL clock 132 * @min_su_sta_ns: min set-up time for a repeated START condition 133 * @max_hd_dat_ns: max data hold time 134 * @min_su_dat_ns: min data set-up time 135 */ 136 struct i2c_spec_values { 137 uint32_t min_low_ns; 138 uint32_t min_su_sta_ns; 139 uint32_t max_hd_dat_ns; 140 uint32_t min_su_dat_ns; 141 }; 142 143 extern struct mtk_i2c mtk_i2c_bus_controller[]; 144 const struct i2c_spec_values *mtk_i2c_get_spec(uint32_t speed); 145 void mtk_i2c_dump_more_info(struct mt_i2c_regs *regs); 146 147 int mtk_i2c_check_ac_timing(uint8_t bus, uint32_t clk_src, 148 uint32_t check_speed, 149 uint32_t step_cnt, 150 uint32_t sample_cnt); 151 int mtk_i2c_calculate_speed(uint8_t bus, uint32_t clk_src, 152 uint32_t target_speed, 153 uint32_t *timing_step_cnt, 154 uint32_t *timing_sample_cnt); 155 void mtk_i2c_speed_init(uint8_t bus, uint32_t speed); 156 void mtk_i2c_config_timing(struct mt_i2c_regs *regs, struct mtk_i2c *bus_ctrl); 157 158 #endif 159