1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef __SOC_NVIDIA_TEGRA_APBMISC_H__ 4 #define __SOC_NVIDIA_TEGRA_APBMISC_H__ 5 6 #include <stdint.h> 7 8 struct apbmisc { 9 u32 reserved0[2]; /* ABP_MISC_PP_ offsets 00 and 04 */ 10 u32 pp_strapping_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */ 11 u32 reserved1[6]; /* ABP_MISC_PP_ offsets 0C-20 */ 12 u32 pp_config_ctl; /* _CONFIG_CTL_0, offset 24 */ 13 u32 reserved2[6]; /* APB_MISC_PP_ offsets 28-3C */ 14 u32 pp_pinmux_global; /* _PINMUX_GLOBAL_0, offset 40 */ 15 }; 16 17 #define PP_CONFIG_CTL_TBE (1 << 7) 18 #define PP_CONFIG_CTL_JTAG (1 << 6) 19 20 #define PP_PINMUX_CLAMP_INPUTS (1 << 0) 21 22 enum { 23 MISC_GP_HIDREV = 0x804 24 }; 25 26 struct tegra_revision { 27 int hid_fam; 28 int chip_id; 29 int major; 30 int minor; 31 }; 32 33 void enable_jtag(void); 34 void clamp_tristate_inputs(void); 35 void tegra_revision_info(struct tegra_revision *id); 36 37 enum { 38 PP_STRAPPING_OPT_A_RAM_CODE_SHIFT = 4, 39 PP_STRAPPING_OPT_A_RAM_CODE_MASK = 40 0xF << PP_STRAPPING_OPT_A_RAM_CODE_SHIFT, 41 }; 42 43 #endif /* __SOC_NVIDIA_TEGRA_APBMISC_H__ */ 44