1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 3 #ifndef __SOC_NVIDIA_TEGRA_DC_H 4 #define __SOC_NVIDIA_TEGRA_DC_H 5 6 #include <device/device.h> 7 #include <types.h> 8 9 /* Register definitions for the Tegra display controller */ 10 11 /* CMD register 0x000 ~ 0x43 */ 12 struct dc_cmd_reg { 13 /* Address 0x000 ~ 0x002 */ 14 u32 gen_incr_syncpt; /* _CMD_GENERAL_INCR_SYNCPT_0 */ 15 u32 gen_incr_syncpt_ctrl; /* _CMD_GENERAL_INCR_SYNCPT_CNTRL_0 */ 16 u32 gen_incr_syncpt_err; /* _CMD_GENERAL_INCR_SYNCPT_ERROR_0 */ 17 18 u32 reserved0[5]; /* reserved_0[5] */ 19 20 /* Address 0x008 ~ 0x00a */ 21 u32 win_a_incr_syncpt; /* _CMD_WIN_A_INCR_SYNCPT_0 */ 22 u32 win_a_incr_syncpt_ctrl; /* _CMD_WIN_A_INCR_SYNCPT_CNTRL_0 */ 23 u32 win_a_incr_syncpt_err; /* _CMD_WIN_A_INCR_SYNCPT_ERROR_0 */ 24 25 u32 reserved1[5]; /* reserved_1[5] */ 26 27 /* Address 0x010 ~ 0x012 */ 28 u32 win_b_incr_syncpt; /* _CMD_WIN_B_INCR_SYNCPT_0 */ 29 u32 win_b_incr_syncpt_ctrl; /* _CMD_WIN_B_INCR_SYNCPT_CNTRL_0 */ 30 u32 win_b_incr_syncpt_err; /* _CMD_WIN_B_INCR_SYNCPT_ERROR_0 */ 31 32 u32 reserved2[5]; /* reserved_2[5] */ 33 34 /* Address 0x018 ~ 0x01a */ 35 u32 win_c_incr_syncpt; /* _CMD_WIN_C_INCR_SYNCPT_0 */ 36 u32 win_c_incr_syncpt_ctrl; /* _CMD_WIN_C_INCR_SYNCPT_CNTRL_0 */ 37 u32 win_c_incr_syncpt_err; /* _CMD_WIN_C_INCR_SYNCPT_ERROR_0 */ 38 39 u32 reserved3[13]; /* reserved_3[13] */ 40 41 /* Address 0x028 */ 42 u32 cont_syncpt_vsync; /* _CMD_CONT_SYNCPT_VSYNC_0 */ 43 44 u32 reserved4[7]; /* reserved_4[7] */ 45 46 /* Address 0x030 ~ 0x033 */ 47 u32 ctxsw; /* _CMD_CTXSW_0 */ 48 u32 disp_cmd_opt0; /* _CMD_DISPLAY_COMMAND_OPTION0_0 */ 49 u32 disp_cmd; /* _CMD_DISPLAY_COMMAND_0 */ 50 u32 sig_raise; /* _CMD_SIGNAL_RAISE_0 */ 51 52 u32 reserved5[2]; /* reserved_0[2] */ 53 54 /* Address 0x036 ~ 0x03e */ 55 u32 disp_pow_ctrl; /* _CMD_DISPLAY_POWER_CONTROL_0 */ 56 u32 int_stat; /* _CMD_INT_STATUS_0 */ 57 u32 int_mask; /* _CMD_INT_MASK_0 */ 58 u32 int_enb; /* _CMD_INT_ENABLE_0 */ 59 u32 int_type; /* _CMD_INT_TYPE_0 */ 60 u32 int_polarity; /* _CMD_INT_POLARITY_0 */ 61 u32 sig_raise1; /* _CMD_SIGNAL_RAISE1_0 */ 62 u32 sig_raise2; /* _CMD_SIGNAL_RAISE2_0 */ 63 u32 sig_raise3; /* _CMD_SIGNAL_RAISE3_0 */ 64 65 u32 reserved6; /* reserved_6 */ 66 67 /* Address 0x040 ~ 0x043 */ 68 u32 state_access; /* _CMD_STATE_ACCESS_0 */ 69 u32 state_ctrl; /* _CMD_STATE_CONTROL_0 */ 70 u32 disp_win_header; /* _CMD_DISPLAY_WINDOW_HEADER_0 */ 71 u32 reg_act_ctrl; /* _CMD_REG_ACT_CONTROL_0 */ 72 }; 73 check_member(dc_cmd_reg, reg_act_ctrl, 0x43 * 4); 74 75 enum { 76 PIN_REG_COUNT = 4, 77 PIN_OUTPUT_SEL_COUNT = 7, 78 }; 79 80 /* COM register 0x300 ~ 0x329 */ 81 struct dc_com_reg { 82 /* Address 0x300 ~ 0x301 */ 83 u32 crc_ctrl; /* _COM_CRC_CONTROL_0 */ 84 u32 crc_checksum; /* _COM_CRC_CHECKSUM_0 */ 85 86 /* _COM_PIN_OUTPUT_ENABLE0/1/2/3_0: Address 0x302 ~ 0x305 */ 87 u32 pin_output_enb[PIN_REG_COUNT]; 88 89 /* _COM_PIN_OUTPUT_POLARITY0/1/2/3_0: Address 0x306 ~ 0x309 */ 90 u32 pin_output_polarity[PIN_REG_COUNT]; 91 92 /* _COM_PIN_OUTPUT_DATA0/1/2/3_0: Address 0x30a ~ 0x30d */ 93 u32 pin_output_data[PIN_REG_COUNT]; 94 95 /* _COM_PIN_INPUT_ENABLE0_0: Address 0x30e ~ 0x311 */ 96 u32 pin_input_enb[PIN_REG_COUNT]; 97 98 /* Address 0x312 ~ 0x313 */ 99 u32 pin_input_data0; /* _COM_PIN_INPUT_DATA0_0 */ 100 u32 pin_input_data1; /* _COM_PIN_INPUT_DATA1_0 */ 101 102 /* _COM_PIN_OUTPUT_SELECT0/1/2/3/4/5/6_0: Address 0x314 ~ 0x31a */ 103 u32 pin_output_sel[PIN_OUTPUT_SEL_COUNT]; 104 105 /* Address 0x31b ~ 0x329 */ 106 u32 pin_misc_ctrl; /* _COM_PIN_MISC_CONTROL_0 */ 107 u32 pm0_ctrl; /* _COM_PM0_CONTROL_0 */ 108 u32 pm0_duty_cycle; /* _COM_PM0_DUTY_CYCLE_0 */ 109 u32 pm1_ctrl; /* _COM_PM1_CONTROL_0 */ 110 u32 pm1_duty_cycle; /* _COM_PM1_DUTY_CYCLE_0 */ 111 u32 spi_ctrl; /* _COM_SPI_CONTROL_0 */ 112 u32 spi_start_byte; /* _COM_SPI_START_BYTE_0 */ 113 u32 hspi_wr_data_ab; /* _COM_HSPI_WRITE_DATA_AB_0 */ 114 u32 hspi_wr_data_cd; /* _COM_HSPI_WRITE_DATA_CD */ 115 u32 hspi_cs_dc; /* _COM_HSPI_CS_DC_0 */ 116 u32 scratch_reg_a; /* _COM_SCRATCH_REGISTER_A_0 */ 117 u32 scratch_reg_b; /* _COM_SCRATCH_REGISTER_B_0 */ 118 u32 gpio_ctrl; /* _COM_GPIO_CTRL_0 */ 119 u32 gpio_debounce_cnt; /* _COM_GPIO_DEBOUNCE_COUNTER_0 */ 120 u32 crc_checksum_latched; /* _COM_CRC_CHECKSUM_LATCHED_0 */ 121 }; 122 check_member(dc_com_reg, crc_checksum_latched, (0x329 - 0x300) * 4); 123 124 enum dc_disp_h_pulse_pos { 125 H_PULSE0_POSITION_A, 126 H_PULSE0_POSITION_B, 127 H_PULSE0_POSITION_C, 128 H_PULSE0_POSITION_D, 129 H_PULSE0_POSITION_COUNT, 130 }; 131 132 struct _disp_h_pulse { 133 /* _DISP_H_PULSE0/1/2_CONTROL_0 */ 134 u32 h_pulse_ctrl; 135 /* _DISP_H_PULSE0/1/2_POSITION_A/B/C/D_0 */ 136 u32 h_pulse_pos[H_PULSE0_POSITION_COUNT]; 137 }; 138 139 enum dc_disp_v_pulse_pos { 140 V_PULSE0_POSITION_A, 141 V_PULSE0_POSITION_B, 142 V_PULSE0_POSITION_C, 143 V_PULSE0_POSITION_COUNT, 144 }; 145 146 struct _disp_v_pulse0 { 147 /* _DISP_H_PULSE0/1_CONTROL_0 */ 148 u32 v_pulse_ctrl; 149 /* _DISP_H_PULSE0/1_POSITION_A/B/C_0 */ 150 u32 v_pulse_pos[V_PULSE0_POSITION_COUNT]; 151 }; 152 153 struct _disp_v_pulse2 { 154 /* _DISP_H_PULSE2/3_CONTROL_0 */ 155 u32 v_pulse_ctrl; 156 /* _DISP_H_PULSE2/3_POSITION_A_0 */ 157 u32 v_pulse_pos_a; 158 }; 159 160 enum dc_disp_h_pulse_reg { 161 H_PULSE0, 162 H_PULSE1, 163 H_PULSE2, 164 H_PULSE_COUNT, 165 }; 166 167 enum dc_disp_pp_select { 168 PP_SELECT_A, 169 PP_SELECT_B, 170 PP_SELECT_C, 171 PP_SELECT_D, 172 PP_SELECT_COUNT, 173 }; 174 175 /* DISP register 0x400 ~ 0x4c1 */ 176 struct dc_disp_reg { 177 /* Address 0x400 ~ 0x40a */ 178 u32 disp_signal_opt0; /* _DISP_DISP_SIGNAL_OPTIONS0_0 */ 179 u32 rsvd_401; 180 u32 disp_win_opt; /* _DISP_DISP_WIN_OPTIONS_0 */ 181 u32 rsvd_403[2]; /* 403 - 404 */ 182 u32 disp_timing_opt; /* _DISP_DISP_TIMING_OPTIONS_0 */ 183 u32 ref_to_sync; /* _DISP_REF_TO_SYNC_0 */ 184 u32 sync_width; /* _DISP_SYNC_WIDTH_0 */ 185 u32 back_porch; /* _DISP_BACK_PORCH_0 */ 186 u32 disp_active; /* _DISP_DISP_ACTIVE_0 */ 187 u32 front_porch; /* _DISP_FRONT_PORCH_0 */ 188 189 /* Address 0x40b ~ 0x419: _DISP_H_PULSE0/1/2_ */ 190 struct _disp_h_pulse h_pulse[H_PULSE_COUNT]; 191 192 /* Address 0x41a ~ 0x421 */ 193 struct _disp_v_pulse0 v_pulse0; /* _DISP_V_PULSE0_ */ 194 struct _disp_v_pulse0 v_pulse1; /* _DISP_V_PULSE1_ */ 195 196 /* Address 0x422 ~ 0x425 */ 197 struct _disp_v_pulse2 v_pulse3; /* _DISP_V_PULSE2_ */ 198 struct _disp_v_pulse2 v_pulse4; /* _DISP_V_PULSE3_ */ 199 200 u32 rsvd_426[8]; /* 426 - 42d */ 201 202 /* Address 0x42e ~ 0x430 */ 203 u32 disp_clk_ctrl; /* _DISP_DISP_CLOCK_CONTROL_0 */ 204 u32 disp_interface_ctrl; /* _DISP_DISP_INTERFACE_CONTROL_0 */ 205 u32 disp_color_ctrl; /* _DISP_DISP_COLOR_CONTROL_0 */ 206 207 u32 rsvd_431[6]; /* 431 - 436 */ 208 209 /* Address 0x437 ~ 0x439 */ 210 u32 color_key0_upper; /* _DISP_COLOR_KEY0_UPPER_0 */ 211 u32 color_key1_lower; /* _DISP_COLOR_KEY1_LOWER_0 */ 212 u32 color_key1_upper; /* _DISP_COLOR_KEY1_UPPER_0 */ 213 214 u32 reserved0[2]; /* 43a - 43b */ 215 216 /* Address 0x43c ~ 0x441 */ 217 u32 cursor_foreground; /* _DISP_CURSOR_FOREGROUND_0 */ 218 u32 cursor_background; /* _DISP_CURSOR_BACKGROUND_0 */ 219 u32 cursor_start_addr; /* _DISP_CURSOR_START_ADDR_0 */ 220 u32 cursor_start_addr_ns; /* _DISP_CURSOR_START_ADDR_NS_0 */ 221 u32 cursor_pos; /* _DISP_CURSOR_POSITION_0 */ 222 u32 cursor_pos_ns; /* _DISP_CURSOR_POSITION_NS_0 */ 223 224 u32 rsvd_442[62]; /* 442 - 47f */ 225 226 /* Address 0x480 ~ 0x483 */ 227 u32 dc_mccif_fifoctrl; /* _DISP_DC_MCCIF_FIFOCTRL_0 */ 228 u32 mccif_disp0a_hyst; /* _DISP_MCCIF_DISPLAY0A_HYST_0 */ 229 u32 mccif_disp0b_hyst; /* _DISP_MCCIF_DISPLAY0B_HYST_0 */ 230 u32 mccif_disp0c_hyst; /* _DISP_MCCIF_DISPLAY0C_HYST_0 */ 231 232 u32 rsvd_484[61]; /* 484 - 4c0 */ 233 234 /* Address 0x4c1 */ 235 u32 disp_misc_ctrl; /* _DISP_DISP_MISC_CONTROL_0 */ 236 237 u32 rsvd_4c2[34]; /* 4c2 - 4e3 */ 238 239 /* Address 0x4e4 */ 240 u32 blend_background_color; /* _DISP_BLEND_BACKGROUND_COLOR_0 */ 241 }; 242 check_member(dc_disp_reg, blend_background_color, (0x4e4 - 0x400) * 4); 243 244 enum dc_winc_filter_p { 245 WINC_FILTER_COUNT = 0x10, 246 }; 247 248 /* Window A/B/C register 0x500 ~ 0x628 */ 249 struct dc_winc_reg { 250 /* Address 0x500 */ 251 u32 color_palette; /* _WINC_COLOR_PALETTE_0 */ 252 253 u32 reserved0[0xff]; /* reserved_0[0xff] */ 254 255 /* Address 0x600 */ 256 u32 palette_color_ext; /* _WINC_PALETTE_COLOR_EXT_0 */ 257 258 /* _WINC_H_FILTER_P00~0F_0 */ 259 /* Address 0x601 ~ 0x610 */ 260 u32 h_filter_p[WINC_FILTER_COUNT]; 261 262 /* Address 0x611 ~ 0x618 */ 263 u32 csc_yof; /* _WINC_CSC_YOF_0 */ 264 u32 csc_kyrgb; /* _WINC_CSC_KYRGB_0 */ 265 u32 csc_kur; /* _WINC_CSC_KUR_0 */ 266 u32 csc_kvr; /* _WINC_CSC_KVR_0 */ 267 u32 csc_kug; /* _WINC_CSC_KUG_0 */ 268 u32 csc_kvg; /* _WINC_CSC_KVG_0 */ 269 u32 csc_kub; /* _WINC_CSC_KUB_0 */ 270 u32 csc_kvb; /* _WINC_CSC_KVB_0 */ 271 272 /* Address 0x619 ~ 0x628: _WINC_V_FILTER_P00~0F_0 */ 273 u32 v_filter_p[WINC_FILTER_COUNT]; 274 }; 275 check_member(dc_winc_reg, v_filter_p, (0x619 - 0x500) * 4); 276 277 /* WIN A/B/C Register 0x700 ~ 0x719*/ 278 struct dc_win_reg { 279 /* Address 0x700 ~ 0x719 */ 280 u32 win_opt; /* _WIN_WIN_OPTIONS_0 */ 281 u32 byte_swap; /* _WIN_BYTE_SWAP_0 */ 282 u32 buffer_ctrl; /* _WIN_BUFFER_CONTROL_0 */ 283 u32 color_depth; /* _WIN_COLOR_DEPTH_0 */ 284 u32 pos; /* _WIN_POSITION_0 */ 285 u32 size; /* _WIN_SIZE_0 */ 286 u32 prescaled_size; /* _WIN_PRESCALED_SIZE_0 */ 287 u32 h_initial_dda; /* _WIN_H_INITIAL_DDA_0 */ 288 u32 v_initial_dda; /* _WIN_V_INITIAL_DDA_0 */ 289 u32 dda_increment; /* _WIN_DDA_INCREMENT_0 */ 290 u32 line_stride; /* _WIN_LINE_STRIDE_0 */ 291 u32 buf_stride; /* _WIN_BUF_STRIDE_0 */ 292 u32 uv_buf_stride; /* _WIN_UV_BUF_STRIDE_0 */ 293 u32 buffer_addr_mode; /* _WIN_BUFFER_ADDR_MODE_0 */ 294 u32 dv_ctrl; /* _WIN_DV_CONTROL_0 */ 295 u32 blend_nokey; /* _WIN_BLEND_NOKEY_0 */ 296 u32 blend_1win; /* _WIN_BLEND_1WIN_0 */ 297 u32 blend_2win_x; /* _WIN_BLEND_2WIN_X_0 */ 298 u32 blend_2win_y; /* _WIN_BLEND_2WIN_Y_0 */ 299 u32 blend_3win_xy; /* _WIN_BLEND_3WIN_XY_0 */ 300 u32 hp_fetch_ctrl; /* _WIN_HP_FETCH_CONTROL_0 */ 301 u32 global_alpha; /* _WIN_GLOBAL_ALPHA */ 302 u32 blend_layer_ctrl; /* _WINBUF_BLEND_LAYER_CONTROL_0 */ 303 u32 blend_match_select; /* _WINBUF_BLEND_MATCH_SELECT_0 */ 304 u32 blend_nomatch_select; /* _WINBUF_BLEND_NOMATCH_SELECT_0 */ 305 u32 blend_alpha_1bit; /* _WINBUF_BLEND_ALPHA_1BIT_0 */ 306 }; 307 check_member(dc_win_reg, blend_alpha_1bit, (0x719 - 0x700) * 4); 308 309 /* WINBUF A/B/C Register 0x800 ~ 0x80d */ 310 struct dc_winbuf_reg { 311 /* Address 0x800 ~ 0x80d */ 312 u32 start_addr; /* _WINBUF_START_ADDR_0 */ 313 u32 start_addr_ns; /* _WINBUF_START_ADDR_NS_0 */ 314 u32 start_addr_u; /* _WINBUF_START_ADDR_U_0 */ 315 u32 start_addr_u_ns; /* _WINBUF_START_ADDR_U_NS_0 */ 316 u32 start_addr_v; /* _WINBUF_START_ADDR_V_0 */ 317 u32 start_addr_v_ns; /* _WINBUF_START_ADDR_V_NS_0 */ 318 u32 addr_h_offset; /* _WINBUF_ADDR_H_OFFSET_0 */ 319 u32 addr_h_offset_ns; /* _WINBUF_ADDR_H_OFFSET_NS_0 */ 320 u32 addr_v_offset; /* _WINBUF_ADDR_V_OFFSET_0 */ 321 u32 addr_v_offset_ns; /* _WINBUF_ADDR_V_OFFSET_NS_0 */ 322 u32 uflow_status; /* _WINBUF_UFLOW_STATUS_0 */ 323 u32 buffer_surface_kind; /* DC_WIN_BUFFER_SURFACE_KIND */ 324 u32 rsvd_80c; 325 u32 start_addr_hi; /* DC_WINBUF_START_ADDR_HI_0 */ 326 }; 327 check_member(dc_winbuf_reg, start_addr_hi, (0x80d - 0x800) * 4); 328 329 /* Display Controller (DC_) regs */ 330 struct display_controller { 331 struct dc_cmd_reg cmd; /* CMD register 0x000 ~ 0x43 */ 332 u32 reserved0[0x2bc]; 333 334 struct dc_com_reg com; /* COM register 0x300 ~ 0x329 */ 335 u32 reserved1[0xd6]; 336 337 struct dc_disp_reg disp; /* DISP register 0x400 ~ 0x4e4 */ 338 u32 reserved2[0x1b]; 339 340 struct dc_winc_reg winc; /* Window A/B/C 0x500 ~ 0x628 */ 341 u32 reserved3[0xd7]; 342 343 struct dc_win_reg win; /* WIN A/B/C 0x700 ~ 0x719*/ 344 u32 reserved4[0xe6]; 345 346 struct dc_winbuf_reg winbuf; /* WINBUF A/B/C 0x800 ~ 0x80d */ 347 }; 348 check_member(display_controller, winbuf, 0x800 * 4); 349 350 /* DC_CMD_DISPLAY_COMMAND 0x032 */ 351 #define DISP_COMMAND_RAISE (1 << 0) 352 #define DISP_CTRL_MODE_STOP (0 << 5) 353 #define DISP_CTRL_MODE_C_DISPLAY (1 << 5) 354 #define DISP_CTRL_MODE_NC_DISPLAY (2 << 5) 355 #define DISP_COMMAND_RAISE_VECTOR(x) (((x) & 0x1f) << 22) 356 #define DISP_COMMAND_RAISE_CHANNEL_ID(x) (((x) & 0xf) << 27) 357 358 /* DC_CMD_DISPLAY_POWER_CONTROL 0x036 */ 359 #define PW0_ENABLE BIT(0) 360 #define PW1_ENABLE BIT(2) 361 #define PW2_ENABLE BIT(4) 362 #define PW3_ENABLE BIT(6) 363 #define PW4_ENABLE BIT(8) 364 #define PM0_ENABLE BIT(16) 365 #define PM1_ENABLE BIT(18) 366 #define SPI_ENABLE BIT(24) 367 #define HSPI_ENABLE BIT(25) 368 369 /* DC_CMD_STATE_ACCESS 0x040 */ 370 #define READ_MUX_ASSEMBLY (0 << 0) 371 #define READ_MUX_ACTIVE (1 << 0) 372 #define WRITE_MUX_ASSEMBLY (0 << 2) 373 #define WRITE_MUX_ACTIVE (1 << 2) 374 375 /* DC_CMD_STATE_CONTROL 0x041 */ 376 #define GENERAL_ACT_REQ BIT(0) 377 #define WIN_A_ACT_REQ BIT(1) 378 #define WIN_B_ACT_REQ BIT(2) 379 #define WIN_C_ACT_REQ BIT(3) 380 #define WIN_D_ACT_REQ BIT(4) 381 #define WIN_H_ACT_REQ BIT(5) 382 #define CURSOR_ACT_REQ BIT(7) 383 #define GENERAL_UPDATE BIT(8) 384 #define WIN_A_UPDATE BIT(9) 385 #define WIN_B_UPDATE BIT(10) 386 #define WIN_C_UPDATE BIT(11) 387 #define WIN_D_UPDATE BIT(12) 388 #define WIN_H_UPDATE BIT(13) 389 #define CURSOR_UPDATE BIT(15) 390 #define NC_HOST_TRIG BIT(24) 391 392 /* DC_CMD_DISPLAY_WINDOW_HEADER 0x042 */ 393 #define WINDOW_A_SELECT BIT(4) 394 #define WINDOW_B_SELECT BIT(5) 395 #define WINDOW_C_SELECT BIT(6) 396 #define WINDOW_D_SELECT BIT(7) 397 #define WINDOW_H_SELECT BIT(8) 398 399 /* DC_DISP_DISP_WIN_OPTIONS 0x402 */ 400 #define CURSOR_ENABLE BIT(16) 401 #define SOR_ENABLE BIT(25) 402 #define TVO_ENABLE BIT(28) 403 #define DSI_ENABLE BIT(29) 404 #define HDMI_ENABLE BIT(30) 405 406 /* DC_DISP_DISP_TIMING_OPTIONS 0x405 */ 407 #define VSYNC_H_POSITION(x) ((x) & 0xfff) 408 409 /* DC_DISP_DISP_CLOCK_CONTROL 0x42e */ 410 #define SHIFT_CLK_DIVIDER_SHIFT 0 411 #define SHIFT_CLK_DIVIDER_MASK (0xff << SHIFT_CLK_DIVIDER_SHIFT) 412 #define PIXEL_CLK_DIVIDER_SHIFT 8 413 #define PIXEL_CLK_DIVIDER_MSK (0xf << PIXEL_CLK_DIVIDER_SHIFT) 414 enum { 415 PIXEL_CLK_DIVIDER_PCD1, 416 PIXEL_CLK_DIVIDER_PCD1H, 417 PIXEL_CLK_DIVIDER_PCD2, 418 PIXEL_CLK_DIVIDER_PCD3, 419 PIXEL_CLK_DIVIDER_PCD4, 420 PIXEL_CLK_DIVIDER_PCD6, 421 PIXEL_CLK_DIVIDER_PCD8, 422 PIXEL_CLK_DIVIDER_PCD9, 423 PIXEL_CLK_DIVIDER_PCD12, 424 PIXEL_CLK_DIVIDER_PCD16, 425 PIXEL_CLK_DIVIDER_PCD18, 426 PIXEL_CLK_DIVIDER_PCD24, 427 PIXEL_CLK_DIVIDER_PCD13, 428 }; 429 #define SHIFT_CLK_DIVIDER(x) (((x) - 1) * 2) 430 431 /* DC_WIN_WIN_OPTIONS 0x700 */ 432 #define H_DIRECTION_DECREMENT(x) ((x) << 0) 433 #define V_DIRECTION_DECREMENT(x) ((x) << 2) 434 #define WIN_SCAN_COLUMN BIT(4) 435 #define COLOR_EXPAND BIT(6) 436 #define H_FILTER_ENABLE(x) ((x) << 8) 437 #define V_FILTER_ENABLE(x) ((x) << 10) 438 #define CP_ENABLE BIT(16) 439 #define CSC_ENABLE BIT(18) 440 #define DV_ENABLE BIT(20) 441 #define INTERLACE_ENABLE BIT(23) 442 #define INTERLACE_DISABLE (0 << 23) 443 #define WIN_ENABLE BIT(30) 444 445 /* _WIN_COLOR_DEPTH_0 0x703 */ 446 enum { 447 COLOR_DEPTH_P8 = 3, 448 COLOR_DEPTH_B4G4R4A4, 449 COLOR_DEPTH_B5G5R5A, 450 COLOR_DEPTH_B5G6R5, 451 COLOR_DEPTH_AB5G5R5, 452 COLOR_DEPTH_B8G8R8A8 = 12, 453 COLOR_DEPTH_R8G8B8A8, 454 COLOR_DEPTH_YCbCr422 = 16, 455 COLOR_DEPTH_YUV422, 456 COLOR_DEPTH_YCbCr420P, 457 COLOR_DEPTH_YUV420P, 458 COLOR_DEPTH_YCbCr422P, 459 COLOR_DEPTH_YUV422P, 460 COLOR_DEPTH_N422R, 461 COLOR_DEPTH_YCbCr422R = COLOR_DEPTH_N422R, 462 COLOR_DEPTH_N422R_TRUE, 463 COLOR_DEPTH_YUV422R = COLOR_DEPTH_N422R_TRUE, 464 COLOR_DEPTH_CrYCbY422, 465 COLOR_DEPTH_VYUY422, 466 }; 467 468 /* DC_WIN_DDA_INCREMENT 0x709 */ 469 #define DDA_INC(prescaled_size, post_scaled_size) \ 470 (((prescaled_size) - 1) * 0x1000 / ((post_scaled_size) - 1)) 471 #define H_DDA_INC(x) (((x) & 0xffff) << 0) 472 #define V_DDA_INC(x) (((x) & 0xffff) << 16) 473 474 struct tegra_dc { 475 void *config; 476 void *out; 477 void *base; 478 }; 479 480 struct tegra_dc_mode { 481 int pclk; 482 int rated_pclk; 483 int h_ref_to_sync; 484 int v_ref_to_sync; 485 int h_sync_width; 486 int v_sync_width; 487 int h_back_porch; 488 int v_back_porch; 489 int h_active; 490 int v_active; 491 int h_front_porch; 492 int v_front_porch; 493 int stereo_mode; 494 u32 flags; 495 u8 avi_m; 496 u32 vmode; 497 }; 498 499 unsigned long READL(void *p); 500 void WRITEL(unsigned long value, void *p); 501 502 void display_startup(struct device *dev); 503 void dp_init(void *_config); 504 void dp_enable(void *_dp); 505 unsigned int fb_base_mb(void); 506 507 #endif /* __SOC_NVIDIA_TEGRA_DC_H */ 508