1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef QCOM_PHY_QMP_H_ 4 #define QCOM_PHY_QMP_H_ 5 6 /* Only for QMP V4 PHY - QSERDES COM registers */ 7 #define QSERDES_V4_COM_SSC_EN_CENTER 0x010 8 #define QSERDES_V4_COM_SSC_PER1 0x01c 9 #define QSERDES_V4_COM_SSC_PER2 0x020 10 #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0 0x024 11 #define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0 0x028 12 #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1 0x030 13 #define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1 0x034 14 #define QSERDES_V4_COM_CLK_ENABLE1 0x048 15 #define QSERDES_V4_COM_SYSCLK_BUF_ENABLE 0x050 16 #define QSERDES_V4_COM_PLL_IVCO 0x058 17 #define QSERDES_V4_COM_CMN_IPTRIM 0x060 18 #define QSERDES_V4_COM_CP_CTRL_MODE0 0x074 19 #define QSERDES_V4_COM_CP_CTRL_MODE1 0x078 20 #define QSERDES_V4_COM_PLL_RCTRL_MODE0 0x07c 21 #define QSERDES_V4_COM_PLL_RCTRL_MODE1 0x080 22 #define QSERDES_V4_COM_PLL_CCTRL_MODE0 0x084 23 #define QSERDES_V4_COM_PLL_CCTRL_MODE1 0x088 24 #define QSERDES_V4_COM_SYSCLK_EN_SEL 0x094 25 #define QSERDES_V4_COM_LOCK_CMP_EN 0x0a4 26 #define QSERDES_V4_COM_LOCK_CMP1_MODE0 0x0ac 27 #define QSERDES_V4_COM_LOCK_CMP2_MODE0 0x0b0 28 #define QSERDES_V4_COM_LOCK_CMP1_MODE1 0x0b4 29 #define QSERDES_V4_COM_DEC_START_MODE0 0x0bc 30 #define QSERDES_V4_COM_LOCK_CMP2_MODE1 0x0b8 31 #define QSERDES_V4_COM_DEC_START_MODE1 0x0c4 32 #define QSERDES_V4_COM_DIV_FRAC_START1_MODE0 0x0cc 33 #define QSERDES_V4_COM_DIV_FRAC_START2_MODE0 0x0d0 34 #define QSERDES_V4_COM_DIV_FRAC_START3_MODE0 0x0d4 35 #define QSERDES_V4_COM_DIV_FRAC_START1_MODE1 0x0d8 36 #define QSERDES_V4_COM_DIV_FRAC_START2_MODE1 0x0dc 37 #define QSERDES_V4_COM_DIV_FRAC_START3_MODE1 0x0e0 38 #define QSERDES_V4_COM_VCO_TUNE_MAP 0x10c 39 #define QSERDES_V4_COM_VCO_TUNE1_MODE0 0x110 40 #define QSERDES_V4_COM_VCO_TUNE2_MODE0 0x114 41 #define QSERDES_V4_COM_VCO_TUNE1_MODE1 0x118 42 #define QSERDES_V4_COM_VCO_TUNE2_MODE1 0x11c 43 #define QSERDES_V4_COM_VCO_TUNE_INITVAL2 0x124 44 #define QSERDES_V4_COM_CLK_SELECT 0x154 45 #define QSERDES_V4_COM_HSCLK_SEL 0x158 46 #define QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL 0x15c 47 #define QSERDES_V4_COM_CORECLK_DIV_MODE1 0x16c 48 #define QSERDES_V4_COM_SVS_MODE_CLK_SEL 0x184 49 #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac 50 #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 51 #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 52 #define QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc 53 #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 54 55 /* Only for QMP V4 PHY - TX registers */ 56 #define QSERDES_V4_TX_RES_CODE_LANE_TX 0x34 57 #define QSERDES_V4_TX_RES_CODE_LANE_RX 0x38 58 #define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX 0x3c 59 #define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX 0x40 60 #define QSERDES_V4_TX_LANE_MODE_1 0x84 61 #define QSERDES_V4_TX_LANE_MODE_2 0x88 62 #define QSERDES_V4_TX_RCV_DETECT_LVL_2 0x9c 63 #define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0xd8 64 #define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0xdC 65 #define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0xe0 66 #define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0xe4 67 #define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0xb8 68 #define QSERDES_V4_TX_PI_QEC_CTRL 0x104 69 70 /* Only for QMP V4 PHY - RX registers */ 71 #define QSERDES_V4_RX_UCDR_FO_GAIN 0x008 72 #define QSERDES_V4_RX_UCDR_SO_GAIN 0x014 73 #define QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN 0x030 74 #define QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 75 #define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 76 #define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 77 #define QSERDES_V4_RX_UCDR_PI_CONTROLS 0x044 78 #define QSERDES_V4_RX_UCDR_PI_CTRL2 0x048 79 #define QSERDES_V4_RX_UCDR_SB2_THRESH1 0x04c 80 #define QSERDES_V4_RX_UCDR_SB2_THRESH2 0x050 81 #define QSERDES_V4_RX_UCDR_SB2_GAIN1 0x054 82 #define QSERDES_V4_RX_UCDR_SB2_GAIN2 0x058 83 #define QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE 0x060 84 #define QSERDES_V4_RX_RCLK_AUXDATA_SEL 0x064 85 #define QSERDES_V4_RX_AC_JTAG_ENABLE 0x068 86 #define QSERDES_V4_RX_AC_JTAG_MODE 0x078 87 #define QSERDES_V4_RX_RX_TERM_BW 0x080 88 #define QSERDES_V4_RX_VGA_CAL_CNTRL1 0x0d4 89 #define QSERDES_V4_RX_VGA_CAL_CNTRL2 0x0d8 90 #define QSERDES_V4_RX_GM_CAL 0x0dc 91 #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8 92 #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec 93 #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 94 #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 95 #define QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW 0x0f8 96 #define QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH 0x0fc 97 #define QSERDES_V4_RX_RX_IDAC_MEASURE_TIME 0x100 98 #define QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 99 #define QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 100 #define QSERDES_V4_RX_SIGDET_ENABLES 0x118 101 #define QSERDES_V4_RX_SIGDET_CNTRL 0x11c 102 #define QSERDES_V4_RX_SIGDET_LVL 0x120 103 #define QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL 0x124 104 #define QSERDES_V4_RX_RX_BAND 0x128 105 #define QSERDES_V4_RX_RX_MODE_00_LOW 0x170 106 #define QSERDES_V4_RX_RX_MODE_00_HIGH 0x174 107 #define QSERDES_V4_RX_RX_MODE_00_HIGH2 0x178 108 #define QSERDES_V4_RX_RX_MODE_00_HIGH3 0x17c 109 #define QSERDES_V4_RX_RX_MODE_00_HIGH4 0x180 110 #define QSERDES_V4_RX_RX_MODE_01_LOW 0x184 111 #define QSERDES_V4_RX_RX_MODE_01_HIGH 0x188 112 #define QSERDES_V4_RX_RX_MODE_01_HIGH2 0x18c 113 #define QSERDES_V4_RX_RX_MODE_01_HIGH3 0x190 114 #define QSERDES_V4_RX_RX_MODE_01_HIGH4 0x194 115 #define QSERDES_V4_RX_RX_MODE_10_LOW 0x198 116 #define QSERDES_V4_RX_RX_MODE_10_HIGH 0x19c 117 #define QSERDES_V4_RX_RX_MODE_10_HIGH2 0x1a0 118 #define QSERDES_V4_RX_RX_MODE_10_HIGH3 0x1a4 119 #define QSERDES_V4_RX_RX_MODE_10_HIGH4 0x1a8 120 #define QSERDES_V4_RX_DFE_EN_TIMER 0x1b4 121 #define QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET 0x1b8 122 #define QSERDES_V4_RX_DCC_CTRL1 0x1bc 123 #define QSERDES_V4_RX_VTH_CODE 0x1c4 124 125 /* Only for QMP V4 PHY - PCIe PCS registers */ 126 #define QPHY_V4_PCS_SW_RESET 0x000 127 #define QPHY_V4_PCS_REVISION_ID0 0x004 128 #define QPHY_V4_PCS_REVISION_ID1 0x008 129 #define QPHY_V4_PCS_REVISION_ID2 0x00c 130 #define QPHY_V4_PCS_REVISION_ID3 0x010 131 #define QPHY_V4_PCS_PCS_STATUS1 0x014 132 #define QPHY_V4_PCS_PCS_STATUS2 0x018 133 #define QPHY_V4_PCS_PCS_STATUS3 0x01c 134 #define QPHY_V4_PCS_PCS_STATUS4 0x020 135 #define QPHY_V4_PCS_PCS_STATUS5 0x024 136 #define QPHY_V4_PCS_PCS_STATUS6 0x028 137 #define QPHY_V4_PCS_PCS_STATUS7 0x02c 138 #define QPHY_V4_PCS_DEBUG_BUS_0_STATUS 0x030 139 #define QPHY_V4_PCS_DEBUG_BUS_1_STATUS 0x034 140 #define QPHY_V4_PCS_DEBUG_BUS_2_STATUS 0x038 141 #define QPHY_V4_PCS_DEBUG_BUS_3_STATUS 0x03c 142 #define QPHY_V4_PCS_POWER_DOWN_CONTROL 0x040 143 #define QPHY_V4_PCS_START_CONTROL 0x044 144 #define QPHY_V4_PCS_INSIG_SW_CTRL1 0x048 145 #define QPHY_V4_PCS_INSIG_SW_CTRL2 0x04c 146 #define QPHY_V4_PCS_INSIG_SW_CTRL3 0x050 147 #define QPHY_V4_PCS_INSIG_SW_CTRL4 0x054 148 #define QPHY_V4_PCS_INSIG_SW_CTRL5 0x058 149 #define QPHY_V4_PCS_INSIG_SW_CTRL6 0x05c 150 #define QPHY_V4_PCS_INSIG_SW_CTRL7 0x060 151 #define QPHY_V4_PCS_INSIG_SW_CTRL8 0x064 152 #define QPHY_V4_PCS_INSIG_MX_CTRL1 0x068 153 #define QPHY_V4_PCS_INSIG_MX_CTRL2 0x06c 154 #define QPHY_V4_PCS_INSIG_MX_CTRL3 0x070 155 #define QPHY_V4_PCS_INSIG_MX_CTRL4 0x074 156 #define QPHY_V4_PCS_INSIG_MX_CTRL5 0x078 157 #define QPHY_V4_PCS_INSIG_MX_CTRL7 0x07c 158 #define QPHY_V4_PCS_INSIG_MX_CTRL8 0x080 159 #define QPHY_V4_PCS_OUTSIG_SW_CTRL1 0x084 160 #define QPHY_V4_PCS_OUTSIG_MX_CTRL1 0x088 161 #define QPHY_V4_PCS_CLAMP_ENABLE 0x08c 162 #define QPHY_V4_PCS_POWER_STATE_CONFIG1 0x090 163 #define QPHY_V4_PCS_POWER_STATE_CONFIG2 0x094 164 #define QPHY_V4_PCS_FLL_CNTRL1 0x098 165 #define QPHY_V4_PCS_FLL_CNTRL2 0x09c 166 #define QPHY_V4_PCS_FLL_CNT_VAL_L 0x0a0 167 #define QPHY_V4_PCS_FLL_CNT_VAL_H_TOL 0x0a4 168 #define QPHY_V4_PCS_FLL_MAN_CODE 0x0a8 169 #define QPHY_V4_PCS_TEST_CONTROL1 0x0ac 170 #define QPHY_V4_PCS_TEST_CONTROL2 0x0b0 171 #define QPHY_V4_PCS_TEST_CONTROL3 0x0b4 172 #define QPHY_V4_PCS_TEST_CONTROL4 0x0b8 173 #define QPHY_V4_PCS_TEST_CONTROL5 0x0bc 174 #define QPHY_V4_PCS_TEST_CONTROL6 0x0c0 175 #define QPHY_V4_PCS_LOCK_DETECT_CONFIG1 0x0c4 176 #define QPHY_V4_PCS_LOCK_DETECT_CONFIG2 0x0c8 177 #define QPHY_V4_PCS_LOCK_DETECT_CONFIG3 0x0cc 178 #define QPHY_V4_PCS_LOCK_DETECT_CONFIG4 0x0d0 179 #define QPHY_V4_PCS_LOCK_DETECT_CONFIG5 0x0d4 180 #define QPHY_V4_PCS_LOCK_DETECT_CONFIG6 0x0d8 181 #define QPHY_V4_PCS_REFGEN_REQ_CONFIG1 0x0dc 182 #define QPHY_V4_PCS_REFGEN_REQ_CONFIG2 0x0e0 183 #define QPHY_V4_PCS_REFGEN_REQ_CONFIG3 0x0e4 184 #define QPHY_V4_PCS_BIST_CTRL 0x0e8 185 #define QPHY_V4_PCS_PRBS_POLY0 0x0ec 186 #define QPHY_V4_PCS_PRBS_POLY1 0x0f0 187 #define QPHY_V4_PCS_FIXED_PAT0 0x0f4 188 #define QPHY_V4_PCS_FIXED_PAT1 0x0f8 189 #define QPHY_V4_PCS_FIXED_PAT2 0x0fc 190 #define QPHY_V4_PCS_FIXED_PAT3 0x100 191 #define QPHY_V4_PCS_FIXED_PAT4 0x104 192 #define QPHY_V4_PCS_FIXED_PAT5 0x108 193 #define QPHY_V4_PCS_FIXED_PAT6 0x10c 194 #define QPHY_V4_PCS_FIXED_PAT7 0x110 195 #define QPHY_V4_PCS_FIXED_PAT8 0x114 196 #define QPHY_V4_PCS_FIXED_PAT9 0x118 197 #define QPHY_V4_PCS_FIXED_PAT10 0x11c 198 #define QPHY_V4_PCS_FIXED_PAT11 0x120 199 #define QPHY_V4_PCS_FIXED_PAT12 0x124 200 #define QPHY_V4_PCS_FIXED_PAT13 0x128 201 #define QPHY_V4_PCS_FIXED_PAT14 0x12c 202 #define QPHY_V4_PCS_FIXED_PAT15 0x130 203 #define QPHY_V4_PCS_TXMGN_CONFIG 0x134 204 #define QPHY_V4_PCS_G12S1_TXMGN_V0 0x138 205 #define QPHY_V4_PCS_G12S1_TXMGN_V1 0x13c 206 #define QPHY_V4_PCS_G12S1_TXMGN_V2 0x140 207 #define QPHY_V4_PCS_G12S1_TXMGN_V3 0x144 208 #define QPHY_V4_PCS_G12S1_TXMGN_V4 0x148 209 #define QPHY_V4_PCS_G12S1_TXMGN_V0_RS 0x14c 210 #define QPHY_V4_PCS_G12S1_TXMGN_V1_RS 0x150 211 #define QPHY_V4_PCS_G12S1_TXMGN_V2_RS 0x154 212 #define QPHY_V4_PCS_G12S1_TXMGN_V3_RS 0x158 213 #define QPHY_V4_PCS_G12S1_TXMGN_V4_RS 0x15c 214 #define QPHY_V4_PCS_G3S2_TXMGN_MAIN 0x160 215 #define QPHY_V4_PCS_G3S2_TXMGN_MAIN_RS 0x164 216 #define QPHY_V4_PCS_G12S1_TXDEEMPH_M6DB 0x168 217 #define QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB 0x16c 218 #define QPHY_V4_PCS_G3S2_PRE_GAIN 0x170 219 #define QPHY_V4_PCS_G3S2_POST_GAIN 0x174 220 #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET 0x178 221 #define QPHY_V4_PCS_G3S2_PRE_GAIN_RS 0x17c 222 #define QPHY_V4_PCS_G3S2_POST_GAIN_RS 0x180 223 #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET_RS 0x184 224 #define QPHY_V4_PCS_RX_SIGDET_LVL 0x188 225 #define QPHY_V4_PCS_RX_SIGDET_DTCT_CNTRL 0x18c 226 #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 227 #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 228 #define QPHY_V4_PCS_RATE_SLEW_CNTRL1 0x198 229 #define QPHY_V4_PCS_RATE_SLEW_CNTRL2 0x19c 230 #define QPHY_V4_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1a0 231 #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4 232 #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8 233 #define QPHY_V4_PCS_TSYNC_RSYNC_TIME 0x1ac 234 #define QPHY_V4_PCS_CDR_RESET_TIME 0x1b0 235 #define QPHY_V4_PCS_TSYNC_DLY_TIME 0x1b4 236 #define QPHY_V4_PCS_ELECIDLE_DLY_SEL 0x1b8 237 #define QPHY_V4_PCS_CMN_ACK_OUT_SEL 0x1bc 238 #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG1 0x1c0 239 #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG2 0x1c4 240 #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG3 0x1c8 241 #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG4 0x1cc 242 #define QPHY_V4_PCS_PCS_TX_RX_CONFIG 0x1d0 243 #define QPHY_V4_PCS_RX_IDLE_DTCT_CNTRL 0x1d4 244 #define QPHY_V4_PCS_RX_DCC_CAL_CONFIG 0x1d8 245 #define QPHY_V4_PCS_EQ_CONFIG1 0x1dc 246 #define QPHY_V4_PCS_EQ_CONFIG2 0x1e0 247 #define QPHY_V4_PCS_EQ_CONFIG3 0x1e4 248 #define QPHY_V4_PCS_EQ_CONFIG4 0x1e8 249 #define QPHY_V4_PCS_EQ_CONFIG5 0x1ec 250 251 /* Only for QMP V4 PHY - PCS_MISC registers */ 252 #define QPHY_V4_PCS_MISC_TYPEC_CTRL 0x00 253 #define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL 0x04 254 #define QPHY_V4_PCS_MISC_PCS_MISC_CONFIG1 0x08 255 #define QPHY_V4_PCS_MISC_CLAMP_ENABLE 0x0c 256 #define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10 257 #define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14 258 259 /* Only for QMP V4 PHY - PCS_PCIE registers */ 260 #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2 0x0c 261 #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4 0x14 262 #define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x1c 263 #define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x40 264 #define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x48 265 #define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x50 266 #define QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS 0x90 267 #define QPHY_V4_PCS_PCIE_EQ_CONFIG2 0xa4 268 #define QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE 0xb4 269 #define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc 270 #define QPHY_V4_PCS_PCIE_PRESET_P10_POST 0xe0 271 272 #endif 273