1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef _ROCKCHIP_LCD_H_ 4 #define _ROCKCHIP_LCD_H_ 5 #include <stdint.h> 6 #include <edid.h> 7 8 struct rockchip_vop_regs { 9 u32 reg_cfg_done; 10 u32 version_info; 11 u32 sys_ctrl; 12 u32 sys_ctrl1; 13 u32 dsp_ctrl0; 14 u32 dsp_ctrl1; 15 u32 dsp_bg; 16 u32 mcu_ctrl; 17 union { 18 u32 intr_ctrl0; /* RK3288 */ 19 u32 wb_ctrl0; /* RK3399 */ 20 }; 21 union { 22 u32 intr_ctrl1; /* RK3288 */ 23 u32 wb_ctrl1; /* RK3399 */ 24 }; 25 union { 26 u32 intr_reserved0; /* RK3288 */ 27 u32 wb_yrgb_mst; /* RK3399 */ 28 }; 29 union { 30 u32 intr_reserved1; /* RK3288 */ 31 u32 wb_cbr_mst; /* RK3399 */ 32 }; 33 u32 win0_ctrl0; 34 u32 win0_ctrl1; 35 u32 win0_color_key; 36 u32 win0_vir; 37 u32 win0_yrgb_mst; 38 u32 win0_cbr_mst; 39 u32 win0_act_info; 40 u32 win0_dsp_info; 41 u32 win0_dsp_st; 42 u32 win0_scl_factor_yrgb; 43 u32 win0_scl_factor_cbr; 44 u32 win0_scl_offset; 45 u32 win0_src_alpha_ctrl; 46 u32 win0_dst_alpha_ctrl; 47 u32 win0_fading_ctrl; 48 union { 49 u32 win0_reserved0; /* RK3288 */ 50 u32 win0_ctrl2; /* RK3399 */ 51 }; 52 u32 win1_ctrl0; 53 u32 win1_ctrl1; 54 u32 win1_color_key; 55 u32 win1_vir; 56 u32 win1_yrgb_mst; 57 u32 win1_cbr_mst; 58 u32 win1_act_info; 59 u32 win1_dsp_info; 60 u32 win1_dsp_st; 61 u32 win1_scl_factor_yrgb; 62 u32 win1_scl_factor_cbr; 63 u32 win1_scl_offset; 64 u32 win1_src_alpha_ctrl; 65 u32 win1_dst_alpha_ctrl; 66 u32 win1_fading_ctrl; 67 union { 68 u32 win1_reservd0; /* RK3288 */ 69 u32 win1_ctrl2; /* RK3399 */ 70 }; 71 u32 reserved2[48]; 72 u32 post_dsp_hact_info; 73 u32 post_dsp_vact_info; 74 u32 post_scl_factor_yrgb; 75 u32 post_reserved; 76 u32 post_scl_ctrl; 77 u32 post_dsp_vact_info_f1; 78 u32 dsp_htotal_hs_end; 79 u32 dsp_hact_st_end; 80 u32 dsp_vtotal_vs_end; 81 u32 dsp_vact_st_end; 82 u32 dsp_vs_st_end_f1; 83 u32 dsp_vact_st_end_f1; 84 }; 85 check_member(rockchip_vop_regs, dsp_vact_st_end_f1, 0x19c); 86 87 enum rockchip_fb_data_format_t { 88 ARGB8888 = 0, 89 RGB888 = 1, 90 RGB565 = 2, 91 }; 92 93 enum { 94 LB_YUV_3840X5 = 0x0, 95 LB_YUV_2560X8 = 0x1, 96 LB_RGB_3840X2 = 0x2, 97 LB_RGB_2560X4 = 0x3, 98 LB_RGB_1920X5 = 0x4, 99 LB_RGB_1280X8 = 0x5 100 }; 101 102 enum vop_modes { 103 /* EDP == 0 is used for most RK3288 products and is the most likely 104 * use case for RK3399, so keep it as the default. Other desired 105 * modes should be set explicitly in the board's devicetree.cb. 106 */ 107 VOP_MODE_EDP = 0, 108 VOP_MODE_HDMI, 109 VOP_MODE_MIPI, 110 VOP_MODE_DUAL_MIPI, 111 VOP_MODE_NONE, 112 VOP_MODE_AUTO_DETECT, 113 VOP_MODE_UNKNOWN, 114 }; 115 116 /* VOP_VERSION_INFO */ 117 #define M_FPGA_VERSION (0xffff << 16) 118 #define M_RTL_VERSION (0xffff) 119 120 /* VOP_SYS_CTRL */ 121 #define M_AUTO_GATING_EN (1 << 23) 122 #define M_STANDBY_EN (1 << 22) 123 #define M_DMA_STOP (1 << 21) 124 #define M_MMU_EN (1 << 20) 125 #define M_DAM_BURST_LENGTH (0x3 << 18) 126 #define M_MIPI_OUT_EN (1 << 15) 127 #define M_EDP_OUT_EN (1 << 14) 128 #define M_HDMI_OUT_EN (1 << 13) 129 #define M_RGB_OUT_EN (1 << 12) 130 #define M_DUAL_MIPI_OUT_EN (1 << 3) 131 #define M_ALL_OUT_EN (M_MIPI_OUT_EN | M_EDP_OUT_EN | M_HDMI_OUT_EN |\ 132 M_RGB_OUT_EN | M_DUAL_MIPI_OUT_EN) 133 #define M_EDPI_WMS_FS (1 << 10) 134 #define M_EDPI_WMS_MODE (1 << 9) 135 #define M_EDPI_HALT_EN (1 << 8) 136 #define M_DOUB_CH_OVERLAP_NUM (0xf << 4) 137 #define M_DOUB_CHANNEL_EN (1 << 3) 138 #define M_DIRECT_PATH_LAYER_SEL (0x3 << 1) 139 #define M_DIRECT_PATH_EN (1) 140 141 #define V_AUTO_GATING_EN(x) (((x) & 1) << 23) 142 #define V_STANDBY_EN(x) (((x) & 1) << 22) 143 #define V_DMA_STOP(x) (((x) & 1) << 21) 144 #define V_MMU_EN(x) (((x) & 1) << 20) 145 #define V_DMA_BURST_LENGTH(x) (((x) & 3) << 18) 146 #define V_MIPI_OUT_EN(x) (((x) & 1) << 15) 147 #define V_DUAL_MIPI_EN(x) (((x) & 1) << 3) 148 #define V_EDP_OUT_EN(x) (((x) & 1) << 14) 149 #define V_HDMI_OUT_EN(x) (((x) & 1) << 13) 150 #define V_RGB_OUT_EN(x) (((x) & 1) << 12) 151 #define V_EDPI_WMS_FS(x) (((x) & 1) << 10) 152 #define V_EDPI_WMS_MODE(x) (((x) & 1) << 9) 153 #define V_EDPI_HALT_EN(x) (((x)&1)<<8) 154 #define V_DOUB_CH_OVERLAP_NUM(x) (((x) & 0xf) << 4) 155 #define V_DOUB_CHANNEL_EN(x) (((x) & 1) << 3) 156 #define V_DIRECT_PATH_LAYER_SEL(x) (((x) & 3) << 1) 157 #define V_DIRECT_PATH_EN(x) ((x) & 1) 158 159 /* VOP_SYS_CTRL1 */ 160 #define M_AXI_OUTSTANDING_MAX_NUM (0x1f << 13) 161 #define M_AXI_MAX_OUTSTANDING_EN (1 << 12) 162 #define M_NOC_WIN_QOS (3 << 10) 163 #define M_NOC_QOS_EN (1 << 9) 164 #define M_NOC_HURRY_THRESHOLD (0x3f << 3) 165 #define M_NOC_HURRY_VALUE (0x3 << 1) 166 #define M_NOC_HURRY_EN (1) 167 168 #define V_AXI_OUTSTANDING_MAX_NUM(x) (((x) & 0x1f) << 13) 169 #define V_AXI_MAX_OUTSTANDING_EN(x) (((x) & 1) << 12) 170 #define V_NOC_WIN_QOS(x) (((x) & 3) << 10) 171 #define V_NOC_QOS_EN(x) (((x) & 1) << 9) 172 #define V_NOC_HURRY_THRESHOLD(x) (((x) & 0x3f) << 3) 173 #define V_NOC_HURRY_VALUE(x) (((x) & 3) << 1) 174 #define V_NOC_HURRY_EN(x) ((x) & 1) 175 176 /* VOP_DSP_CTRL0 */ 177 #define M_DSP_Y_MIR_EN (1 << 23) 178 #define M_DSP_X_MIR_EN (1 << 22) 179 #define M_DSP_YUV_CLIP (1 << 21) 180 #define M_DSP_CCIR656_AVG (1 << 20) 181 #define M_DSP_BLACK_EN (1 << 19) 182 #define M_DSP_BLANK_EN (1 << 18) 183 #define M_DSP_OUT_ZERO (1 << 17) 184 #define M_DSP_DUMMY_SWAP (1 << 16) 185 #define M_DSP_DELTA_SWAP (1 << 15) 186 #define M_DSP_RG_SWAP (1 << 14) 187 #define M_DSP_RB_SWAP (1 << 13) 188 #define M_DSP_BG_SWAP (1 << 12) 189 #define M_DSP_FIELD_POL (1 << 11) 190 #define M_DSP_INTERLACE (1 << 10) 191 #define M_DSP_DDR_PHASE (1 << 9) 192 #define M_DSP_DCLK_DDR (1 << 8) 193 #define M_DSP_DCLK_POL (1 << 7) 194 #define M_DSP_DEN_POL (1 << 6) 195 #define M_DSP_VSYNC_POL (1 << 5) 196 #define M_DSP_HSYNC_POL (1 << 4) 197 #define M_DSP_OUT_MODE (0xf) 198 199 #define V_DSP_Y_MIR_EN(x) (((x) & 1) << 23) 200 #define V_DSP_X_MIR_EN(x) (((x) & 1) << 22) 201 #define V_DSP_YUV_CLIP(x) (((x) & 1) << 21) 202 #define V_DSP_CCIR656_AVG(x) (((x) & 1) << 20) 203 #define V_DSP_BLACK_EN(x) (((x) & 1) << 19) 204 #define V_DSP_BLANK_EN(x) (((x) & 1) << 18) 205 #define V_DSP_OUT_ZERO(x) (((x) & 1) << 17) 206 #define V_DSP_DUMMY_SWAP(x) (((x) & 1) << 16) 207 #define V_DSP_DELTA_SWAP(x) (((x) & 1) << 15) 208 #define V_DSP_RG_SWAP(x) (((x) & 1) << 14) 209 #define V_DSP_RB_SWAP(x) (((x) & 1) << 13) 210 #define V_DSP_BG_SWAP(x) (((x) & 1) << 12) 211 #define V_DSP_FIELD_POL(x) (((x) & 1) << 11) 212 #define V_DSP_INTERLACE(x) (((x) & 1) << 10) 213 #define V_DSP_DDR_PHASE(x) (((x) & 1) << 9) 214 #define V_DSP_DCLK_DDR(x) (((x) & 1) << 8) 215 #define V_DSP_DCLK_POL(x) (((x) & 1) << 7) 216 #define V_DSP_DEN_POL(x) (((x) & 1) << 6) 217 #define V_DSP_VSYNC_POL(x) (((x) & 1) << 5) 218 #define V_DSP_HSYNC_POL(x) (((x) & 1) << 4) 219 #define V_DSP_OUT_MODE(x) ((x) & 0xf) 220 221 /* VOP_DSP_CTRL1 */ 222 #define M_DSP_LAYER3_SEL (3 << 14) 223 #define M_DSP_LAYER2_SEL (3 << 12) 224 #define M_DSP_LAYER1_SEL (3 << 10) 225 #define M_DSP_LAYER0_SEL (3 << 8) 226 #define M_DITHER_UP_EN (1 << 6) 227 #define M_DITHER_DOWN_SEL (1 << 4) 228 #define M_DITHER_DOWN_MODE (1 << 3) 229 #define M_DITHER_DOWN_EN (1 << 2) 230 #define M_PRE_DITHER_DOWN_EN (1 << 1) 231 #define M_DSP_LUT_EN (1) 232 233 #define V_DSP_LAYER3_SEL(x) (((x) & 3) << 14) 234 #define V_DSP_LAYER2_SEL(x) (((x) & 3) << 12) 235 #define V_DSP_LAYER1_SEL(x) (((x) & 3) << 10) 236 #define V_DSP_LAYER0_SEL(x) (((x) & 3) << 8) 237 #define V_DITHER_UP_EN(x) (((x) & 1) << 6) 238 #define V_DITHER_DOWN_SEL(x) (((x) & 1) << 4) 239 #define V_DITHER_DOWN_MODE(x) (((x) & 1) << 3) 240 #define V_DITHER_DOWN_EN(x) (((x) & 1) << 2) 241 #define V_PRE_DITHER_DOWN_EN(x) (((x) & 1) << 1) 242 #define V_DSP_LUT_EN(x) ((x)&1) 243 244 /* VOP_DSP_BG */ 245 #define M_DSP_BG_RED (0x3f << 20) 246 #define M_DSP_BG_GREEN (0x3f << 10) 247 #define M_DSP_BG_BLUE (0x3f << 0) 248 249 #define V_DSP_BG_RED(x) (((x) & 0x3f) << 20) 250 #define V_DSP_BG_GREEN(x) (((x) & 0x3f) << 10) 251 #define V_DSP_BG_BLUE(x) (((x) & 0x3f) << 0) 252 253 /* VOP_WIN0_CTRL0 */ 254 #define M_WIN0_YUV_CLIP (1 << 20) 255 #define M_WIN0_CBR_DEFLICK (1 << 19) 256 #define M_WIN0_YRGB_DEFLICK (1 << 18) 257 #define M_WIN0_PPAS_ZERO_EN (1 << 16) 258 #define M_WIN0_UV_SWAP (1 << 15) 259 #define M_WIN0_MID_SWAP (1 << 14) 260 #define M_WIN0_ALPHA_SWAP (1 << 13) 261 #define M_WIN0_RB_SWAP (1 << 12) 262 #define M_WIN0_CSC_MODE (3 << 10) 263 #define M_WIN0_NO_OUTSTANDING (1 << 9) 264 #define M_WIN0_INTERLACE_READ (1 << 8) 265 #define M_WIN0_LB_MODE (7 << 5) 266 #define M_WIN0_FMT_10 (1 << 4) 267 #define M_WIN0_DATA_FMT (7 << 1) 268 #define M_WIN0_EN (1 << 0) 269 270 #define V_WIN0_YUV_CLIP(x) (((x) & 1) << 20) 271 #define V_WIN0_CBR_DEFLICK(x) (((x) & 1) << 19) 272 #define V_WIN0_YRGB_DEFLICK(x) (((x) & 1) << 18) 273 #define V_WIN0_PPAS_ZERO_EN(x) (((x) & 1) << 16) 274 #define V_WIN0_UV_SWAP(x) (((x) & 1) << 15) 275 #define V_WIN0_MID_SWAP(x) (((x) & 1) << 14) 276 #define V_WIN0_ALPHA_SWAP(x) (((x) & 1) << 13) 277 #define V_WIN0_RB_SWAP(x) (((x) & 1) << 12) 278 #define V_WIN0_CSC_MODE(x) (((x) & 3) << 10) 279 #define V_WIN0_NO_OUTSTANDING(x) (((x) & 1) << 9) 280 #define V_WIN0_INTERLACE_READ(x) (((x) & 1) << 8) 281 #define V_WIN0_LB_MODE(x) (((x) & 7) << 5) 282 #define V_WIN0_FMT_10(x) (((x) & 1) << 4) 283 #define V_WIN0_DATA_FMT(x) (((x) & 7) << 1) 284 #define V_WIN0_EN(x) ((x) & 1) 285 286 /* VOP_WIN0_CTRL1 */ 287 #define M_WIN0_CBR_VSD_MODE (1 << 31) 288 #define M_WIN0_CBR_VSU_MODE (1 << 30) 289 #define M_WIN0_CBR_HSD_MODE (3 << 28) 290 #define M_WIN0_CBR_VER_SCL_MODE (3 << 26) 291 #define M_WIN0_CBR_HOR_SCL_MODE (3 << 24) 292 #define M_WIN0_YRGB_VSD_MODE (1 << 23) 293 #define M_WIN0_YRGB_VSU_MODE (1 << 22) 294 #define M_WIN0_YRGB_HSD_MODE (3 << 20) 295 #define M_WIN0_YRGB_VER_SCL_MODE (3 << 18) 296 #define M_WIN0_YRGB_HOR_SCL_MODE (3 << 16) 297 #define M_WIN0_LINE_LOAD_MODE (1 << 15) 298 #define M_WIN0_CBR_AXI_GATHER_NUM (7 << 12) 299 #define M_WIN0_YRGB_AXI_GATHER_NUM (0xf << 8) 300 #define M_WIN0_VSD_CBR_GT2 (1 << 7) 301 #define M_WIN0_VSD_CBR_GT4 (1 << 6) 302 #define M_WIN0_VSD_YRGB_GT2 (1 << 5) 303 #define M_WIN0_VSD_YRGB_GT4 (1 << 4) 304 #define M_WIN0_BIC_COE_SEL (3 << 2) 305 #define M_WIN0_CBR_AXI_GATHER_EN (1 << 1) 306 #define M_WIN0_YRGB_AXI_GATHER_EN (1) 307 308 #define V_WIN0_CBR_VSD_MODE(x) (((x) & 1) << 31) 309 #define V_WIN0_CBR_VSU_MODE(x) (((x) & 1) << 30) 310 #define V_WIN0_CBR_HSD_MODE(x) (((x) & 3) << 28) 311 #define V_WIN0_CBR_VER_SCL_MODE(x) (((x) & 3) << 26) 312 #define V_WIN0_CBR_HOR_SCL_MODE(x) (((x) & 3) << 24) 313 #define V_WIN0_YRGB_VSD_MODE(x) (((x) & 1) << 23) 314 #define V_WIN0_YRGB_VSU_MODE(x) (((x) & 1) << 22) 315 #define V_WIN0_YRGB_HSD_MODE(x) (((x) & 3) << 20) 316 #define V_WIN0_YRGB_VER_SCL_MODE(x) (((x) & 3) << 18) 317 #define V_WIN0_YRGB_HOR_SCL_MODE(x) (((x) & 3) << 16) 318 #define V_WIN0_LINE_LOAD_MODE(x) (((x) & 1) << 15) 319 #define V_WIN0_CBR_AXI_GATHER_NUM(x) (((x) & 7) << 12) 320 #define V_WIN0_YRGB_AXI_GATHER_NUM(x) (((x) & 0xf) << 8) 321 #define V_WIN0_VSD_CBR_GT2(x) (((x) & 1) << 7) 322 #define V_WIN0_VSD_CBR_GT4(x) (((x) & 1) << 6) 323 #define V_WIN0_VSD_YRGB_GT2(x) (((x) & 1) << 5) 324 #define V_WIN0_VSD_YRGB_GT4(x) (((x) & 1) << 4) 325 #define V_WIN0_BIC_COE_SEL(x) (((x) & 3) << 2) 326 #define V_WIN0_CBR_AXI_GATHER_EN(x) (((x) & 1) << 1) 327 #define V_WIN0_YRGB_AXI_GATHER_EN(x) ((x) & 1) 328 329 /*VOP_WIN0_COLOR_KEY*/ 330 #define M_WIN0_KEY_EN (1 << 31) 331 #define M_WIN0_KEY_COLOR (0x3fffffff) 332 333 #define V_WIN0_KEY_EN(x) (((x) & 1) << 31) 334 #define V_WIN0_KEY_COLOR(x) ((x) & 0x3fffffff) 335 336 /* VOP_WIN0_VIR */ 337 #define V_ARGB888_VIRWIDTH(x) (((x) & 0x3fff) << 0) 338 #define V_RGB888_VIRWIDTH(x) (((((x * 3) >> 2)+((x) % 3)) & 0x3fff) << 0) 339 #define V_RGB565_VIRWIDTH(x) (((x / 2) & 0x3fff) << 0) 340 #define YUV_VIRWIDTH(x) (((x / 4) & 0x3fff) << 0) 341 342 /* VOP_WIN0_ACT_INFO */ 343 #define V_ACT_HEIGHT(x) (((x) & 0x1fff) << 16) 344 #define V_ACT_WIDTH(x) ((x) & 0x1fff) 345 346 /* VOP_WIN0_DSP_INFO */ 347 #define V_DSP_HEIGHT(x) (((x) & 0xfff) << 16) 348 #define V_DSP_WIDTH(x) ((x) & 0xfff) 349 350 /* VOP_WIN0_DSP_ST */ 351 #define V_DSP_YST(x) (((x) & 0x1fff) << 16) 352 #define V_DSP_XST(x) ((x) & 0x1fff) 353 354 /* VOP_WIN0_SCL_OFFSET */ 355 #define V_WIN0_VS_OFFSET_CBR(x) (((x) & 0xff) << 24) 356 #define V_WIN0_VS_OFFSET_YRGB(x) (((x) & 0xff) << 16) 357 #define V_WIN0_HS_OFFSET_CBR(x) (((x) & 0xff) << 8) 358 #define V_WIN0_HS_OFFSET_YRGB(x) ((x) & 0xff) 359 360 #define V_HSYNC(x) (((x)&0x1fff)<<0) /* hsync pulse width */ 361 #define V_HORPRD(x) (((x)&0x1fff)<<16) /* horizontal period */ 362 #define V_VSYNC(x) (((x)&0x1fff)<<0) 363 #define V_VERPRD(x) (((x)&0x1fff)<<16) 364 365 #define V_HEAP(x) (((x)&0x1fff)<<0)/* horizontal active end */ 366 #define V_HASP(x) (((x)&0x1fff)<<16)/* horizontal active start */ 367 #define V_VAEP(x) (((x)&0x1fff)<<0) 368 #define V_VASP(x) (((x)&0x1fff)<<16) 369 370 void rkvop_mode_set(u32 vop_id, const struct edid *edid, u32 mode); 371 void rkvop_prepare(u32 vop_id, const struct edid *edid); 372 void rkvop_enable(u32 vop_id, u32 fbbase); 373 #endif 374