1 /*
2  * Copyright (c) 2024, Intel Corporation. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef SOCFPGA_ROS_H
8 #define SOCFPGA_ROS_H
9 
10 #include <arch_helpers.h>
11 #include <lib/utils_def.h>
12 
13 /** status response*/
14 #define ROS_RET_OK			(0x00U)
15 #define ROS_RET_INVALID			(0x01U)
16 #define ROS_RET_NOT_RSU_MODE		(0x02U)
17 #define ROS_QSPI_READ_ERROR		(0x03U)
18 #define ROS_SPT_BAD_MAGIC_NUM		(0x04U)
19 #define ROS_SPT_CRC_ERROR		(0x05U)
20 #define ROS_IMAGE_INDEX_ERR		(0x06U)
21 #define ROS_IMAGE_PARTNUM_OVFL		(0x07U)
22 
23 #define ADDR_64(h, l)			(((((unsigned long)(h)) & 0xffffffff) << 32) | \
24 						(((unsigned long)(l)) & 0xffffffff))
25 
26 #define RSU_GET_SPT_RESP_SIZE		(4U)
27 
28 #define RSU_STATUS_RES_SIZE		(9U)
29 
30 #define SPT_MAGIC_NUMBER		(0x57713427U)
31 #define SPT_VERSION			(0U)
32 #define SPT_FLAG_RESERVED		(1U)
33 #define SPT_FLAG_READONLY		(2U)
34 
35 #define SPT_MAX_PARTITIONS		(127U)
36 #define SPT_PARTITION_NAME_LENGTH	(16U)
37 #define SPT_RSVD_LENGTH			(4U)
38 #define SPT_SIZE			(4096U)
39 /*BOOT_INFO + FACTORY_IMAGE + SPT0 + SPT1 + CPB0 + CPB1 + FACTORY_IM.SSBL+ *APP* + *APP*.SSBL*/
40 #define SPT_MIN_PARTITIONS		(9U)
41 
42 #define FACTORY_IMAGE			"FACTORY_IMAGE"
43 #define FACTORY_SSBL			"FACTORY_IM.SSBL"
44 #define SSBL_SUFFIX			".SSBL"
45 
46 typedef struct {
47 	const uint32_t magic_number;
48 	const uint32_t version;
49 	const uint32_t partitions;
50 	uint32_t checksum;
51 	const uint32_t __RSVD[SPT_RSVD_LENGTH];
52 	struct {
53 		const char name[SPT_PARTITION_NAME_LENGTH];
54 		const uint64_t offset;
55 		const uint32_t length;
56 		const uint32_t flags;
57 	} partition[SPT_MAX_PARTITIONS];
58 } __packed spt_table_t;
59 
60 uint32_t ros_qspi_get_ssbl_offset(unsigned long *offset);
61 
62 #endif /* SOCFPGA_ROS_H */
63