1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2
3 #include <device/device.h>
4 #include <device/pci.h>
5 #include <device/pci_ids.h>
6 #include <intelblocks/sram.h>
7 #include <soc/iomap.h>
8
soc_sram_init(struct device * dev)9 __weak void soc_sram_init(struct device *dev) { /* no-op */ }
10
sram_read_resources(struct device * dev)11 static void sram_read_resources(struct device *dev)
12 {
13 struct resource *res;
14 pci_dev_read_resources(dev);
15
16 res = new_resource(dev, PCI_BASE_ADDRESS_0);
17 res->base = SRAM_BASE_0;
18 res->size = SRAM_SIZE_0;
19 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
20
21 res = new_resource(dev, PCI_BASE_ADDRESS_2);
22 res->base = SRAM_BASE_2;
23 res->size = SRAM_SIZE_2;
24 res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
25 }
26
27 static const struct device_operations device_ops = {
28 .read_resources = sram_read_resources,
29 .set_resources = pci_dev_set_resources,
30 .enable_resources = pci_dev_enable_resources,
31 .init = soc_sram_init,
32 .ops_pci = &pci_dev_ops_pci,
33 };
34
35 static const unsigned short pci_device_ids[] = {
36 PCI_DID_INTEL_PTL_SRAM,
37 PCI_DID_INTEL_LNL_SRAM,
38 PCI_DID_INTEL_MTL_SOC_SRAM,
39 PCI_DID_INTEL_MTL_IOE_M_SRAM,
40 PCI_DID_INTEL_MTL_IOE_P_SRAM,
41 PCI_DID_INTEL_MTL_CRASHLOG_SRAM,
42 PCI_DID_INTEL_APL_SRAM,
43 PCI_DID_INTEL_GLK_SRAM,
44 PCI_DID_INTEL_CMP_SRAM,
45 PCI_DID_INTEL_CMP_H_SRAM,
46 PCI_DID_INTEL_TGP_PMC_CRASHLOG_SRAM,
47 PCI_DID_INTEL_TGL_H_SRAM,
48 PCI_DID_INTEL_MCC_SRAM,
49 PCI_DID_INTEL_JSP_SRAM,
50 PCI_DID_INTEL_ADP_S_PMC_CRASHLOG_SRAM,
51 PCI_DID_INTEL_ADP_P_PMC_CRASHLOG_SRAM,
52 PCI_DID_INTEL_ADP_N_PMC_CRASHLOG_SRAM,
53 PCI_DID_INTEL_RPP_S_PMC_CRASHLOG_SRAM,
54 0,
55 };
56
57 static const struct pci_driver sram __pci_driver = {
58 .ops = &device_ops,
59 .vendor = PCI_VID_INTEL,
60 .devices = pci_device_ids,
61 };
62