1 /* 2 ************************************************************************************************************************ 3 * 4 * Copyright (C) 2007-2023 Advanced Micro Devices, Inc. All rights reserved. 5 * SPDX-License-Identifier: MIT 6 * 7 ***********************************************************************************************************************/ 8 9 #if !defined (__GFX12_GB_REG_H__) 10 #define __GFX12_GB_REG_H__ 11 12 /* 13 * gfx12_gb_reg.h 14 * 15 * Register Spec Release: 1.0 16 * 17 */ 18 19 // 20 // Make sure the necessary endian defines are there. 21 // 22 #if defined(LITTLEENDIAN_CPU) 23 #elif defined(BIGENDIAN_CPU) 24 #else 25 #error "BIGENDIAN_CPU or LITTLEENDIAN_CPU must be defined" 26 #endif 27 28 union GB_ADDR_CONFIG_GFX12 { 29 struct { 30 #if defined(LITTLEENDIAN_CPU) 31 unsigned int NUM_PIPES : 3; 32 unsigned int PIPE_INTERLEAVE_SIZE : 3; 33 unsigned int MAX_COMPRESSED_FRAGS : 2; 34 unsigned int NUM_PKRS : 3; 35 unsigned int : 8; 36 unsigned int NUM_SHADER_ENGINES : 4; 37 unsigned int : 3; 38 unsigned int NUM_RB_PER_SE : 2; 39 unsigned int : 4; 40 #elif defined(BIGENDIAN_CPU) 41 unsigned int : 4; 42 unsigned int NUM_RB_PER_SE : 2; 43 unsigned int : 3; 44 unsigned int NUM_SHADER_ENGINES : 4; 45 unsigned int : 8; 46 unsigned int NUM_PKRS : 3; 47 unsigned int MAX_COMPRESSED_FRAGS : 2; 48 unsigned int PIPE_INTERLEAVE_SIZE : 3; 49 unsigned int NUM_PIPES : 3; 50 #endif 51 } bitfields, bits; 52 unsigned int u32All; 53 int i32All; 54 float f32All; 55 }; 56 57 #endif