1 /* 2 ************************************************************************************************************************ 3 * 4 * Copyright (C) 2007-2022 Advanced Micro Devices, Inc. All rights reserved. 5 * SPDX-License-Identifier: MIT 6 * 7 ***********************************************************************************************************************/ 8 9 #if !defined (__GFX9_GB_REG_H__) 10 #define __GFX9_GB_REG_H__ 11 12 /* 13 * gfx9_gb_reg.h 14 * 15 * Register Spec Release: 1.0 16 * 17 */ 18 19 // 20 // Make sure the necessary endian defines are there. 21 // 22 #if defined(LITTLEENDIAN_CPU) 23 #elif defined(BIGENDIAN_CPU) 24 #else 25 #error "BIGENDIAN_CPU or LITTLEENDIAN_CPU must be defined" 26 #endif 27 28 union GB_ADDR_CONFIG_GFX9 { 29 struct { 30 #if defined(LITTLEENDIAN_CPU) 31 unsigned int NUM_PIPES : 3; 32 unsigned int PIPE_INTERLEAVE_SIZE : 3; 33 unsigned int MAX_COMPRESSED_FRAGS : 2; 34 unsigned int BANK_INTERLEAVE_SIZE : 3; 35 unsigned int : 1; 36 unsigned int NUM_BANKS : 3; 37 unsigned int : 1; 38 unsigned int SHADER_ENGINE_TILE_SIZE : 3; 39 unsigned int NUM_SHADER_ENGINES : 2; 40 unsigned int NUM_GPUS : 3; 41 unsigned int MULTI_GPU_TILE_SIZE : 2; 42 unsigned int NUM_RB_PER_SE : 2; 43 unsigned int ROW_SIZE : 2; 44 unsigned int NUM_LOWER_PIPES : 1; 45 unsigned int SE_ENABLE : 1; 46 #elif defined(BIGENDIAN_CPU) 47 unsigned int SE_ENABLE : 1; 48 unsigned int NUM_LOWER_PIPES : 1; 49 unsigned int ROW_SIZE : 2; 50 unsigned int NUM_RB_PER_SE : 2; 51 unsigned int MULTI_GPU_TILE_SIZE : 2; 52 unsigned int NUM_GPUS : 3; 53 unsigned int NUM_SHADER_ENGINES : 2; 54 unsigned int SHADER_ENGINE_TILE_SIZE : 3; 55 unsigned int : 1; 56 unsigned int NUM_BANKS : 3; 57 unsigned int : 1; 58 unsigned int BANK_INTERLEAVE_SIZE : 3; 59 unsigned int MAX_COMPRESSED_FRAGS : 2; 60 unsigned int PIPE_INTERLEAVE_SIZE : 3; 61 unsigned int NUM_PIPES : 3; 62 #endif 63 } bitfields, bits; 64 unsigned int u32All; 65 signed int i32All; 66 float f32All; 67 }; 68 69 #endif 70 71