1 /* 2 ************************************************************************************************************************ 3 * 4 * Copyright (C) 2007-2022 Advanced Micro Devices, Inc. All rights reserved. 5 * SPDX-License-Identifier: MIT 6 * 7 ***********************************************************************************************************************/ 8 9 #if !defined (__SI_GB_REG_H__) 10 #define __SI_GB_REG_H__ 11 12 /***************************************************************************************************************** 13 * 14 * si_gb_reg.h 15 * 16 * Register Spec Release: Chip Spec 0.28 17 * 18 *****************************************************************************************************************/ 19 20 // 21 // Make sure the necessary endian defines are there. 22 // 23 #if defined(LITTLEENDIAN_CPU) 24 #elif defined(BIGENDIAN_CPU) 25 #else 26 #error "BIGENDIAN_CPU or LITTLEENDIAN_CPU must be defined" 27 #endif 28 29 /* 30 * GB_ADDR_CONFIG struct 31 */ 32 33 #if defined(LITTLEENDIAN_CPU) 34 35 typedef struct _GB_ADDR_CONFIG_T { 36 unsigned int num_pipes : 3; 37 unsigned int : 1; 38 unsigned int pipe_interleave_size : 3; 39 unsigned int : 1; 40 unsigned int bank_interleave_size : 3; 41 unsigned int : 1; 42 unsigned int num_shader_engines : 2; 43 unsigned int : 2; 44 unsigned int shader_engine_tile_size : 3; 45 unsigned int : 1; 46 unsigned int num_gpus : 3; 47 unsigned int : 1; 48 unsigned int multi_gpu_tile_size : 2; 49 unsigned int : 2; 50 unsigned int row_size : 2; 51 unsigned int num_lower_pipes : 1; 52 unsigned int : 1; 53 } GB_ADDR_CONFIG_T; 54 55 #elif defined(BIGENDIAN_CPU) 56 57 typedef struct _GB_ADDR_CONFIG_T { 58 unsigned int : 1; 59 unsigned int num_lower_pipes : 1; 60 unsigned int row_size : 2; 61 unsigned int : 2; 62 unsigned int multi_gpu_tile_size : 2; 63 unsigned int : 1; 64 unsigned int num_gpus : 3; 65 unsigned int : 1; 66 unsigned int shader_engine_tile_size : 3; 67 unsigned int : 2; 68 unsigned int num_shader_engines : 2; 69 unsigned int : 1; 70 unsigned int bank_interleave_size : 3; 71 unsigned int : 1; 72 unsigned int pipe_interleave_size : 3; 73 unsigned int : 1; 74 unsigned int num_pipes : 3; 75 } GB_ADDR_CONFIG_T; 76 77 #endif 78 79 #if defined(LITTLEENDIAN_CPU) 80 81 typedef struct _GB_ADDR_CONFIG_N { 82 unsigned int num_pipes : 3; 83 unsigned int pipe_interleave_size : 3; 84 unsigned int max_compressed_frags : 2; 85 unsigned int bank_interleave_size : 3; 86 unsigned int : 1; 87 unsigned int num_banks : 3; 88 unsigned int : 1; 89 unsigned int shader_engine_tile_size : 3; 90 unsigned int num_shader_engines : 2; 91 unsigned int num_gpus : 3; 92 unsigned int multi_gpu_tile_size : 2; 93 unsigned int num_rb_per_se : 2; 94 unsigned int row_size : 2; 95 unsigned int num_lower_pipes : 1; 96 unsigned int se_enable : 1; 97 } GB_ADDR_CONFIG_N; 98 99 #elif defined(BIGENDIAN_CPU) 100 101 typedef struct _GB_ADDR_CONFIG_N { 102 unsigned int se_enable : 1; 103 unsigned int num_lower_pipes : 1; 104 unsigned int row_size : 2; 105 unsigned int num_rb_per_se : 2; 106 unsigned int multi_gpu_tile_size : 2; 107 unsigned int num_gpus : 3; 108 unsigned int num_shader_engines : 2; 109 unsigned int shader_engine_tile_size : 3; 110 unsigned int : 1; 111 unsigned int num_banks : 3; 112 unsigned int : 1; 113 unsigned int bank_interleave_size : 3; 114 unsigned int max_compressed_frags : 2; 115 unsigned int pipe_interleave_size : 3; 116 unsigned int num_pipes : 3; 117 } GB_ADDR_CONFIG_N; 118 119 #endif 120 121 typedef union { 122 unsigned int val : 32; 123 GB_ADDR_CONFIG_T f; 124 GB_ADDR_CONFIG_N n; 125 } GB_ADDR_CONFIG; 126 127 #if defined(LITTLEENDIAN_CPU) 128 129 typedef struct _GB_TILE_MODE_T { 130 unsigned int micro_tile_mode : 2; 131 unsigned int array_mode : 4; 132 unsigned int pipe_config : 5; 133 unsigned int tile_split : 3; 134 unsigned int bank_width : 2; 135 unsigned int bank_height : 2; 136 unsigned int macro_tile_aspect : 2; 137 unsigned int num_banks : 2; 138 unsigned int micro_tile_mode_new : 3; 139 unsigned int sample_split : 2; 140 unsigned int alt_pipe_config : 5; 141 } GB_TILE_MODE_T; 142 143 typedef struct _GB_MACROTILE_MODE_T { 144 unsigned int bank_width : 2; 145 unsigned int bank_height : 2; 146 unsigned int macro_tile_aspect : 2; 147 unsigned int num_banks : 2; 148 unsigned int alt_bank_height : 2; 149 unsigned int alt_macro_tile_aspect : 2; 150 unsigned int alt_num_banks : 2; 151 unsigned int : 18; 152 } GB_MACROTILE_MODE_T; 153 154 #elif defined(BIGENDIAN_CPU) 155 156 typedef struct _GB_TILE_MODE_T { 157 unsigned int alt_pipe_config : 5; 158 unsigned int sample_split : 2; 159 unsigned int micro_tile_mode_new : 3; 160 unsigned int num_banks : 2; 161 unsigned int macro_tile_aspect : 2; 162 unsigned int bank_height : 2; 163 unsigned int bank_width : 2; 164 unsigned int tile_split : 3; 165 unsigned int pipe_config : 5; 166 unsigned int array_mode : 4; 167 unsigned int micro_tile_mode : 2; 168 } GB_TILE_MODE_T; 169 170 typedef struct _GB_MACROTILE_MODE_T { 171 unsigned int : 18; 172 unsigned int alt_num_banks : 2; 173 unsigned int alt_macro_tile_aspect : 2; 174 unsigned int alt_bank_height : 2; 175 unsigned int num_banks : 2; 176 unsigned int macro_tile_aspect : 2; 177 unsigned int bank_height : 2; 178 unsigned int bank_width : 2; 179 } GB_MACROTILE_MODE_T; 180 181 #endif 182 183 typedef union { 184 unsigned int val : 32; 185 GB_TILE_MODE_T f; 186 } GB_TILE_MODE; 187 188 typedef union { 189 unsigned int val : 32; 190 GB_MACROTILE_MODE_T f; 191 } GB_MACROTILE_MODE; 192 193 #endif 194 195