1 #ifndef VPE_1_0_OFFSET_H 2 #define VPE_1_0_OFFSET_H 3 4 5 #define MAX_INSTANCE 9 6 #define MAX_SEGMENT 7 7 8 9 struct IP_BASE_INSTANCE 10 { 11 unsigned int segment[MAX_SEGMENT]; 12 }; 13 14 struct IP_BASE 15 { 16 struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; 17 }; 18 19 20 struct IP_SIZE 21 { 22 unsigned int segment[1][MAX_SEGMENT]; 23 }; 24 25 26 static const struct IP_BASE VPE_BASE = { { { { 0x00011800, 0x02456C00, 0x3C56C000, 0, 0, 0, 0 } }, 27 { { 0, 0, 0, 0, 0, 0 } }, 28 { { 0, 0, 0, 0, 0, 0 } }, 29 { { 0, 0, 0, 0, 0, 0 } }, 30 { { 0, 0, 0, 0, 0, 0 } }, 31 { { 0, 0, 0, 0, 0, 0 } }, 32 { { 0, 0, 0, 0, 0, 0 } }, 33 { { 0, 0, 0, 0, 0, 0 } }, 34 { { 0, 0, 0, 0, 0, 0 } } } }; 35 static const struct IP_SIZE VPE_SIZE = { { { 0x00001400, 0x00000400, 0x00004000, 0, 0, 0, 0 } } }; 36 37 38 39 #define VPE_BASE__INST0_SEG0 0x00011800 40 #define VPE_BASE__INST0_SEG1 0x02456C00 41 #define VPE_BASE__INST0_SEG2 0x3C56C000 42 #define VPE_BASE__INST0_SEG3 0 43 #define VPE_BASE__INST0_SEG4 0 44 #define VPE_BASE__INST0_SEG5 0 45 #define VPE_BASE__INST0_SEG6 0 46 47 #define VPE_BASE__INST1_SEG0 0 48 #define VPE_BASE__INST1_SEG1 0 49 #define VPE_BASE__INST1_SEG2 0 50 #define VPE_BASE__INST1_SEG3 0 51 #define VPE_BASE__INST1_SEG4 0 52 #define VPE_BASE__INST1_SEG5 0 53 #define VPE_BASE__INST1_SEG6 0 54 55 #define VPE_BASE__INST2_SEG0 0 56 #define VPE_BASE__INST2_SEG1 0 57 #define VPE_BASE__INST2_SEG2 0 58 #define VPE_BASE__INST2_SEG3 0 59 #define VPE_BASE__INST2_SEG4 0 60 #define VPE_BASE__INST2_SEG5 0 61 #define VPE_BASE__INST2_SEG6 0 62 63 #define VPE_BASE__INST3_SEG0 0 64 #define VPE_BASE__INST3_SEG1 0 65 #define VPE_BASE__INST3_SEG2 0 66 #define VPE_BASE__INST3_SEG3 0 67 #define VPE_BASE__INST3_SEG4 0 68 #define VPE_BASE__INST3_SEG5 0 69 #define VPE_BASE__INST3_SEG6 0 70 71 #define VPE_BASE__INST4_SEG0 0 72 #define VPE_BASE__INST4_SEG1 0 73 #define VPE_BASE__INST4_SEG2 0 74 #define VPE_BASE__INST4_SEG3 0 75 #define VPE_BASE__INST4_SEG4 0 76 #define VPE_BASE__INST4_SEG5 0 77 #define VPE_BASE__INST4_SEG6 0 78 79 #define VPE_BASE__INST5_SEG0 0 80 #define VPE_BASE__INST5_SEG1 0 81 #define VPE_BASE__INST5_SEG2 0 82 #define VPE_BASE__INST5_SEG3 0 83 #define VPE_BASE__INST5_SEG4 0 84 #define VPE_BASE__INST5_SEG5 0 85 #define VPE_BASE__INST5_SEG6 0 86 87 #define VPE_BASE__INST6_SEG0 0 88 #define VPE_BASE__INST6_SEG1 0 89 #define VPE_BASE__INST6_SEG2 0 90 #define VPE_BASE__INST6_SEG3 0 91 #define VPE_BASE__INST6_SEG4 0 92 #define VPE_BASE__INST6_SEG5 0 93 #define VPE_BASE__INST6_SEG6 0 94 95 #define VPE_BASE__INST7_SEG0 0 96 #define VPE_BASE__INST7_SEG1 0 97 #define VPE_BASE__INST7_SEG2 0 98 #define VPE_BASE__INST7_SEG3 0 99 #define VPE_BASE__INST7_SEG4 0 100 #define VPE_BASE__INST7_SEG5 0 101 #define VPE_BASE__INST7_SEG6 0 102 103 #define VPE_BASE__INST8_SEG0 0 104 #define VPE_BASE__INST8_SEG1 0 105 #define VPE_BASE__INST8_SEG2 0 106 #define VPE_BASE__INST8_SEG3 0 107 #define VPE_BASE__INST8_SEG4 0 108 #define VPE_BASE__INST8_SEG5 0 109 #define VPE_BASE__INST8_SEG6 0 110 111 #endif 112