1 /* Copyright 2022 Advanced Micro Devices, Inc. 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice shall be included in 11 * all copies or substantial portions of the Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 19 * OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * Authors: AMD 22 * 23 */ 24 #pragma once 25 26 #include "cdc.h" 27 #include "reg_helper.h" 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #define VPE10_CDC_VUPDATE_OFFSET_DEFAULT (21) 34 #define VPE10_CDC_VUPDATE_WIDTH_DEFAULT (60) 35 #define VPE10_CDC_VREADY_OFFSET_DEFAULT (150) 36 37 /* macros for filing variable or field list 38 SRI, SFRB should be defined in the resource file */ 39 #define CDC_REG_LIST_VPE10(id) \ 40 SRIDFVL(VPEP_MGCG_CNTL, CDC, id), SRIDFVL(VPCDC_SOFT_RESET, CDC, id), \ 41 SRIDFVL(VPCDC_FE0_SURFACE_CONFIG, CDC, id), SRIDFVL(VPCDC_FE0_CROSSBAR_CONFIG, CDC, id), \ 42 SRIDFVL(VPCDC_FE0_VIEWPORT_START_CONFIG, CDC, id), \ 43 SRIDFVL(VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG, CDC, id), \ 44 SRIDFVL(VPCDC_FE0_VIEWPORT_START_C_CONFIG, CDC, id), \ 45 SRIDFVL(VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG, CDC, id), \ 46 SRIDFVL(VPCDC_BE0_P2B_CONFIG, CDC, id), SRIDFVL(VPCDC_BE0_GLOBAL_SYNC_CONFIG, CDC, id), \ 47 SRIDFVL(VPCDC_GLOBAL_SYNC_TRIGGER, CDC, id), \ 48 SRIDFVL(VPEP_MEM_GLOBAL_PWR_REQ_CNTL, CDC, id), SRIDFVL(VPFE_MEM_PWR_CNTL, CDC, id), \ 49 SRIDFVL(VPBE_MEM_PWR_CNTL, CDC, id) 50 51 #define CDC_FLIED_LIST_VPE10(post_fix) \ 52 SFRB(VPDPP0_CLK_GATE_DIS, VPEP_MGCG_CNTL, post_fix), \ 53 SFRB(VPMPC_CLK_GATE_DIS, VPEP_MGCG_CNTL, post_fix), \ 54 SFRB(VPOPP_CLK_GATE_DIS, VPEP_MGCG_CNTL, post_fix), \ 55 SFRB(VPCDC_SOCCLK_G_GATE_DIS, VPEP_MGCG_CNTL, post_fix), \ 56 SFRB(VPCDC_SOCCLK_R_GATE_DIS, VPEP_MGCG_CNTL, post_fix), \ 57 SFRB(VPCDC_VPECLK_G_GATE_DIS, VPEP_MGCG_CNTL, post_fix), \ 58 SFRB(VPCDC_VPECLK_R_GATE_DIS, VPEP_MGCG_CNTL, post_fix), \ 59 SFRB(VPCDC_SOCCLK_SOFT_RESET, VPCDC_SOFT_RESET, post_fix), \ 60 SFRB(VPCDC_VPECLK_SOFT_RESET, VPCDC_SOFT_RESET, post_fix), \ 61 SFRB(SURFACE_PIXEL_FORMAT_FE0, VPCDC_FE0_SURFACE_CONFIG, post_fix), \ 62 SFRB(ROTATION_ANGLE_FE0, VPCDC_FE0_SURFACE_CONFIG, post_fix), \ 63 SFRB(H_MIRROR_EN_FE0, VPCDC_FE0_SURFACE_CONFIG, post_fix), \ 64 SFRB(PIX_SURFACE_LINEAR_FE0, VPCDC_FE0_SURFACE_CONFIG, post_fix), \ 65 SFRB(CROSSBAR_SRC_ALPHA_FE0, VPCDC_FE0_CROSSBAR_CONFIG, post_fix), \ 66 SFRB(CROSSBAR_SRC_Y_G_FE0, VPCDC_FE0_CROSSBAR_CONFIG, post_fix), \ 67 SFRB(CROSSBAR_SRC_CB_B_FE0, VPCDC_FE0_CROSSBAR_CONFIG, post_fix), \ 68 SFRB(CROSSBAR_SRC_CR_R_FE0, VPCDC_FE0_CROSSBAR_CONFIG, post_fix), \ 69 SFRB(VIEWPORT_X_START_FE0, VPCDC_FE0_VIEWPORT_START_CONFIG, post_fix), \ 70 SFRB(VIEWPORT_Y_START_FE0, VPCDC_FE0_VIEWPORT_START_CONFIG, post_fix), \ 71 SFRB(VIEWPORT_WIDTH_FE0, VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG, post_fix), \ 72 SFRB(VIEWPORT_HEIGHT_FE0, VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG, post_fix), \ 73 SFRB(VIEWPORT_X_START_C_FE0, VPCDC_FE0_VIEWPORT_START_C_CONFIG, post_fix), \ 74 SFRB(VIEWPORT_Y_START_C_FE0, VPCDC_FE0_VIEWPORT_START_C_CONFIG, post_fix), \ 75 SFRB(VIEWPORT_WIDTH_C_FE0, VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG, post_fix), \ 76 SFRB(VIEWPORT_HEIGHT_C_FE0, VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG, post_fix), \ 77 SFRB(VPCDC_BE0_P2B_XBAR_SEL0, VPCDC_BE0_P2B_CONFIG, post_fix), \ 78 SFRB(VPCDC_BE0_P2B_XBAR_SEL1, VPCDC_BE0_P2B_CONFIG, post_fix), \ 79 SFRB(VPCDC_BE0_P2B_XBAR_SEL2, VPCDC_BE0_P2B_CONFIG, post_fix), \ 80 SFRB(VPCDC_BE0_P2B_XBAR_SEL3, VPCDC_BE0_P2B_CONFIG, post_fix), \ 81 SFRB(VPCDC_BE0_P2B_FORMAT_SEL, VPCDC_BE0_P2B_CONFIG, post_fix), \ 82 SFRB(BE0_VUPDATE_OFFSET, VPCDC_BE0_GLOBAL_SYNC_CONFIG, post_fix), \ 83 SFRB(BE0_VUPDATE_WIDTH, VPCDC_BE0_GLOBAL_SYNC_CONFIG, post_fix), \ 84 SFRB(BE0_VREADY_OFFSET, VPCDC_BE0_GLOBAL_SYNC_CONFIG, post_fix), \ 85 SFRB(VPBE_GS_TRIG, VPCDC_GLOBAL_SYNC_TRIGGER, post_fix), \ 86 SFRB(VPFE_VR_STATUS, VPCDC_VREADY_STATUS, post_fix), \ 87 SFRB(MEM_GLOBAL_PWR_REQ_DIS, VPEP_MEM_GLOBAL_PWR_REQ_CNTL, post_fix), \ 88 SFRB(VPFE0_MEM_PWR_FORCE, VPFE_MEM_PWR_CNTL, post_fix), \ 89 SFRB(VPFE0_MEM_PWR_MODE, VPFE_MEM_PWR_CNTL, post_fix), \ 90 SFRB(VPFE0_MEM_PWR_STATE, VPFE_MEM_PWR_CNTL, post_fix), \ 91 SFRB(VPFE0_MEM_PWR_DIS, VPFE_MEM_PWR_CNTL, post_fix), \ 92 SFRB(VPBE0_MEM_PWR_FORCE, VPBE_MEM_PWR_CNTL, post_fix), \ 93 SFRB(VPBE0_MEM_PWR_MODE, VPBE_MEM_PWR_CNTL, post_fix), \ 94 SFRB(VPBE0_MEM_PWR_STATE, VPBE_MEM_PWR_CNTL, post_fix), \ 95 SFRB(VPBE0_MEM_PWR_DIS, VPBE_MEM_PWR_CNTL, post_fix) 96 97 /* define all structure register variables below */ 98 #define CDC_REG_VARIABLE_LIST_VPE10 \ 99 reg_id_val VPEP_MGCG_CNTL; \ 100 reg_id_val VPCDC_SOFT_RESET; \ 101 reg_id_val VPCDC_FE0_SURFACE_CONFIG; \ 102 reg_id_val VPCDC_FE0_CROSSBAR_CONFIG; \ 103 reg_id_val VPCDC_FE0_VIEWPORT_START_CONFIG; \ 104 reg_id_val VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG; \ 105 reg_id_val VPCDC_FE0_VIEWPORT_START_C_CONFIG; \ 106 reg_id_val VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG; \ 107 reg_id_val VPCDC_BE0_P2B_CONFIG; \ 108 reg_id_val VPCDC_BE0_GLOBAL_SYNC_CONFIG; \ 109 reg_id_val VPCDC_GLOBAL_SYNC_TRIGGER; \ 110 reg_id_val VPEP_MEM_GLOBAL_PWR_REQ_CNTL; \ 111 reg_id_val VPFE_MEM_PWR_CNTL; \ 112 reg_id_val VPBE_MEM_PWR_CNTL; 113 114 #define CDC_FIELD_VARIABLE_LIST_VPE10(type) \ 115 type VPDPP0_CLK_GATE_DIS; \ 116 type VPMPC_CLK_GATE_DIS; \ 117 type VPOPP_CLK_GATE_DIS; \ 118 type VPCDC_SOCCLK_G_GATE_DIS; \ 119 type VPCDC_SOCCLK_R_GATE_DIS; \ 120 type VPCDC_VPECLK_G_GATE_DIS; \ 121 type VPCDC_VPECLK_R_GATE_DIS; \ 122 type VPCDC_SOCCLK_SOFT_RESET; \ 123 type VPCDC_VPECLK_SOFT_RESET; \ 124 type SURFACE_PIXEL_FORMAT_FE0; \ 125 type ROTATION_ANGLE_FE0; \ 126 type H_MIRROR_EN_FE0; \ 127 type PIX_SURFACE_LINEAR_FE0; \ 128 type CROSSBAR_SRC_ALPHA_FE0; \ 129 type CROSSBAR_SRC_Y_G_FE0; \ 130 type CROSSBAR_SRC_CB_B_FE0; \ 131 type CROSSBAR_SRC_CR_R_FE0; \ 132 type VIEWPORT_X_START_FE0; \ 133 type VIEWPORT_Y_START_FE0; \ 134 type VIEWPORT_WIDTH_FE0; \ 135 type VIEWPORT_HEIGHT_FE0; \ 136 type VIEWPORT_X_START_C_FE0; \ 137 type VIEWPORT_Y_START_C_FE0; \ 138 type VIEWPORT_WIDTH_C_FE0; \ 139 type VIEWPORT_HEIGHT_C_FE0; \ 140 type VPCDC_BE0_P2B_XBAR_SEL0; \ 141 type VPCDC_BE0_P2B_XBAR_SEL1; \ 142 type VPCDC_BE0_P2B_XBAR_SEL2; \ 143 type VPCDC_BE0_P2B_XBAR_SEL3; \ 144 type VPCDC_BE0_P2B_FORMAT_SEL; \ 145 type BE0_VUPDATE_OFFSET; \ 146 type BE0_VUPDATE_WIDTH; \ 147 type BE0_VREADY_OFFSET; \ 148 type VPBE_GS_TRIG; \ 149 type VPFE_VR_STATUS; \ 150 type MEM_GLOBAL_PWR_REQ_DIS; \ 151 type VPFE0_MEM_PWR_FORCE; \ 152 type VPFE0_MEM_PWR_MODE; \ 153 type VPFE0_MEM_PWR_STATE; \ 154 type VPFE0_MEM_PWR_DIS; \ 155 type VPBE0_MEM_PWR_FORCE; \ 156 type VPBE0_MEM_PWR_MODE; \ 157 type VPBE0_MEM_PWR_STATE; \ 158 type VPBE0_MEM_PWR_DIS; 159 160 struct vpe10_cdc_registers { 161 CDC_REG_VARIABLE_LIST_VPE10 162 }; 163 164 struct vpe10_cdc_shift { 165 CDC_FIELD_VARIABLE_LIST_VPE10(uint8_t) 166 }; 167 168 struct vpe10_cdc_mask { 169 CDC_FIELD_VARIABLE_LIST_VPE10(uint32_t) 170 }; 171 172 struct vpe10_cdc { 173 struct cdc base; // base class, must be the first field 174 struct vpe10_cdc_registers *regs; 175 const struct vpe10_cdc_shift *shift; 176 const struct vpe10_cdc_mask *mask; 177 }; 178 179 void vpe10_construct_cdc(struct vpe_priv *vpe_priv, struct cdc *cdc); 180 181 bool vpe10_cdc_check_input_format(struct cdc *cdc, enum vpe_surface_pixel_format format); 182 183 bool vpe10_cdc_check_output_format(struct cdc *cdc, enum vpe_surface_pixel_format format); 184 185 void vpe10_cdc_program_surface_config(struct cdc *cdc, enum vpe_surface_pixel_format format, 186 enum vpe_rotation_angle rotation, bool horizontal_mirror, enum vpe_swizzle_mode_values swizzle); 187 188 void vpe10_cdc_program_crossbar_config(struct cdc *cdc, enum vpe_surface_pixel_format format); 189 190 void vpe10_cdc_program_global_sync( 191 struct cdc *cdc, uint32_t vupdate_offset, uint32_t vupdate_width, uint32_t vready_offset); 192 193 void vpe10_cdc_program_p2b_config(struct cdc *cdc, enum vpe_surface_pixel_format format); 194 195 /***** segment register programming *****/ 196 void vpe10_cdc_program_viewport( 197 struct cdc *cdc, const struct vpe_rect *viewport, const struct vpe_rect *viewport_c); 198 199 #ifdef __cplusplus 200 } 201 #endif 202