1 /* Copyright 2024 Advanced Micro Devices, Inc.
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice shall be included in
11 * all copies or substantial portions of the Software.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
19 * OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * Authors: AMD
22 *
23 */
24
25 #include "vpe_assert.h"
26 #include "common.h"
27 #include "reg_helper.h"
28 #include "vpe10_vpe_desc_writer.h"
29 #include "vpe10_command.h"
30
vpe10_construct_vpe_desc_writer(struct vpe_desc_writer * writer)31 void vpe10_construct_vpe_desc_writer(struct vpe_desc_writer *writer)
32 {
33 writer->init = vpe10_vpe_desc_writer_init;
34 writer->add_plane_desc = vpe10_vpe_desc_writer_add_plane_desc;
35 writer->add_config_desc = vpe10_vpe_desc_writer_add_config_desc;
36 writer->complete = vpe10_vpe_desc_writer_complete;
37 }
38
vpe10_vpe_desc_writer_init(struct vpe_desc_writer * writer,struct vpe_buf * buf,int cd)39 enum vpe_status vpe10_vpe_desc_writer_init(
40 struct vpe_desc_writer *writer, struct vpe_buf *buf, int cd)
41 {
42 uint32_t *cmd_space;
43 uint64_t size = sizeof(uint32_t);
44
45 writer->base_cpu_va = buf->cpu_va;
46 writer->base_gpu_va = buf->gpu_va;
47 writer->buf = buf;
48 writer->num_config_desc = 0;
49 writer->plane_desc_added = false;
50 writer->status = VPE_STATUS_OK;
51
52 if (buf->size < size) {
53 writer->status = VPE_STATUS_BUFFER_OVERFLOW;
54 return writer->status;
55 }
56
57 if (writer->status == VPE_STATUS_OK) {
58 cmd_space = (uint32_t *)(uintptr_t)writer->buf->cpu_va;
59 *cmd_space++ = VPE_DESC_CMD_HEADER(cd);
60
61 writer->buf->cpu_va += size;
62 writer->buf->gpu_va += size;
63 writer->buf->size -= size;
64 }
65
66 return writer->status;
67 }
68
vpe10_vpe_desc_writer_add_plane_desc(struct vpe_desc_writer * writer,uint64_t plane_desc_addr,uint8_t tmz)69 void vpe10_vpe_desc_writer_add_plane_desc(
70 struct vpe_desc_writer *writer, uint64_t plane_desc_addr, uint8_t tmz)
71 {
72 uint32_t *cmd_space;
73 uint64_t size = 3 * sizeof(uint32_t);
74
75 if (writer->status != VPE_STATUS_OK)
76 return;
77
78 /* Buffer does not have enough space to write */
79 if (writer->buf->size < size) {
80 writer->status = VPE_STATUS_BUFFER_OVERFLOW;
81 return;
82 }
83
84 cmd_space = (uint32_t *)(uintptr_t)writer->buf->cpu_va;
85
86 VPE_ASSERT(!(plane_desc_addr & 0x3));
87 VPE_ASSERT(!writer->plane_desc_added);
88
89 *cmd_space++ = (ADDR_LO(plane_desc_addr) | (unsigned)(tmz & 1));
90 *cmd_space++ = ADDR_HI(plane_desc_addr);
91
92 // skip the DW3 as well, which is finalized during complete
93
94 writer->buf->cpu_va += size;
95 writer->buf->gpu_va += size;
96 writer->buf->size -= size;
97 writer->plane_desc_added = true;
98 }
99
vpe10_vpe_desc_writer_add_config_desc(struct vpe_desc_writer * writer,uint64_t config_desc_addr,bool reuse,uint8_t tmz)100 void vpe10_vpe_desc_writer_add_config_desc(
101 struct vpe_desc_writer *writer, uint64_t config_desc_addr, bool reuse, uint8_t tmz)
102 {
103 uint32_t *cmd_space;
104 uint64_t size = 2 * sizeof(uint32_t);
105
106 if (writer->status != VPE_STATUS_OK)
107 return;
108
109 /* Buffer does not have enough space to write */
110 if (writer->buf->size < size) {
111 writer->status = VPE_STATUS_BUFFER_OVERFLOW;
112 return;
113 }
114
115 cmd_space = (uint32_t *)(uintptr_t)writer->buf->cpu_va;
116
117 VPE_ASSERT(!(config_desc_addr & 0x3));
118
119 *cmd_space++ = (ADDR_LO(config_desc_addr) | ((unsigned)reuse << 1) | (unsigned)(tmz & 1));
120 *cmd_space++ = ADDR_HI(config_desc_addr);
121
122 writer->buf->cpu_va += size;
123 writer->buf->gpu_va += size;
124 writer->buf->size -= size;
125 writer->num_config_desc++;
126 }
127
vpe10_vpe_desc_writer_complete(struct vpe_desc_writer * writer)128 void vpe10_vpe_desc_writer_complete(struct vpe_desc_writer *writer)
129 {
130 uint32_t *cmd_space;
131
132 if (writer->status != VPE_STATUS_OK)
133 return;
134
135 // NUM_CONFIG_DESCRIPTOR is at DW3
136 cmd_space = (uint32_t *)(uintptr_t)(writer->base_cpu_va + 3 * sizeof(uint32_t));
137
138 VPE_ASSERT(!(writer->num_config_desc & 0xFFFFFF00));
139 VPE_ASSERT(writer->num_config_desc > 0);
140 // NUM_CONFIG_DESCRIPTOR is 1-based
141 *cmd_space = (writer->num_config_desc - 1) & 0xFF;
142 }
143