1 /* Copyright 2023 Advanced Micro Devices, Inc.
2 *
3 * Permission is hereby granted, free of charge, to any person obtaining a
4 * copy of this software and associated documentation files (the "Software"),
5 * to deal in the Software without restriction, including without limitation
6 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
7 * and/or sell copies of the Software, and to permit persons to whom the
8 * Software is furnished to do so, subject to the following conditions:
9 *
10 * The above copyright notice and this permission notice shall be included in
11 * all copies or substantial portions of the Software.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
19 * OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * Authors: AMD
22 *
23 */
24 #include <string.h>
25 #include "vpe_priv.h"
26 #include "common.h"
27 #include "vpe11_resource.h"
28 #include "vpe10_resource.h"
29 #include "vpe11_cmd_builder.h"
30 #include "vpe10_vpec.h"
31 #include "vpe10_cdc.h"
32 #include "vpe10_dpp.h"
33 #include "vpe10_mpc.h"
34 #include "vpe10_opp.h"
35 #include "vpe11_command.h"
36 #include "vpe10_cm_common.h"
37 #include "vpe10_background.h"
38 #include "vpe10_plane_desc_writer.h"
39 #include "vpe11_vpe_desc_writer.h"
40 #include "vpe10/inc/asic/bringup_vpe_6_1_0_offset.h"
41 #include "vpe10/inc/asic/bringup_vpe_6_1_0_sh_mask.h"
42 #include "vpe10/inc/asic/bringup_vpe_6_1_0_default.h"
43 #include "vpe10/inc/asic/vpe_1_0_offset.h"
44 #include "custom_fp16.h"
45 #include "custom_float.h"
46 #include "background.h"
47
48 #define LUT_NUM_ENTRIES (17 * 17 * 17)
49 #define LUT_ENTRY_SIZE (2)
50 #define LUT_NUM_COMPONENT (3)
51 #define LUT_BUFFER_SIZE (LUT_NUM_ENTRIES * LUT_ENTRY_SIZE * LUT_NUM_COMPONENT)
52
53 // set field/register/bitfield name
54 #define SFRB(field_name, reg_name, post_fix) .field_name = reg_name##__##field_name##post_fix
55
56 #define BASE_INNER(seg_id) VPE_BASE__INST0_SEG##seg_id
57
58 #define BASE(seg_id) BASE_INNER(seg_id)
59
60 // set register with block id and default val, init lastWrittenVal as default while isWritten set to
61 // false
62 #define SRIDFVL(reg_name, block, id) \
63 .reg_name = {BASE(reg##reg_name##_BASE_IDX) + reg##reg_name, reg##reg_name##_##DEFAULT, \
64 reg##reg_name##_##DEFAULT, false}
65
66 static struct vpe_caps caps = {
67 .lut_size = LUT_BUFFER_SIZE,
68 .rotation_support = 0,
69 .h_mirror_support = 1,
70 .v_mirror_support = 0,
71 .is_apu = 1,
72 .bg_color_check_support = 0,
73 .resource_caps =
74 {
75 .num_dpp = 1,
76 .num_opp = 1,
77 .num_mpc_3dlut = 1,
78 .num_queue = 8,
79 },
80 .color_caps = {.dpp =
81 {
82 .pre_csc = 1,
83 .luma_key = 0,
84 .dgam_ram = 0,
85 .post_csc = 1,
86 .gamma_corr = 1,
87 .hw_3dlut = 1,
88 .ogam_ram = 1, /**< programmable gam in output -> gamma_corr */
89 .ocsc = 0,
90 .dgam_rom_caps =
91 {
92 .srgb = 1,
93 .bt2020 = 1,
94 .gamma2_2 = 1,
95 .pq = 1,
96 .hlg = 1,
97 },
98 },
99 .mpc =
100 {
101 .gamut_remap = 1,
102 .ogam_ram = 1,
103 .ocsc = 1,
104 .shared_3d_lut = 1,
105 .global_alpha = 1,
106 .top_bottom_blending = 0,
107 }},
108 .plane_caps =
109 {
110 .per_pixel_alpha = 1,
111 .input_pixel_format_support =
112 {
113 .argb_packed_32b = 1,
114 .nv12 = 1,
115 .fp16 = 0,
116 .p010 = 1, /**< planar 4:2:0 10-bit */
117 .p016 = 0, /**< planar 4:2:0 16-bit */
118 .ayuv = 0, /**< packed 4:4:4 */
119 .yuy2 = 0
120 },
121 .output_pixel_format_support =
122 {
123 .argb_packed_32b = 1,
124 .nv12 = 0,
125 .fp16 = 1,
126 .p010 = 0, /**< planar 4:2:0 10-bit */
127 .p016 = 0, /**< planar 4:2:0 16-bit */
128 .ayuv = 0, /**< packed 4:4:4 */
129 .yuy2 = 0
130 },
131 .max_upscale_factor = 64000,
132
133 // 6:1 downscaling ratio: 1000/6 = 166.666
134 .max_downscale_factor = 167,
135
136 .pitch_alignment = 256,
137 .addr_alignment = 256,
138 .max_viewport_width = 1024,
139 },
140 };
141
142 static struct vpe_cap_funcs cap_funcs =
143 {
144 .get_dcc_compression_output_cap = vpe10_get_dcc_compression_output_cap,
145 .get_dcc_compression_input_cap = vpe10_get_dcc_compression_input_cap
146 };
147
vpe11_construct_resource(struct vpe_priv * vpe_priv,struct resource * res)148 enum vpe_status vpe11_construct_resource(struct vpe_priv *vpe_priv, struct resource *res)
149 {
150 struct vpe *vpe = &vpe_priv->pub;
151
152 vpe->caps = ∩︀
153 vpe->cap_funcs = &cap_funcs;
154
155 vpe10_construct_vpec(vpe_priv, &res->vpec);
156
157 res->cdc[0] = vpe10_cdc_create(vpe_priv, 0);
158 if (!res->cdc[0])
159 goto err;
160
161 res->dpp[0] = vpe10_dpp_create(vpe_priv, 0);
162 if (!res->dpp[0])
163 goto err;
164
165 res->mpc[0] = vpe10_mpc_create(vpe_priv, 0);
166 if (!res->mpc[0])
167 goto err;
168
169 res->opp[0] = vpe10_opp_create(vpe_priv, 0);
170 if (!res->opp[0])
171 goto err;
172
173 vpe11_construct_cmd_builder(vpe_priv, &res->cmd_builder);
174 vpe10_construct_plane_desc_writer(&vpe_priv->plane_desc_writer);
175 vpe11_construct_vpe_desc_writer(&vpe_priv->vpe_desc_writer);
176
177 vpe_priv->num_pipe = 1;
178
179 res->internal_hdr_normalization = 1;
180
181 res->check_input_color_space = vpe10_check_input_color_space;
182 res->check_output_color_space = vpe10_check_output_color_space;
183 res->check_h_mirror_support = vpe10_check_h_mirror_support;
184 res->calculate_segments = vpe10_calculate_segments;
185 res->set_num_segments = vpe11_set_num_segments;
186 res->split_bg_gap = vpe10_split_bg_gap;
187 res->calculate_dst_viewport_and_active = vpe10_calculate_dst_viewport_and_active;
188 res->find_bg_gaps = vpe_find_bg_gaps;
189 res->create_bg_segments = vpe_create_bg_segments;
190 res->populate_cmd_info = vpe10_populate_cmd_info;
191 res->program_frontend = vpe10_program_frontend;
192 res->program_backend = vpe10_program_backend;
193 res->get_bufs_req = vpe10_get_bufs_req;
194 res->check_bg_color_support = vpe10_check_bg_color_support;
195
196 return VPE_STATUS_OK;
197 err:
198 vpe11_destroy_resource(vpe_priv, res);
199 return VPE_STATUS_ERROR;
200 }
201
vpe11_destroy_resource(struct vpe_priv * vpe_priv,struct resource * res)202 void vpe11_destroy_resource(struct vpe_priv *vpe_priv, struct resource *res)
203 {
204 if (res->cdc[0] != NULL) {
205 vpe_free(container_of(res->cdc[0], struct vpe10_cdc, base));
206 res->cdc[0] = NULL;
207 }
208
209 if (res->dpp[0] != NULL) {
210 vpe_free(container_of(res->dpp[0], struct vpe10_dpp, base));
211 res->dpp[0] = NULL;
212 }
213
214 if (res->mpc[0] != NULL) {
215 vpe_free(container_of(res->mpc[0], struct vpe10_mpc, base));
216 res->mpc[0] = NULL;
217 }
218
219 if (res->opp[0] != NULL) {
220 vpe_free(container_of(res->opp[0], struct vpe10_opp, base));
221 res->opp[0] = NULL;
222 }
223 }
224
vpe11_set_num_segments(struct vpe_priv * vpe_priv,struct stream_ctx * stream_ctx,struct scaler_data * scl_data,struct vpe_rect * src_rect,struct vpe_rect * dst_rect,uint32_t * max_seg_width)225 enum vpe_status vpe11_set_num_segments(struct vpe_priv *vpe_priv, struct stream_ctx *stream_ctx,
226 struct scaler_data *scl_data, struct vpe_rect *src_rect, struct vpe_rect *dst_rect,
227 uint32_t *max_seg_width)
228 {
229
230 uint16_t num_segs;
231 struct dpp *dpp = vpe_priv->resource.dpp[0];
232 const uint32_t max_lb_size = dpp->funcs->get_line_buffer_size();
233
234 *max_seg_width = min(*max_seg_width, max_lb_size / scl_data->taps.v_taps);
235
236 num_segs = vpe_get_num_segments(vpe_priv, src_rect, dst_rect, *max_seg_width);
237 if ((src_rect->width > (uint32_t)(vpe_priv->vpe_num_instance * VPE_MIN_VIEWPORT_SIZE)) &&
238 (num_segs % vpe_priv->vpe_num_instance != 0)) {
239 num_segs += (vpe_priv->vpe_num_instance - (num_segs % vpe_priv->vpe_num_instance));
240 }
241
242 stream_ctx->segment_ctx = vpe_alloc_segment_ctx(vpe_priv, num_segs);
243 if (!stream_ctx->segment_ctx)
244 return VPE_STATUS_NO_MEMORY;
245
246 stream_ctx->num_segments = num_segs;
247
248 return VPE_STATUS_OK;
249 }
250