1## SPDX-License-Identifier: GPL-2.0-only 2 3config MICROCODE_UPDATE_PRE_RAM 4 bool 5 depends on SUPPORT_CPU_UCODE_IN_CBFS 6 default n if CPU_INTEL_FIRMWARE_INTERFACE_TABLE 7 default y 8 help 9 Select this option if you want to update the microcode 10 during the cache as RAM setup. 11 12config RELOAD_MICROCODE_PATCH 13 bool 14 default n 15 help 16 Select this option if SoC recommends to re-load microcode 17 patch as part of CPU multiprocessor initialization process. 18 This feature is mostly required with Intel latest generation 19 processors starting with Alder Lake (with modified MCHECK init 20 flow). 21 22config CPU_INTEL_MICROCODE_CBFS_SPLIT_BINS 23 bool "For Intel CPU, include microcode per CPUID into CBFS" 24 depends on CBFS_VERIFICATION && !MICROCODE_UPDATE_PRE_RAM 25 default n 26 help 27 This option controls whether to include external microcode binaries per 28 CPUID in CBFS. 29 30 The current approach of loading microcode blobs post CPU reset is to search 31 the unified blob in the CBFS and then perform the CBFS verification. The bigger 32 the unified microcode blob in size the longer it takes to perform the verification. 33 34 Select this option to store the split microcode blobs per CPUID in the CBFS. 35 As the microcode blobs will be divided into smaller chunks per CPUID, which will 36 reduce the overall search, verify and load time. 37 38 The microcode file may be removed from the ROM image at a later 39 time with cbfstool, if desired. 40 41 If unsure, and applicable, select "Generate from tree" 42 43config CPU_INTEL_UCODE_SPLIT_BINARIES 44 string "Specify the split microcode blob directory path" 45 depends on CPU_INTEL_MICROCODE_CBFS_SPLIT_BINS 46 default "" 47 help 48 Provide the split microcode blob directory path if 49 CPU_INTEL_MICROCODE_CBFS_SPLIT_BINS config is enabled. 50 51 CPU_INTEL_MICROCODE_CBFS_SPLIT_BINS config is allowed to pack the individual microcode 52 patch file per CPUID inside the CBFS. 53 54 Intel distributes CPU microcode updates based on CPUID as part of the github repository 55 in INC format and expects it also getting used in binary form. 56 57 For example: Intel CPU microcode `m506e3.inc` is getting converted into F-MO-S 58 (06-5e-03) binary file for Linux kernel. 59 60 `MicrocodeConverter` is an Intel-provided tool for converting binary form MCU into 61 several other common formats for integration. 62 63 Implementation logic behind CPU_INTEL_MICROCODE_CBFS_SPLIT_BINS config relies on 64 converting Intel CPU microcode INC file into the binary file as per format specified 65 here `cpu_microcode_$(CPUID).bin`. For example: Intel CPU microcode `m506e3.inc` to 66 convert into `cpu_microcode_506e3.bin` binary file for coreboot to integrate if 67 CPU_INTEL_MICROCODE_CBFS_SPLIT_BINS config is enabled. 68 69 This config provides the directory name (including path) that holds the split microcode 70 binary files per CPUID as mentioned above for each coreboot variants. For example: if 71 google/kunimitsu had built with Intel SkyLake processor with CPUID `506e3` and `506e4` 72 then CPU_INTEL_UCODE_SPLIT_BINARIES refers to the directory path that holds the split 73 microcode binary files aka `cpu_microcode_506e3.bin` and `cpu_microcode_506e4.bin`. 74 75 CONFIG_CPU_UCODE_SPLIT_BINARIES="3rdparty/blobs/mainboard/google/kunimitsu/microcode_inputs/kunimitsu" 76 Refer to the file representation below: 77 |---3rdparty 78 | |--- blobs 79 | | |--- mainboard 80 | | | |--- google 81 | | | | |--- kunimitsu 82 | | | | | |--- microcode_inputs 83 | | | | | | |--- kunimitsu 84 | | | | | | | |--- cpu_microcode_506e3.bin 85 | | | | | | | |--- cpu_microcode_506e4.bin 86 87 Users of this config option requires to manually place the microcode binary files per 88 CPUIDs as per the given format (`cpu_microcode_$(CPUID).bin`) in a directory. 89 Finally specify the microcode binary directory path using CPU_UCODE_SPLIT_BINARIES 90 config. 91 92 At runtime (either from romstage/ramstage), coreboot read the CPUID and search for the 93 `cpu_microcode_$(CPUID).bin` file (in this example: cpu_microcode_506e3.bin) inside RW 94 CBFS. Eventually able to locate the appropriate `cpu_microcode_$(CPUID).bin` file and 95 perform the verification prior loading into the CPUs (BSP and APs). 96 97 If unsure, leave this blank. 98