1 /* 2 * Copyright (c) 2017-2022 Arm Limited. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to 8 * deal in the Software without restriction, including without limitation the 9 * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or 10 * sell copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in all 14 * copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 19 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 22 * SOFTWARE. 23 */ 24 #ifndef ARM_COMPUTE_CPU_DIRECT_CONV2D_OUTPUT_STAGE_KERNEL_H 25 #define ARM_COMPUTE_CPU_DIRECT_CONV2D_OUTPUT_STAGE_KERNEL_H 26 27 #include "arm_compute/core/KernelDescriptors.h" 28 #include "src/core/common/Macros.h" 29 #include "src/cpu/ICpuKernel.h" 30 31 namespace arm_compute 32 { 33 namespace cpu 34 { 35 namespace kernels 36 { 37 /** Kernel to accumulate the biases, if provided, or downscale in case of quantized input. 38 * 39 * @note We assume bias to be shared 40 * @note For quantized computations (i.e. @p src of S32 type) the output data type for auto-initialization must be passed as part 41 * of the @ref DirectConvolutionLayerOutputStageKernelInfo. 42 */ 43 class CpuDirectConv2dOutputStageKernel : public ICpuKernel<CpuDirectConv2dOutputStageKernel> 44 { 45 public: 46 CpuDirectConv2dOutputStageKernel() = default; 47 ARM_COMPUTE_DISALLOW_COPY_ALLOW_MOVE(CpuDirectConv2dOutputStageKernel); 48 /** Set the accumulate buffer and the biases of the kernel. 49 * 50 * @param[in, out] src Input to add the bias to. If @p dst is not specified then accumulation is done in-place. 51 * Data type supported: F16/F32/S32 52 * @param[in] bias (Optional) The shared bias tensor to add. It must be 1D Tensor. Data type supported: Same as @p src 53 * @param[out] dst (Optional) If the dst tensor is specified the accumulation is done out-of-place. (Defaults to nullptr) 54 * Note that in-place computation is only supported for F16/F32. For S32 this must not be nullptr. 55 * Data type supported: F16/F32 or QASYMM8/QASYMM8_SIGNED if @p src is S32 56 * @param[in] info (Optional) DirectConvolutionLayerOutputStageKernel descriptor metadata 57 */ 58 void configure(ITensorInfo *src, const ITensorInfo *bias = nullptr, ITensorInfo *dst = nullptr, 59 const DirectConvolutionLayerOutputStageKernelInfo &info = DirectConvolutionLayerOutputStageKernelInfo()); 60 /** Static function to check if given info will lead to a valid configuration 61 * 62 * Similar to CpuDirectConv2dOutputStageKernel::configure() 63 * 64 * @return a status 65 */ 66 static Status validate(const ITensorInfo *src, const ITensorInfo *bias = nullptr, const ITensorInfo *dst = nullptr, 67 const DirectConvolutionLayerOutputStageKernelInfo &info = DirectConvolutionLayerOutputStageKernelInfo()); 68 69 // Inherited methods overridden: 70 void run_op(ITensorPack &tensors, const Window &window, const ThreadInfo &info) override; 71 const char *name() const override; 72 73 private: 74 using OutputStageKernel = void(ITensor *src, const ITensor *bias, const Window &window, ITensor *dst, 75 int result_fixedpoint_multiplier, int result_shift, int result_offset_after_shift); 76 77 OutputStageKernel *_func{ nullptr }; 78 int _result_fixedpoint_multiplier{ 0 }; 79 int _result_shift{ 0 }; 80 int _result_offset_after_shift{ 0 }; 81 }; 82 } // namespace kernels 83 } // namespace cpu 84 } // namespace arm_compute 85 #endif /* ARM_COMPUTE_CPU_DIRECT_CONV2D_OUTPUT_STAGE_KERNEL_H */ 86