1// Copyright 2020 Google LLC 2// 3// This source code is licensed under the BSD-style license found in the 4// LICENSE file in the root directory of this source tree. 5 6$assert NR == 2 7$assert MR % 2 == 0 8$assert ACTIVATION != "MINMAX" or ARCH in ["ARM", "X86", "RELAXED"] 9$assert not FMA or ARCH == "RELAXED" 10#include <assert.h> 11 12#include <wasm_simd128.h> 13 14#include <xnnpack/igemm.h> 15 16 17$assert ACTIVATION in ["LINEAR", "RELU", "MINMAX"] 18$if ACTIVATION == "MINMAX": 19$ WASM_F32X4_MIN={"ARM": "wasm_f32x4_min", "X86": "wasm_f32x4_pmin", "RELAXED": "__builtin_wasm_relaxed_min_f32x4"}[ARCH] 20$ WASM_F32X4_MAX={"ARM": "wasm_f32x4_max", "X86": "wasm_f32x4_pmax", "RELAXED": "__builtin_wasm_relaxed_max_f32x4"}[ARCH] 21$ACTIVATION_SUFFIX = {"LINEAR": ""}.get(ACTIVATION, "_" + ACTIVATION.lower()) 22$ISA = "wasmsimd" if not FMA and (ACTIVATION in ["LINEAR", "RELU"] or ARCH != "RELAXED") else "wasmrelaxedsimd" 23$ARCH_SUFFIX = "" if not FMA and (ACTIVATION in ["LINEAR", "RELU"] or ARCH == "RELAXED") else "_" + ("fma" if FMA else ARCH.lower()) 24$PARAMS = {"LINEAR": "xnn_f32_default_params", "RELU": "xnn_f32_relu_params", "MINMAX": "xnn_f32_minmax_params"}[ACTIVATION] 25void xnn_f32_igemm${ACTIVATION_SUFFIX}_ukernel_${MR}x${NR}c4__${ISA}${ARCH_SUFFIX}( 26 size_t mr, 27 size_t nc, 28 size_t kc, 29 size_t ks, 30 const float**restrict a, 31 const float*restrict w, 32 float*restrict c, 33 size_t cm_stride, 34 size_t cn_stride, 35 size_t a_offset, 36 const float* zero, 37 const union ${PARAMS} params[restrict XNN_MIN_ELEMENTS(1)]) XNN_OOB_READS 38{ 39 assert(mr != 0); 40 assert(mr <= ${MR}); 41 assert(nc != 0); 42 assert(kc != 0); 43 assert(kc % sizeof(float) == 0); 44 assert(ks != 0); 45 assert(ks % (${MR} * sizeof(void*)) == 0); 46 assert(a_offset % sizeof(float) == 0); 47 assert(a != NULL); 48 assert(w != NULL); 49 assert(c != NULL); 50 51 float* c0 = c; 52 $for M in range(1, MR): 53 float* c${M} = (float*) ((uintptr_t) c${M-1} + cm_stride); 54 $if M % 2 == 0: 55 if XNN_UNPREDICTABLE(mr <= ${M}) { 56 c${M} = c${M-1}; 57 } 58 $elif M + 1 == MR: 59 if XNN_UNPREDICTABLE(mr != ${M+1}) { 60 c${M} = c${M-1}; 61 } 62 $else: 63 if XNN_UNPREDICTABLE(mr < ${M+1}) { 64 c${M} = c${M-1}; 65 } 66 67 $if ACTIVATION == "MINMAX": 68 const v128_t vmin = wasm_v128_load64_splat(params->wasmsimd.min); 69 const v128_t vmax = wasm_v128_load64_splat(params->wasmsimd.max); 70 do { 71 v128_t vacc0x0c4 = wasm_f32x4_replace_lane(wasm_f32x4_const_splat(0.0f), 0, w[0]); 72 $for N in range(1, NR): 73 v128_t vacc0x${N}c4 = wasm_f32x4_replace_lane(vacc0x0c4, 0, w[${N}]); 74 $for M in range(1, MR): 75 $for N in range(NR): 76 v128_t vacc${M}x${N}c4 = vacc0x${N}c4; 77 w += ${NR}; 78 79 size_t p = ks; 80 do { 81 $for M in range(MR): 82 const float* restrict a${M} = a[${M}]; 83 assert(a${M} != NULL); 84 if XNN_UNPREDICTABLE(a${M} != zero) { 85 a${M} = (const float*) ((uintptr_t) a${M} + a_offset); 86 } 87 a += ${MR}; 88 89 size_t k = kc; 90 for (; k >= 4 * sizeof(float); k -= 4 * sizeof(float)) { 91 $for M in range(MR): 92 const v128_t va${M} = wasm_v128_load(a${M}); 93 a${M} += 4; 94 95 const v128_t vb0 = wasm_v128_load(w); 96 $for N in range(1, NR): 97 const v128_t vb${N} = wasm_v128_load(w + ${N * 4}); 98 w += ${NR * 4}; 99 100 $for M in range(MR): 101 $for N in range(NR): 102 $if FMA: 103 vacc${M}x${N}c4 = __builtin_wasm_fma_f32x4(vacc${M}x${N}c4, va${M}, vb${N}); 104 $else: 105 vacc${M}x${N}c4 = wasm_f32x4_add(vacc${M}x${N}c4, wasm_f32x4_mul(va${M}, vb${N})); 106 } 107 if XNN_UNLIKELY(k != 0) { 108 $for M in range(MR): 109 const v128_t va${M} = wasm_v128_load(a${M}); 110 111 const v128_t vb0 = wasm_v128_load(w); 112 $for N in range(1, NR): 113 const v128_t vb${N} = wasm_v128_load(w + ${N * 4}); 114 w += ${NR * 4}; 115 116 const v128_t vzero = wasm_f32x4_const_splat(0.0f); 117 $for N in range(NR): 118 const v128_t vmask${N} = wasm_f32x4_eq(vb${N}, vzero); 119 120 $for M in range(MR): 121 $for N in range(NR): 122 $if FMA: 123 vacc${M}x${N}c4 = __builtin_wasm_fma_f32x4(vacc${M}x${N}c4, wasm_v128_andnot(va${M}, vmask${N}), vb${N}); 124 $else: 125 vacc${M}x${N}c4 = wasm_f32x4_add(vacc${M}x${N}c4, wasm_f32x4_mul(wasm_v128_andnot(va${M}, vmask${N}), vb${N})); 126 } 127 p -= ${MR} * sizeof(void*); 128 } while (p != 0); 129 130 $for M in range(MR): 131 const v128_t vacc${M}x01c2 = wasm_f32x4_add( 132 wasm_v32x4_shuffle(vacc${M}x0c4, vacc${M}x1c4, 0, 4, 1, 5), 133 wasm_v32x4_shuffle(vacc${M}x0c4, vacc${M}x1c4, 2, 6, 3, 7)); 134 135 $for M in range(0, MR, 2): 136 v128_t vacc${M}${M+1}x01 = wasm_f32x4_add( 137 wasm_v32x4_shuffle(vacc${M}x01c2, vacc${M+1}x01c2, 0, 1, 4, 5), 138 wasm_v32x4_shuffle(vacc${M}x01c2, vacc${M+1}x01c2, 2, 3, 6, 7)); 139 140 $if ACTIVATION == "MINMAX": 141 $for M in range(0, MR, 2): 142 vacc${M}${M+1}x01 = ${WASM_F32X4_MAX}(vmin, vacc${M}${M+1}x01); 143 144 $for M in range(0, MR, 2): 145 vacc${M}${M+1}x01 = ${WASM_F32X4_MIN}(vmax, vacc${M}${M+1}x01); 146 $elif ACTIVATION == "RELU": 147 const v128_t vzero = wasm_i32x4_const_splat(0); 148 $for M in range(0, MR, 2): 149 vacc${M}${M+1}x01 = wasm_i32x4_max(vacc${M}${M+1}x01, vzero); 150 151 if XNN_LIKELY(nc >= ${NR}) { 152 $for M in reversed(range(0, MR, 2)): 153 *((double*) c${M+1}) = wasm_f64x2_extract_lane(vacc${M}${M+1}x01, 1); 154 c${M+1} = (float*) ((uintptr_t) c${M+1} + cn_stride); 155 *((double*) c${M}) = wasm_f64x2_extract_lane(vacc${M}${M+1}x01, 0); 156 c${M} = (float*) ((uintptr_t) c${M} + cn_stride); 157 158 a = (const float**restrict) ((uintptr_t) a - ks); 159 nc -= ${NR}; 160 } else { 161 assert(nc == 1); 162 $for M in reversed(range(0, MR, 2)): 163 *c${M+1} = wasm_f32x4_extract_lane(vacc${M}${M+1}x01, 2); 164 *c${M} = wasm_f32x4_extract_lane(vacc${M}${M+1}x01, 0); 165 166 nc = 0; 167 } 168 } while (nc != 0); 169} 170