1 /* 2 ************************************************************************************************************************ 3 * 4 * Copyright (C) 2007-2022 Advanced Micro Devices, Inc. All rights reserved. 5 * SPDX-License-Identifier: MIT 6 * 7 ***********************************************************************************************************************/ 8 9 /** 10 ************************************************************************************************************************ 11 * @file gfx10addrlib.h 12 * @brief Contains the Gfx10Lib class definition. 13 ************************************************************************************************************************ 14 */ 15 16 #ifndef __GFX10_ADDR_LIB_H__ 17 #define __GFX10_ADDR_LIB_H__ 18 19 #include "addrlib2.h" 20 #include "coord.h" 21 #include "gfx10SwizzlePattern.h" 22 23 namespace Addr 24 { 25 namespace V2 26 { 27 28 /** 29 ************************************************************************************************************************ 30 * @brief GFX10 specific settings structure. 31 ************************************************************************************************************************ 32 */ 33 struct Gfx10ChipSettings 34 { 35 struct 36 { 37 UINT_32 reserved1 : 32; 38 39 // Misc configuration bits 40 UINT_32 isDcn20 : 1; // If using DCN2.0 41 UINT_32 supportRbPlus : 1; 42 UINT_32 dsMipmapHtileFix : 1; 43 UINT_32 dccUnsup3DSwDis : 1; 44 UINT_32 : 4; 45 UINT_32 reserved2 : 24; 46 }; 47 }; 48 49 /** 50 ************************************************************************************************************************ 51 * @brief GFX10 data surface type. 52 ************************************************************************************************************************ 53 */ 54 enum Gfx10DataType 55 { 56 Gfx10DataColor, 57 Gfx10DataDepthStencil, 58 Gfx10DataFmask 59 }; 60 61 const UINT_32 Gfx10LinearSwModeMask = (1u << ADDR_SW_LINEAR); 62 63 const UINT_32 Gfx10Blk256BSwModeMask = (1u << ADDR_SW_256B_S) | 64 (1u << ADDR_SW_256B_D); 65 66 const UINT_32 Gfx10Blk4KBSwModeMask = (1u << ADDR_SW_4KB_S) | 67 (1u << ADDR_SW_4KB_D) | 68 (1u << ADDR_SW_4KB_S_X) | 69 (1u << ADDR_SW_4KB_D_X); 70 71 const UINT_32 Gfx10Blk64KBSwModeMask = (1u << ADDR_SW_64KB_S) | 72 (1u << ADDR_SW_64KB_D) | 73 (1u << ADDR_SW_64KB_S_T) | 74 (1u << ADDR_SW_64KB_D_T) | 75 (1u << ADDR_SW_64KB_Z_X) | 76 (1u << ADDR_SW_64KB_S_X) | 77 (1u << ADDR_SW_64KB_D_X) | 78 (1u << ADDR_SW_64KB_R_X); 79 80 const UINT_32 Gfx10BlkVarSwModeMask = (1u << ADDR_SW_VAR_Z_X) | 81 (1u << ADDR_SW_VAR_R_X); 82 83 const UINT_32 Gfx10ZSwModeMask = (1u << ADDR_SW_64KB_Z_X) | 84 (1u << ADDR_SW_VAR_Z_X); 85 86 const UINT_32 Gfx10StandardSwModeMask = (1u << ADDR_SW_256B_S) | 87 (1u << ADDR_SW_4KB_S) | 88 (1u << ADDR_SW_64KB_S) | 89 (1u << ADDR_SW_64KB_S_T) | 90 (1u << ADDR_SW_4KB_S_X) | 91 (1u << ADDR_SW_64KB_S_X); 92 93 const UINT_32 Gfx10DisplaySwModeMask = (1u << ADDR_SW_256B_D) | 94 (1u << ADDR_SW_4KB_D) | 95 (1u << ADDR_SW_64KB_D) | 96 (1u << ADDR_SW_64KB_D_T) | 97 (1u << ADDR_SW_4KB_D_X) | 98 (1u << ADDR_SW_64KB_D_X); 99 100 const UINT_32 Gfx10RenderSwModeMask = (1u << ADDR_SW_64KB_R_X) | 101 (1u << ADDR_SW_VAR_R_X); 102 103 const UINT_32 Gfx10XSwModeMask = (1u << ADDR_SW_4KB_S_X) | 104 (1u << ADDR_SW_4KB_D_X) | 105 (1u << ADDR_SW_64KB_Z_X) | 106 (1u << ADDR_SW_64KB_S_X) | 107 (1u << ADDR_SW_64KB_D_X) | 108 (1u << ADDR_SW_64KB_R_X) | 109 Gfx10BlkVarSwModeMask; 110 111 const UINT_32 Gfx10TSwModeMask = (1u << ADDR_SW_64KB_S_T) | 112 (1u << ADDR_SW_64KB_D_T); 113 114 const UINT_32 Gfx10XorSwModeMask = Gfx10XSwModeMask | 115 Gfx10TSwModeMask; 116 117 const UINT_32 Gfx10Rsrc1dSwModeMask = Gfx10LinearSwModeMask | 118 Gfx10RenderSwModeMask | 119 Gfx10ZSwModeMask; 120 121 const UINT_32 Gfx10Rsrc2dSwModeMask = Gfx10LinearSwModeMask | 122 Gfx10Blk256BSwModeMask | 123 Gfx10Blk4KBSwModeMask | 124 Gfx10Blk64KBSwModeMask | 125 Gfx10BlkVarSwModeMask; 126 127 const UINT_32 Gfx10Rsrc3dSwModeMask = (1u << ADDR_SW_LINEAR) | 128 (1u << ADDR_SW_4KB_S) | 129 (1u << ADDR_SW_64KB_S) | 130 (1u << ADDR_SW_64KB_S_T) | 131 (1u << ADDR_SW_4KB_S_X) | 132 (1u << ADDR_SW_64KB_Z_X) | 133 (1u << ADDR_SW_64KB_S_X) | 134 (1u << ADDR_SW_64KB_D_X) | 135 (1u << ADDR_SW_64KB_R_X) | 136 Gfx10BlkVarSwModeMask; 137 138 const UINT_32 Gfx10Rsrc2dPrtSwModeMask = (Gfx10Blk4KBSwModeMask | Gfx10Blk64KBSwModeMask) & ~Gfx10XSwModeMask; 139 140 const UINT_32 Gfx10Rsrc3dPrtSwModeMask = Gfx10Rsrc2dPrtSwModeMask & ~Gfx10DisplaySwModeMask; 141 142 const UINT_32 Gfx10Rsrc3dThin64KBSwModeMask = (1u << ADDR_SW_64KB_Z_X) | 143 (1u << ADDR_SW_64KB_R_X); 144 145 146 const UINT_32 Gfx10Rsrc3dThinSwModeMask = Gfx10Rsrc3dThin64KBSwModeMask | 147 Gfx10BlkVarSwModeMask; 148 149 const UINT_32 Gfx10Rsrc3dViewAs2dSwModeMask = Gfx10Rsrc3dThinSwModeMask | Gfx10LinearSwModeMask; 150 151 const UINT_32 Gfx10Rsrc3dThickSwModeMask = Gfx10Rsrc3dSwModeMask & ~(Gfx10Rsrc3dThinSwModeMask | Gfx10LinearSwModeMask); 152 153 const UINT_32 Gfx10Rsrc3dThick4KBSwModeMask = Gfx10Rsrc3dThickSwModeMask & Gfx10Blk4KBSwModeMask; 154 155 const UINT_32 Gfx10Rsrc3dThick64KBSwModeMask = Gfx10Rsrc3dThickSwModeMask & Gfx10Blk64KBSwModeMask; 156 157 const UINT_32 Gfx10MsaaSwModeMask = (Gfx10ZSwModeMask | 158 Gfx10RenderSwModeMask) 159 ; 160 161 const UINT_32 Dcn20NonBpp64SwModeMask = (1u << ADDR_SW_LINEAR) | 162 (1u << ADDR_SW_4KB_S) | 163 (1u << ADDR_SW_64KB_S) | 164 (1u << ADDR_SW_64KB_S_T) | 165 (1u << ADDR_SW_4KB_S_X) | 166 (1u << ADDR_SW_64KB_S_X) | 167 (1u << ADDR_SW_64KB_R_X); 168 169 const UINT_32 Dcn20Bpp64SwModeMask = (1u << ADDR_SW_4KB_D) | 170 (1u << ADDR_SW_64KB_D) | 171 (1u << ADDR_SW_64KB_D_T) | 172 (1u << ADDR_SW_4KB_D_X) | 173 (1u << ADDR_SW_64KB_D_X) | 174 Dcn20NonBpp64SwModeMask; 175 176 const UINT_32 Dcn21NonBpp64SwModeMask = (1u << ADDR_SW_LINEAR) | 177 (1u << ADDR_SW_64KB_S) | 178 (1u << ADDR_SW_64KB_S_T) | 179 (1u << ADDR_SW_64KB_S_X) | 180 (1u << ADDR_SW_64KB_R_X); 181 182 const UINT_32 Dcn21Bpp64SwModeMask = (1u << ADDR_SW_64KB_D) | 183 (1u << ADDR_SW_64KB_D_T) | 184 (1u << ADDR_SW_64KB_D_X) | 185 Dcn21NonBpp64SwModeMask; 186 187 /** 188 ************************************************************************************************************************ 189 * @brief This class is the GFX10 specific address library 190 * function set. 191 ************************************************************************************************************************ 192 */ 193 class Gfx10Lib : public Lib 194 { 195 public: 196 /// Creates Gfx10Lib object CreateObj(const Client * pClient)197 static Addr::Lib* CreateObj(const Client* pClient) 198 { 199 VOID* pMem = Object::ClientAlloc(sizeof(Gfx10Lib), pClient); 200 return (pMem != NULL) ? new (pMem) Gfx10Lib(pClient) : NULL; 201 } 202 203 protected: 204 Gfx10Lib(const Client* pClient); 205 virtual ~Gfx10Lib(); 206 HwlIsStandardSwizzle(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)207 virtual BOOL_32 HwlIsStandardSwizzle( 208 AddrResourceType resourceType, 209 AddrSwizzleMode swizzleMode) const 210 { 211 return m_swizzleModeTable[swizzleMode].isStd; 212 } 213 HwlIsDisplaySwizzle(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)214 virtual BOOL_32 HwlIsDisplaySwizzle( 215 AddrResourceType resourceType, 216 AddrSwizzleMode swizzleMode) const 217 { 218 return m_swizzleModeTable[swizzleMode].isDisp; 219 } 220 HwlIsThin(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)221 virtual BOOL_32 HwlIsThin( 222 AddrResourceType resourceType, 223 AddrSwizzleMode swizzleMode) const 224 { 225 return ((IsTex1d(resourceType) == TRUE) || 226 (IsTex2d(resourceType) == TRUE) || 227 ((IsTex3d(resourceType) == TRUE) && 228 (m_swizzleModeTable[swizzleMode].isStd == FALSE) && 229 (m_swizzleModeTable[swizzleMode].isDisp == FALSE))); 230 } 231 HwlIsThick(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)232 virtual BOOL_32 HwlIsThick( 233 AddrResourceType resourceType, 234 AddrSwizzleMode swizzleMode) const 235 { 236 return ((IsTex3d(resourceType) == TRUE) && 237 (m_swizzleModeTable[swizzleMode].isStd || m_swizzleModeTable[swizzleMode].isDisp)); 238 } 239 240 virtual ADDR_E_RETURNCODE HwlComputeHtileInfo( 241 const ADDR2_COMPUTE_HTILE_INFO_INPUT* pIn, 242 ADDR2_COMPUTE_HTILE_INFO_OUTPUT* pOut) const; 243 244 virtual ADDR_E_RETURNCODE HwlComputeCmaskInfo( 245 const ADDR2_COMPUTE_CMASK_INFO_INPUT* pIn, 246 ADDR2_COMPUTE_CMASK_INFO_OUTPUT* pOut) const; 247 248 virtual ADDR_E_RETURNCODE HwlComputeDccInfo( 249 const ADDR2_COMPUTE_DCCINFO_INPUT* pIn, 250 ADDR2_COMPUTE_DCCINFO_OUTPUT* pOut) const; 251 252 virtual ADDR_E_RETURNCODE HwlComputeCmaskAddrFromCoord( 253 const ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_INPUT* pIn, 254 ADDR2_COMPUTE_CMASK_ADDRFROMCOORD_OUTPUT* pOut); 255 256 virtual ADDR_E_RETURNCODE HwlComputeHtileAddrFromCoord( 257 const ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_INPUT* pIn, 258 ADDR2_COMPUTE_HTILE_ADDRFROMCOORD_OUTPUT* pOut); 259 260 virtual ADDR_E_RETURNCODE HwlComputeHtileCoordFromAddr( 261 const ADDR2_COMPUTE_HTILE_COORDFROMADDR_INPUT* pIn, 262 ADDR2_COMPUTE_HTILE_COORDFROMADDR_OUTPUT* pOut); 263 264 virtual ADDR_E_RETURNCODE HwlSupportComputeDccAddrFromCoord( 265 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn); 266 267 virtual VOID HwlComputeDccAddrFromCoord( 268 const ADDR2_COMPUTE_DCC_ADDRFROMCOORD_INPUT* pIn, 269 ADDR2_COMPUTE_DCC_ADDRFROMCOORD_OUTPUT* pOut); 270 271 virtual UINT_32 HwlGetEquationIndex( 272 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 273 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 274 HwlGetEquationTableInfo(const ADDR_EQUATION ** ppEquationTable)275 virtual UINT_32 HwlGetEquationTableInfo(const ADDR_EQUATION** ppEquationTable) const 276 { 277 *ppEquationTable = m_equationTable; 278 279 return m_numEquations; 280 } 281 282 virtual ADDR_E_RETURNCODE HwlComputePipeBankXor( 283 const ADDR2_COMPUTE_PIPEBANKXOR_INPUT* pIn, 284 ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT* pOut) const; 285 286 virtual ADDR_E_RETURNCODE HwlComputeSlicePipeBankXor( 287 const ADDR2_COMPUTE_SLICE_PIPEBANKXOR_INPUT* pIn, 288 ADDR2_COMPUTE_SLICE_PIPEBANKXOR_OUTPUT* pOut) const; 289 290 virtual ADDR_E_RETURNCODE HwlComputeSubResourceOffsetForSwizzlePattern( 291 const ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_INPUT* pIn, 292 ADDR2_COMPUTE_SUBRESOURCE_OFFSET_FORSWIZZLEPATTERN_OUTPUT* pOut) const; 293 294 virtual ADDR_E_RETURNCODE HwlComputeNonBlockCompressedView( 295 const ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_INPUT* pIn, 296 ADDR2_COMPUTE_NONBLOCKCOMPRESSEDVIEW_OUTPUT* pOut) const; 297 298 virtual ADDR_E_RETURNCODE HwlGetPreferredSurfaceSetting( 299 const ADDR2_GET_PREFERRED_SURF_SETTING_INPUT* pIn, 300 ADDR2_GET_PREFERRED_SURF_SETTING_OUTPUT* pOut) const; 301 302 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoSanityCheck( 303 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 304 305 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoTiled( 306 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 307 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 308 309 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfoLinear( 310 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 311 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 312 313 virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoordTiled( 314 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 315 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const; 316 317 virtual UINT_32 HwlComputeMaxBaseAlignments() const; 318 319 virtual UINT_32 HwlComputeMaxMetaBaseAlignments() const; 320 321 virtual BOOL_32 HwlInitGlobalParams(const ADDR_CREATE_INPUT* pCreateIn); 322 323 virtual ChipFamily HwlConvertChipFamily(UINT_32 uChipFamily, UINT_32 uChipRevision); 324 325 private: 326 // Initialize equation table 327 VOID InitEquationTable(); 328 329 ADDR_E_RETURNCODE ComputeSurfaceInfoMacroTiled( 330 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 331 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 332 333 ADDR_E_RETURNCODE ComputeSurfaceInfoMicroTiled( 334 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 335 ADDR2_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 336 337 ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoordMacroTiled( 338 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 339 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const; 340 341 ADDR_E_RETURNCODE ComputeSurfaceAddrFromCoordMicroTiled( 342 const ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 343 ADDR2_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const; 344 345 UINT_32 ComputeOffsetFromSwizzlePattern( 346 const UINT_64* pPattern, 347 UINT_32 numBits, 348 UINT_32 x, 349 UINT_32 y, 350 UINT_32 z, 351 UINT_32 s) const; 352 353 UINT_32 ComputeOffsetFromEquation( 354 const ADDR_EQUATION* pEq, 355 UINT_32 x, 356 UINT_32 y, 357 UINT_32 z) const; 358 359 ADDR_E_RETURNCODE ComputeStereoInfo( 360 const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn, 361 UINT_32* pAlignY, 362 UINT_32* pRightXor) const; 363 364 static void GetMipSize( 365 UINT_32 mip0Width, 366 UINT_32 mip0Height, 367 UINT_32 mip0Depth, 368 UINT_32 mipId, 369 UINT_32* pMipWidth, 370 UINT_32* pMipHeight, 371 UINT_32* pMipDepth = NULL) 372 { 373 *pMipWidth = ShiftCeil(Max(mip0Width, 1u), mipId); 374 *pMipHeight = ShiftCeil(Max(mip0Height, 1u), mipId); 375 376 if (pMipDepth != NULL) 377 { 378 *pMipDepth = ShiftCeil(Max(mip0Depth, 1u), mipId); 379 } 380 } 381 382 const ADDR_SW_PATINFO* GetSwizzlePatternInfo( 383 AddrSwizzleMode swizzleMode, 384 AddrResourceType resourceType, 385 UINT_32 log2Elem, 386 UINT_32 numFrag) const; 387 388 /** 389 * Will use the indices, "nibbles", to build an index equation inside pSwizzle 390 * 391 * @param pPatInfo Pointer to a patInfo. Contains indices mapping to the 2D nibble arrays which will be used to build an index equation. 392 * @param pSwizzle Array to write the index equation to. 393 */ GetSwizzlePatternFromPatternInfo(const ADDR_SW_PATINFO * pPatInfo,ADDR_BIT_SETTING (& pSwizzle)[20])394 VOID GetSwizzlePatternFromPatternInfo( 395 const ADDR_SW_PATINFO* pPatInfo, 396 ADDR_BIT_SETTING (&pSwizzle)[20]) const 397 { 398 memcpy(pSwizzle, 399 GFX10_SW_PATTERN_NIBBLE01[pPatInfo->nibble01Idx], 400 sizeof(GFX10_SW_PATTERN_NIBBLE01[pPatInfo->nibble01Idx])); 401 402 memcpy(&pSwizzle[8], 403 GFX10_SW_PATTERN_NIBBLE2[pPatInfo->nibble2Idx], 404 sizeof(GFX10_SW_PATTERN_NIBBLE2[pPatInfo->nibble2Idx])); 405 406 memcpy(&pSwizzle[12], 407 GFX10_SW_PATTERN_NIBBLE3[pPatInfo->nibble3Idx], 408 sizeof(GFX10_SW_PATTERN_NIBBLE3[pPatInfo->nibble3Idx])); 409 410 memcpy(&pSwizzle[16], 411 GFX10_SW_PATTERN_NIBBLE4[pPatInfo->nibble4Idx], 412 sizeof(GFX10_SW_PATTERN_NIBBLE4[pPatInfo->nibble4Idx])); 413 } 414 415 VOID ConvertSwizzlePatternToEquation( 416 UINT_32 elemLog2, 417 AddrResourceType rsrcType, 418 AddrSwizzleMode swMode, 419 const ADDR_SW_PATINFO* pPatInfo, 420 ADDR_EQUATION* pEquation) const; 421 422 static INT_32 GetMetaElementSizeLog2(Gfx10DataType dataType); 423 424 static INT_32 GetMetaCacheSizeLog2(Gfx10DataType dataType); 425 426 void GetBlk256SizeLog2( 427 AddrResourceType resourceType, 428 AddrSwizzleMode swizzleMode, 429 UINT_32 elemLog2, 430 UINT_32 numSamplesLog2, 431 Dim3d* pBlock) const; 432 433 void GetCompressedBlockSizeLog2( 434 Gfx10DataType dataType, 435 AddrResourceType resourceType, 436 AddrSwizzleMode swizzleMode, 437 UINT_32 elemLog2, 438 UINT_32 numSamplesLog2, 439 Dim3d* pBlock) const; 440 441 INT_32 GetMetaOverlapLog2( 442 Gfx10DataType dataType, 443 AddrResourceType resourceType, 444 AddrSwizzleMode swizzleMode, 445 UINT_32 elemLog2, 446 UINT_32 numSamplesLog2) const; 447 448 INT_32 Get3DMetaOverlapLog2( 449 AddrResourceType resourceType, 450 AddrSwizzleMode swizzleMode, 451 UINT_32 elemLog2) const; 452 453 UINT_32 GetMetaBlkSize( 454 Gfx10DataType dataType, 455 AddrResourceType resourceType, 456 AddrSwizzleMode swizzleMode, 457 UINT_32 elemLog2, 458 UINT_32 numSamplesLog2, 459 BOOL_32 pipeAlign, 460 Dim3d* pBlock) const; 461 462 INT_32 GetPipeRotateAmount( 463 AddrResourceType resourceType, 464 AddrSwizzleMode swizzleMode) const; 465 GetEffectiveNumPipes()466 INT_32 GetEffectiveNumPipes() const 467 { 468 return ((m_settings.supportRbPlus == FALSE) || 469 ((m_numSaLog2 + 1) >= m_pipesLog2)) ? m_pipesLog2 : m_numSaLog2 + 1; 470 } 471 IsRbAligned(AddrResourceType resourceType,AddrSwizzleMode swizzleMode)472 BOOL_32 IsRbAligned( 473 AddrResourceType resourceType, 474 AddrSwizzleMode swizzleMode) const 475 { 476 const BOOL_32 isRtopt = IsRtOptSwizzle(swizzleMode); 477 const BOOL_32 isZ = IsZOrderSwizzle(swizzleMode); 478 const BOOL_32 isDisplay = IsDisplaySwizzle(swizzleMode); 479 480 return (IsTex2d(resourceType) && (isRtopt || isZ)) || 481 (IsTex3d(resourceType) && isDisplay); 482 483 } 484 485 UINT_32 GetValidDisplaySwizzleModes(UINT_32 bpp) const; 486 487 BOOL_32 IsValidDisplaySwizzleMode(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 488 489 UINT_32 GetMaxNumMipsInTail(UINT_32 blockSizeLog2, BOOL_32 isThin) const; 490 GetAllowedBlockSet(ADDR2_SWMODE_SET allowedSwModeSet,AddrResourceType rsrcType)491 static ADDR2_BLOCK_SET GetAllowedBlockSet(ADDR2_SWMODE_SET allowedSwModeSet, AddrResourceType rsrcType) 492 { 493 ADDR2_BLOCK_SET allowedBlockSet = {}; 494 495 allowedBlockSet.micro = (allowedSwModeSet.value & Gfx10Blk256BSwModeMask) ? TRUE : FALSE; 496 allowedBlockSet.linear = (allowedSwModeSet.value & Gfx10LinearSwModeMask) ? TRUE : FALSE; 497 allowedBlockSet.var = (allowedSwModeSet.value & Gfx10BlkVarSwModeMask) ? TRUE : FALSE; 498 499 if (rsrcType == ADDR_RSRC_TEX_3D) 500 { 501 allowedBlockSet.macroThick4KB = (allowedSwModeSet.value & Gfx10Rsrc3dThick4KBSwModeMask) ? TRUE : FALSE; 502 allowedBlockSet.macroThin64KB = (allowedSwModeSet.value & Gfx10Rsrc3dThin64KBSwModeMask) ? TRUE : FALSE; 503 allowedBlockSet.macroThick64KB = (allowedSwModeSet.value & Gfx10Rsrc3dThick64KBSwModeMask) ? TRUE : FALSE; 504 } 505 else 506 { 507 allowedBlockSet.macroThin4KB = (allowedSwModeSet.value & Gfx10Blk4KBSwModeMask) ? TRUE : FALSE; 508 allowedBlockSet.macroThin64KB = (allowedSwModeSet.value & Gfx10Blk64KBSwModeMask) ? TRUE : FALSE; 509 } 510 511 return allowedBlockSet; 512 } 513 GetAllowedSwSet(ADDR2_SWMODE_SET allowedSwModeSet)514 static ADDR2_SWTYPE_SET GetAllowedSwSet(ADDR2_SWMODE_SET allowedSwModeSet) 515 { 516 ADDR2_SWTYPE_SET allowedSwSet = {}; 517 518 allowedSwSet.sw_Z = (allowedSwModeSet.value & Gfx10ZSwModeMask) ? TRUE : FALSE; 519 allowedSwSet.sw_S = (allowedSwModeSet.value & Gfx10StandardSwModeMask) ? TRUE : FALSE; 520 allowedSwSet.sw_D = (allowedSwModeSet.value & Gfx10DisplaySwModeMask) ? TRUE : FALSE; 521 allowedSwSet.sw_R = (allowedSwModeSet.value & Gfx10RenderSwModeMask) ? TRUE : FALSE; 522 523 return allowedSwSet; 524 } 525 IsInMipTail(Dim3d mipTailDim,UINT_32 maxNumMipsInTail,UINT_32 mipWidth,UINT_32 mipHeight,UINT_32 numMipsToTheEnd)526 BOOL_32 IsInMipTail( 527 Dim3d mipTailDim, 528 UINT_32 maxNumMipsInTail, 529 UINT_32 mipWidth, 530 UINT_32 mipHeight, 531 UINT_32 numMipsToTheEnd) const 532 { 533 BOOL_32 inTail = ((mipWidth <= mipTailDim.w) && 534 (mipHeight <= mipTailDim.h) && 535 (numMipsToTheEnd <= maxNumMipsInTail)); 536 537 return inTail; 538 } 539 GetBankXorBits(UINT_32 blockBits)540 UINT_32 GetBankXorBits(UINT_32 blockBits) const 541 { 542 return (blockBits > m_pipeInterleaveLog2 + m_pipesLog2 + ColumnBits) ? 543 Min(blockBits - m_pipeInterleaveLog2 - m_pipesLog2 - ColumnBits, BankBits) : 0; 544 } 545 546 BOOL_32 ValidateNonSwModeParams(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 547 BOOL_32 ValidateSwModeParams(const ADDR2_COMPUTE_SURFACE_INFO_INPUT* pIn) const; 548 549 static const UINT_32 ColumnBits = 2; 550 static const UINT_32 BankBits = 4; 551 static const UINT_32 UnalignedDccType = 3; 552 553 static const Dim3d Block256_3d[MaxNumOfBpp]; 554 static const Dim3d Block64K_Log2_3d[MaxNumOfBpp]; 555 static const Dim3d Block4K_Log2_3d[MaxNumOfBpp]; 556 557 static const SwizzleModeFlags SwizzleModeTable[ADDR_SW_MAX_TYPE]; 558 559 // Number of packers log2 560 UINT_32 m_numPkrLog2; 561 // Number of shader array log2 562 UINT_32 m_numSaLog2; 563 564 Gfx10ChipSettings m_settings; 565 566 UINT_32 m_colorBaseIndex; 567 UINT_32 m_xmaskBaseIndex; 568 UINT_32 m_htileBaseIndex; 569 UINT_32 m_dccBaseIndex; 570 }; 571 572 } // V2 573 } // Addr 574 575 #endif 576 577