1FLASH 16M { 2 WP_RO@0x0 0x400000 { 3 SI_DESC@0x0 0x1000 4 IFWI@0x1000 0x1ff000 5 RO_VPD(PRESERVE)@0x200000 0x4000 6 RO_SECTION@0x204000 0x1fc000 { 7 FMAP@0x0 0x800 8 RO_FRID@0x800 0x40 9 RO_FRID_PAD@0x840 0x7c0 10 COREBOOT(CBFS)@0x1000 0x1f8000 11 GBB@0x1f9000 0x3000 12 } 13 } 14 MISC_RW@0x400000 0x30000 { 15 RW_PRESERVE(PRESERVE) { 16 UNIFIED_MRC_CACHE@0x0 0x21000 { 17 RECOVERY_MRC_CACHE@0x0 0x10000 18 RW_MRC_CACHE@0x10000 0x10000 19 RW_VAR_MRC_CACHE@0x20000 0x1000 20 } 21 } 22 RW_ELOG(PRESERVE)@0x21000 0x3000 23 RW_SHARED@0x24000 0x4000 { 24 SHARED_DATA@0x0 0x2000 25 VBLOCK_DEV@0x2000 0x2000 26 } 27 RW_VPD(PRESERVE)@0x28000 0x2000 28 RW_NVRAM(PRESERVE)@0x2a000 0x5000 29 FPF_STATUS@0x2f000 0x1000 30 } 31 RW_SECTION_A@0x430000 0x480000 { 32 VBLOCK_A@0x0 0x10000 33 FW_MAIN_A(CBFS)@0x10000 0x46ffc0 34 RW_FWID_A@0x47ffc0 0x40 35 } 36 RW_SECTION_B@0x8b0000 0x480000 { 37 VBLOCK_B@0x0 0x10000 38 FW_MAIN_B(CBFS)@0x10000 0x46ffc0 39 RW_FWID_B@0x47ffc0 0x40 40 } 41 SMMSTORE(PRESERVE)@0xd30000 0x40000 42 RW_LEGACY(CBFS)@0xd70000 0x1c0000 43 BIOS_UNUSABLE@0xf30000 0x4f000 44 DEVICE_EXTENSION@0xf7f000 0x80000 45 # Currently, it is required that the BIOS region be a multiple of 8KiB. 46 # This is required so that the recovery mechanism can find SIGN_CSE 47 # region aligned to 4K at the center of BIOS region. Since the 48 # descriptor at the beginning uses 4K and BIOS starts at an offset of 49 # 4K, a hole of 4K is created towards the end of the flash to compensate 50 # for the size requirement of BIOS region. 51 # FIT tool thus creates descriptor with following regions: 52 # Descriptor --> 0 to 4K 53 # BIOS --> 4K to 0xf7f000 54 # Device ext --> 0xf7f000 to 0xfff000 55 UNUSED_HOLE@0xfff000 0x1000 56} 57