1 /* 2 ************************************************************************************************************************ 3 * 4 * Copyright (C) 2007-2022 Advanced Micro Devices, Inc. All rights reserved. 5 * SPDX-License-Identifier: MIT 6 * 7 ***********************************************************************************************************************/ 8 9 /** 10 **************************************************************************************************** 11 * @file egbaddrlib.h 12 * @brief Contains the EgBasedLib class definition. 13 **************************************************************************************************** 14 */ 15 16 #ifndef __EG_BASED_ADDR_LIB_H__ 17 #define __EG_BASED_ADDR_LIB_H__ 18 19 #include "addrlib1.h" 20 21 namespace Addr 22 { 23 namespace V1 24 { 25 /// Structures for functions 26 struct CoordFromBankPipe 27 { 28 UINT_32 xBits : 3; 29 UINT_32 yBits : 4; 30 31 UINT_32 xBit3 : 1; 32 UINT_32 xBit4 : 1; 33 UINT_32 xBit5 : 1; 34 UINT_32 yBit3 : 1; 35 UINT_32 yBit4 : 1; 36 UINT_32 yBit5 : 1; 37 UINT_32 yBit6 : 1; 38 }; 39 40 /** 41 **************************************************************************************************** 42 * @brief This class is the Evergreen based address library 43 * @note Abstract class 44 **************************************************************************************************** 45 */ 46 class EgBasedLib : public Lib 47 { 48 protected: 49 EgBasedLib(const Client* pClient); 50 virtual ~EgBasedLib(); 51 52 public: 53 54 /// Surface info functions 55 56 // NOTE: DispatchComputeSurfaceInfo using TileInfo takes both an input and an output. 57 // On input: 58 // One or more fields may be 0 to be calculated/defaulted - pre-SI h/w. 59 // H/W using tile mode index only accepts none or all 0's - SI and newer h/w. 60 // It then returns the actual tiling configuration used. 61 // Other methods' TileInfo must be valid on entry 62 BOOL_32 DispatchComputeSurfaceInfo( 63 const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, 64 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 65 66 ADDR_E_RETURNCODE DispatchComputeFmaskInfo( 67 const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn, 68 ADDR_COMPUTE_FMASK_INFO_OUTPUT* pOut); 69 70 protected: 71 // Hwl interface 72 virtual ADDR_E_RETURNCODE HwlComputeSurfaceInfo( 73 const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, 74 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 75 76 virtual ADDR_E_RETURNCODE HwlComputeSurfaceAddrFromCoord( 77 const ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 78 ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const; 79 80 virtual ADDR_E_RETURNCODE HwlComputeSurfaceCoordFromAddr( 81 const ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn, 82 ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const; 83 84 virtual ADDR_E_RETURNCODE HwlComputeSliceTileSwizzle( 85 const ADDR_COMPUTE_SLICESWIZZLE_INPUT* pIn, 86 ADDR_COMPUTE_SLICESWIZZLE_OUTPUT* pOut) const; 87 88 virtual ADDR_E_RETURNCODE HwlExtractBankPipeSwizzle( 89 const ADDR_EXTRACT_BANKPIPE_SWIZZLE_INPUT* pIn, 90 ADDR_EXTRACT_BANKPIPE_SWIZZLE_OUTPUT* pOut) const; 91 92 virtual ADDR_E_RETURNCODE HwlCombineBankPipeSwizzle( 93 UINT_32 bankSwizzle, UINT_32 pipeSwizzle, ADDR_TILEINFO* pTileInfo, 94 UINT_64 baseAddr, UINT_32* pTileSwizzle) const; 95 96 virtual ADDR_E_RETURNCODE HwlComputeBaseSwizzle( 97 const ADDR_COMPUTE_BASE_SWIZZLE_INPUT* pIn, 98 ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT* pOut) const; 99 100 virtual ADDR_E_RETURNCODE HwlConvertTileInfoToHW( 101 const ADDR_CONVERT_TILEINFOTOHW_INPUT* pIn, 102 ADDR_CONVERT_TILEINFOTOHW_OUTPUT* pOut) const; 103 104 virtual UINT_32 HwlComputeHtileBpp( 105 BOOL_32 isWidth8, BOOL_32 isHeight8) const; 106 107 virtual UINT_32 HwlComputeHtileBaseAlign( 108 BOOL_32 isTcCompatible, BOOL_32 isLinear, ADDR_TILEINFO* pTileInfo) const; 109 110 virtual ADDR_E_RETURNCODE HwlComputeFmaskInfo( 111 const ADDR_COMPUTE_FMASK_INFO_INPUT* pIn, 112 ADDR_COMPUTE_FMASK_INFO_OUTPUT* pOut); 113 114 virtual ADDR_E_RETURNCODE HwlComputeFmaskAddrFromCoord( 115 const ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn, 116 ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut) const; 117 118 virtual ADDR_E_RETURNCODE HwlComputeFmaskCoordFromAddr( 119 const ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn, 120 ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut) const; 121 122 virtual BOOL_32 HwlGetAlignmentInfoMacroTiled( 123 const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, 124 UINT_32* pPitchAlign, UINT_32* pHeightAlign, UINT_32* pSizeAlign) const; 125 126 virtual UINT_32 HwlComputeQbStereoRightSwizzle( 127 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pInfo) const; 128 129 virtual VOID HwlComputePixelCoordFromOffset( 130 UINT_32 offset, UINT_32 bpp, UINT_32 numSamples, 131 AddrTileMode tileMode, UINT_32 tileBase, UINT_32 compBits, 132 UINT_32* pX, UINT_32* pY, UINT_32* pSlice, UINT_32* pSample, 133 AddrTileType microTileType, BOOL_32 isDepthSampleOrder) const; 134 135 /// Return Cmask block max HwlGetMaxCmaskBlockMax()136 virtual BOOL_32 HwlGetMaxCmaskBlockMax() const 137 { 138 return 0x3FFF; // 14 bits, 0n16383 139 } 140 141 // Sub-hwl interface 142 /// Pure virtual function to setup tile info (indices) if client requests to do so 143 virtual VOID HwlSetupTileInfo( 144 AddrTileMode tileMode, ADDR_SURFACE_FLAGS flags, 145 UINT_32 bpp, UINT_32 pitch, UINT_32 height, UINT_32 numSamples, 146 ADDR_TILEINFO* inputTileInfo, ADDR_TILEINFO* outputTileInfo, 147 AddrTileType inTileType, ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const = 0; 148 149 /// Pure virtual function to get pitch alignment for linear modes 150 virtual UINT_32 HwlGetPitchAlignmentLinear(UINT_32 bpp, ADDR_SURFACE_FLAGS flags) const = 0; 151 152 /// Pure virtual function to get size adjustment for linear modes 153 virtual UINT_64 HwlGetSizeAdjustmentLinear( 154 AddrTileMode tileMode, 155 UINT_32 bpp, UINT_32 numSamples, UINT_32 baseAlign, UINT_32 pitchAlign, 156 UINT_32 *pPitch, UINT_32 *pHeight, UINT_32 *pHeightAlign) const = 0; 157 158 virtual UINT_32 HwlGetPitchAlignmentMicroTiled( 159 AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, UINT_32 numSamples) const; 160 161 virtual UINT_64 HwlGetSizeAdjustmentMicroTiled( 162 UINT_32 thickness, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, UINT_32 numSamples, 163 UINT_32 baseAlign, UINT_32 pitchAlign, 164 UINT_32 *pPitch, UINT_32 *pHeight) const; 165 166 /// Pure virtual function to do extra sanity check 167 virtual BOOL_32 HwlSanityCheckMacroTiled( 168 ADDR_TILEINFO* pTileInfo) const = 0; 169 170 /// Pure virtual function to check current level to be the last macro tiled one 171 virtual VOID HwlCheckLastMacroTiledLvl( 172 const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, 173 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const = 0; 174 175 /// Adjusts bank before bank is modified by rotation 176 virtual UINT_32 HwlPreAdjustBank( 177 UINT_32 tileX, UINT_32 bank, ADDR_TILEINFO* pTileInfo) const = 0; 178 179 virtual VOID HwlComputeSurfaceCoord2DFromBankPipe( 180 AddrTileMode tileMode, UINT_32* pX, UINT_32* pY, UINT_32 slice, 181 UINT_32 bank, UINT_32 pipe, 182 UINT_32 bankSwizzle, UINT_32 pipeSwizzle, UINT_32 tileSlices, 183 BOOL_32 ignoreSE, 184 ADDR_TILEINFO* pTileInfo) const = 0; 185 186 virtual BOOL_32 HwlTileInfoEqual( 187 const ADDR_TILEINFO* pLeft, const ADDR_TILEINFO* pRight) const; 188 189 virtual AddrTileMode HwlDegradeThickTileMode( 190 AddrTileMode baseTileMode, UINT_32 numSlices, UINT_32* pBytesPerTile) const; 191 192 virtual INT_32 HwlPostCheckTileIndex( 193 const ADDR_TILEINFO* pInfo, AddrTileMode mode, AddrTileType type, 194 INT curIndex = TileIndexInvalid) const 195 { 196 return TileIndexInvalid; 197 } 198 HwlFmaskPreThunkSurfInfo(const ADDR_COMPUTE_FMASK_INFO_INPUT * pFmaskIn,const ADDR_COMPUTE_FMASK_INFO_OUTPUT * pFmaskOut,ADDR_COMPUTE_SURFACE_INFO_INPUT * pSurfIn,ADDR_COMPUTE_SURFACE_INFO_OUTPUT * pSurfOut)199 virtual VOID HwlFmaskPreThunkSurfInfo( 200 const ADDR_COMPUTE_FMASK_INFO_INPUT* pFmaskIn, 201 const ADDR_COMPUTE_FMASK_INFO_OUTPUT* pFmaskOut, 202 ADDR_COMPUTE_SURFACE_INFO_INPUT* pSurfIn, 203 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pSurfOut) const 204 { 205 } 206 HwlFmaskPostThunkSurfInfo(const ADDR_COMPUTE_SURFACE_INFO_OUTPUT * pSurfOut,ADDR_COMPUTE_FMASK_INFO_OUTPUT * pFmaskOut)207 virtual VOID HwlFmaskPostThunkSurfInfo( 208 const ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pSurfOut, 209 ADDR_COMPUTE_FMASK_INFO_OUTPUT* pFmaskOut) const 210 { 211 } 212 213 virtual UINT_32 HwlStereoCheckRightOffsetPadding(ADDR_TILEINFO* pTileInfo) const; 214 215 virtual BOOL_32 HwlReduceBankWidthHeight( 216 UINT_32 tileSize, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, UINT_32 numSamples, 217 UINT_32 bankHeightAlign, UINT_32 pipes, 218 ADDR_TILEINFO* pTileInfo) const; 219 220 // Protected non-virtual functions 221 222 /// Mip level functions 223 AddrTileMode ComputeSurfaceMipLevelTileMode( 224 AddrTileMode baseTileMode, UINT_32 bpp, 225 UINT_32 pitch, UINT_32 height, UINT_32 numSlices, UINT_32 numSamples, 226 UINT_32 pitchAlign, UINT_32 heightAlign, 227 ADDR_TILEINFO* pTileInfo) const; 228 229 /// Swizzle functions 230 VOID ExtractBankPipeSwizzle( 231 UINT_32 base256b, ADDR_TILEINFO* pTileInfo, 232 UINT_32* pBankSwizzle, UINT_32* pPipeSwizzle) const; 233 234 UINT_32 GetBankPipeSwizzle( 235 UINT_32 bankSwizzle, UINT_32 pipeSwizzle, 236 UINT_64 baseAddr, ADDR_TILEINFO* pTileInfo) const; 237 238 UINT_32 ComputeSliceTileSwizzle( 239 AddrTileMode tileMode, UINT_32 baseSwizzle, UINT_32 slice, UINT_64 baseAddr, 240 ADDR_TILEINFO* pTileInfo) const; 241 242 /// Addressing functions ComputeBankEquation(UINT_32 log2BytesPP,UINT_32 threshX,UINT_32 threshY,ADDR_TILEINFO * pTileInfo,ADDR_EQUATION * pEquation)243 virtual ADDR_E_RETURNCODE ComputeBankEquation( 244 UINT_32 log2BytesPP, UINT_32 threshX, UINT_32 threshY, 245 ADDR_TILEINFO* pTileInfo, ADDR_EQUATION* pEquation) const 246 { 247 return ADDR_NOTSUPPORTED; 248 } 249 250 UINT_32 ComputeBankFromCoord( 251 UINT_32 x, UINT_32 y, UINT_32 slice, 252 AddrTileMode tileMode, UINT_32 bankSwizzle, UINT_32 tileSpitSlice, 253 ADDR_TILEINFO* pTileInfo) const; 254 255 UINT_32 ComputeBankFromAddr( 256 UINT_64 addr, UINT_32 numBanks, UINT_32 numPipes) const; 257 258 UINT_32 ComputePipeRotation( 259 AddrTileMode tileMode, UINT_32 numPipes) const; 260 261 UINT_32 ComputeBankRotation( 262 AddrTileMode tileMode, UINT_32 numBanks, 263 UINT_32 numPipes) const; 264 265 VOID ComputeSurfaceCoord2DFromBankPipe( 266 AddrTileMode tileMode, UINT_32 x, UINT_32 y, UINT_32 slice, 267 UINT_32 bank, UINT_32 pipe, 268 UINT_32 bankSwizzle, UINT_32 pipeSwizzle, UINT_32 tileSlices, 269 ADDR_TILEINFO* pTileInfo, 270 CoordFromBankPipe *pOutput) const; 271 272 /// Htile/Cmask functions 273 UINT_64 ComputeHtileBytes( 274 UINT_32 pitch, UINT_32 height, UINT_32 bpp, 275 BOOL_32 isLinear, UINT_32 numSlices, UINT_64* sliceBytes, UINT_32 baseAlign) const; 276 277 ADDR_E_RETURNCODE ComputeMacroTileEquation( 278 UINT_32 log2BytesPP, AddrTileMode tileMode, AddrTileType microTileType, 279 ADDR_TILEINFO* pTileInfo, ADDR_EQUATION* pEquation) const; 280 281 // Static functions 282 static BOOL_32 IsTileInfoAllZero(const ADDR_TILEINFO* pTileInfo); 283 static UINT_32 ComputeFmaskNumPlanesFromNumSamples(UINT_32 numSamples); 284 static UINT_32 ComputeFmaskResolvedBppFromNumSamples(UINT_32 numSamples); 285 HwlComputeSurfaceAlignmentsMacroTiled(AddrTileMode tileMode,UINT_32 bpp,ADDR_SURFACE_FLAGS flags,UINT_32 mipLevel,UINT_32 numSamples,ADDR_COMPUTE_SURFACE_INFO_OUTPUT * pOut)286 virtual VOID HwlComputeSurfaceAlignmentsMacroTiled( 287 AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, 288 UINT_32 mipLevel, UINT_32 numSamples, ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const 289 { 290 } 291 292 private: 293 294 BOOL_32 ComputeSurfaceInfoLinear( 295 const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, 296 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut, 297 UINT_32 padDims) const; 298 299 BOOL_32 ComputeSurfaceInfoMicroTiled( 300 const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, 301 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut, 302 UINT_32 padDims, 303 AddrTileMode expTileMode) const; 304 305 BOOL_32 ComputeSurfaceInfoMacroTiled( 306 const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, 307 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut, 308 UINT_32 padDims, 309 AddrTileMode expTileMode) const; 310 311 BOOL_32 ComputeSurfaceAlignmentsLinear( 312 AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, 313 UINT_32* pBaseAlign, UINT_32* pPitchAlign, UINT_32* pHeightAlign) const; 314 315 BOOL_32 ComputeSurfaceAlignmentsMicroTiled( 316 AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, 317 UINT_32 mipLevel, UINT_32 numSamples, 318 UINT_32* pBaseAlign, UINT_32* pPitchAlign, UINT_32* pHeightAlign) const; 319 320 BOOL_32 ComputeSurfaceAlignmentsMacroTiled( 321 AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags, 322 UINT_32 mipLevel, UINT_32 numSamples, 323 ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const; 324 325 /// Surface addressing functions 326 UINT_64 DispatchComputeSurfaceAddrFromCoord( 327 const ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn, 328 ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const; 329 330 VOID DispatchComputeSurfaceCoordFromAddr( 331 const ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn, 332 ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const; 333 334 UINT_64 ComputeSurfaceAddrFromCoordMicroTiled( 335 UINT_32 x, UINT_32 y, UINT_32 slice, UINT_32 sample, 336 UINT_32 bpp, UINT_32 pitch, UINT_32 height, UINT_32 numSamples, 337 AddrTileMode tileMode, 338 AddrTileType microTileType, BOOL_32 isDepthSampleOrder, 339 UINT_32* pBitPosition) const; 340 341 UINT_64 ComputeSurfaceAddrFromCoordMacroTiled( 342 UINT_32 x, UINT_32 y, UINT_32 slice, UINT_32 sample, 343 UINT_32 bpp, UINT_32 pitch, UINT_32 height, UINT_32 numSamples, 344 AddrTileMode tileMode, 345 AddrTileType microTileType, BOOL_32 ignoreSE, BOOL_32 isDepthSampleOrder, 346 UINT_32 pipeSwizzle, UINT_32 bankSwizzle, 347 ADDR_TILEINFO* pTileInfo, 348 UINT_32* pBitPosition) const; 349 350 VOID ComputeSurfaceCoordFromAddrMacroTiled( 351 UINT_64 addr, UINT_32 bitPosition, 352 UINT_32 bpp, UINT_32 pitch, UINT_32 height, UINT_32 numSamples, 353 AddrTileMode tileMode, UINT_32 tileBase, UINT_32 compBits, 354 AddrTileType microTileType, BOOL_32 ignoreSE, BOOL_32 isDepthSampleOrder, 355 UINT_32 pipeSwizzle, UINT_32 bankSwizzle, 356 ADDR_TILEINFO* pTileInfo, 357 UINT_32* pX, UINT_32* pY, UINT_32* pSlice, UINT_32* pSample) const; 358 359 /// Fmask functions 360 UINT_64 DispatchComputeFmaskAddrFromCoord( 361 const ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn, 362 ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut) const; 363 364 VOID DispatchComputeFmaskCoordFromAddr( 365 const ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn, 366 ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut) const; 367 368 // FMASK related methods - private 369 UINT_64 ComputeFmaskAddrFromCoordMicroTiled( 370 UINT_32 x, UINT_32 y, UINT_32 slice, UINT_32 sample, UINT_32 plane, 371 UINT_32 pitch, UINT_32 height, UINT_32 numSamples, AddrTileMode tileMode, 372 BOOL_32 resolved, UINT_32* pBitPosition) const; 373 374 VOID ComputeFmaskCoordFromAddrMicroTiled( 375 UINT_64 addr, UINT_32 bitPosition, 376 UINT_32 pitch, UINT_32 height, UINT_32 numSamples, 377 AddrTileMode tileMode, BOOL_32 resolved, 378 UINT_32* pX, UINT_32* pY, UINT_32* pSlice, UINT_32* pSample, UINT_32* pPlane) const; 379 380 VOID ComputeFmaskCoordFromAddrMacroTiled( 381 UINT_64 addr, UINT_32 bitPosition, 382 UINT_32 pitch, UINT_32 height, UINT_32 numSamples, AddrTileMode tileMode, 383 UINT_32 pipeSwizzle, UINT_32 bankSwizzle, 384 BOOL_32 ignoreSE, 385 ADDR_TILEINFO* pTileInfo, 386 BOOL_32 resolved, 387 UINT_32* pX, UINT_32* pY, UINT_32* pSlice, UINT_32* pSample, UINT_32* pPlane) const; 388 389 UINT_64 ComputeFmaskAddrFromCoordMacroTiled( 390 UINT_32 x, UINT_32 y, UINT_32 slice, UINT_32 sample, UINT_32 plane, 391 UINT_32 pitch, UINT_32 height, UINT_32 numSamples, 392 AddrTileMode tileMode, UINT_32 pipeSwizzle, UINT_32 bankSwizzle, 393 BOOL_32 ignoreSE, 394 ADDR_TILEINFO* pTileInfo, 395 BOOL_32 resolved, 396 UINT_32* pBitPosition) const; 397 398 /// Sanity check functions 399 BOOL_32 SanityCheckMacroTiled( 400 ADDR_TILEINFO* pTileInfo) const; 401 402 protected: 403 UINT_32 m_ranks; ///< Number of ranks - MC_ARB_RAMCFG.NOOFRANK 404 UINT_32 m_logicalBanks; ///< Logical banks = m_banks * m_ranks if m_banks != 16 405 UINT_32 m_bankInterleave; ///< Bank interleave, as a multiple of pipe interleave size 406 }; 407 408 } // V1 409 } // Addr 410 411 #endif 412 413