1## SPDX-License-Identifier: GPL-2.0-only 2 3config SOC_AMD_PI 4 bool 5 depends on SOC_AMD_COMMON_BLOCK_ACPI 6 select CACHE_MRC_SETTINGS 7 select HAVE_DEBUG_RAM_SETUP 8 select MRC_WRITE_NV_LATE 9 help 10 This option builds functions that interface AMD's AGESA reference 11 code packaged in the binaryPI form and S3-related functionality. 12 13if SOC_AMD_PI 14 15config PI_AGESA_CAR_HEAP_BASE 16 hex 17 default 0x400000 18 help 19 The AGESA PI blob may be built to allow an optional callout for 20 AgesaHeapRebase. If AGESA calls AgesaHeapRebase, this option 21 determines the location of the heap prior to DRAM availability. 22 23config PI_AGESA_TEMP_RAM_BASE 24 hex 25 default 0x100000 26 help 27 During a boot from S5, AGESA copies its CAR-based heap to a temporary 28 location in DRAM. Once coreboot has established cbmem, the heap 29 is moved again. This symbol determines the temporary location for 30 the heap. 31 32config PI_AGESA_HEAP_SIZE 33 hex 34 default 0x20000 35 help 36 This option determines the amount of space allowed for AGESA heap 37 prior to DRAM availability. 38 39endif # SOC_AMD_PI 40