1 /** 2 ****************************************************************************** 3 * @file stm32l0xx_hal_cortex.h 4 * @author MCD Application Team 5 * @brief Header file of CORTEX HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright(c) 2016 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef __STM32L0xx_HAL_CORTEX_H 22 #define __STM32L0xx_HAL_CORTEX_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32l0xx_hal_def.h" 30 31 /** @addtogroup STM32L0xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @defgroup CORTEX CORTEX 36 * @{ 37 */ 38 /* Exported types ------------------------------------------------------------*/ 39 40 /** @defgroup CORTEX_Exported_Types CORTEX Exported Types 41 * @{ 42 */ 43 44 #if (__MPU_PRESENT == 1) 45 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition 46 * @{ 47 */ 48 typedef struct 49 { 50 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ 51 52 uint8_t Enable; /*!< Specifies the status of the region. 53 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ 54 uint8_t Number; /*!< Specifies the number of the region to protect. 55 This parameter can be a value of @ref CORTEX_MPU_Region_Number */ 56 57 uint8_t Size; /*!< Specifies the size of the region to protect. 58 This parameter can be a value of @ref CORTEX_MPU_Region_Size */ 59 uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. 60 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 61 uint8_t TypeExtField; /*!< This parameter is NOT used but is kept to keep API unified through all families*/ 62 63 uint8_t AccessPermission; /*!< Specifies the region access permission type. 64 This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ 65 uint8_t DisableExec; /*!< Specifies the instruction access status. 66 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ 67 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. 68 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ 69 uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. 70 This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ 71 uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. 72 This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ 73 }MPU_Region_InitTypeDef; 74 /** 75 * @} 76 */ 77 #endif /* __MPU_PRESENT */ 78 79 /** 80 * @} 81 */ 82 83 84 /* Exported constants --------------------------------------------------------*/ 85 86 /** @defgroup CORTEX_Exported_Constants CORTEx Exported Constants 87 * @{ 88 */ 89 90 91 #define IS_NVIC_PREEMPTION_PRIORITY(__PRIORITY__) ((__PRIORITY__) < 0x4U) 92 93 #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x0) 94 95 /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick Clock Source 96 * @{ 97 */ 98 #define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U) 99 #define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) 100 #define IS_SYSTICK_CLK_SOURCE(__SOURCE__) (((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK) || \ 101 ((__SOURCE__) == SYSTICK_CLKSOURCE_HCLK_DIV8)) 102 /** 103 * @} 104 */ 105 106 #if (__MPU_PRESENT == 1) 107 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control 108 * @{ 109 */ 110 #define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U) 111 #define MPU_HARDFAULT_NMI ((uint32_t)0x00000002U) 112 #define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004U) 113 #define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006U) 114 /** 115 * @} 116 */ 117 118 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable 119 * @{ 120 */ 121 #define MPU_REGION_ENABLE ((uint8_t)0x01U) 122 #define MPU_REGION_DISABLE ((uint8_t)0x00U) 123 /** 124 * @} 125 */ 126 127 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access 128 * @{ 129 */ 130 #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U) 131 #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U) 132 /** 133 * @} 134 */ 135 136 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable 137 * @{ 138 */ 139 #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U) 140 #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U) 141 /** 142 * @} 143 */ 144 145 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable 146 * @{ 147 */ 148 #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U) 149 #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U) 150 /** 151 * @} 152 */ 153 154 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable 155 * @{ 156 */ 157 #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U) 158 #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U) 159 /** 160 * @} 161 */ 162 163 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size 164 * @{ 165 */ 166 #define MPU_REGION_SIZE_32B ((uint8_t)0x04U) 167 #define MPU_REGION_SIZE_64B ((uint8_t)0x05U) 168 #define MPU_REGION_SIZE_128B ((uint8_t)0x06U) 169 #define MPU_REGION_SIZE_256B ((uint8_t)0x07U) 170 #define MPU_REGION_SIZE_512B ((uint8_t)0x08U) 171 #define MPU_REGION_SIZE_1KB ((uint8_t)0x09U) 172 #define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) 173 #define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) 174 #define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) 175 #define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) 176 #define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) 177 #define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) 178 #define MPU_REGION_SIZE_128KB ((uint8_t)0x10U) 179 #define MPU_REGION_SIZE_256KB ((uint8_t)0x11U) 180 #define MPU_REGION_SIZE_512KB ((uint8_t)0x12U) 181 #define MPU_REGION_SIZE_1MB ((uint8_t)0x13U) 182 #define MPU_REGION_SIZE_2MB ((uint8_t)0x14U) 183 #define MPU_REGION_SIZE_4MB ((uint8_t)0x15U) 184 #define MPU_REGION_SIZE_8MB ((uint8_t)0x16U) 185 #define MPU_REGION_SIZE_16MB ((uint8_t)0x17U) 186 #define MPU_REGION_SIZE_32MB ((uint8_t)0x18U) 187 #define MPU_REGION_SIZE_64MB ((uint8_t)0x19U) 188 #define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) 189 #define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) 190 #define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) 191 #define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) 192 #define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) 193 #define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) 194 /** 195 * @} 196 */ 197 198 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 199 * @{ 200 */ 201 #define MPU_REGION_NO_ACCESS ((uint8_t)0x00U) 202 #define MPU_REGION_PRIV_RW ((uint8_t)0x01U) 203 #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U) 204 #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U) 205 #define MPU_REGION_PRIV_RO ((uint8_t)0x05U) 206 #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U) 207 /** 208 * @} 209 */ 210 211 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number 212 * @{ 213 */ 214 #define MPU_REGION_NUMBER0 ((uint8_t)0x00U) 215 #define MPU_REGION_NUMBER1 ((uint8_t)0x01U) 216 #define MPU_REGION_NUMBER2 ((uint8_t)0x02U) 217 #define MPU_REGION_NUMBER3 ((uint8_t)0x03U) 218 #define MPU_REGION_NUMBER4 ((uint8_t)0x04U) 219 #define MPU_REGION_NUMBER5 ((uint8_t)0x05U) 220 #define MPU_REGION_NUMBER6 ((uint8_t)0x06U) 221 #define MPU_REGION_NUMBER7 ((uint8_t)0x07U) 222 /** 223 * @} 224 */ 225 #endif /* __MPU_PRESENT */ 226 227 228 /** 229 * @} 230 */ 231 232 /* Exported functions --------------------------------------------------------*/ 233 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions 234 * @{ 235 */ 236 237 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions 238 * @brief Initialization and Configuration functions 239 * @{ 240 */ 241 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); 242 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); 243 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); 244 void HAL_NVIC_SystemReset(void); 245 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); 246 /** 247 * @} 248 */ 249 250 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions 251 * @brief Cortex control functions 252 * @{ 253 */ 254 255 uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn); 256 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); 257 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); 258 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); 259 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); 260 void HAL_SYSTICK_IRQHandler(void); 261 void HAL_SYSTICK_Callback(void); 262 #if (__MPU_PRESENT == 1U) 263 void HAL_MPU_Enable(uint32_t MPU_Control); 264 void HAL_MPU_Disable(void); 265 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); 266 #endif /* __MPU_PRESENT */ 267 /** 268 * @} 269 */ 270 271 /** 272 * @} 273 */ 274 275 /* Private types -------------------------------------------------------------*/ 276 /* Private variables ---------------------------------------------------------*/ 277 /* Private constants ---------------------------------------------------------*/ 278 /* Private macros ------------------------------------------------------------*/ 279 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros 280 * @{ 281 */ 282 283 #if (__MPU_PRESENT == 1) 284 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ 285 ((STATE) == MPU_REGION_DISABLE)) 286 287 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ 288 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) 289 290 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ 291 ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) 292 293 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ 294 ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) 295 296 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ 297 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) 298 299 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ 300 ((TYPE) == MPU_REGION_PRIV_RW) || \ 301 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ 302 ((TYPE) == MPU_REGION_FULL_ACCESS) || \ 303 ((TYPE) == MPU_REGION_PRIV_RO) || \ 304 ((TYPE) == MPU_REGION_PRIV_RO_URO)) 305 306 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ 307 ((NUMBER) == MPU_REGION_NUMBER1) || \ 308 ((NUMBER) == MPU_REGION_NUMBER2) || \ 309 ((NUMBER) == MPU_REGION_NUMBER3) || \ 310 ((NUMBER) == MPU_REGION_NUMBER4) || \ 311 ((NUMBER) == MPU_REGION_NUMBER5) || \ 312 ((NUMBER) == MPU_REGION_NUMBER6) || \ 313 ((NUMBER) == MPU_REGION_NUMBER7)) 314 315 #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_256B) || \ 316 ((SIZE) == MPU_REGION_SIZE_512B) || \ 317 ((SIZE) == MPU_REGION_SIZE_1KB) || \ 318 ((SIZE) == MPU_REGION_SIZE_2KB) || \ 319 ((SIZE) == MPU_REGION_SIZE_4KB) || \ 320 ((SIZE) == MPU_REGION_SIZE_8KB) || \ 321 ((SIZE) == MPU_REGION_SIZE_16KB) || \ 322 ((SIZE) == MPU_REGION_SIZE_32KB) || \ 323 ((SIZE) == MPU_REGION_SIZE_64KB) || \ 324 ((SIZE) == MPU_REGION_SIZE_128KB) || \ 325 ((SIZE) == MPU_REGION_SIZE_256KB) || \ 326 ((SIZE) == MPU_REGION_SIZE_512KB) || \ 327 ((SIZE) == MPU_REGION_SIZE_1MB) || \ 328 ((SIZE) == MPU_REGION_SIZE_2MB) || \ 329 ((SIZE) == MPU_REGION_SIZE_4MB) || \ 330 ((SIZE) == MPU_REGION_SIZE_8MB) || \ 331 ((SIZE) == MPU_REGION_SIZE_16MB) || \ 332 ((SIZE) == MPU_REGION_SIZE_32MB) || \ 333 ((SIZE) == MPU_REGION_SIZE_64MB) || \ 334 ((SIZE) == MPU_REGION_SIZE_128MB) || \ 335 ((SIZE) == MPU_REGION_SIZE_256MB) || \ 336 ((SIZE) == MPU_REGION_SIZE_512MB) || \ 337 ((SIZE) == MPU_REGION_SIZE_1GB) || \ 338 ((SIZE) == MPU_REGION_SIZE_2GB) || \ 339 ((SIZE) == MPU_REGION_SIZE_4GB)) 340 341 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU) 342 #endif /* __MPU_PRESENT */ 343 344 345 /** 346 * @} 347 */ 348 349 /** 350 * @} 351 */ 352 353 /** 354 * @} 355 */ 356 357 #ifdef __cplusplus 358 } 359 #endif 360 361 #endif /* __STM32L0xx_HAL_CORTEX_H */ 362 363 364 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 365 366