1 /** 2 ****************************************************************************** 3 * @file stm32l0xx_hal_pwr.h 4 * @author MCD Application Team 5 * @brief Header file of PWR HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright(c) 2016 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef __STM32L0xx_HAL_PWR_H 22 #define __STM32L0xx_HAL_PWR_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32l0xx_hal_def.h" 30 31 /** @addtogroup STM32L0xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @defgroup PWR PWR 36 * @{ 37 */ 38 39 /** @defgroup PWR_Exported_Types PWR Exported Types 40 * @{ 41 */ 42 43 #if defined(PWR_PVD_SUPPORT) 44 /** 45 * @brief PWR PVD configuration structure definition 46 */ 47 typedef struct 48 { 49 uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. 50 This parameter can be a value of @ref PWR_PVD_detection_level */ 51 52 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. 53 This parameter can be a value of @ref PWR_PVD_Mode */ 54 }PWR_PVDTypeDef; 55 #endif 56 57 /** 58 * @} 59 */ 60 61 /** @addtogroup PWR_Private 62 * @{ 63 */ 64 65 #if defined(PWR_PVD_SUPPORT) 66 #define PWR_EXTI_LINE_PVD EXTI_FTSR_TR16 /*!< External interrupt line 16 Connected to the PVD EXTI Line */ 67 #endif 68 69 /** 70 * @} 71 */ 72 73 /** @defgroup PWR_Exported_Constants PWR Exported Constants 74 * @{ 75 */ 76 77 /** @defgroup PWR_register_alias_address PWR Register alias address 78 * @{ 79 */ 80 #define PWR_WAKEUP_PIN1 PWR_CSR_EWUP1 81 #if defined (STM32L010x4) || defined (STM32L011xx) || defined (STM32L021xx) 82 #else 83 #define PWR_WAKEUP_PIN2 PWR_CSR_EWUP2 84 #endif 85 #if defined (STM32L010x4) || defined (STM32L010x6) || defined (STM32L011xx) || defined (STM32L021xx) || \ 86 defined (STM32L031xx) || defined (STM32L041xx) || defined (STM32L071xx) || defined (STM32L072xx) || \ 87 defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) 88 #define PWR_WAKEUP_PIN3 PWR_CSR_EWUP3 89 #endif 90 /** 91 * @} 92 */ 93 94 #if defined(PWR_PVD_SUPPORT) 95 /** @defgroup PWR_PVD_detection_level PVD detection level 96 * @{ 97 */ 98 #define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0 99 #define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1 100 #define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2 101 #define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3 102 #define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4 103 #define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5 104 #define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6 105 #define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7 /* External input analog voltage 106 (Compare internally to VREFINT) */ 107 /** 108 * @} 109 */ 110 111 /** @defgroup PWR_PVD_Mode PWR PVD Mode 112 * @{ 113 */ 114 #define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000U) /*!< basic mode is used */ 115 #define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */ 116 #define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */ 117 #define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ 118 #define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001U) /*!< Event Mode with Rising edge trigger detection */ 119 #define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U) /*!< Event Mode with Falling edge trigger detection */ 120 #define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */ 121 /** 122 * @} 123 */ 124 #endif /* PWR_PVD_SUPPORT */ 125 126 /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode 127 * @{ 128 */ 129 #define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000U) 130 #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPSDSR 131 132 /** 133 * @} 134 */ 135 136 /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry 137 * @{ 138 */ 139 #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U) 140 #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U) 141 /** 142 * @} 143 */ 144 145 /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry 146 * @{ 147 */ 148 #define PWR_STOPENTRY_WFI ((uint8_t)0x01U) 149 #define PWR_STOPENTRY_WFE ((uint8_t)0x02U) 150 /** 151 * @} 152 */ 153 154 /** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale 155 * @{ 156 */ 157 158 #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS_0 159 #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1 160 #define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS 161 162 #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ 163 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \ 164 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE3)) 165 /** 166 * @} 167 */ 168 169 /** @defgroup PWR_Flag PWR Flag 170 * @{ 171 */ 172 #define PWR_FLAG_WU PWR_CSR_WUF 173 #define PWR_FLAG_SB PWR_CSR_SBF 174 #if defined(PWR_PVD_SUPPORT) 175 #define PWR_FLAG_PVDO PWR_CSR_PVDO 176 #endif 177 #define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF 178 #define PWR_FLAG_VOS PWR_CSR_VOSF 179 #define PWR_FLAG_REGLP PWR_CSR_REGLPF 180 181 182 /** 183 * @} 184 */ 185 186 /** 187 * @} 188 */ 189 190 /** @defgroup PWR_Exported_Macro PWR Exported Macros 191 * @{ 192 */ 193 /** @brief macros configure the main internal regulator output voltage. 194 * When exiting Low Power Run Mode or during dynamic voltage scaling configuration, 195 * the reference manual recommends to poll PWR_FLAG_REGLP bit to wait for the regulator 196 * to reach main mode (resp. to get stabilized) for a transition from 0 to 1. 197 * Only then the clock can be increased. 198 * 199 * @param __REGULATOR__ specifies the regulator output voltage to achieve 200 * a tradeoff between performance and power consumption when the device does 201 * not operate at the maximum frequency (refer to the datasheets for more details). 202 * This parameter can be one of the following values: 203 * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode, 204 * System frequency up to 32 MHz. 205 * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode, 206 * System frequency up to 16 MHz. 207 * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode, 208 * System frequency up to 4.2 MHz 209 * @retval None 210 */ 211 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) (MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__))) 212 213 /** @brief Check PWR flag is set or not. 214 * @param __FLAG__ specifies the flag to check. 215 * This parameter can be one of the following values: 216 * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event 217 * was received from the WKUP pin or from the RTC alarm (Alarm B), 218 * RTC Tamper event, RTC TimeStamp event or RTC Wakeup. 219 * An additional wakeup event is detected if the WKUP pin is enabled 220 * (by setting the EWUP bit) when the WKUP pin level is already high. 221 * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was 222 * resumed from StandBy mode. 223 * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled 224 * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode. 225 * For this reason, this bit is equal to 0 after Standby or reset 226 * until the PVDE bit is set. Not available on L0 Value line. 227 * @arg PWR_FLAG_VREFINTRDY: Internal voltage reference (VREFINT) ready flag. 228 * This bit indicates the state of the internal voltage reference, VREFINT. 229 * @arg PWR_FLAG_VOS: Voltage Scaling select flag. A delay is required for 230 * the internal regulator to be ready after the voltage range is changed. 231 * The VOSF bit indicates that the regulator has reached the voltage level 232 * defined with bits VOS of PWR_CR register. 233 * @arg PWR_FLAG_REGLP: Regulator LP flag. When the MCU exits from Low power run 234 * mode, this bit stays at 1 until the regulator is ready in main mode. 235 * A polling on this bit is recommended to wait for the regulator main mode. 236 * This bit is reset by hardware when the regulator is ready. 237 * @retval The new state of __FLAG__ (TRUE or FALSE). 238 */ 239 #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) 240 241 /** @brief Clear the PWR pending flags. 242 * @param __FLAG__ specifies the flag to clear. 243 * This parameter can be one of the following values: 244 * @arg PWR_FLAG_WU: Wake Up flag 245 * @arg PWR_FLAG_SB: StandBy flag 246 */ 247 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, (__FLAG__) << 2U) 248 249 #if defined(PWR_PVD_SUPPORT) 250 /** 251 * @brief Enable interrupt on PVD Exti Line 16. 252 * @retval None. 253 */ 254 #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) 255 256 /** 257 * @brief Disable interrupt on PVD Exti Line 16. 258 * @retval None. 259 */ 260 #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) 261 262 /** 263 * @brief Enable event on PVD Exti Line 16. 264 * @retval None. 265 */ 266 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) 267 268 /** 269 * @brief Disable event on PVD Exti Line 16. 270 * @retval None. 271 */ 272 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) 273 274 /** 275 * @brief PVD EXTI line configuration: set falling edge trigger. 276 * @retval None. 277 */ 278 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) 279 280 /** 281 * @brief Disable the PVD Extended Interrupt Falling Trigger. 282 * @retval None. 283 */ 284 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) 285 286 /** 287 * @brief PVD EXTI line configuration: set rising edge trigger. 288 * @retval None. 289 */ 290 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) 291 292 /** 293 * @brief Disable the PVD Extended Interrupt Rising Trigger. 294 * This parameter can be: 295 * @retval None. 296 */ 297 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) 298 299 /** 300 * @brief PVD EXTI line configuration: set rising & falling edge trigger. 301 * @retval None. 302 */ 303 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() do { __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); } while(0); 304 305 /** 306 * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. 307 * This parameter can be: 308 * @retval None. 309 */ 310 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0); 311 312 /** 313 * @brief Check whether the specified PVD EXTI interrupt flag is set or not. 314 * @retval EXTI PVD Line Status. 315 */ 316 #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) 317 318 /** 319 * @brief Clear the PVD EXTI flag. 320 * @retval None. 321 */ 322 #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) 323 324 /** 325 * @brief Generate a Software interrupt on selected EXTI line. 326 * @retval None. 327 */ 328 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD) 329 330 /** 331 * @brief Generate a Software interrupt on selected EXTI line. 332 * @retval None. 333 */ 334 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD) 335 336 #endif /* PWR_PVD_SUPPORT */ 337 338 /** 339 * @} 340 */ 341 342 /** @addtogroup PWR_Private 343 * @{ 344 */ 345 #if defined(PWR_PVD_SUPPORT) 346 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ 347 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ 348 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ 349 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) 350 351 #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ 352 ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ 353 ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ 354 ((MODE) == PWR_PVD_MODE_NORMAL)) 355 #endif /* PWR_PVD_SUPPORT */ 356 357 #if defined (STM32L010x6) || defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) 358 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ 359 ((PIN) == PWR_WAKEUP_PIN2) || \ 360 ((PIN) == PWR_WAKEUP_PIN3)) 361 #elif defined (STM32L010xB) || defined (STM32L051xx) || defined (STM32L052xx) || defined (STM32L053xx) || defined (STM32L061xx) || defined (STM32L062xx) || defined (STM32L063xx) 362 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ 363 ((PIN) == PWR_WAKEUP_PIN2)) 364 #elif defined (STM32L010x8) || defined (STM32L031xx) || defined (STM32L041xx) 365 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ 366 ((PIN) == PWR_WAKEUP_PIN2)) 367 #elif defined (STM32L010x4) || defined (STM32L011xx) || defined (STM32L021xx) 368 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ 369 ((PIN) == PWR_WAKEUP_PIN3)) 370 #endif 371 372 #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ 373 ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) 374 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) 375 376 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) 377 378 /** 379 * @} 380 */ 381 382 /* Include PWR HAL Extension module */ 383 #include "stm32l0xx_hal_pwr_ex.h" 384 385 /** @defgroup PWR_Exported_Functions PWR Exported Functions 386 * @{ 387 */ 388 389 /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 390 * @{ 391 */ 392 void HAL_PWR_DeInit(void); 393 void HAL_PWR_EnableBkUpAccess(void); 394 void HAL_PWR_DisableBkUpAccess(void); 395 /** 396 * @} 397 */ 398 399 /** @defgroup PWR_Exported_Functions_Group2 Low Power modes configuration functions 400 * @{ 401 */ 402 403 #if defined(PWR_PVD_SUPPORT) 404 /* PVD control functions ************************************************/ 405 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); 406 void HAL_PWR_EnablePVD(void); 407 void HAL_PWR_DisablePVD(void); 408 void HAL_PWR_PVD_IRQHandler(void); 409 void HAL_PWR_PVDCallback(void); 410 #endif 411 412 /* WakeUp pins configuration functions ****************************************/ 413 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); 414 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); 415 416 /* Low Power modes configuration functions ************************************/ 417 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); 418 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); 419 void HAL_PWR_EnterSTANDBYMode(void); 420 421 void HAL_PWR_EnableSleepOnExit(void); 422 void HAL_PWR_DisableSleepOnExit(void); 423 void HAL_PWR_EnableSEVOnPend(void); 424 void HAL_PWR_DisableSEVOnPend(void); 425 426 /** 427 * @} 428 */ 429 430 /** 431 * @} 432 */ 433 434 /* Define the private group ***********************************/ 435 /**************************************************************/ 436 /** @defgroup PWR_Private PWR Private 437 * @{ 438 */ 439 /** 440 * @} 441 */ 442 /**************************************************************/ 443 444 /** 445 * @} 446 */ 447 448 /** 449 * @} 450 */ 451 452 #ifdef __cplusplus 453 } 454 #endif 455 456 457 #endif /* __STM32L0xx_HAL_PWR_H */ 458 459 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 460 461