1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_dfsdm.h 4 * @author MCD Application Team 5 * @brief Header file of DFSDM HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32L4xx_HAL_DFSDM_H 22 #define STM32L4xx_HAL_DFSDM_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ 29 defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ 30 defined(STM32L496xx) || defined(STM32L4A6xx) || \ 31 defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) || \ 32 defined(STM32L4P5xx) || defined(STM32L4Q5xx) 33 34 /* Includes ------------------------------------------------------------------*/ 35 #include "stm32l4xx_hal_def.h" 36 37 /** @addtogroup STM32L4xx_HAL_Driver 38 * @{ 39 */ 40 41 /** @addtogroup DFSDM 42 * @{ 43 */ 44 45 /* Exported types ------------------------------------------------------------*/ 46 /** @defgroup DFSDM_Exported_Types DFSDM Exported Types 47 * @{ 48 */ 49 50 /** 51 * @brief HAL DFSDM Channel states definition 52 */ 53 typedef enum 54 { 55 HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */ 56 HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /*!< DFSDM channel initialized and ready for use */ 57 HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU /*!< DFSDM channel state error */ 58 } HAL_DFSDM_Channel_StateTypeDef; 59 60 /** 61 * @brief DFSDM channel output clock structure definition 62 */ 63 typedef struct 64 { 65 FunctionalState Activation; /*!< Output clock enable/disable */ 66 uint32_t Selection; /*!< Output clock is system clock or audio clock. 67 This parameter can be a value of @ref DFSDM_Channel_OuputClock */ 68 uint32_t Divider; /*!< Output clock divider. 69 This parameter must be a number between Min_Data = 2 and Max_Data = 256 */ 70 } DFSDM_Channel_OutputClockTypeDef; 71 72 /** 73 * @brief DFSDM channel input structure definition 74 */ 75 typedef struct 76 { 77 uint32_t Multiplexer; /*!< Input is external serial inputs, internal register or ADC output. 78 ADC output is available only on STM32L451xx, STM32L452xx, STM32L462xx, 79 STM32L496xx, STM32L4A6xx, STM32L4R5xx, STM32L4R7xx, STM32L4R9xx, 80 STM32L4S5xx, STM32L4S7xx, STM32L4S9xx, STM32L4P5xx and STM32L4Q5xx products. 81 This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */ 82 uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register. 83 This parameter can be a value of @ref DFSDM_Channel_DataPacking */ 84 uint32_t Pins; /*!< Input pins are taken from same or following channel. 85 This parameter can be a value of @ref DFSDM_Channel_InputPins */ 86 } DFSDM_Channel_InputTypeDef; 87 88 /** 89 * @brief DFSDM channel serial interface structure definition 90 */ 91 typedef struct 92 { 93 uint32_t Type; /*!< SPI or Manchester modes. 94 This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */ 95 uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point). 96 This parameter can be a value of @ref DFSDM_Channel_SpiClock */ 97 } DFSDM_Channel_SerialInterfaceTypeDef; 98 99 /** 100 * @brief DFSDM channel analog watchdog structure definition 101 */ 102 typedef struct 103 { 104 uint32_t FilterOrder; /*!< Analog watchdog Sinc filter order. 105 This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */ 106 uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio. 107 This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ 108 } DFSDM_Channel_AwdTypeDef; 109 110 /** 111 * @brief DFSDM channel init structure definition 112 */ 113 typedef struct 114 { 115 DFSDM_Channel_OutputClockTypeDef OutputClock; /*!< DFSDM channel output clock parameters */ 116 DFSDM_Channel_InputTypeDef Input; /*!< DFSDM channel input parameters */ 117 DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /*!< DFSDM channel serial interface parameters */ 118 DFSDM_Channel_AwdTypeDef Awd; /*!< DFSDM channel analog watchdog parameters */ 119 int32_t Offset; /*!< DFSDM channel offset. 120 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ 121 uint32_t RightBitShift; /*!< DFSDM channel right bit shift. 122 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ 123 } DFSDM_Channel_InitTypeDef; 124 125 /** 126 * @brief DFSDM channel handle structure definition 127 */ 128 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 129 typedef struct __DFSDM_Channel_HandleTypeDef 130 #else 131 typedef struct 132 #endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */ 133 { 134 DFSDM_Channel_TypeDef *Instance; /*!< DFSDM channel instance */ 135 DFSDM_Channel_InitTypeDef Init; /*!< DFSDM channel init parameters */ 136 HAL_DFSDM_Channel_StateTypeDef State; /*!< DFSDM channel state */ 137 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 138 void (*CkabCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel clock absence detection callback */ 139 void (*ScdCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel short circuit detection callback */ 140 void (*MspInitCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP init callback */ 141 void (*MspDeInitCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP de-init callback */ 142 #endif 143 } DFSDM_Channel_HandleTypeDef; 144 145 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 146 /** 147 * @brief DFSDM channel callback ID enumeration definition 148 */ 149 typedef enum 150 { 151 HAL_DFSDM_CHANNEL_CKAB_CB_ID = 0x00U, /*!< DFSDM channel clock absence detection callback ID */ 152 HAL_DFSDM_CHANNEL_SCD_CB_ID = 0x01U, /*!< DFSDM channel short circuit detection callback ID */ 153 HAL_DFSDM_CHANNEL_MSPINIT_CB_ID = 0x02U, /*!< DFSDM channel MSP init callback ID */ 154 HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID = 0x03U /*!< DFSDM channel MSP de-init callback ID */ 155 } HAL_DFSDM_Channel_CallbackIDTypeDef; 156 157 /** 158 * @brief DFSDM channel callback pointer definition 159 */ 160 typedef void (*pDFSDM_Channel_CallbackTypeDef)(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 161 #endif 162 163 /** 164 * @brief HAL DFSDM Filter states definition 165 */ 166 typedef enum 167 { 168 HAL_DFSDM_FILTER_STATE_RESET = 0x00U, /*!< DFSDM filter not initialized */ 169 HAL_DFSDM_FILTER_STATE_READY = 0x01U, /*!< DFSDM filter initialized and ready for use */ 170 HAL_DFSDM_FILTER_STATE_REG = 0x02U, /*!< DFSDM filter regular conversion in progress */ 171 HAL_DFSDM_FILTER_STATE_INJ = 0x03U, /*!< DFSDM filter injected conversion in progress */ 172 HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /*!< DFSDM filter regular and injected conversions in progress */ 173 HAL_DFSDM_FILTER_STATE_ERROR = 0xFFU /*!< DFSDM filter state error */ 174 } HAL_DFSDM_Filter_StateTypeDef; 175 176 /** 177 * @brief DFSDM filter regular conversion parameters structure definition 178 */ 179 typedef struct 180 { 181 uint32_t Trigger; /*!< Trigger used to start regular conversion: software or synchronous. 182 This parameter can be a value of @ref DFSDM_Filter_Trigger */ 183 FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */ 184 FunctionalState DmaMode; /*!< Enable/disable DMA for regular conversion */ 185 } DFSDM_Filter_RegularParamTypeDef; 186 187 /** 188 * @brief DFSDM filter injected conversion parameters structure definition 189 */ 190 typedef struct 191 { 192 uint32_t Trigger; /*!< Trigger used to start injected conversion: software, external or synchronous. 193 This parameter can be a value of @ref DFSDM_Filter_Trigger */ 194 FunctionalState ScanMode; /*!< Enable/disable scanning mode for injected conversion */ 195 FunctionalState DmaMode; /*!< Enable/disable DMA for injected conversion */ 196 uint32_t ExtTrigger; /*!< External trigger. 197 This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */ 198 uint32_t ExtTriggerEdge; /*!< External trigger edge: rising, falling or both. 199 This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */ 200 } DFSDM_Filter_InjectedParamTypeDef; 201 202 /** 203 * @brief DFSDM filter parameters structure definition 204 */ 205 typedef struct 206 { 207 uint32_t SincOrder; /*!< Sinc filter order. 208 This parameter can be a value of @ref DFSDM_Filter_SincOrder */ 209 uint32_t Oversampling; /*!< Filter oversampling ratio. 210 This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */ 211 uint32_t IntOversampling; /*!< Integrator oversampling ratio. 212 This parameter must be a number between Min_Data = 1 and Max_Data = 256 */ 213 } DFSDM_Filter_FilterParamTypeDef; 214 215 /** 216 * @brief DFSDM filter init structure definition 217 */ 218 typedef struct 219 { 220 DFSDM_Filter_RegularParamTypeDef RegularParam; /*!< DFSDM regular conversion parameters */ 221 DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */ 222 DFSDM_Filter_FilterParamTypeDef FilterParam; /*!< DFSDM filter parameters */ 223 } DFSDM_Filter_InitTypeDef; 224 225 /** 226 * @brief DFSDM filter handle structure definition 227 */ 228 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 229 typedef struct __DFSDM_Filter_HandleTypeDef 230 #else 231 typedef struct 232 #endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */ 233 { 234 DFSDM_Filter_TypeDef *Instance; /*!< DFSDM filter instance */ 235 DFSDM_Filter_InitTypeDef Init; /*!< DFSDM filter init parameters */ 236 DMA_HandleTypeDef *hdmaReg; /*!< Pointer on DMA handler for regular conversions */ 237 DMA_HandleTypeDef *hdmaInj; /*!< Pointer on DMA handler for injected conversions */ 238 uint32_t RegularContMode; /*!< Regular conversion continuous mode */ 239 uint32_t RegularTrigger; /*!< Trigger used for regular conversion */ 240 uint32_t InjectedTrigger; /*!< Trigger used for injected conversion */ 241 uint32_t ExtTriggerEdge; /*!< Rising, falling or both edges selected */ 242 FunctionalState InjectedScanMode; /*!< Injected scanning mode */ 243 uint32_t InjectedChannelsNbr; /*!< Number of channels in injected sequence */ 244 uint32_t InjConvRemaining; /*!< Injected conversions remaining */ 245 HAL_DFSDM_Filter_StateTypeDef State; /*!< DFSDM filter state */ 246 uint32_t ErrorCode; /*!< DFSDM filter error code */ 247 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 248 void (*AwdCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 249 uint32_t Channel, uint32_t Threshold); /*!< DFSDM filter analog watchdog callback */ 250 void (*RegConvCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter regular conversion complete callback */ 251 void (*RegConvHalfCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter half regular conversion complete callback */ 252 void (*InjConvCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter injected conversion complete callback */ 253 void (*InjConvHalfCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter half injected conversion complete callback */ 254 void (*ErrorCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter error callback */ 255 void (*MspInitCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter MSP init callback */ 256 void (*MspDeInitCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter MSP de-init callback */ 257 #endif 258 } DFSDM_Filter_HandleTypeDef; 259 260 /** 261 * @brief DFSDM filter analog watchdog parameters structure definition 262 */ 263 typedef struct 264 { 265 uint32_t DataSource; /*!< Values from digital filter or from channel watchdog filter. 266 This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */ 267 uint32_t Channel; /*!< Analog watchdog channel selection. 268 This parameter can be a values combination of @ref DFSDM_Channel_Selection */ 269 int32_t HighThreshold; /*!< High threshold for the analog watchdog. 270 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ 271 int32_t LowThreshold; /*!< Low threshold for the analog watchdog. 272 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ 273 uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event. 274 This parameter can be a values combination of @ref DFSDM_BreakSignals */ 275 uint32_t LowBreakSignal; /*!< Break signal assigned to analog watchdog low threshold event. 276 This parameter can be a values combination of @ref DFSDM_BreakSignals */ 277 } DFSDM_Filter_AwdParamTypeDef; 278 279 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 280 /** 281 * @brief DFSDM filter callback ID enumeration definition 282 */ 283 typedef enum 284 { 285 HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID = 0x00U, /*!< DFSDM filter regular conversion complete callback ID */ 286 HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID = 0x01U, /*!< DFSDM filter half regular conversion complete callback ID */ 287 HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID = 0x02U, /*!< DFSDM filter injected conversion complete callback ID */ 288 HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID = 0x03U, /*!< DFSDM filter half injected conversion complete callback ID */ 289 HAL_DFSDM_FILTER_ERROR_CB_ID = 0x04U, /*!< DFSDM filter error callback ID */ 290 HAL_DFSDM_FILTER_MSPINIT_CB_ID = 0x05U, /*!< DFSDM filter MSP init callback ID */ 291 HAL_DFSDM_FILTER_MSPDEINIT_CB_ID = 0x06U /*!< DFSDM filter MSP de-init callback ID */ 292 } HAL_DFSDM_Filter_CallbackIDTypeDef; 293 294 /** 295 * @brief DFSDM filter callback pointer definition 296 */ 297 typedef void (*pDFSDM_Filter_CallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 298 typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold); 299 #endif 300 301 /** 302 * @} 303 */ 304 /* End of exported types -----------------------------------------------------*/ 305 306 /* Exported constants --------------------------------------------------------*/ 307 /** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants 308 * @{ 309 */ 310 311 /** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection 312 * @{ 313 */ 314 #define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM 0x00000000U /*!< Source for ouput clock is system clock */ 315 #define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */ 316 /** 317 * @} 318 */ 319 320 /** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer 321 * @{ 322 */ 323 #define DFSDM_CHANNEL_EXTERNAL_INPUTS 0x00000000U /*!< Data are taken from external inputs */ 324 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ 325 defined(STM32L496xx) || defined(STM32L4A6xx) || \ 326 defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) || \ 327 defined(STM32L4P5xx) || defined(STM32L4Q5xx) 328 #define DFSDM_CHANNEL_ADC_OUTPUT DFSDM_CHCFGR1_DATMPX_0 /*!< Data are taken from ADC output */ 329 #endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx || STM32L4P5xx || STM32L4Q5xx */ 330 #define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1 /*!< Data are taken from internal register */ 331 /** 332 * @} 333 */ 334 335 /** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing 336 * @{ 337 */ 338 #define DFSDM_CHANNEL_STANDARD_MODE 0x00000000U /*!< Standard data packing mode */ 339 #define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */ 340 #define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */ 341 /** 342 * @} 343 */ 344 345 /** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins 346 * @{ 347 */ 348 #define DFSDM_CHANNEL_SAME_CHANNEL_PINS 0x00000000U /*!< Input from pins on same channel */ 349 #define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL /*!< Input from pins on following channel */ 350 /** 351 * @} 352 */ 353 354 /** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type 355 * @{ 356 */ 357 #define DFSDM_CHANNEL_SPI_RISING 0x00000000U /*!< SPI with rising edge */ 358 #define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0 /*!< SPI with falling edge */ 359 #define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1 /*!< Manchester with rising edge */ 360 #define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP /*!< Manchester with falling edge */ 361 /** 362 * @} 363 */ 364 365 /** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection 366 * @{ 367 */ 368 #define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL 0x00000000U /*!< External SPI clock */ 369 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */ 370 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */ 371 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL /*!< Internal SPI clock divided by 2, rising edge */ 372 /** 373 * @} 374 */ 375 376 /** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order 377 * @{ 378 */ 379 #define DFSDM_CHANNEL_FASTSINC_ORDER 0x00000000U /*!< FastSinc filter type */ 380 #define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */ 381 #define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */ 382 #define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD /*!< Sinc 3 filter type */ 383 /** 384 * @} 385 */ 386 387 /** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger 388 * @{ 389 */ 390 #define DFSDM_FILTER_SW_TRIGGER 0x00000000U /*!< Software trigger */ 391 #define DFSDM_FILTER_SYNC_TRIGGER 0x00000001U /*!< Synchronous with DFSDM_FLT0 */ 392 #define DFSDM_FILTER_EXT_TRIGGER 0x00000002U /*!< External trigger (only for injected conversion) */ 393 /** 394 * @} 395 */ 396 397 /** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger 398 * @{ 399 */ 400 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) 401 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For DFSDM filter 0, 1, 2 and 3 */ 402 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM filter 0, 1, 2 and 3 */ 403 #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM filter 0, 1, 2 and 3 */ 404 #define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1 and 2 */ 405 #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0 and 1 */ 406 #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */ 407 #define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /*!< For DFSDM filter 0, 1, 2 and 3 */ 408 #elif defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) || \ 409 defined(STM32L4P5xx) || defined(STM32L4Q5xx) 410 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For all DFSDM filters */ 411 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For all DFSDM filters */ 412 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For all DFSDM filters */ 413 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For all DFSDM filters */ 414 #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For all DFSDM filters */ 415 #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */ 416 #define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */ 417 #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1 | \ 418 DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */ 419 #define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO DFSDM_FLTCR1_JEXTSEL_3 /*!< For all DFSDM filters */ 420 #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */ 421 #define DFSDM_FILTER_EXT_TRIG_EXTI15 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_3 | \ 422 DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */ 423 #define DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_3 | \ 424 DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */ 425 #else 426 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For DFSDM filter 0, 1, 2 and 3 */ 427 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM filter 0, 1, 2 and 3 */ 428 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM filter 0, 1, 2 and 3 */ 429 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1 and 2 */ 430 #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 3 */ 431 #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM filter 0, 1 and 2 */ 432 #define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM filter 3 */ 433 #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0 and 1 */ 434 #define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 2 and 3 */ 435 #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */ 436 #define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /*!< For DFSDM filter 0, 1, 2 and 3 */ 437 #endif /* STM32L451xx || STM32L452xx || STM32L462xx */ 438 /** 439 * @} 440 */ 441 442 /** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge 443 * @{ 444 */ 445 #define DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0 /*!< External rising edge */ 446 #define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 /*!< External falling edge */ 447 #define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN /*!< External rising and falling edges */ 448 /** 449 * @} 450 */ 451 452 /** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order 453 * @{ 454 */ 455 #define DFSDM_FILTER_FASTSINC_ORDER 0x00000000U /*!< FastSinc filter type */ 456 #define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0 /*!< Sinc 1 filter type */ 457 #define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1 /*!< Sinc 2 filter type */ 458 #define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */ 459 #define DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2 /*!< Sinc 4 filter type */ 460 #define DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */ 461 /** 462 * @} 463 */ 464 465 /** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source 466 * @{ 467 */ 468 #define DFSDM_FILTER_AWD_FILTER_DATA 0x00000000U /*!< From digital filter */ 469 #define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL /*!< From analog watchdog channel */ 470 /** 471 * @} 472 */ 473 474 /** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code 475 * @{ 476 */ 477 #define DFSDM_FILTER_ERROR_NONE 0x00000000U /*!< No error */ 478 #define DFSDM_FILTER_ERROR_REGULAR_OVERRUN 0x00000001U /*!< Overrun occurs during regular conversion */ 479 #define DFSDM_FILTER_ERROR_INJECTED_OVERRUN 0x00000002U /*!< Overrun occurs during injected conversion */ 480 #define DFSDM_FILTER_ERROR_DMA 0x00000003U /*!< DMA error occurs */ 481 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 482 #define DFSDM_FILTER_ERROR_INVALID_CALLBACK 0x00000004U /*!< Invalid callback error occurs */ 483 #endif 484 /** 485 * @} 486 */ 487 488 /** @defgroup DFSDM_BreakSignals DFSDM break signals 489 * @{ 490 */ 491 #define DFSDM_NO_BREAK_SIGNAL 0x00000000U /*!< No break signal */ 492 #define DFSDM_BREAK_SIGNAL_0 0x00000001U /*!< Break signal 0 */ 493 #define DFSDM_BREAK_SIGNAL_1 0x00000002U /*!< Break signal 1 */ 494 #define DFSDM_BREAK_SIGNAL_2 0x00000004U /*!< Break signal 2 */ 495 #define DFSDM_BREAK_SIGNAL_3 0x00000008U /*!< Break signal 3 */ 496 /** 497 * @} 498 */ 499 500 /** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection 501 * @{ 502 */ 503 /* DFSDM Channels ------------------------------------------------------------*/ 504 /* The DFSDM channels are defined as follows: 505 - in 16-bit LSB the channel mask is set 506 - in 16-bit MSB the channel number is set 507 e.g. for channel 5 definition: 508 - the channel mask is 0x00000020 (bit 5 is set) 509 - the channel number 5 is 0x00050000 510 --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */ 511 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ 512 defined(STM32L4P5xx) || defined(STM32L4Q5xx) 513 #define DFSDM_CHANNEL_0 0x00000001U 514 #define DFSDM_CHANNEL_1 0x00010002U 515 #define DFSDM_CHANNEL_2 0x00020004U 516 #define DFSDM_CHANNEL_3 0x00030008U 517 #else 518 #define DFSDM_CHANNEL_0 0x00000001U 519 #define DFSDM_CHANNEL_1 0x00010002U 520 #define DFSDM_CHANNEL_2 0x00020004U 521 #define DFSDM_CHANNEL_3 0x00030008U 522 #define DFSDM_CHANNEL_4 0x00040010U 523 #define DFSDM_CHANNEL_5 0x00050020U 524 #define DFSDM_CHANNEL_6 0x00060040U 525 #define DFSDM_CHANNEL_7 0x00070080U 526 #endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L4P5xx || STM32L4Q5xx */ 527 /** 528 * @} 529 */ 530 531 /** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode 532 * @{ 533 */ 534 #define DFSDM_CONTINUOUS_CONV_OFF 0x00000000U /*!< Conversion are not continuous */ 535 #define DFSDM_CONTINUOUS_CONV_ON 0x00000001U /*!< Conversion are continuous */ 536 /** 537 * @} 538 */ 539 540 /** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold 541 * @{ 542 */ 543 #define DFSDM_AWD_HIGH_THRESHOLD 0x00000000U /*!< Analog watchdog high threshold */ 544 #define DFSDM_AWD_LOW_THRESHOLD 0x00000001U /*!< Analog watchdog low threshold */ 545 /** 546 * @} 547 */ 548 549 /** 550 * @} 551 */ 552 /* End of exported constants -------------------------------------------------*/ 553 554 /* Exported macros -----------------------------------------------------------*/ 555 /** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros 556 * @{ 557 */ 558 559 /** @brief Reset DFSDM channel handle state. 560 * @param __HANDLE__ DFSDM channel handle. 561 * @retval None 562 */ 563 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 564 #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) do{ \ 565 (__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET; \ 566 (__HANDLE__)->MspInitCallback = NULL; \ 567 (__HANDLE__)->MspDeInitCallback = NULL; \ 568 } while(0) 569 #else 570 #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET) 571 #endif 572 573 /** @brief Reset DFSDM filter handle state. 574 * @param __HANDLE__ DFSDM filter handle. 575 * @retval None 576 */ 577 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 578 #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) do{ \ 579 (__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET; \ 580 (__HANDLE__)->MspInitCallback = NULL; \ 581 (__HANDLE__)->MspDeInitCallback = NULL; \ 582 } while(0) 583 #else 584 #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET) 585 #endif 586 587 /** 588 * @} 589 */ 590 /* End of exported macros ----------------------------------------------------*/ 591 592 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) || \ 593 defined(STM32L4P5xx) || defined(STM32L4Q5xx) 594 /* Include DFSDM HAL Extension module */ 595 #include "stm32l4xx_hal_dfsdm_ex.h" 596 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx || STM32L4P5xx || STM32L4Q5xx */ 597 598 /* Exported functions --------------------------------------------------------*/ 599 /** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions 600 * @{ 601 */ 602 603 /** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions 604 * @{ 605 */ 606 /* Channel initialization and de-initialization functions *********************/ 607 HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 608 HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 609 void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 610 void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 611 612 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 613 /* Channel callbacks register/unregister functions ****************************/ 614 HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, 615 HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID, 616 pDFSDM_Channel_CallbackTypeDef pCallback); 617 HAL_StatusTypeDef HAL_DFSDM_Channel_UnRegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, 618 HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID); 619 #endif 620 /** 621 * @} 622 */ 623 624 /** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions 625 * @{ 626 */ 627 /* Channel operation functions ************************************************/ 628 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 629 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 630 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 631 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 632 633 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal); 634 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal); 635 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 636 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 637 638 int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 639 HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset); 640 641 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); 642 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); 643 644 void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 645 void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 646 /** 647 * @} 648 */ 649 650 /** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function 651 * @{ 652 */ 653 /* Channel state function *****************************************************/ 654 HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 655 /** 656 * @} 657 */ 658 659 /** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions 660 * @{ 661 */ 662 /* Filter initialization and de-initialization functions *********************/ 663 HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 664 HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 665 void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 666 void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 667 668 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 669 /* Filter callbacks register/unregister functions ****************************/ 670 HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 671 HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID, 672 pDFSDM_Filter_CallbackTypeDef pCallback); 673 HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 674 HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID); 675 HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 676 pDFSDM_Filter_AwdCallbackTypeDef pCallback); 677 HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 678 #endif 679 /** 680 * @} 681 */ 682 683 /** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions 684 * @{ 685 */ 686 /* Filter control functions *********************/ 687 HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 688 uint32_t Channel, 689 uint32_t ContinuousMode); 690 HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 691 uint32_t Channel); 692 /** 693 * @} 694 */ 695 696 /** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions 697 * @{ 698 */ 699 /* Filter operation functions *********************/ 700 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 701 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 702 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length); 703 HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length); 704 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 705 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 706 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 707 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 708 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 709 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length); 710 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length); 711 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 712 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 713 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 714 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 715 DFSDM_Filter_AwdParamTypeDef *awdParam); 716 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 717 HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel); 718 HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 719 720 int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel); 721 int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel); 722 int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel); 723 int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel); 724 uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 725 726 void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 727 728 HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout); 729 HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout); 730 731 void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 732 void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 733 void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 734 void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 735 void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold); 736 void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 737 /** 738 * @} 739 */ 740 741 /** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions 742 * @{ 743 */ 744 /* Filter state functions *****************************************************/ 745 HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 746 uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 747 /** 748 * @} 749 */ 750 751 /** 752 * @} 753 */ 754 /* End of exported functions -------------------------------------------------*/ 755 756 /* Private macros ------------------------------------------------------------*/ 757 /** @defgroup DFSDM_Private_Macros DFSDM Private Macros 758 * @{ 759 */ 760 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \ 761 ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO)) 762 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2U <= (DIVIDER)) && ((DIVIDER) <= 256U)) 763 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ 764 defined(STM32L496xx) || defined(STM32L4A6xx) || \ 765 defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) || \ 766 defined(STM32L4P5xx) || defined(STM32L4Q5xx) 767 #define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \ 768 ((INPUT) == DFSDM_CHANNEL_ADC_OUTPUT) || \ 769 ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER)) 770 #else 771 #define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \ 772 ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER)) 773 #endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ 774 /* STM32L496xx || STM32L4A6xx || */ 775 /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx || */ 776 /* STM32L4P5xx || STM32L4Q5xx || */ 777 #define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \ 778 ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \ 779 ((MODE) == DFSDM_CHANNEL_DUAL_MODE)) 780 #define IS_DFSDM_CHANNEL_INPUT_PINS(PINS) (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \ 781 ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS)) 782 #define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE) (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \ 783 ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \ 784 ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \ 785 ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING)) 786 #define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE) (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \ 787 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \ 788 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \ 789 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING)) 790 #define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER) (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \ 791 ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \ 792 ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \ 793 ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER)) 794 #define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 32U)) 795 #define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) 796 #define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1FU) 797 #define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFFU) 798 #define IS_DFSDM_FILTER_REG_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ 799 ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER)) 800 #define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ 801 ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \ 802 ((TRIG) == DFSDM_FILTER_EXT_TRIGGER)) 803 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) 804 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \ 805 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \ 806 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \ 807 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \ 808 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \ 809 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \ 810 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15)) 811 #elif defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) || \ 812 defined(STM32L4P5xx) || defined(STM32L4Q5xx) 813 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \ 814 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \ 815 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \ 816 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \ 817 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \ 818 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \ 819 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \ 820 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \ 821 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \ 822 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \ 823 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) || \ 824 ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT)) 825 #else 826 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \ 827 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \ 828 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \ 829 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \ 830 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \ 831 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \ 832 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \ 833 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \ 834 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \ 835 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \ 836 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15)) 837 #endif /* STM32L451xx || STM32L452xx || STM32L462xx */ 838 #define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE) (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE) || \ 839 ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE) || \ 840 ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES)) 841 #define IS_DFSDM_FILTER_SINC_ORDER(ORDER) (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \ 842 ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \ 843 ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \ 844 ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \ 845 ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \ 846 ((ORDER) == DFSDM_FILTER_SINC5_ORDER)) 847 #define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 1024U)) 848 #define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 256U)) 849 #define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA) (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA) || \ 850 ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA)) 851 #define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) 852 #define IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0xFU) 853 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ 854 defined(STM32L4P5xx) || defined(STM32L4Q5xx) 855 #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \ 856 ((CHANNEL) == DFSDM_CHANNEL_1) || \ 857 ((CHANNEL) == DFSDM_CHANNEL_2) || \ 858 ((CHANNEL) == DFSDM_CHANNEL_3)) 859 #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x0003000FU)) 860 #else 861 #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \ 862 ((CHANNEL) == DFSDM_CHANNEL_1) || \ 863 ((CHANNEL) == DFSDM_CHANNEL_2) || \ 864 ((CHANNEL) == DFSDM_CHANNEL_3) || \ 865 ((CHANNEL) == DFSDM_CHANNEL_4) || \ 866 ((CHANNEL) == DFSDM_CHANNEL_5) || \ 867 ((CHANNEL) == DFSDM_CHANNEL_6) || \ 868 ((CHANNEL) == DFSDM_CHANNEL_7)) 869 #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F00FFU)) 870 #endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L4P5xx || STM32L4Q5xx */ 871 #define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) || \ 872 ((MODE) == DFSDM_CONTINUOUS_CONV_ON)) 873 /** 874 * @} 875 */ 876 /* End of private macros -----------------------------------------------------*/ 877 878 /** 879 * @} 880 */ 881 882 /** 883 * @} 884 */ 885 #endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ 886 /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ 887 /* STM32L496xx || STM32L4A6xx || */ 888 /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx || */ 889 /* STM32L4P5xx || STM32L4Q5xx */ 890 891 #ifdef __cplusplus 892 } 893 #endif 894 895 #endif /* STM32L4xx_HAL_DFSDM_H */ 896 897 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 898