1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_sai.h 4 * @author MCD Application Team 5 * @brief Header file of SAI HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32L4xx_HAL_SAI_H 22 #define STM32L4xx_HAL_SAI_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 #if !defined(STM32L412xx) && !defined(STM32L422xx) 29 30 /* Includes ------------------------------------------------------------------*/ 31 #include "stm32l4xx_hal_def.h" 32 33 /** @addtogroup STM32L4xx_HAL_Driver 34 * @{ 35 */ 36 37 /** @addtogroup SAI 38 * @{ 39 */ 40 41 /* Exported types ------------------------------------------------------------*/ 42 /** @defgroup SAI_Exported_Types SAI Exported Types 43 * @{ 44 */ 45 46 /** 47 * @brief HAL State structures definition 48 */ 49 typedef enum 50 { 51 HAL_SAI_STATE_RESET = 0x00U, /*!< SAI not yet initialized or disabled */ 52 HAL_SAI_STATE_READY = 0x01U, /*!< SAI initialized and ready for use */ 53 HAL_SAI_STATE_BUSY = 0x02U, /*!< SAI internal process is ongoing */ 54 HAL_SAI_STATE_BUSY_TX = 0x12U, /*!< Data transmission process is ongoing */ 55 HAL_SAI_STATE_BUSY_RX = 0x22U, /*!< Data reception process is ongoing */ 56 } HAL_SAI_StateTypeDef; 57 58 /** 59 * @brief SAI Callback prototype 60 */ 61 typedef void (*SAIcallback)(void); 62 63 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) || \ 64 defined(STM32L4P5xx) || defined(STM32L4Q5xx) 65 /** @defgroup SAI_PDM_Structure_definition SAI PDM Structure definition 66 * @brief SAI PDM Init structure definition 67 * @{ 68 */ 69 typedef struct 70 { 71 FunctionalState Activation; /*!< Enable/disable PDM interface */ 72 uint32_t MicPairsNbr; /*!< Specifies the number of microphone pairs used. 73 This parameter must be a number between Min_Data = 1 and Max_Data = 3. */ 74 uint32_t ClockEnable; /*!< Specifies which clock must be enabled. 75 This parameter can be a values combination of @ref SAI_PDM_ClockEnable */ 76 } SAI_PdmInitTypeDef; 77 /** 78 * @} 79 */ 80 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx || */ 81 /* STM32L4P5xx || STM32L4Q5xx */ 82 83 /** @defgroup SAI_Init_Structure_definition SAI Init Structure definition 84 * @brief SAI Init Structure definition 85 * @{ 86 */ 87 typedef struct 88 { 89 uint32_t AudioMode; /*!< Specifies the SAI Block audio Mode. 90 This parameter can be a value of @ref SAI_Block_Mode */ 91 92 uint32_t Synchro; /*!< Specifies SAI Block synchronization 93 This parameter can be a value of @ref SAI_Block_Synchronization */ 94 95 uint32_t SynchroExt; /*!< Specifies SAI external output synchronization, this setup is common 96 for BlockA and BlockB 97 This parameter can be a value of @ref SAI_Block_SyncExt 98 @note If both audio blocks of same SAI are used, this parameter has 99 to be set to the same value for each audio block */ 100 101 uint32_t OutputDrive; /*!< Specifies when SAI Block outputs are driven. 102 This parameter can be a value of @ref SAI_Block_Output_Drive 103 @note This value has to be set before enabling the audio block 104 but after the audio block configuration. */ 105 106 uint32_t NoDivider; /*!< Specifies whether master clock will be divided or not. 107 This parameter can be a value of @ref SAI_Block_NoDivider 108 @note For STM32L4Rx/STM32L4Sx devices : 109 If bit NOMCK in the SAI_xCR1 register is cleared, the frame length 110 should be aligned to a number equal to a power of 2, from 8 to 256. 111 If bit NOMCK in the SAI_xCR1 register is set, the frame length can 112 take any of the values without constraint. There is no MCLK_x clock 113 which can be output. 114 For other devices : 115 If bit NODIV in the SAI_xCR1 register is cleared, the frame length 116 should be aligned to a number equal to a power of 2, from 8 to 256. 117 If bit NODIV in the SAI_xCR1 register is set, the frame length can 118 take any of the values without constraint since the input clock of 119 the audio block should be equal to the bit clock. 120 There is no MCLK_x clock which can be output. */ 121 122 uint32_t FIFOThreshold; /*!< Specifies SAI Block FIFO threshold. 123 This parameter can be a value of @ref SAI_Block_Fifo_Threshold */ 124 125 uint32_t AudioFrequency; /*!< Specifies the audio frequency sampling. 126 This parameter can be a value of @ref SAI_Audio_Frequency */ 127 128 uint32_t Mckdiv; /*!< Specifies the master clock divider. 129 This parameter must be a number between Min_Data = 0 and Max_Data = 63 on STM32L4Rx/STM32L4Sx devices. 130 This parameter must be a number between Min_Data = 0 and Max_Data = 15 on other devices. 131 @note This parameter is used only if AudioFrequency is set to 132 SAI_AUDIO_FREQUENCY_MCKDIV otherwise it is internally computed. */ 133 134 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) || \ 135 defined(STM32L4P5xx) || defined(STM32L4Q5xx) 136 uint32_t MckOverSampling; /*!< Specifies the master clock oversampling. 137 This parameter can be a value of @ref SAI_Block_Mck_OverSampling */ 138 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx || */ 139 /* STM32L4P5xx || STM32L4Q5xx */ 140 141 uint32_t MonoStereoMode; /*!< Specifies if the mono or stereo mode is selected. 142 This parameter can be a value of @ref SAI_Mono_Stereo_Mode */ 143 144 uint32_t CompandingMode; /*!< Specifies the companding mode type. 145 This parameter can be a value of @ref SAI_Block_Companding_Mode */ 146 147 uint32_t TriState; /*!< Specifies the companding mode type. 148 This parameter can be a value of @ref SAI_TRIState_Management */ 149 150 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) || \ 151 defined(STM32L4P5xx) || defined(STM32L4Q5xx) 152 SAI_PdmInitTypeDef PdmInit; /*!< Specifies the PDM configuration. */ 153 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx || */ 154 /* STM32L4P5xx || STM32L4Q5xx */ 155 156 /* This part of the structure is automatically filled if your are using the high level initialisation 157 function HAL_SAI_InitProtocol */ 158 159 uint32_t Protocol; /*!< Specifies the SAI Block protocol. 160 This parameter can be a value of @ref SAI_Block_Protocol */ 161 162 uint32_t DataSize; /*!< Specifies the SAI Block data size. 163 This parameter can be a value of @ref SAI_Block_Data_Size */ 164 165 uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. 166 This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission */ 167 168 uint32_t ClockStrobing; /*!< Specifies the SAI Block clock strobing edge sensitivity. 169 This parameter can be a value of @ref SAI_Block_Clock_Strobing */ 170 } SAI_InitTypeDef; 171 /** 172 * @} 173 */ 174 175 /** @defgroup SAI_Frame_Structure_definition SAI Frame Structure definition 176 * @brief SAI Frame Init structure definition 177 * @note For SPDIF and AC97 protocol, these parameters are not used (set by hardware). 178 * @{ 179 */ 180 typedef struct 181 { 182 183 uint32_t FrameLength; /*!< Specifies the Frame length, the number of SCK clocks for each audio frame. 184 This parameter must be a number between Min_Data = 8 and Max_Data = 256. 185 @note If master clock MCLK_x pin is declared as an output, the frame length 186 should be aligned to a number equal to power of 2 in order to keep 187 in an audio frame, an integer number of MCLK pulses by bit Clock. */ 188 189 uint32_t ActiveFrameLength; /*!< Specifies the Frame synchronization active level length. 190 This Parameter specifies the length in number of bit clock (SCK + 1) 191 of the active level of FS signal in audio frame. 192 This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ 193 194 uint32_t FSDefinition; /*!< Specifies the Frame synchronization definition. 195 This parameter can be a value of @ref SAI_Block_FS_Definition */ 196 197 uint32_t FSPolarity; /*!< Specifies the Frame synchronization Polarity. 198 This parameter can be a value of @ref SAI_Block_FS_Polarity */ 199 200 uint32_t FSOffset; /*!< Specifies the Frame synchronization Offset. 201 This parameter can be a value of @ref SAI_Block_FS_Offset */ 202 203 } SAI_FrameInitTypeDef; 204 /** 205 * @} 206 */ 207 208 /** @defgroup SAI_Slot_Structure_definition SAI Slot Structure definition 209 * @brief SAI Block Slot Init Structure definition 210 * @note For SPDIF protocol, these parameters are not used (set by hardware). 211 * @note For AC97 protocol, only SlotActive parameter is used (the others are set by hardware). 212 * @{ 213 */ 214 typedef struct 215 { 216 uint32_t FirstBitOffset; /*!< Specifies the position of first data transfer bit in the slot. 217 This parameter must be a number between Min_Data = 0 and Max_Data = 24 */ 218 219 uint32_t SlotSize; /*!< Specifies the Slot Size. 220 This parameter can be a value of @ref SAI_Block_Slot_Size */ 221 222 uint32_t SlotNumber; /*!< Specifies the number of slot in the audio frame. 223 This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ 224 225 uint32_t SlotActive; /*!< Specifies the slots in audio frame that will be activated. 226 This parameter can be a value of @ref SAI_Block_Slot_Active */ 227 } SAI_SlotInitTypeDef; 228 /** 229 * @} 230 */ 231 232 /** @defgroup SAI_Handle_Structure_definition SAI Handle Structure definition 233 * @brief SAI handle Structure definition 234 * @{ 235 */ 236 typedef struct __SAI_HandleTypeDef 237 { 238 SAI_Block_TypeDef *Instance; /*!< SAI Blockx registers base address */ 239 240 SAI_InitTypeDef Init; /*!< SAI communication parameters */ 241 242 SAI_FrameInitTypeDef FrameInit; /*!< SAI Frame configuration parameters */ 243 244 SAI_SlotInitTypeDef SlotInit; /*!< SAI Slot configuration parameters */ 245 246 uint8_t *pBuffPtr; /*!< Pointer to SAI transfer Buffer */ 247 248 uint16_t XferSize; /*!< SAI transfer size */ 249 250 uint16_t XferCount; /*!< SAI transfer counter */ 251 252 DMA_HandleTypeDef *hdmatx; /*!< SAI Tx DMA handle parameters */ 253 254 DMA_HandleTypeDef *hdmarx; /*!< SAI Rx DMA handle parameters */ 255 256 SAIcallback mutecallback; /*!< SAI mute callback */ 257 258 void (*InterruptServiceRoutine)(struct __SAI_HandleTypeDef *hsai); /* function pointer for IRQ handler */ 259 260 HAL_LockTypeDef Lock; /*!< SAI locking object */ 261 262 __IO HAL_SAI_StateTypeDef State; /*!< SAI communication state */ 263 264 __IO uint32_t ErrorCode; /*!< SAI Error code */ 265 266 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) 267 void (*RxCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI receive complete callback */ 268 void (*RxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI receive half complete callback */ 269 void (*TxCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI transmit complete callback */ 270 void (*TxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI transmit half complete callback */ 271 void (*ErrorCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI error callback */ 272 void (*MspInitCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI MSP init callback */ 273 void (*MspDeInitCallback)(struct __SAI_HandleTypeDef *hsai); /*!< SAI MSP de-init callback */ 274 #endif 275 } SAI_HandleTypeDef; 276 /** 277 * @} 278 */ 279 280 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) 281 /** 282 * @brief SAI callback ID enumeration definition 283 */ 284 typedef enum 285 { 286 HAL_SAI_RX_COMPLETE_CB_ID = 0x00U, /*!< SAI receive complete callback ID */ 287 HAL_SAI_RX_HALFCOMPLETE_CB_ID = 0x01U, /*!< SAI receive half complete callback ID */ 288 HAL_SAI_TX_COMPLETE_CB_ID = 0x02U, /*!< SAI transmit complete callback ID */ 289 HAL_SAI_TX_HALFCOMPLETE_CB_ID = 0x03U, /*!< SAI transmit half complete callback ID */ 290 HAL_SAI_ERROR_CB_ID = 0x04U, /*!< SAI error callback ID */ 291 HAL_SAI_MSPINIT_CB_ID = 0x05U, /*!< SAI MSP init callback ID */ 292 HAL_SAI_MSPDEINIT_CB_ID = 0x06U /*!< SAI MSP de-init callback ID */ 293 } HAL_SAI_CallbackIDTypeDef; 294 295 /** 296 * @brief SAI callback pointer definition 297 */ 298 typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai); 299 #endif 300 301 /** 302 * @} 303 */ 304 305 /* Exported constants --------------------------------------------------------*/ 306 /** @defgroup SAI_Exported_Constants SAI Exported Constants 307 * @{ 308 */ 309 310 /** @defgroup SAI_Error_Code SAI Error Code 311 * @{ 312 */ 313 #define HAL_SAI_ERROR_NONE 0x00000000U /*!< No error */ 314 #define HAL_SAI_ERROR_OVR 0x00000001U /*!< Overrun Error */ 315 #define HAL_SAI_ERROR_UDR 0x00000002U /*!< Underrun error */ 316 #define HAL_SAI_ERROR_AFSDET 0x00000004U /*!< Anticipated Frame synchronisation detection */ 317 #define HAL_SAI_ERROR_LFSDET 0x00000008U /*!< Late Frame synchronisation detection */ 318 #define HAL_SAI_ERROR_CNREADY 0x00000010U /*!< codec not ready */ 319 #define HAL_SAI_ERROR_WCKCFG 0x00000020U /*!< Wrong clock configuration */ 320 #define HAL_SAI_ERROR_TIMEOUT 0x00000040U /*!< Timeout error */ 321 #define HAL_SAI_ERROR_DMA 0x00000080U /*!< DMA error */ 322 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) 323 #define HAL_SAI_ERROR_INVALID_CALLBACK 0x00000100U /*!< Invalid callback error */ 324 #endif 325 /** 326 * @} 327 */ 328 329 /** @defgroup SAI_Block_SyncExt SAI External synchronisation 330 * @{ 331 */ 332 #define SAI_SYNCEXT_DISABLE 0U 333 #define SAI_SYNCEXT_OUTBLOCKA_ENABLE 1U 334 #define SAI_SYNCEXT_OUTBLOCKB_ENABLE 2U 335 /** 336 * @} 337 */ 338 339 /** @defgroup SAI_Protocol SAI Supported protocol 340 * @{ 341 */ 342 #define SAI_I2S_STANDARD 0U 343 #define SAI_I2S_MSBJUSTIFIED 1U 344 #define SAI_I2S_LSBJUSTIFIED 2U 345 #define SAI_PCM_LONG 3U 346 #define SAI_PCM_SHORT 4U 347 /** 348 * @} 349 */ 350 351 /** @defgroup SAI_Protocol_DataSize SAI protocol data size 352 * @{ 353 */ 354 #define SAI_PROTOCOL_DATASIZE_16BIT 0U 355 #define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1U 356 #define SAI_PROTOCOL_DATASIZE_24BIT 2U 357 #define SAI_PROTOCOL_DATASIZE_32BIT 3U 358 /** 359 * @} 360 */ 361 362 /** @defgroup SAI_Audio_Frequency SAI Audio Frequency 363 * @{ 364 */ 365 #define SAI_AUDIO_FREQUENCY_192K 192000U 366 #define SAI_AUDIO_FREQUENCY_96K 96000U 367 #define SAI_AUDIO_FREQUENCY_48K 48000U 368 #define SAI_AUDIO_FREQUENCY_44K 44100U 369 #define SAI_AUDIO_FREQUENCY_32K 32000U 370 #define SAI_AUDIO_FREQUENCY_22K 22050U 371 #define SAI_AUDIO_FREQUENCY_16K 16000U 372 #define SAI_AUDIO_FREQUENCY_11K 11025U 373 #define SAI_AUDIO_FREQUENCY_8K 8000U 374 #define SAI_AUDIO_FREQUENCY_MCKDIV 0U 375 /** 376 * @} 377 */ 378 379 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) || \ 380 defined(STM32L4P5xx) || defined(STM32L4Q5xx) 381 /** @defgroup SAI_Block_Mck_OverSampling SAI Block Master Clock OverSampling 382 * @{ 383 */ 384 #define SAI_MCK_OVERSAMPLING_DISABLE 0x00000000U 385 #define SAI_MCK_OVERSAMPLING_ENABLE SAI_xCR1_OSR 386 /** 387 * @} 388 */ 389 390 /** @defgroup SAI_PDM_ClockEnable SAI PDM Clock Enable 391 * @{ 392 */ 393 #define SAI_PDM_CLOCK1_ENABLE SAI_PDMCR_CKEN1 394 #define SAI_PDM_CLOCK2_ENABLE SAI_PDMCR_CKEN2 395 /** 396 * @} 397 */ 398 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx || */ 399 /* STM32L4P5xx || STM32L4Q5xx */ 400 401 /** @defgroup SAI_Block_Mode SAI Block Mode 402 * @{ 403 */ 404 #define SAI_MODEMASTER_TX 0x00000000U 405 #define SAI_MODEMASTER_RX SAI_xCR1_MODE_0 406 #define SAI_MODESLAVE_TX SAI_xCR1_MODE_1 407 #define SAI_MODESLAVE_RX (SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0) 408 409 /** 410 * @} 411 */ 412 413 /** @defgroup SAI_Block_Protocol SAI Block Protocol 414 * @{ 415 */ 416 #define SAI_FREE_PROTOCOL 0x00000000U 417 #define SAI_SPDIF_PROTOCOL SAI_xCR1_PRTCFG_0 418 #define SAI_AC97_PROTOCOL SAI_xCR1_PRTCFG_1 419 /** 420 * @} 421 */ 422 423 /** @defgroup SAI_Block_Data_Size SAI Block Data Size 424 * @{ 425 */ 426 #define SAI_DATASIZE_8 SAI_xCR1_DS_1 427 #define SAI_DATASIZE_10 (SAI_xCR1_DS_1 | SAI_xCR1_DS_0) 428 #define SAI_DATASIZE_16 SAI_xCR1_DS_2 429 #define SAI_DATASIZE_20 (SAI_xCR1_DS_2 | SAI_xCR1_DS_0) 430 #define SAI_DATASIZE_24 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1) 431 #define SAI_DATASIZE_32 (SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0) 432 /** 433 * @} 434 */ 435 436 /** @defgroup SAI_Block_MSB_LSB_transmission SAI Block MSB LSB transmission 437 * @{ 438 */ 439 #define SAI_FIRSTBIT_MSB 0x00000000U 440 #define SAI_FIRSTBIT_LSB SAI_xCR1_LSBFIRST 441 /** 442 * @} 443 */ 444 445 /** @defgroup SAI_Block_Clock_Strobing SAI Block Clock Strobing 446 * @{ 447 */ 448 #define SAI_CLOCKSTROBING_FALLINGEDGE 0U 449 #define SAI_CLOCKSTROBING_RISINGEDGE 1U 450 /** 451 * @} 452 */ 453 454 /** @defgroup SAI_Block_Synchronization SAI Block Synchronization 455 * @{ 456 */ 457 #define SAI_ASYNCHRONOUS 0U /*!< Asynchronous */ 458 #define SAI_SYNCHRONOUS 1U /*!< Synchronous with other block of same SAI */ 459 #define SAI_SYNCHRONOUS_EXT_SAI1 2U /*!< Synchronous with other SAI, SAI1 */ 460 #define SAI_SYNCHRONOUS_EXT_SAI2 3U /*!< Synchronous with other SAI, SAI2 */ 461 /** 462 * @} 463 */ 464 465 /** @defgroup SAI_Block_Output_Drive SAI Block Output Drive 466 * @{ 467 */ 468 #define SAI_OUTPUTDRIVE_DISABLE 0x00000000U 469 #define SAI_OUTPUTDRIVE_ENABLE SAI_xCR1_OUTDRIV 470 /** 471 * @} 472 */ 473 474 /** @defgroup SAI_Block_NoDivider SAI Block NoDivider 475 * @{ 476 */ 477 #define SAI_MASTERDIVIDER_ENABLE 0x00000000U 478 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) || \ 479 defined(STM32L4P5xx) || defined(STM32L4Q5xx) 480 #define SAI_MASTERDIVIDER_DISABLE SAI_xCR1_NOMCK 481 #else 482 #define SAI_MASTERDIVIDER_DISABLE SAI_xCR1_NODIV 483 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx || */ 484 /* STM32L4P5xx || STM32L4Q5xx */ 485 /** 486 * @} 487 */ 488 489 /** @defgroup SAI_Block_FS_Definition SAI Block FS Definition 490 * @{ 491 */ 492 #define SAI_FS_STARTFRAME 0x00000000U 493 #define SAI_FS_CHANNEL_IDENTIFICATION SAI_xFRCR_FSDEF 494 /** 495 * @} 496 */ 497 498 /** @defgroup SAI_Block_FS_Polarity SAI Block FS Polarity 499 * @{ 500 */ 501 #define SAI_FS_ACTIVE_LOW 0x00000000U 502 #define SAI_FS_ACTIVE_HIGH SAI_xFRCR_FSPOL 503 /** 504 * @} 505 */ 506 507 /** @defgroup SAI_Block_FS_Offset SAI Block FS Offset 508 * @{ 509 */ 510 #define SAI_FS_FIRSTBIT 0x00000000U 511 #define SAI_FS_BEFOREFIRSTBIT SAI_xFRCR_FSOFF 512 /** 513 * @} 514 */ 515 516 /** @defgroup SAI_Block_Slot_Size SAI Block Slot Size 517 * @{ 518 */ 519 #define SAI_SLOTSIZE_DATASIZE 0x00000000U 520 #define SAI_SLOTSIZE_16B SAI_xSLOTR_SLOTSZ_0 521 #define SAI_SLOTSIZE_32B SAI_xSLOTR_SLOTSZ_1 522 /** 523 * @} 524 */ 525 526 /** @defgroup SAI_Block_Slot_Active SAI Block Slot Active 527 * @{ 528 */ 529 #define SAI_SLOT_NOTACTIVE 0x00000000U 530 #define SAI_SLOTACTIVE_0 0x00000001U 531 #define SAI_SLOTACTIVE_1 0x00000002U 532 #define SAI_SLOTACTIVE_2 0x00000004U 533 #define SAI_SLOTACTIVE_3 0x00000008U 534 #define SAI_SLOTACTIVE_4 0x00000010U 535 #define SAI_SLOTACTIVE_5 0x00000020U 536 #define SAI_SLOTACTIVE_6 0x00000040U 537 #define SAI_SLOTACTIVE_7 0x00000080U 538 #define SAI_SLOTACTIVE_8 0x00000100U 539 #define SAI_SLOTACTIVE_9 0x00000200U 540 #define SAI_SLOTACTIVE_10 0x00000400U 541 #define SAI_SLOTACTIVE_11 0x00000800U 542 #define SAI_SLOTACTIVE_12 0x00001000U 543 #define SAI_SLOTACTIVE_13 0x00002000U 544 #define SAI_SLOTACTIVE_14 0x00004000U 545 #define SAI_SLOTACTIVE_15 0x00008000U 546 #define SAI_SLOTACTIVE_ALL 0x0000FFFFU 547 /** 548 * @} 549 */ 550 551 /** @defgroup SAI_Mono_Stereo_Mode SAI Mono Stereo Mode 552 * @{ 553 */ 554 #define SAI_STEREOMODE 0x00000000U 555 #define SAI_MONOMODE SAI_xCR1_MONO 556 /** 557 * @} 558 */ 559 560 /** @defgroup SAI_TRIState_Management SAI TRIState Management 561 * @{ 562 */ 563 #define SAI_OUTPUT_NOTRELEASED 0x00000000U 564 #define SAI_OUTPUT_RELEASED SAI_xCR2_TRIS 565 /** 566 * @} 567 */ 568 569 /** @defgroup SAI_Block_Fifo_Threshold SAI Block Fifo Threshold 570 * @{ 571 */ 572 #define SAI_FIFOTHRESHOLD_EMPTY 0x00000000U 573 #define SAI_FIFOTHRESHOLD_1QF SAI_xCR2_FTH_0 574 #define SAI_FIFOTHRESHOLD_HF SAI_xCR2_FTH_1 575 #define SAI_FIFOTHRESHOLD_3QF (SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0) 576 #define SAI_FIFOTHRESHOLD_FULL SAI_xCR2_FTH_2 577 /** 578 * @} 579 */ 580 581 /** @defgroup SAI_Block_Companding_Mode SAI Block Companding Mode 582 * @{ 583 */ 584 #define SAI_NOCOMPANDING 0x00000000U 585 #define SAI_ULAW_1CPL_COMPANDING SAI_xCR2_COMP_1 586 #define SAI_ALAW_1CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0) 587 #define SAI_ULAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_CPL) 588 #define SAI_ALAW_2CPL_COMPANDING (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL) 589 /** 590 * @} 591 */ 592 593 /** @defgroup SAI_Block_Mute_Value SAI Block Mute Value 594 * @{ 595 */ 596 #define SAI_ZERO_VALUE 0x00000000U 597 #define SAI_LAST_SENT_VALUE SAI_xCR2_MUTEVAL 598 /** 599 * @} 600 */ 601 602 /** @defgroup SAI_Block_Interrupts_Definition SAI Block Interrupts Definition 603 * @{ 604 */ 605 #define SAI_IT_OVRUDR SAI_xIMR_OVRUDRIE 606 #define SAI_IT_MUTEDET SAI_xIMR_MUTEDETIE 607 #define SAI_IT_WCKCFG SAI_xIMR_WCKCFGIE 608 #define SAI_IT_FREQ SAI_xIMR_FREQIE 609 #define SAI_IT_CNRDY SAI_xIMR_CNRDYIE 610 #define SAI_IT_AFSDET SAI_xIMR_AFSDETIE 611 #define SAI_IT_LFSDET SAI_xIMR_LFSDETIE 612 /** 613 * @} 614 */ 615 616 /** @defgroup SAI_Block_Flags_Definition SAI Block Flags Definition 617 * @{ 618 */ 619 #define SAI_FLAG_OVRUDR SAI_xSR_OVRUDR 620 #define SAI_FLAG_MUTEDET SAI_xSR_MUTEDET 621 #define SAI_FLAG_WCKCFG SAI_xSR_WCKCFG 622 #define SAI_FLAG_FREQ SAI_xSR_FREQ 623 #define SAI_FLAG_CNRDY SAI_xSR_CNRDY 624 #define SAI_FLAG_AFSDET SAI_xSR_AFSDET 625 #define SAI_FLAG_LFSDET SAI_xSR_LFSDET 626 /** 627 * @} 628 */ 629 630 /** @defgroup SAI_Block_Fifo_Status_Level SAI Block Fifo Status Level 631 * @{ 632 */ 633 #define SAI_FIFOSTATUS_EMPTY 0x00000000U 634 #define SAI_FIFOSTATUS_LESS1QUARTERFULL 0x00010000U 635 #define SAI_FIFOSTATUS_1QUARTERFULL 0x00020000U 636 #define SAI_FIFOSTATUS_HALFFULL 0x00030000U 637 #define SAI_FIFOSTATUS_3QUARTERFULL 0x00040000U 638 #define SAI_FIFOSTATUS_FULL 0x00050000U 639 /** 640 * @} 641 */ 642 643 /** 644 * @} 645 */ 646 647 /* Exported macro ------------------------------------------------------------*/ 648 /** @defgroup SAI_Exported_Macros SAI Exported Macros 649 * @brief macros to handle interrupts and specific configurations 650 * @{ 651 */ 652 653 /** @brief Reset SAI handle state. 654 * @param __HANDLE__ specifies the SAI Handle. 655 * @retval None 656 */ 657 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) 658 #define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) do{ \ 659 (__HANDLE__)->State = HAL_SAI_STATE_RESET; \ 660 (__HANDLE__)->MspInitCallback = NULL; \ 661 (__HANDLE__)->MspDeInitCallback = NULL; \ 662 } while(0) 663 #else 664 #define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET) 665 #endif 666 667 /** @brief Enable the specified SAI interrupts. 668 * @param __HANDLE__ specifies the SAI Handle. 669 * @param __INTERRUPT__ specifies the interrupt source to enable or disable. 670 * This parameter can be one of the following values: 671 * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable 672 * @arg SAI_IT_MUTEDET: Mute detection interrupt enable 673 * @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable 674 * @arg SAI_IT_FREQ: FIFO request interrupt enable 675 * @arg SAI_IT_CNRDY: Codec not ready interrupt enable 676 * @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable 677 * @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable 678 * @retval None 679 */ 680 #define __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__)) 681 682 /** @brief Disable the specified SAI interrupts. 683 * @param __HANDLE__ specifies the SAI Handle. 684 * @param __INTERRUPT__ specifies the interrupt source to enable or disable. 685 * This parameter can be one of the following values: 686 * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable 687 * @arg SAI_IT_MUTEDET: Mute detection interrupt enable 688 * @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable 689 * @arg SAI_IT_FREQ: FIFO request interrupt enable 690 * @arg SAI_IT_CNRDY: Codec not ready interrupt enable 691 * @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable 692 * @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable 693 * @retval None 694 */ 695 #define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__))) 696 697 /** @brief Check whether the specified SAI interrupt source is enabled or not. 698 * @param __HANDLE__ specifies the SAI Handle. 699 * @param __INTERRUPT__ specifies the SAI interrupt source to check. 700 * This parameter can be one of the following values: 701 * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable 702 * @arg SAI_IT_MUTEDET: Mute detection interrupt enable 703 * @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable 704 * @arg SAI_IT_FREQ: FIFO request interrupt enable 705 * @arg SAI_IT_CNRDY: Codec not ready interrupt enable 706 * @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable 707 * @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable 708 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 709 */ 710 #define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 711 712 /** @brief Check whether the specified SAI flag is set or not. 713 * @param __HANDLE__ specifies the SAI Handle. 714 * @param __FLAG__ specifies the flag to check. 715 * This parameter can be one of the following values: 716 * @arg SAI_FLAG_OVRUDR: Overrun underrun flag. 717 * @arg SAI_FLAG_MUTEDET: Mute detection flag. 718 * @arg SAI_FLAG_WCKCFG: Wrong Clock Configuration flag. 719 * @arg SAI_FLAG_FREQ: FIFO request flag. 720 * @arg SAI_FLAG_CNRDY: Codec not ready flag. 721 * @arg SAI_FLAG_AFSDET: Anticipated frame synchronization detection flag. 722 * @arg SAI_FLAG_LFSDET: Late frame synchronization detection flag. 723 * @retval The new state of __FLAG__ (TRUE or FALSE). 724 */ 725 #define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) 726 727 /** @brief Clear the specified SAI pending flag. 728 * @param __HANDLE__ specifies the SAI Handle. 729 * @param __FLAG__ specifies the flag to check. 730 * This parameter can be any combination of the following values: 731 * @arg SAI_FLAG_OVRUDR: Clear Overrun underrun 732 * @arg SAI_FLAG_MUTEDET: Clear Mute detection 733 * @arg SAI_FLAG_WCKCFG: Clear Wrong Clock Configuration 734 * @arg SAI_FLAG_FREQ: Clear FIFO request 735 * @arg SAI_FLAG_CNRDY: Clear Codec not ready 736 * @arg SAI_FLAG_AFSDET: Clear Anticipated frame synchronization detection 737 * @arg SAI_FLAG_LFSDET: Clear Late frame synchronization detection 738 * 739 * @retval None 740 */ 741 #define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__)) 742 743 /** @brief Enable SAI. 744 * @param __HANDLE__ specifies the SAI Handle. 745 * @retval None 746 */ 747 #define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN) 748 749 /** @brief Disable SAI. 750 * @param __HANDLE__ specifies the SAI Handle. 751 * @retval None 752 */ 753 #define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN) 754 755 /** 756 * @} 757 */ 758 759 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) || \ 760 defined(STM32L4P5xx) || defined(STM32L4Q5xx) 761 /* Include SAI HAL Extension module */ 762 #include "stm32l4xx_hal_sai_ex.h" 763 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx || */ 764 /* STM32L4P5xx || STM32L4Q5xx */ 765 766 /* Exported functions --------------------------------------------------------*/ 767 /** @addtogroup SAI_Exported_Functions 768 * @{ 769 */ 770 771 /* Initialization/de-initialization functions ********************************/ 772 /** @addtogroup SAI_Exported_Functions_Group1 773 * @{ 774 */ 775 HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot); 776 HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai); 777 HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai); 778 void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai); 779 void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai); 780 781 #if (USE_HAL_SAI_REGISTER_CALLBACKS == 1) 782 /* SAI callbacks register/unregister functions ********************************/ 783 HAL_StatusTypeDef HAL_SAI_RegisterCallback(SAI_HandleTypeDef *hsai, 784 HAL_SAI_CallbackIDTypeDef CallbackID, 785 pSAI_CallbackTypeDef pCallback); 786 HAL_StatusTypeDef HAL_SAI_UnRegisterCallback(SAI_HandleTypeDef *hsai, 787 HAL_SAI_CallbackIDTypeDef CallbackID); 788 #endif 789 /** 790 * @} 791 */ 792 793 /* I/O operation functions ***************************************************/ 794 /** @addtogroup SAI_Exported_Functions_Group2 795 * @{ 796 */ 797 /* Blocking mode: Polling */ 798 HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout); 799 HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout); 800 801 /* Non-Blocking mode: Interrupt */ 802 HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size); 803 HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size); 804 805 /* Non-Blocking mode: DMA */ 806 HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size); 807 HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size); 808 HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai); 809 HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai); 810 HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai); 811 812 /* Abort function */ 813 HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai); 814 815 /* Mute management */ 816 HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val); 817 HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai); 818 HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter); 819 HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai); 820 821 /* SAI IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ 822 void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai); 823 void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai); 824 void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai); 825 void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai); 826 void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai); 827 void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai); 828 /** 829 * @} 830 */ 831 832 /** @addtogroup SAI_Exported_Functions_Group3 833 * @{ 834 */ 835 /* Peripheral State functions ************************************************/ 836 HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai); 837 uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai); 838 /** 839 * @} 840 */ 841 842 /** 843 * @} 844 */ 845 846 /* Private macros ------------------------------------------------------------*/ 847 /** @defgroup SAI_Private_Macros SAI Private Macros 848 * @{ 849 */ 850 #define IS_SAI_BLOCK_SYNCEXT(STATE) (((STATE) == SAI_SYNCEXT_DISABLE) ||\ 851 ((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE) ||\ 852 ((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE)) 853 854 #define IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_I2S_STANDARD) ||\ 855 ((PROTOCOL) == SAI_I2S_MSBJUSTIFIED) ||\ 856 ((PROTOCOL) == SAI_I2S_LSBJUSTIFIED) ||\ 857 ((PROTOCOL) == SAI_PCM_LONG) ||\ 858 ((PROTOCOL) == SAI_PCM_SHORT)) 859 860 #define IS_SAI_PROTOCOL_DATASIZE(DATASIZE) (((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BIT) ||\ 861 ((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) ||\ 862 ((DATASIZE) == SAI_PROTOCOL_DATASIZE_24BIT) ||\ 863 ((DATASIZE) == SAI_PROTOCOL_DATASIZE_32BIT)) 864 865 #define IS_SAI_AUDIO_FREQUENCY(AUDIO) (((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || \ 866 ((AUDIO) == SAI_AUDIO_FREQUENCY_48K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \ 867 ((AUDIO) == SAI_AUDIO_FREQUENCY_32K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \ 868 ((AUDIO) == SAI_AUDIO_FREQUENCY_16K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \ 869 ((AUDIO) == SAI_AUDIO_FREQUENCY_8K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV)) 870 871 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) || \ 872 defined(STM32L4P5xx) || defined(STM32L4Q5xx) 873 #define IS_SAI_BLOCK_MCK_OVERSAMPLING(VALUE) (((VALUE) == SAI_MCK_OVERSAMPLING_DISABLE) || \ 874 ((VALUE) == SAI_MCK_OVERSAMPLING_ENABLE)) 875 876 #define IS_SAI_PDM_MIC_PAIRS_NUMBER(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 3U)) 877 878 #define IS_SAI_PDM_CLOCK_ENABLE(CLOCK) (((CLOCK) != 0U) && \ 879 (((CLOCK) & ~(SAI_PDM_CLOCK1_ENABLE | SAI_PDM_CLOCK2_ENABLE)) == 0U)) 880 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx || */ 881 /* STM32L4P5xx || STM32L4Q5xx */ 882 883 #define IS_SAI_BLOCK_MODE(MODE) (((MODE) == SAI_MODEMASTER_TX) || \ 884 ((MODE) == SAI_MODEMASTER_RX) || \ 885 ((MODE) == SAI_MODESLAVE_TX) || \ 886 ((MODE) == SAI_MODESLAVE_RX)) 887 888 #define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_FREE_PROTOCOL) || \ 889 ((PROTOCOL) == SAI_AC97_PROTOCOL) || \ 890 ((PROTOCOL) == SAI_SPDIF_PROTOCOL)) 891 892 #define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DATASIZE_8) || \ 893 ((DATASIZE) == SAI_DATASIZE_10) || \ 894 ((DATASIZE) == SAI_DATASIZE_16) || \ 895 ((DATASIZE) == SAI_DATASIZE_20) || \ 896 ((DATASIZE) == SAI_DATASIZE_24) || \ 897 ((DATASIZE) == SAI_DATASIZE_32)) 898 899 #define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FIRSTBIT_MSB) || \ 900 ((BIT) == SAI_FIRSTBIT_LSB)) 901 902 #define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \ 903 ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE)) 904 905 #define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS) || \ 906 ((SYNCHRO) == SAI_SYNCHRONOUS) || \ 907 ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1) || \ 908 ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2)) 909 910 #define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OUTPUTDRIVE_DISABLE) || \ 911 ((DRIVE) == SAI_OUTPUTDRIVE_ENABLE)) 912 913 #define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \ 914 ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE)) 915 916 #define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63U) 917 918 #define IS_SAI_BLOCK_MUTE_VALUE(VALUE) (((VALUE) == SAI_ZERO_VALUE) || \ 919 ((VALUE) == SAI_LAST_SENT_VALUE)) 920 921 #define IS_SAI_BLOCK_COMPANDING_MODE(MODE) (((MODE) == SAI_NOCOMPANDING) || \ 922 ((MODE) == SAI_ULAW_1CPL_COMPANDING) || \ 923 ((MODE) == SAI_ALAW_1CPL_COMPANDING) || \ 924 ((MODE) == SAI_ULAW_2CPL_COMPANDING) || \ 925 ((MODE) == SAI_ALAW_2CPL_COMPANDING)) 926 927 #define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY) || \ 928 ((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF) || \ 929 ((THRESHOLD) == SAI_FIFOTHRESHOLD_HF) || \ 930 ((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF) || \ 931 ((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL)) 932 933 #define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_OUTPUT_NOTRELEASED) ||\ 934 ((STATE) == SAI_OUTPUT_RELEASED)) 935 936 #define IS_SAI_MONO_STEREO_MODE(MODE) (((MODE) == SAI_MONOMODE) ||\ 937 ((MODE) == SAI_STEREOMODE)) 938 939 #define IS_SAI_SLOT_ACTIVE(ACTIVE) ((ACTIVE) <= SAI_SLOTACTIVE_ALL) 940 941 #define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1U <= (NUMBER)) && ((NUMBER) <= 16U)) 942 943 #define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \ 944 ((SIZE) == SAI_SLOTSIZE_16B) || \ 945 ((SIZE) == SAI_SLOTSIZE_32B)) 946 947 #define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24U) 948 949 #define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \ 950 ((OFFSET) == SAI_FS_BEFOREFIRSTBIT)) 951 952 #define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ACTIVE_LOW) || \ 953 ((POLARITY) == SAI_FS_ACTIVE_HIGH)) 954 955 #define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \ 956 ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION)) 957 958 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) || \ 959 defined(STM32L4P5xx) || defined(STM32L4Q5xx) 960 #define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 63U) 961 #else 962 #define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 15U) 963 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx || */ 964 /* STM32L4P5xx || STM32L4Q5xx */ 965 966 #define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8U <= (LENGTH)) && ((LENGTH) <= 256U)) 967 968 #define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1U <= (LENGTH)) && ((LENGTH) <= 128U)) 969 970 /** 971 * @} 972 */ 973 974 /* Private functions ---------------------------------------------------------*/ 975 /** @defgroup SAI_Private_Functions SAI Private Functions 976 * @{ 977 */ 978 979 /** 980 * @} 981 */ 982 983 /** 984 * @} 985 */ 986 987 /** 988 * @} 989 */ 990 991 #endif /* !STM32L412xx && !STM32L422xx */ 992 993 #ifdef __cplusplus 994 } 995 #endif 996 997 #endif /* STM32L4xx_HAL_SAI_H */ 998 999 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 1000