1 /** 2 ****************************************************************************** 3 * @file stm32l4xx_hal_smbus.h 4 * @author MCD Application Team 5 * @brief Header file of SMBUS HAL module. 6 ****************************************************************************** 7 * @attention 8 * 9 * <h2><center>© Copyright (c) 2017 STMicroelectronics. 10 * All rights reserved.</center></h2> 11 * 12 * This software component is licensed by ST under BSD 3-Clause license, 13 * the "License"; You may not use this file except in compliance with the 14 * License. You may obtain a copy of the License at: 15 * opensource.org/licenses/BSD-3-Clause 16 * 17 ****************************************************************************** 18 */ 19 20 /* Define to prevent recursive inclusion -------------------------------------*/ 21 #ifndef STM32L4xx_HAL_SMBUS_H 22 #define STM32L4xx_HAL_SMBUS_H 23 24 #ifdef __cplusplus 25 extern "C" { 26 #endif 27 28 /* Includes ------------------------------------------------------------------*/ 29 #include "stm32l4xx_hal_def.h" 30 31 /** @addtogroup STM32L4xx_HAL_Driver 32 * @{ 33 */ 34 35 /** @addtogroup SMBUS 36 * @{ 37 */ 38 39 /* Exported types ------------------------------------------------------------*/ 40 /** @defgroup SMBUS_Exported_Types SMBUS Exported Types 41 * @{ 42 */ 43 44 /** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition 45 * @brief SMBUS Configuration Structure definition 46 * @{ 47 */ 48 typedef struct 49 { 50 uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value. 51 This parameter calculated by referring to SMBUS initialization 52 section in Reference manual */ 53 uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not. 54 This parameter can be a value of @ref SMBUS_Analog_Filter */ 55 56 uint32_t OwnAddress1; /*!< Specifies the first device own address. 57 This parameter can be a 7-bit or 10-bit address. */ 58 59 uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected. 60 This parameter can be a value of @ref SMBUS_addressing_mode */ 61 62 uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. 63 This parameter can be a value of @ref SMBUS_dual_addressing_mode */ 64 65 uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected 66 This parameter can be a 7-bit address. */ 67 68 uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected 69 This parameter can be a value of @ref SMBUS_own_address2_masks. */ 70 71 uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. 72 This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */ 73 74 uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. 75 This parameter can be a value of @ref SMBUS_nostretch_mode */ 76 77 uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected. 78 This parameter can be a value of @ref SMBUS_packet_error_check_mode */ 79 80 uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected. 81 This parameter can be a value of @ref SMBUS_peripheral_mode */ 82 83 uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value. 84 (Enable bits and different timeout values) 85 This parameter calculated by referring to SMBUS initialization 86 section in Reference manual */ 87 } SMBUS_InitTypeDef; 88 /** 89 * @} 90 */ 91 92 /** @defgroup HAL_state_definition HAL state definition 93 * @brief HAL State definition 94 * @{ 95 */ 96 #define HAL_SMBUS_STATE_RESET (0x00000000U) /*!< SMBUS not yet initialized or disabled */ 97 #define HAL_SMBUS_STATE_READY (0x00000001U) /*!< SMBUS initialized and ready for use */ 98 #define HAL_SMBUS_STATE_BUSY (0x00000002U) /*!< SMBUS internal process is ongoing */ 99 #define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */ 100 #define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */ 101 #define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ 102 #define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ 103 #define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ 104 #define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ 105 #define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ 106 /** 107 * @} 108 */ 109 110 /** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition 111 * @brief SMBUS Error Code definition 112 * @{ 113 */ 114 #define HAL_SMBUS_ERROR_NONE (0x00000000U) /*!< No error */ 115 #define HAL_SMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */ 116 #define HAL_SMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */ 117 #define HAL_SMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */ 118 #define HAL_SMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */ 119 #define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */ 120 #define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */ 121 #define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */ 122 #define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */ 123 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) 124 #define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ 125 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ 126 #define HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ 127 /** 128 * @} 129 */ 130 131 /** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition 132 * @brief SMBUS handle Structure definition 133 * @{ 134 */ 135 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) 136 typedef struct __SMBUS_HandleTypeDef 137 #else 138 typedef struct 139 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ 140 { 141 I2C_TypeDef *Instance; /*!< SMBUS registers base address */ 142 143 SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */ 144 145 uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */ 146 147 uint16_t XferSize; /*!< SMBUS transfer size */ 148 149 __IO uint16_t XferCount; /*!< SMBUS transfer counter */ 150 151 __IO uint32_t XferOptions; /*!< SMBUS transfer options */ 152 153 __IO uint32_t PreviousState; /*!< SMBUS communication Previous state */ 154 155 HAL_LockTypeDef Lock; /*!< SMBUS locking object */ 156 157 __IO uint32_t State; /*!< SMBUS communication state */ 158 159 __IO uint32_t ErrorCode; /*!< SMBUS Error code */ 160 161 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) 162 void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Tx Transfer completed callback */ 163 void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Rx Transfer completed callback */ 164 void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Slave Tx Transfer completed callback */ 165 void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Slave Rx Transfer completed callback */ 166 void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Listen Complete callback */ 167 void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Error callback */ 168 169 void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< SMBUS Slave Address Match callback */ 170 171 void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Msp Init callback */ 172 void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Msp DeInit callback */ 173 174 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ 175 } SMBUS_HandleTypeDef; 176 177 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) 178 /** 179 * @brief HAL SMBUS Callback ID enumeration definition 180 */ 181 typedef enum 182 { 183 HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< SMBUS Master Tx Transfer completed callback ID */ 184 HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< SMBUS Master Rx Transfer completed callback ID */ 185 HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< SMBUS Slave Tx Transfer completed callback ID */ 186 HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< SMBUS Slave Rx Transfer completed callback ID */ 187 HAL_SMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< SMBUS Listen Complete callback ID */ 188 HAL_SMBUS_ERROR_CB_ID = 0x05U, /*!< SMBUS Error callback ID */ 189 190 HAL_SMBUS_MSPINIT_CB_ID = 0x06U, /*!< SMBUS Msp Init callback ID */ 191 HAL_SMBUS_MSPDEINIT_CB_ID = 0x07U /*!< SMBUS Msp DeInit callback ID */ 192 193 } HAL_SMBUS_CallbackIDTypeDef; 194 195 /** 196 * @brief HAL SMBUS Callback pointer definition 197 */ 198 typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus); /*!< pointer to an SMBUS callback function */ 199 typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an SMBUS Address Match callback function */ 200 201 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ 202 /** 203 * @} 204 */ 205 206 /** 207 * @} 208 */ 209 /* Exported constants --------------------------------------------------------*/ 210 211 /** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants 212 * @{ 213 */ 214 215 /** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter 216 * @{ 217 */ 218 #define SMBUS_ANALOGFILTER_ENABLE (0x00000000U) 219 #define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF 220 /** 221 * @} 222 */ 223 224 /** @defgroup SMBUS_addressing_mode SMBUS addressing mode 225 * @{ 226 */ 227 #define SMBUS_ADDRESSINGMODE_7BIT (0x00000001U) 228 #define SMBUS_ADDRESSINGMODE_10BIT (0x00000002U) 229 /** 230 * @} 231 */ 232 233 /** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode 234 * @{ 235 */ 236 237 #define SMBUS_DUALADDRESS_DISABLE (0x00000000U) 238 #define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN 239 /** 240 * @} 241 */ 242 243 /** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks 244 * @{ 245 */ 246 247 #define SMBUS_OA2_NOMASK ((uint8_t)0x00U) 248 #define SMBUS_OA2_MASK01 ((uint8_t)0x01U) 249 #define SMBUS_OA2_MASK02 ((uint8_t)0x02U) 250 #define SMBUS_OA2_MASK03 ((uint8_t)0x03U) 251 #define SMBUS_OA2_MASK04 ((uint8_t)0x04U) 252 #define SMBUS_OA2_MASK05 ((uint8_t)0x05U) 253 #define SMBUS_OA2_MASK06 ((uint8_t)0x06U) 254 #define SMBUS_OA2_MASK07 ((uint8_t)0x07U) 255 /** 256 * @} 257 */ 258 259 260 /** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode 261 * @{ 262 */ 263 #define SMBUS_GENERALCALL_DISABLE (0x00000000U) 264 #define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN 265 /** 266 * @} 267 */ 268 269 /** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode 270 * @{ 271 */ 272 #define SMBUS_NOSTRETCH_DISABLE (0x00000000U) 273 #define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH 274 /** 275 * @} 276 */ 277 278 /** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode 279 * @{ 280 */ 281 #define SMBUS_PEC_DISABLE (0x00000000U) 282 #define SMBUS_PEC_ENABLE I2C_CR1_PECEN 283 /** 284 * @} 285 */ 286 287 /** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode 288 * @{ 289 */ 290 #define SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN 291 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U) 292 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN 293 /** 294 * @} 295 */ 296 297 /** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition 298 * @{ 299 */ 300 301 #define SMBUS_SOFTEND_MODE (0x00000000U) 302 #define SMBUS_RELOAD_MODE I2C_CR2_RELOAD 303 #define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND 304 #define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE 305 /** 306 * @} 307 */ 308 309 /** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition 310 * @{ 311 */ 312 313 #define SMBUS_NO_STARTSTOP (0x00000000U) 314 #define SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) 315 #define SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) 316 #define SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) 317 /** 318 * @} 319 */ 320 321 /** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition 322 * @{ 323 */ 324 325 /* List of XferOptions in usage of : 326 * 1- Restart condition when direction change 327 * 2- No Restart condition in other use cases 328 */ 329 #define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE 330 #define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE)) 331 #define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE 332 #define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE 333 #define SMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(SMBUS_SOFTEND_MODE | SMBUS_SENDPEC_MODE)) 334 #define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) 335 #define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) 336 337 /* List of XferOptions in usage of : 338 * 1- Restart condition in all use cases (direction change or not) 339 */ 340 #define SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU) 341 #define SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U) 342 #define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U) 343 #define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U) 344 /** 345 * @} 346 */ 347 348 /** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition 349 * @brief SMBUS Interrupt definition 350 * Elements values convention: 0xXXXXXXXX 351 * - XXXXXXXX : Interrupt control mask 352 * @{ 353 */ 354 #define SMBUS_IT_ERRI I2C_CR1_ERRIE 355 #define SMBUS_IT_TCI I2C_CR1_TCIE 356 #define SMBUS_IT_STOPI I2C_CR1_STOPIE 357 #define SMBUS_IT_NACKI I2C_CR1_NACKIE 358 #define SMBUS_IT_ADDRI I2C_CR1_ADDRIE 359 #define SMBUS_IT_RXI I2C_CR1_RXIE 360 #define SMBUS_IT_TXI I2C_CR1_TXIE 361 #define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI) 362 #define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI) 363 #define SMBUS_IT_ALERT (SMBUS_IT_ERRI) 364 #define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI) 365 /** 366 * @} 367 */ 368 369 /** @defgroup SMBUS_Flag_definition SMBUS Flag definition 370 * @brief Flag definition 371 * Elements values convention: 0xXXXXYYYY 372 * - XXXXXXXX : Flag mask 373 * @{ 374 */ 375 376 #define SMBUS_FLAG_TXE I2C_ISR_TXE 377 #define SMBUS_FLAG_TXIS I2C_ISR_TXIS 378 #define SMBUS_FLAG_RXNE I2C_ISR_RXNE 379 #define SMBUS_FLAG_ADDR I2C_ISR_ADDR 380 #define SMBUS_FLAG_AF I2C_ISR_NACKF 381 #define SMBUS_FLAG_STOPF I2C_ISR_STOPF 382 #define SMBUS_FLAG_TC I2C_ISR_TC 383 #define SMBUS_FLAG_TCR I2C_ISR_TCR 384 #define SMBUS_FLAG_BERR I2C_ISR_BERR 385 #define SMBUS_FLAG_ARLO I2C_ISR_ARLO 386 #define SMBUS_FLAG_OVR I2C_ISR_OVR 387 #define SMBUS_FLAG_PECERR I2C_ISR_PECERR 388 #define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT 389 #define SMBUS_FLAG_ALERT I2C_ISR_ALERT 390 #define SMBUS_FLAG_BUSY I2C_ISR_BUSY 391 #define SMBUS_FLAG_DIR I2C_ISR_DIR 392 /** 393 * @} 394 */ 395 396 /** 397 * @} 398 */ 399 400 /* Exported macros ------------------------------------------------------------*/ 401 /** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros 402 * @{ 403 */ 404 405 /** @brief Reset SMBUS handle state. 406 * @param __HANDLE__ specifies the SMBUS Handle. 407 * @retval None 408 */ 409 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) 410 #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \ 411 (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \ 412 (__HANDLE__)->MspInitCallback = NULL; \ 413 (__HANDLE__)->MspDeInitCallback = NULL; \ 414 } while(0) 415 #else 416 #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET) 417 #endif 418 419 /** @brief Enable the specified SMBUS interrupts. 420 * @param __HANDLE__ specifies the SMBUS Handle. 421 * @param __INTERRUPT__ specifies the interrupt source to enable. 422 * This parameter can be one of the following values: 423 * @arg @ref SMBUS_IT_ERRI Errors interrupt enable 424 * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable 425 * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable 426 * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable 427 * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable 428 * @arg @ref SMBUS_IT_RXI RX interrupt enable 429 * @arg @ref SMBUS_IT_TXI TX interrupt enable 430 * 431 * @retval None 432 */ 433 #define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) 434 435 /** @brief Disable the specified SMBUS interrupts. 436 * @param __HANDLE__ specifies the SMBUS Handle. 437 * @param __INTERRUPT__ specifies the interrupt source to disable. 438 * This parameter can be one of the following values: 439 * @arg @ref SMBUS_IT_ERRI Errors interrupt enable 440 * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable 441 * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable 442 * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable 443 * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable 444 * @arg @ref SMBUS_IT_RXI RX interrupt enable 445 * @arg @ref SMBUS_IT_TXI TX interrupt enable 446 * 447 * @retval None 448 */ 449 #define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) 450 451 /** @brief Check whether the specified SMBUS interrupt source is enabled or not. 452 * @param __HANDLE__ specifies the SMBUS Handle. 453 * @param __INTERRUPT__ specifies the SMBUS interrupt source to check. 454 * This parameter can be one of the following values: 455 * @arg @ref SMBUS_IT_ERRI Errors interrupt enable 456 * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable 457 * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable 458 * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable 459 * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable 460 * @arg @ref SMBUS_IT_RXI RX interrupt enable 461 * @arg @ref SMBUS_IT_TXI TX interrupt enable 462 * 463 * @retval The new state of __IT__ (SET or RESET). 464 */ 465 #define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 466 467 /** @brief Check whether the specified SMBUS flag is set or not. 468 * @param __HANDLE__ specifies the SMBUS Handle. 469 * @param __FLAG__ specifies the flag to check. 470 * This parameter can be one of the following values: 471 * @arg @ref SMBUS_FLAG_TXE Transmit data register empty 472 * @arg @ref SMBUS_FLAG_TXIS Transmit interrupt status 473 * @arg @ref SMBUS_FLAG_RXNE Receive data register not empty 474 * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode) 475 * @arg @ref SMBUS_FLAG_AF NACK received flag 476 * @arg @ref SMBUS_FLAG_STOPF STOP detection flag 477 * @arg @ref SMBUS_FLAG_TC Transfer complete (master mode) 478 * @arg @ref SMBUS_FLAG_TCR Transfer complete reload 479 * @arg @ref SMBUS_FLAG_BERR Bus error 480 * @arg @ref SMBUS_FLAG_ARLO Arbitration lost 481 * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun 482 * @arg @ref SMBUS_FLAG_PECERR PEC error in reception 483 * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag 484 * @arg @ref SMBUS_FLAG_ALERT SMBus alert 485 * @arg @ref SMBUS_FLAG_BUSY Bus busy 486 * @arg @ref SMBUS_FLAG_DIR Transfer direction (slave mode) 487 * 488 * @retval The new state of __FLAG__ (SET or RESET). 489 */ 490 #define SMBUS_FLAG_MASK (0x0001FFFFU) 491 #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) 492 493 /** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit. 494 * @param __HANDLE__ specifies the SMBUS Handle. 495 * @param __FLAG__ specifies the flag to clear. 496 * This parameter can be any combination of the following values: 497 * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode) 498 * @arg @ref SMBUS_FLAG_AF NACK received flag 499 * @arg @ref SMBUS_FLAG_STOPF STOP detection flag 500 * @arg @ref SMBUS_FLAG_BERR Bus error 501 * @arg @ref SMBUS_FLAG_ARLO Arbitration lost 502 * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun 503 * @arg @ref SMBUS_FLAG_PECERR PEC error in reception 504 * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag 505 * @arg @ref SMBUS_FLAG_ALERT SMBus alert 506 * 507 * @retval None 508 */ 509 #define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) 510 511 /** @brief Enable the specified SMBUS peripheral. 512 * @param __HANDLE__ specifies the SMBUS Handle. 513 * @retval None 514 */ 515 #define __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) 516 517 /** @brief Disable the specified SMBUS peripheral. 518 * @param __HANDLE__ specifies the SMBUS Handle. 519 * @retval None 520 */ 521 #define __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) 522 523 /** @brief Generate a Non-Acknowledge SMBUS peripheral in Slave mode. 524 * @param __HANDLE__ specifies the SMBUS Handle. 525 * @retval None 526 */ 527 #define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) 528 529 /** 530 * @} 531 */ 532 533 534 /* Private constants ---------------------------------------------------------*/ 535 536 /* Private macros ------------------------------------------------------------*/ 537 /** @defgroup SMBUS_Private_Macro SMBUS Private Macros 538 * @{ 539 */ 540 541 #define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \ 542 ((FILTER) == SMBUS_ANALOGFILTER_DISABLE)) 543 544 #define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) 545 546 #define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \ 547 ((MODE) == SMBUS_ADDRESSINGMODE_10BIT)) 548 549 #define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \ 550 ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE)) 551 552 #define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \ 553 ((MASK) == SMBUS_OA2_MASK01) || \ 554 ((MASK) == SMBUS_OA2_MASK02) || \ 555 ((MASK) == SMBUS_OA2_MASK03) || \ 556 ((MASK) == SMBUS_OA2_MASK04) || \ 557 ((MASK) == SMBUS_OA2_MASK05) || \ 558 ((MASK) == SMBUS_OA2_MASK06) || \ 559 ((MASK) == SMBUS_OA2_MASK07)) 560 561 #define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \ 562 ((CALL) == SMBUS_GENERALCALL_ENABLE)) 563 564 #define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \ 565 ((STRETCH) == SMBUS_NOSTRETCH_ENABLE)) 566 567 #define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \ 568 ((PEC) == SMBUS_PEC_ENABLE)) 569 570 #define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \ 571 ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ 572 ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)) 573 574 #define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \ 575 ((MODE) == SMBUS_AUTOEND_MODE) || \ 576 ((MODE) == SMBUS_SOFTEND_MODE) || \ 577 ((MODE) == SMBUS_SENDPEC_MODE) || \ 578 ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \ 579 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \ 580 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \ 581 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE ))) 582 583 584 #define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \ 585 ((REQUEST) == SMBUS_GENERATE_START_READ) || \ 586 ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \ 587 ((REQUEST) == SMBUS_NO_STARTSTOP)) 588 589 590 #define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ 591 ((REQUEST) == SMBUS_FIRST_FRAME) || \ 592 ((REQUEST) == SMBUS_NEXT_FRAME) || \ 593 ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ 594 ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ 595 ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \ 596 ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ 597 ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)) 598 599 #define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \ 600 ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ 601 ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \ 602 ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)) 603 604 #define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN))) 605 #define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) 606 607 #define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ 608 (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) 609 610 #define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U) 611 #define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U) 612 #define SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) 613 #define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE) 614 #define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN) 615 616 #define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) 617 #define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) 618 619 #define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) 620 #define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) 621 622 /** 623 * @} 624 */ 625 626 /* Exported functions --------------------------------------------------------*/ 627 /** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions 628 * @{ 629 */ 630 631 /** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions 632 * @{ 633 */ 634 635 /* Initialization and de-initialization functions ****************************/ 636 HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus); 637 HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus); 638 void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus); 639 void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus); 640 HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter); 641 HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter); 642 643 /* Callbacks Register/UnRegister functions ***********************************/ 644 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) 645 HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback); 646 HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID); 647 648 HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback); 649 HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus); 650 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ 651 /** 652 * @} 653 */ 654 655 /** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions 656 * @{ 657 */ 658 659 /* IO operation functions *****************************************************/ 660 /** @addtogroup Blocking_mode_Polling Blocking mode Polling 661 * @{ 662 */ 663 /******* Blocking mode: Polling */ 664 HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); 665 /** 666 * @} 667 */ 668 669 /** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt 670 * @{ 671 */ 672 /******* Non-Blocking mode: Interrupt */ 673 HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); 674 HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); 675 HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress); 676 HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); 677 HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); 678 679 HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus); 680 HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus); 681 HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus); 682 HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus); 683 /** 684 * @} 685 */ 686 687 /** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks 688 * @{ 689 */ 690 /******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */ 691 void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus); 692 void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus); 693 void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); 694 void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); 695 void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); 696 void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); 697 void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); 698 void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus); 699 void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus); 700 701 /** 702 * @} 703 */ 704 705 /** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions 706 * @{ 707 */ 708 709 /* Peripheral State and Errors functions **************************************************/ 710 uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus); 711 uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); 712 713 /** 714 * @} 715 */ 716 717 /** 718 * @} 719 */ 720 721 /* Private Functions ---------------------------------------------------------*/ 722 /** @defgroup SMBUS_Private_Functions SMBUS Private Functions 723 * @{ 724 */ 725 /* Private functions are defined in stm32l4xx_hal_smbus.c file */ 726 /** 727 * @} 728 */ 729 730 /** 731 * @} 732 */ 733 734 /** 735 * @} 736 */ 737 738 /** 739 * @} 740 */ 741 742 #ifdef __cplusplus 743 } 744 #endif 745 746 747 #endif /* STM32L4xx_HAL_SMBUS_H */ 748 749 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 750