1 /**
2 ******************************************************************************
3 * @file stm32l4xx_ll_pwr.h
4 * @author MCD Application Team
5 * @brief Header file of PWR LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32L4xx_LL_PWR_H
22 #define STM32L4xx_LL_PWR_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32l4xx.h"
30
31 /** @addtogroup STM32L4xx_LL_Driver
32 * @{
33 */
34
35 #if defined(PWR)
36
37 /** @defgroup PWR_LL PWR
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43
44 /* Private constants ---------------------------------------------------------*/
45
46 /* Private macros ------------------------------------------------------------*/
47
48 /* Exported types ------------------------------------------------------------*/
49 /* Exported constants --------------------------------------------------------*/
50 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
51 * @{
52 */
53
54 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
55 * @brief Flags defines which can be used with LL_PWR_WriteReg function
56 * @{
57 */
58 #define LL_PWR_SCR_CSBF PWR_SCR_CSBF
59 #define LL_PWR_SCR_CWUF PWR_SCR_CWUF
60 #define LL_PWR_SCR_CWUF5 PWR_SCR_CWUF5
61 #define LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4
62 #define LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3
63 #define LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2
64 #define LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1
65 /**
66 * @}
67 */
68
69 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
70 * @brief Flags defines which can be used with LL_PWR_ReadReg function
71 * @{
72 */
73 #define LL_PWR_SR1_WUFI PWR_SR1_WUFI
74 #if defined(PWR_SR1_EXT_SMPS_RDY)
75 #define LL_PWR_SR1_EXT_SMPS_RDY PWR_SR1_EXT_SMPS_RDY
76 #endif /* PWR_SR1_EXT_SMPS_RDY */
77 #define LL_PWR_SR1_SBF PWR_SR1_SBF
78 #define LL_PWR_SR1_WUF5 PWR_SR1_WUF5
79 #define LL_PWR_SR1_WUF4 PWR_SR1_WUF4
80 #define LL_PWR_SR1_WUF3 PWR_SR1_WUF3
81 #define LL_PWR_SR1_WUF2 PWR_SR1_WUF2
82 #define LL_PWR_SR1_WUF1 PWR_SR1_WUF1
83 #if defined(PWR_SR2_PVMO4)
84 #define LL_PWR_SR2_PVMO4 PWR_SR2_PVMO4
85 #endif /* PWR_SR2_PVMO4 */
86 #if defined(PWR_SR2_PVMO3)
87 #define LL_PWR_SR2_PVMO3 PWR_SR2_PVMO3
88 #endif /* PWR_SR2_PVMO3 */
89 #if defined(PWR_SR2_PVMO2)
90 #define LL_PWR_SR2_PVMO2 PWR_SR2_PVMO2
91 #endif /* PWR_SR2_PVMO2 */
92 #if defined(PWR_SR2_PVMO1)
93 #define LL_PWR_SR2_PVMO1 PWR_SR2_PVMO1
94 #endif /* PWR_SR2_PVMO1 */
95 #define LL_PWR_SR2_PVDO PWR_SR2_PVDO
96 #define LL_PWR_SR2_VOSF PWR_SR2_VOSF
97 #define LL_PWR_SR2_REGLPF PWR_SR2_REGLPF
98 #define LL_PWR_SR2_REGLPS PWR_SR2_REGLPS
99 /**
100 * @}
101 */
102
103 /** @defgroup PWR_LL_EC_REGU_VOLTAGE REGU VOLTAGE
104 * @{
105 */
106 #define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR1_VOS_0)
107 #define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR1_VOS_1)
108 /**
109 * @}
110 */
111
112 /** @defgroup PWR_LL_EC_MODE_PWR MODE PWR
113 * @{
114 */
115 #define LL_PWR_MODE_STOP0 (PWR_CR1_LPMS_STOP0)
116 #define LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_STOP1)
117 #define LL_PWR_MODE_STOP2 (PWR_CR1_LPMS_STOP2)
118 #define LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_STANDBY)
119 #define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_SHUTDOWN)
120 /**
121 * @}
122 */
123
124 /** @defgroup PWR_LL_EC_PVM_VDDUSB_1 Peripheral voltage monitoring
125 * @{
126 */
127 #if defined(PWR_CR2_PVME1)
128 #define LL_PWR_PVM_VDDUSB_1_2V (PWR_CR2_PVME1) /* Monitoring VDDUSB vs. 1.2V */
129 #endif
130 #if defined(PWR_CR2_PVME2)
131 #define LL_PWR_PVM_VDDIO2_0_9V (PWR_CR2_PVME2) /* Monitoring VDDIO2 vs. 0.9V */
132 #endif
133 #if defined(PWR_CR2_PVME3)
134 #define LL_PWR_PVM_VDDA_1_62V (PWR_CR2_PVME3) /* Monitoring VDDA vs. 1.62V */
135 #endif
136 #if defined(PWR_CR2_PVME4)
137 #define LL_PWR_PVM_VDDA_2_2V (PWR_CR2_PVME4) /* Monitoring VDDA vs. 2.2V */
138 #endif
139 /**
140 * @}
141 */
142
143 /** @defgroup PWR_LL_EC_PVDLEVEL PVDLEVEL
144 * @{
145 */
146 #define LL_PWR_PVDLEVEL_0 (PWR_CR2_PLS_LEV0) /* VPVD0 around 2.0 V */
147 #define LL_PWR_PVDLEVEL_1 (PWR_CR2_PLS_LEV1) /* VPVD1 around 2.2 V */
148 #define LL_PWR_PVDLEVEL_2 (PWR_CR2_PLS_LEV2) /* VPVD2 around 2.4 V */
149 #define LL_PWR_PVDLEVEL_3 (PWR_CR2_PLS_LEV3) /* VPVD3 around 2.5 V */
150 #define LL_PWR_PVDLEVEL_4 (PWR_CR2_PLS_LEV4) /* VPVD4 around 2.6 V */
151 #define LL_PWR_PVDLEVEL_5 (PWR_CR2_PLS_LEV5) /* VPVD5 around 2.8 V */
152 #define LL_PWR_PVDLEVEL_6 (PWR_CR2_PLS_LEV6) /* VPVD6 around 2.9 V */
153 #define LL_PWR_PVDLEVEL_7 (PWR_CR2_PLS_LEV7) /* External input analog voltage (Compare internally to VREFINT) */
154 /**
155 * @}
156 */
157
158 /** @defgroup PWR_LL_EC_WAKEUP WAKEUP
159 * @{
160 */
161 #define LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1)
162 #define LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2)
163 #define LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3)
164 #define LL_PWR_WAKEUP_PIN4 (PWR_CR3_EWUP4)
165 #define LL_PWR_WAKEUP_PIN5 (PWR_CR3_EWUP5)
166 /**
167 * @}
168 */
169
170 /** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR BATT CHARG RESISTOR
171 * @{
172 */
173 #define LL_PWR_BATT_CHARG_RESISTOR_5K (0x00000000U)
174 #define LL_PWR_BATT_CHARGRESISTOR_1_5K (PWR_CR4_VBRS)
175 /**
176 * @}
177 */
178
179 /** @defgroup PWR_LL_EC_SRAM2_CONTENT_RETENTION SRAM2 CONTENT RETENTION
180 * @{
181 */
182 #define LL_PWR_NO_SRAM2_RETENTION (0x00000000U)
183 #if defined(PWR_CR3_RRS_1)
184 #define LL_PWR_FULL_SRAM2_RETENTION PWR_CR3_RRS_0
185 #define LL_PWR_4KBYTES_SRAM2_RETENTION PWR_CR3_RRS_1
186 #else
187 #define LL_PWR_FULL_SRAM2_RETENTION PWR_CR3_RRS
188 #endif /* PWR_CR3_RRS_1 */
189 /**
190 * @}
191 */
192
193 /** @defgroup PWR_LL_EC_GPIO GPIO
194 * @{
195 */
196 #define LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA)))
197 #define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB)))
198 #define LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC)))
199 #define LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD)))
200 #define LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE)))
201 #if defined(GPIOF)
202 #define LL_PWR_GPIO_F ((uint32_t)(&(PWR->PUCRF)))
203 #endif
204 #if defined(GPIOG)
205 #define LL_PWR_GPIO_G ((uint32_t)(&(PWR->PUCRG)))
206 #endif
207 #if defined(GPIOH)
208 #define LL_PWR_GPIO_H ((uint32_t)(&(PWR->PUCRH)))
209 #endif
210 #if defined(GPIOI)
211 #define LL_PWR_GPIO_I ((uint32_t)(&(PWR->PUCRI)))
212 #endif
213 /**
214 * @}
215 */
216
217 /** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT
218 * @{
219 */
220 #define LL_PWR_GPIO_BIT_0 (0x00000001U)
221 #define LL_PWR_GPIO_BIT_1 (0x00000002U)
222 #define LL_PWR_GPIO_BIT_2 (0x00000004U)
223 #define LL_PWR_GPIO_BIT_3 (0x00000008U)
224 #define LL_PWR_GPIO_BIT_4 (0x00000010U)
225 #define LL_PWR_GPIO_BIT_5 (0x00000020U)
226 #define LL_PWR_GPIO_BIT_6 (0x00000040U)
227 #define LL_PWR_GPIO_BIT_7 (0x00000080U)
228 #define LL_PWR_GPIO_BIT_8 (0x00000100U)
229 #define LL_PWR_GPIO_BIT_9 (0x00000200U)
230 #define LL_PWR_GPIO_BIT_10 (0x00000400U)
231 #define LL_PWR_GPIO_BIT_11 (0x00000800U)
232 #define LL_PWR_GPIO_BIT_12 (0x00001000U)
233 #define LL_PWR_GPIO_BIT_13 (0x00002000U)
234 #define LL_PWR_GPIO_BIT_14 (0x00004000U)
235 #define LL_PWR_GPIO_BIT_15 (0x00008000U)
236 /**
237 * @}
238 */
239
240 /**
241 * @}
242 */
243
244 /* Exported macro ------------------------------------------------------------*/
245 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
246 * @{
247 */
248
249 /** @defgroup PWR_LL_EM_WRITE_READ Common Write and read registers Macros
250 * @{
251 */
252
253 /**
254 * @brief Write a value in PWR register
255 * @param __REG__ Register to be written
256 * @param __VALUE__ Value to be written in the register
257 * @retval None
258 */
259 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
260
261 /**
262 * @brief Read a value in PWR register
263 * @param __REG__ Register to be read
264 * @retval Register value
265 */
266 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
267 /**
268 * @}
269 */
270
271 /**
272 * @}
273 */
274
275
276 /* Exported functions --------------------------------------------------------*/
277 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
278 * @{
279 */
280
281 /** @defgroup PWR_LL_EF_Configuration Configuration
282 * @{
283 */
284
285 /**
286 * @brief Switch the regulator from main mode to low-power mode
287 * @rmtoll CR1 LPR LL_PWR_EnableLowPowerRunMode
288 * @retval None
289 */
LL_PWR_EnableLowPowerRunMode(void)290 __STATIC_INLINE void LL_PWR_EnableLowPowerRunMode(void)
291 {
292 SET_BIT(PWR->CR1, PWR_CR1_LPR);
293 }
294
295 /**
296 * @brief Switch the regulator from low-power mode to main mode
297 * @rmtoll CR1 LPR LL_PWR_DisableLowPowerRunMode
298 * @retval None
299 */
LL_PWR_DisableLowPowerRunMode(void)300 __STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void)
301 {
302 CLEAR_BIT(PWR->CR1, PWR_CR1_LPR);
303 }
304
305 /**
306 * @brief Switch from run main mode to run low-power mode.
307 * @rmtoll CR1 LPR LL_PWR_EnterLowPowerRunMode
308 * @retval None
309 */
LL_PWR_EnterLowPowerRunMode(void)310 __STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void)
311 {
312 LL_PWR_EnableLowPowerRunMode();
313 }
314
315 /**
316 * @brief Switch from run main mode to low-power mode.
317 * @rmtoll CR1 LPR LL_PWR_ExitLowPowerRunMode
318 * @retval None
319 */
LL_PWR_ExitLowPowerRunMode(void)320 __STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void)
321 {
322 LL_PWR_DisableLowPowerRunMode();
323 }
324
325 /**
326 * @brief Check if the regulator is in low-power mode
327 * @rmtoll CR1 LPR LL_PWR_IsEnabledLowPowerRunMode
328 * @retval State of bit (1 or 0).
329 */
LL_PWR_IsEnabledLowPowerRunMode(void)330 __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void)
331 {
332 return ((READ_BIT(PWR->CR1, PWR_CR1_LPR) == (PWR_CR1_LPR)) ? 1UL : 0UL);
333 }
334
335 /**
336 * @brief Set the main internal regulator output voltage
337 * @note This configuration may be completed with LL_PWR_EnableRange1BoostMode() on STM32L4Rx/STM32L4Sx devices.
338 * @rmtoll CR1 VOS LL_PWR_SetRegulVoltageScaling
339 * @param VoltageScaling This parameter can be one of the following values:
340 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
341 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
342 * @retval None
343 */
LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)344 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
345 {
346 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);
347 }
348
349 /**
350 * @brief Get the main internal regulator output voltage
351 * @rmtoll CR1 VOS LL_PWR_GetRegulVoltageScaling
352 * @retval Returned value can be one of the following values:
353 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
354 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
355 */
LL_PWR_GetRegulVoltageScaling(void)356 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
357 {
358 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS));
359 }
360
361 #if defined(PWR_CR5_R1MODE)
362 /**
363 * @brief Enable main regulator voltage range 1 boost mode
364 * @rmtoll CR5 R1MODE LL_PWR_EnableRange1BoostMode
365 * @retval None
366 */
LL_PWR_EnableRange1BoostMode(void)367 __STATIC_INLINE void LL_PWR_EnableRange1BoostMode(void)
368 {
369 CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
370 }
371
372 /**
373 * @brief Disable main regulator voltage range 1 boost mode
374 * @rmtoll CR5 R1MODE LL_PWR_DisableRange1BoostMode
375 * @retval None
376 */
LL_PWR_DisableRange1BoostMode(void)377 __STATIC_INLINE void LL_PWR_DisableRange1BoostMode(void)
378 {
379 SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
380 }
381
382 /**
383 * @brief Check if the main regulator voltage range 1 boost mode is enabled
384 * @rmtoll CR5 R1MODE LL_PWR_IsEnabledRange1BoostMode
385 * @retval Inverted state of bit (0 or 1).
386 */
LL_PWR_IsEnabledRange1BoostMode(void)387 __STATIC_INLINE uint32_t LL_PWR_IsEnabledRange1BoostMode(void)
388 {
389 return ((READ_BIT(PWR->CR5, PWR_CR5_R1MODE) == 0x0U) ? 1UL : 0UL);
390 }
391 #endif /* PWR_CR5_R1MODE */
392
393 /**
394 * @brief Enable access to the backup domain
395 * @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess
396 * @retval None
397 */
LL_PWR_EnableBkUpAccess(void)398 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
399 {
400 SET_BIT(PWR->CR1, PWR_CR1_DBP);
401 }
402
403 /**
404 * @brief Disable access to the backup domain
405 * @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess
406 * @retval None
407 */
LL_PWR_DisableBkUpAccess(void)408 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
409 {
410 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
411 }
412
413 /**
414 * @brief Check if the backup domain is enabled
415 * @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess
416 * @retval State of bit (1 or 0).
417 */
LL_PWR_IsEnabledBkUpAccess(void)418 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
419 {
420 return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL);
421 }
422
423 /**
424 * @brief Set Low-Power mode
425 * @rmtoll CR1 LPMS LL_PWR_SetPowerMode
426 * @param LowPowerMode This parameter can be one of the following values:
427 * @arg @ref LL_PWR_MODE_STOP0
428 * @arg @ref LL_PWR_MODE_STOP1
429 * @arg @ref LL_PWR_MODE_STOP2
430 * @arg @ref LL_PWR_MODE_STANDBY
431 * @arg @ref LL_PWR_MODE_SHUTDOWN
432 * @retval None
433 */
LL_PWR_SetPowerMode(uint32_t LowPowerMode)434 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode)
435 {
436 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode);
437 }
438
439 /**
440 * @brief Get Low-Power mode
441 * @rmtoll CR1 LPMS LL_PWR_GetPowerMode
442 * @retval Returned value can be one of the following values:
443 * @arg @ref LL_PWR_MODE_STOP0
444 * @arg @ref LL_PWR_MODE_STOP1
445 * @arg @ref LL_PWR_MODE_STOP2
446 * @arg @ref LL_PWR_MODE_STANDBY
447 * @arg @ref LL_PWR_MODE_SHUTDOWN
448 */
LL_PWR_GetPowerMode(void)449 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
450 {
451 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS));
452 }
453
454 #if defined(PWR_CR1_RRSTP)
455 /**
456 * @brief Enable SRAM3 content retention in Stop mode
457 * @rmtoll CR1 RRSTP LL_PWR_EnableSRAM3Retention
458 * @retval None
459 */
LL_PWR_EnableSRAM3Retention(void)460 __STATIC_INLINE void LL_PWR_EnableSRAM3Retention(void)
461 {
462 SET_BIT(PWR->CR1, PWR_CR1_RRSTP);
463 }
464
465 /**
466 * @brief Disable SRAM3 content retention in Stop mode
467 * @rmtoll CR1 RRSTP LL_PWR_DisableSRAM3Retention
468 * @retval None
469 */
LL_PWR_DisableSRAM3Retention(void)470 __STATIC_INLINE void LL_PWR_DisableSRAM3Retention(void)
471 {
472 CLEAR_BIT(PWR->CR1, PWR_CR1_RRSTP);
473 }
474
475 /**
476 * @brief Check if SRAM3 content retention in Stop mode is enabled
477 * @rmtoll CR1 RRSTP LL_PWR_IsEnabledSRAM3Retention
478 * @retval State of bit (1 or 0).
479 */
LL_PWR_IsEnabledSRAM3Retention(void)480 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM3Retention(void)
481 {
482 return ((READ_BIT(PWR->CR1, PWR_CR1_RRSTP) == (PWR_CR1_RRSTP)) ? 1UL : 0UL);
483 }
484 #endif /* PWR_CR1_RRSTP */
485
486 #if defined(PWR_CR3_DSIPDEN)
487 /**
488 * @brief Enable pull-down activation on DSI pins
489 * @rmtoll CR3 DSIPDEN LL_PWR_EnableDSIPinsPDActivation
490 * @retval None
491 */
LL_PWR_EnableDSIPinsPDActivation(void)492 __STATIC_INLINE void LL_PWR_EnableDSIPinsPDActivation(void)
493 {
494 SET_BIT(PWR->CR3, PWR_CR3_DSIPDEN);
495 }
496
497 /**
498 * @brief Disable pull-down activation on DSI pins
499 * @rmtoll CR3 DSIPDEN LL_PWR_DisableDSIPinsPDActivation
500 * @retval None
501 */
LL_PWR_DisableDSIPinsPDActivation(void)502 __STATIC_INLINE void LL_PWR_DisableDSIPinsPDActivation(void)
503 {
504 CLEAR_BIT(PWR->CR3, PWR_CR3_DSIPDEN);
505 }
506
507 /**
508 * @brief Check if pull-down activation on DSI pins is enabled
509 * @rmtoll CR3 DSIPDEN LL_PWR_IsEnabledDSIPinsPDActivation
510 * @retval State of bit (1 or 0).
511 */
LL_PWR_IsEnabledDSIPinsPDActivation(void)512 __STATIC_INLINE uint32_t LL_PWR_IsEnabledDSIPinsPDActivation(void)
513 {
514 return ((READ_BIT(PWR->CR3, PWR_CR3_DSIPDEN) == (PWR_CR3_DSIPDEN)) ? 1UL : 0UL);
515 }
516 #endif /* PWR_CR3_DSIPDEN */
517
518 #if defined(PWR_CR2_USV)
519 /**
520 * @brief Enable VDDUSB supply
521 * @rmtoll CR2 USV LL_PWR_EnableVddUSB
522 * @retval None
523 */
LL_PWR_EnableVddUSB(void)524 __STATIC_INLINE void LL_PWR_EnableVddUSB(void)
525 {
526 SET_BIT(PWR->CR2, PWR_CR2_USV);
527 }
528
529 /**
530 * @brief Disable VDDUSB supply
531 * @rmtoll CR2 USV LL_PWR_DisableVddUSB
532 * @retval None
533 */
LL_PWR_DisableVddUSB(void)534 __STATIC_INLINE void LL_PWR_DisableVddUSB(void)
535 {
536 CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
537 }
538
539 /**
540 * @brief Check if VDDUSB supply is enabled
541 * @rmtoll CR2 USV LL_PWR_IsEnabledVddUSB
542 * @retval State of bit (1 or 0).
543 */
LL_PWR_IsEnabledVddUSB(void)544 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void)
545 {
546 return ((READ_BIT(PWR->CR2, PWR_CR2_USV) == (PWR_CR2_USV)) ? 1UL : 0UL);
547 }
548 #endif
549
550 #if defined(PWR_CR2_IOSV)
551 /**
552 * @brief Enable VDDIO2 supply
553 * @rmtoll CR2 IOSV LL_PWR_EnableVddIO2
554 * @retval None
555 */
LL_PWR_EnableVddIO2(void)556 __STATIC_INLINE void LL_PWR_EnableVddIO2(void)
557 {
558 SET_BIT(PWR->CR2, PWR_CR2_IOSV);
559 }
560
561 /**
562 * @brief Disable VDDIO2 supply
563 * @rmtoll CR2 IOSV LL_PWR_DisableVddIO2
564 * @retval None
565 */
LL_PWR_DisableVddIO2(void)566 __STATIC_INLINE void LL_PWR_DisableVddIO2(void)
567 {
568 CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV);
569 }
570
571 /**
572 * @brief Check if VDDIO2 supply is enabled
573 * @rmtoll CR2 IOSV LL_PWR_IsEnabledVddIO2
574 * @retval State of bit (1 or 0).
575 */
LL_PWR_IsEnabledVddIO2(void)576 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void)
577 {
578 return ((READ_BIT(PWR->CR2, PWR_CR2_IOSV) == (PWR_CR2_IOSV)) ? 1UL : 0UL);
579 }
580 #endif
581
582 /**
583 * @brief Enable the Power Voltage Monitoring on a peripheral
584 * @rmtoll CR2 PVME1 LL_PWR_EnablePVM\n
585 * CR2 PVME2 LL_PWR_EnablePVM\n
586 * CR2 PVME3 LL_PWR_EnablePVM\n
587 * CR2 PVME4 LL_PWR_EnablePVM
588 * @param PeriphVoltage This parameter can be one of the following values:
589 * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*)
590 * @arg @ref LL_PWR_PVM_VDDIO2_0_9V (*)
591 * @arg @ref LL_PWR_PVM_VDDA_1_62V
592 * @arg @ref LL_PWR_PVM_VDDA_2_2V
593 *
594 * (*) value not defined in all devices
595 * @retval None
596 */
LL_PWR_EnablePVM(uint32_t PeriphVoltage)597 __STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage)
598 {
599 SET_BIT(PWR->CR2, PeriphVoltage);
600 }
601
602 /**
603 * @brief Disable the Power Voltage Monitoring on a peripheral
604 * @rmtoll CR2 PVME1 LL_PWR_DisablePVM\n
605 * CR2 PVME2 LL_PWR_DisablePVM\n
606 * CR2 PVME3 LL_PWR_DisablePVM\n
607 * CR2 PVME4 LL_PWR_DisablePVM
608 * @param PeriphVoltage This parameter can be one of the following values:
609 * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*)
610 * @arg @ref LL_PWR_PVM_VDDIO2_0_9V (*)
611 * @arg @ref LL_PWR_PVM_VDDA_1_62V
612 * @arg @ref LL_PWR_PVM_VDDA_2_2V
613 *
614 * (*) value not defined in all devices
615 * @retval None
616 */
LL_PWR_DisablePVM(uint32_t PeriphVoltage)617 __STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage)
618 {
619 CLEAR_BIT(PWR->CR2, PeriphVoltage);
620 }
621
622 /**
623 * @brief Check if Power Voltage Monitoring is enabled on a peripheral
624 * @rmtoll CR2 PVME1 LL_PWR_IsEnabledPVM\n
625 * CR2 PVME2 LL_PWR_IsEnabledPVM\n
626 * CR2 PVME3 LL_PWR_IsEnabledPVM\n
627 * CR2 PVME4 LL_PWR_IsEnabledPVM
628 * @param PeriphVoltage This parameter can be one of the following values:
629 * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*)
630 * @arg @ref LL_PWR_PVM_VDDIO2_0_9V (*)
631 * @arg @ref LL_PWR_PVM_VDDA_1_62V
632 * @arg @ref LL_PWR_PVM_VDDA_2_2V
633 *
634 * (*) value not defined in all devices
635 * @retval State of bit (1 or 0).
636 */
LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage)637 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage)
638 {
639 return ((READ_BIT(PWR->CR2, PeriphVoltage) == (PeriphVoltage)) ? 1UL : 0UL);
640 }
641
642 /**
643 * @brief Configure the voltage threshold detected by the Power Voltage Detector
644 * @rmtoll CR2 PLS LL_PWR_SetPVDLevel
645 * @param PVDLevel This parameter can be one of the following values:
646 * @arg @ref LL_PWR_PVDLEVEL_0
647 * @arg @ref LL_PWR_PVDLEVEL_1
648 * @arg @ref LL_PWR_PVDLEVEL_2
649 * @arg @ref LL_PWR_PVDLEVEL_3
650 * @arg @ref LL_PWR_PVDLEVEL_4
651 * @arg @ref LL_PWR_PVDLEVEL_5
652 * @arg @ref LL_PWR_PVDLEVEL_6
653 * @arg @ref LL_PWR_PVDLEVEL_7
654 * @retval None
655 */
LL_PWR_SetPVDLevel(uint32_t PVDLevel)656 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
657 {
658 MODIFY_REG(PWR->CR2, PWR_CR2_PLS, PVDLevel);
659 }
660
661 /**
662 * @brief Get the voltage threshold detection
663 * @rmtoll CR2 PLS LL_PWR_GetPVDLevel
664 * @retval Returned value can be one of the following values:
665 * @arg @ref LL_PWR_PVDLEVEL_0
666 * @arg @ref LL_PWR_PVDLEVEL_1
667 * @arg @ref LL_PWR_PVDLEVEL_2
668 * @arg @ref LL_PWR_PVDLEVEL_3
669 * @arg @ref LL_PWR_PVDLEVEL_4
670 * @arg @ref LL_PWR_PVDLEVEL_5
671 * @arg @ref LL_PWR_PVDLEVEL_6
672 * @arg @ref LL_PWR_PVDLEVEL_7
673 */
LL_PWR_GetPVDLevel(void)674 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
675 {
676 return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PLS));
677 }
678
679 /**
680 * @brief Enable Power Voltage Detector
681 * @rmtoll CR2 PVDE LL_PWR_EnablePVD
682 * @retval None
683 */
LL_PWR_EnablePVD(void)684 __STATIC_INLINE void LL_PWR_EnablePVD(void)
685 {
686 SET_BIT(PWR->CR2, PWR_CR2_PVDE);
687 }
688
689 /**
690 * @brief Disable Power Voltage Detector
691 * @rmtoll CR2 PVDE LL_PWR_DisablePVD
692 * @retval None
693 */
LL_PWR_DisablePVD(void)694 __STATIC_INLINE void LL_PWR_DisablePVD(void)
695 {
696 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE);
697 }
698
699 /**
700 * @brief Check if Power Voltage Detector is enabled
701 * @rmtoll CR2 PVDE LL_PWR_IsEnabledPVD
702 * @retval State of bit (1 or 0).
703 */
LL_PWR_IsEnabledPVD(void)704 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
705 {
706 return ((READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE)) ? 1UL : 0UL);
707 }
708
709 /**
710 * @brief Enable Internal Wake-up line
711 * @rmtoll CR3 EIWF LL_PWR_EnableInternWU
712 * @retval None
713 */
LL_PWR_EnableInternWU(void)714 __STATIC_INLINE void LL_PWR_EnableInternWU(void)
715 {
716 SET_BIT(PWR->CR3, PWR_CR3_EIWF);
717 }
718
719 /**
720 * @brief Disable Internal Wake-up line
721 * @rmtoll CR3 EIWF LL_PWR_DisableInternWU
722 * @retval None
723 */
LL_PWR_DisableInternWU(void)724 __STATIC_INLINE void LL_PWR_DisableInternWU(void)
725 {
726 CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF);
727 }
728
729 /**
730 * @brief Check if Internal Wake-up line is enabled
731 * @rmtoll CR3 EIWF LL_PWR_IsEnabledInternWU
732 * @retval State of bit (1 or 0).
733 */
LL_PWR_IsEnabledInternWU(void)734 __STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void)
735 {
736 return ((READ_BIT(PWR->CR3, PWR_CR3_EIWF) == (PWR_CR3_EIWF)) ? 1UL : 0UL);
737 }
738
739 /**
740 * @brief Enable pull-up and pull-down configuration
741 * @rmtoll CR3 APC LL_PWR_EnablePUPDCfg
742 * @retval None
743 */
LL_PWR_EnablePUPDCfg(void)744 __STATIC_INLINE void LL_PWR_EnablePUPDCfg(void)
745 {
746 SET_BIT(PWR->CR3, PWR_CR3_APC);
747 }
748
749 /**
750 * @brief Disable pull-up and pull-down configuration
751 * @rmtoll CR3 APC LL_PWR_DisablePUPDCfg
752 * @retval None
753 */
LL_PWR_DisablePUPDCfg(void)754 __STATIC_INLINE void LL_PWR_DisablePUPDCfg(void)
755 {
756 CLEAR_BIT(PWR->CR3, PWR_CR3_APC);
757 }
758
759 /**
760 * @brief Check if pull-up and pull-down configuration is enabled
761 * @rmtoll CR3 APC LL_PWR_IsEnabledPUPDCfg
762 * @retval State of bit (1 or 0).
763 */
LL_PWR_IsEnabledPUPDCfg(void)764 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void)
765 {
766 return ((READ_BIT(PWR->CR3, PWR_CR3_APC) == (PWR_CR3_APC)) ? 1UL : 0UL);
767 }
768
769 #if defined(PWR_CR3_DSIPDEN)
770 /**
771 * @brief Enable pull-down activation on DSI pins
772 * @rmtoll CR3 DSIPDEN LL_PWR_EnableDSIPullDown
773 * @retval None
774 */
LL_PWR_EnableDSIPullDown(void)775 __STATIC_INLINE void LL_PWR_EnableDSIPullDown(void)
776 {
777 SET_BIT(PWR->CR3, PWR_CR3_DSIPDEN);
778 }
779
780 /**
781 * @brief Disable pull-down activation on DSI pins
782 * @rmtoll CR3 DSIPDEN LL_PWR_DisableDSIPullDown
783 * @retval None
784 */
LL_PWR_DisableDSIPullDown(void)785 __STATIC_INLINE void LL_PWR_DisableDSIPullDown(void)
786 {
787 CLEAR_BIT(PWR->CR3, PWR_CR3_DSIPDEN);
788 }
789
790 /**
791 * @brief Check if pull-down activation on DSI pins is enabled
792 * @rmtoll CR3 DSIPDEN LL_PWR_IsEnabledDSIPullDown
793 * @retval State of bit (1 or 0).
794 */
LL_PWR_IsEnabledDSIPullDown(void)795 __STATIC_INLINE uint32_t LL_PWR_IsEnabledDSIPullDown(void)
796 {
797 return ((READ_BIT(PWR->CR3, PWR_CR3_DSIPDEN) == (PWR_CR3_DSIPDEN)) ? 1UL : 0UL);
798 }
799 #endif /* PWR_CR3_DSIPDEN */
800
801 #if defined(PWR_CR3_ENULP)
802 /**
803 * @brief Enable Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes
804 * @rmtoll CR3 ENULP LL_PWR_EnableBORPVD_ULP
805 * @retval None
806 */
LL_PWR_EnableBORPVD_ULP(void)807 __STATIC_INLINE void LL_PWR_EnableBORPVD_ULP(void)
808 {
809 SET_BIT(PWR->CR3, PWR_CR3_ENULP);
810 }
811
812 /**
813 * @brief Disable Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes
814 * @rmtoll CR3 ENULP LL_PWR_DisableBORPVD_ULP
815 * @retval None
816 */
LL_PWR_DisableBORPVD_ULP(void)817 __STATIC_INLINE void LL_PWR_DisableBORPVD_ULP(void)
818 {
819 CLEAR_BIT(PWR->CR3, PWR_CR3_ENULP);
820 }
821
822 /**
823 * @brief Check if Ultra Low Power BORL, BORH and PVD for STOP2 and Standby modes is enabled
824 * @rmtoll CR3 ENULP LL_PWR_IsEnabledBORPVD_ULP
825 * @retval State of bit (1 or 0).
826 */
LL_PWR_IsEnabledBORPVD_ULP(void)827 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBORPVD_ULP(void)
828 {
829 return ((READ_BIT(PWR->CR3, PWR_CR3_ENULP) == (PWR_CR3_ENULP)) ? 1UL : 0UL);
830 }
831 #endif /* PWR_CR3_ENULP */
832
833 /**
834 * @brief Enable SRAM2 full content retention in Standby mode
835 * @rmtoll CR3 RRS LL_PWR_EnableSRAM2Retention
836 * @retval None
837 */
LL_PWR_EnableSRAM2Retention(void)838 __STATIC_INLINE void LL_PWR_EnableSRAM2Retention(void)
839 {
840 MODIFY_REG(PWR->CR3, PWR_CR3_RRS, LL_PWR_FULL_SRAM2_RETENTION);
841 }
842
843 /**
844 * @brief Disable SRAM2 content retention in Standby mode
845 * @rmtoll CR3 RRS LL_PWR_DisableSRAM2Retention
846 * @retval None
847 */
LL_PWR_DisableSRAM2Retention(void)848 __STATIC_INLINE void LL_PWR_DisableSRAM2Retention(void)
849 {
850 CLEAR_BIT(PWR->CR3, PWR_CR3_RRS);
851 }
852
853 /**
854 * @brief Check if SRAM2 full content retention in Standby mode is enabled
855 * @rmtoll CR3 RRS LL_PWR_IsEnabledSRAM2Retention
856 * @retval State of bit (1 or 0).
857 */
LL_PWR_IsEnabledSRAM2Retention(void)858 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM2Retention(void)
859 {
860 return ((READ_BIT(PWR->CR3, PWR_CR3_RRS) == (LL_PWR_FULL_SRAM2_RETENTION)) ? 1UL : 0UL);
861 }
862
863 /**
864 * @brief Set SRAM2 content retention in Standby mode
865 * @rmtoll CR3 RRS LL_PWR_SetSRAM2ContentRetention
866 * @param SRAM2Size This parameter can be one of the following values:
867 * @arg @ref LL_PWR_NO_SRAM2_RETENTION
868 * @arg @ref LL_PWR_FULL_SRAM2_RETENTION
869 * @arg @ref LL_PWR_4KBYTES_SRAM2_RETENTION
870 * @note LL_PWR_4KBYTES_SRAM2_RETENTION parameter is not available on all devices
871 * @note Setting LL_PWR_NO_SRAM2_RETENTION is same as calling LL_PWR_DisableSRAM2Retention()
872 * @note Setting LL_PWR_FULL_SRAM2_RETENTION is same as calling LL_PWR_EnableSRAM2Retention()
873 * @retval None
874 */
LL_PWR_SetSRAM2ContentRetention(uint32_t SRAM2Size)875 __STATIC_INLINE void LL_PWR_SetSRAM2ContentRetention(uint32_t SRAM2Size)
876 {
877 MODIFY_REG(PWR->CR3, PWR_CR3_RRS, SRAM2Size);
878 }
879
880 /**
881 * @brief Get SRAM2 content retention in Standby mode
882 * @rmtoll CR3 RRS LL_PWR_GetSRAM2ContentRetention
883 * @retval Returned value can be one of the following values:
884 * @arg @ref LL_PWR_NO_SRAM2_RETENTION
885 * @arg @ref LL_PWR_FULL_SRAM2_RETENTION
886 * @arg @ref LL_PWR_4KBYTES_SRAM2_RETENTION
887 * @note LL_PWR_4KBYTES_SRAM2_RETENTION parameter is not available on all devices
888 */
LL_PWR_GetSRAM2ContentRetention(void)889 __STATIC_INLINE uint32_t LL_PWR_GetSRAM2ContentRetention(void)
890 {
891 return (uint32_t)(READ_BIT(PWR->CR3, PWR_CR3_RRS));
892 }
893
894 /**
895 * @brief Enable the WakeUp PINx functionality
896 * @rmtoll CR3 EWUP1 LL_PWR_EnableWakeUpPin\n
897 * CR3 EWUP2 LL_PWR_EnableWakeUpPin\n
898 * CR3 EWUP3 LL_PWR_EnableWakeUpPin\n
899 * CR3 EWUP4 LL_PWR_EnableWakeUpPin\n
900 * CR3 EWUP5 LL_PWR_EnableWakeUpPin\n
901 * @param WakeUpPin This parameter can be one of the following values:
902 * @arg @ref LL_PWR_WAKEUP_PIN1
903 * @arg @ref LL_PWR_WAKEUP_PIN2
904 * @arg @ref LL_PWR_WAKEUP_PIN3
905 * @arg @ref LL_PWR_WAKEUP_PIN4
906 * @arg @ref LL_PWR_WAKEUP_PIN5
907 * @retval None
908 */
LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)909 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
910 {
911 SET_BIT(PWR->CR3, WakeUpPin);
912 }
913
914 /**
915 * @brief Disable the WakeUp PINx functionality
916 * @rmtoll CR3 EWUP1 LL_PWR_DisableWakeUpPin\n
917 * CR3 EWUP2 LL_PWR_DisableWakeUpPin\n
918 * CR3 EWUP3 LL_PWR_DisableWakeUpPin\n
919 * CR3 EWUP4 LL_PWR_DisableWakeUpPin\n
920 * CR3 EWUP5 LL_PWR_DisableWakeUpPin\n
921 * @param WakeUpPin This parameter can be one of the following values:
922 * @arg @ref LL_PWR_WAKEUP_PIN1
923 * @arg @ref LL_PWR_WAKEUP_PIN2
924 * @arg @ref LL_PWR_WAKEUP_PIN3
925 * @arg @ref LL_PWR_WAKEUP_PIN4
926 * @arg @ref LL_PWR_WAKEUP_PIN5
927 * @retval None
928 */
LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)929 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
930 {
931 CLEAR_BIT(PWR->CR3, WakeUpPin);
932 }
933
934 /**
935 * @brief Check if the WakeUp PINx functionality is enabled
936 * @rmtoll CR3 EWUP1 LL_PWR_IsEnabledWakeUpPin\n
937 * CR3 EWUP2 LL_PWR_IsEnabledWakeUpPin\n
938 * CR3 EWUP3 LL_PWR_IsEnabledWakeUpPin\n
939 * CR3 EWUP4 LL_PWR_IsEnabledWakeUpPin\n
940 * CR3 EWUP5 LL_PWR_IsEnabledWakeUpPin\n
941 * @param WakeUpPin This parameter can be one of the following values:
942 * @arg @ref LL_PWR_WAKEUP_PIN1
943 * @arg @ref LL_PWR_WAKEUP_PIN2
944 * @arg @ref LL_PWR_WAKEUP_PIN3
945 * @arg @ref LL_PWR_WAKEUP_PIN4
946 * @arg @ref LL_PWR_WAKEUP_PIN5
947 * @retval State of bit (1 or 0).
948 */
LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)949 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
950 {
951 return ((READ_BIT(PWR->CR3, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
952 }
953
954 #if defined(PWR_CR4_EXT_SMPS_ON)
955 /**
956 * @brief Enable the CFLDO working @ 0.95V
957 * @note When external SMPS is used & CFLDO operating in Range 2, the regulated voltage of the
958 * internal CFLDO can be reduced to 0.95V.
959 * @rmtoll CR4 EXT_SMPS_ON LL_PWR_EnableExtSMPS_0V95
960 * @retval None
961 */
LL_PWR_EnableExtSMPS_0V95(void)962 __STATIC_INLINE void LL_PWR_EnableExtSMPS_0V95(void)
963 {
964 SET_BIT(PWR->CR4, PWR_CR4_EXT_SMPS_ON);
965 }
966
967 /**
968 * @brief Disable the CFLDO working @ 0.95V
969 * @note When external SMPS is used & CFLDO operating in Range 2, the regulated voltage of the
970 * internal CFLDO can be reduced to 0.95V.
971 * @rmtoll CR4 EXT_SMPS_ON LL_PWR_DisableExtSMPS_0V95
972 * @retval None
973 */
LL_PWR_DisableExtSMPS_0V95(void)974 __STATIC_INLINE void LL_PWR_DisableExtSMPS_0V95(void)
975 {
976 CLEAR_BIT(PWR->CR4, PWR_CR4_EXT_SMPS_ON);
977 }
978
979 /**
980 * @brief Check if CFLDO is working @ 0.95V
981 * @note When external SMPS is used & CFLDO operating in Range 2, the regulated voltage of the
982 * internal CFLDO can be reduced to 0.95V.
983 * @rmtoll CR4 EXT_SMPS_ON LL_PWR_IsEnabledExtSMPS_0V95
984 * @retval State of bit (1 or 0).
985 */
LL_PWR_IsEnabledExtSMPS_0V95(void)986 __STATIC_INLINE uint32_t LL_PWR_IsEnabledExtSMPS_0V95(void)
987 {
988 return ((READ_BIT(PWR->CR4, PWR_CR4_EXT_SMPS_ON) == (PWR_CR4_EXT_SMPS_ON)) ? 1UL : 0UL);
989 }
990 #endif /* PWR_CR4_EXT_SMPS_ON */
991
992 /**
993 * @brief Set the resistor impedance
994 * @rmtoll CR4 VBRS LL_PWR_SetBattChargResistor
995 * @param Resistor This parameter can be one of the following values:
996 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
997 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
998 * @retval None
999 */
LL_PWR_SetBattChargResistor(uint32_t Resistor)1000 __STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
1001 {
1002 MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, Resistor);
1003 }
1004
1005 /**
1006 * @brief Get the resistor impedance
1007 * @rmtoll CR4 VBRS LL_PWR_GetBattChargResistor
1008 * @retval Returned value can be one of the following values:
1009 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
1010 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
1011 */
LL_PWR_GetBattChargResistor(void)1012 __STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
1013 {
1014 return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_VBRS));
1015 }
1016
1017 /**
1018 * @brief Enable battery charging
1019 * @rmtoll CR4 VBE LL_PWR_EnableBatteryCharging
1020 * @retval None
1021 */
LL_PWR_EnableBatteryCharging(void)1022 __STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
1023 {
1024 SET_BIT(PWR->CR4, PWR_CR4_VBE);
1025 }
1026
1027 /**
1028 * @brief Disable battery charging
1029 * @rmtoll CR4 VBE LL_PWR_DisableBatteryCharging
1030 * @retval None
1031 */
LL_PWR_DisableBatteryCharging(void)1032 __STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
1033 {
1034 CLEAR_BIT(PWR->CR4, PWR_CR4_VBE);
1035 }
1036
1037 /**
1038 * @brief Check if battery charging is enabled
1039 * @rmtoll CR4 VBE LL_PWR_IsEnabledBatteryCharging
1040 * @retval State of bit (1 or 0).
1041 */
LL_PWR_IsEnabledBatteryCharging(void)1042 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
1043 {
1044 return ((READ_BIT(PWR->CR4, PWR_CR4_VBE) == (PWR_CR4_VBE)) ? 1UL : 0UL);
1045 }
1046
1047 /**
1048 * @brief Set the Wake-Up pin polarity low for the event detection
1049 * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityLow\n
1050 * CR4 WP2 LL_PWR_SetWakeUpPinPolarityLow\n
1051 * CR4 WP3 LL_PWR_SetWakeUpPinPolarityLow\n
1052 * CR4 WP4 LL_PWR_SetWakeUpPinPolarityLow\n
1053 * CR4 WP5 LL_PWR_SetWakeUpPinPolarityLow
1054 * @param WakeUpPin This parameter can be one of the following values:
1055 * @arg @ref LL_PWR_WAKEUP_PIN1
1056 * @arg @ref LL_PWR_WAKEUP_PIN2
1057 * @arg @ref LL_PWR_WAKEUP_PIN3
1058 * @arg @ref LL_PWR_WAKEUP_PIN4
1059 * @arg @ref LL_PWR_WAKEUP_PIN5
1060 * @retval None
1061 */
LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)1062 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
1063 {
1064 SET_BIT(PWR->CR4, WakeUpPin);
1065 }
1066
1067 /**
1068 * @brief Set the Wake-Up pin polarity high for the event detection
1069 * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityHigh\n
1070 * CR4 WP2 LL_PWR_SetWakeUpPinPolarityHigh\n
1071 * CR4 WP3 LL_PWR_SetWakeUpPinPolarityHigh\n
1072 * CR4 WP4 LL_PWR_SetWakeUpPinPolarityHigh\n
1073 * CR4 WP5 LL_PWR_SetWakeUpPinPolarityHigh
1074 * @param WakeUpPin This parameter can be one of the following values:
1075 * @arg @ref LL_PWR_WAKEUP_PIN1
1076 * @arg @ref LL_PWR_WAKEUP_PIN2
1077 * @arg @ref LL_PWR_WAKEUP_PIN3
1078 * @arg @ref LL_PWR_WAKEUP_PIN4
1079 * @arg @ref LL_PWR_WAKEUP_PIN5
1080 * @retval None
1081 */
LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)1082 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
1083 {
1084 CLEAR_BIT(PWR->CR4, WakeUpPin);
1085 }
1086
1087 /**
1088 * @brief Get the Wake-Up pin polarity for the event detection
1089 * @rmtoll CR4 WP1 LL_PWR_IsWakeUpPinPolarityLow\n
1090 * CR4 WP2 LL_PWR_IsWakeUpPinPolarityLow\n
1091 * CR4 WP3 LL_PWR_IsWakeUpPinPolarityLow\n
1092 * CR4 WP4 LL_PWR_IsWakeUpPinPolarityLow\n
1093 * CR4 WP5 LL_PWR_IsWakeUpPinPolarityLow
1094 * @param WakeUpPin This parameter can be one of the following values:
1095 * @arg @ref LL_PWR_WAKEUP_PIN1
1096 * @arg @ref LL_PWR_WAKEUP_PIN2
1097 * @arg @ref LL_PWR_WAKEUP_PIN3
1098 * @arg @ref LL_PWR_WAKEUP_PIN4
1099 * @arg @ref LL_PWR_WAKEUP_PIN5
1100 * @retval State of bit (1 or 0).
1101 */
LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)1102 __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
1103 {
1104 return ((READ_BIT(PWR->CR4, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
1105 }
1106
1107 /**
1108 * @brief Enable GPIO pull-up state in Standby and Shutdown modes
1109 * @rmtoll PUCRA PU0-15 LL_PWR_EnableGPIOPullUp\n
1110 * PUCRB PU0-15 LL_PWR_EnableGPIOPullUp\n
1111 * PUCRC PU0-15 LL_PWR_EnableGPIOPullUp\n
1112 * PUCRD PU0-15 LL_PWR_EnableGPIOPullUp\n
1113 * PUCRE PU0-15 LL_PWR_EnableGPIOPullUp\n
1114 * PUCRF PU0-15 LL_PWR_EnableGPIOPullUp\n
1115 * PUCRG PU0-15 LL_PWR_EnableGPIOPullUp\n
1116 * PUCRH PU0-15 LL_PWR_EnableGPIOPullUp\n
1117 * PUCRI PU0-11 LL_PWR_EnableGPIOPullUp
1118 * @param GPIO This parameter can be one of the following values:
1119 * @arg @ref LL_PWR_GPIO_A
1120 * @arg @ref LL_PWR_GPIO_B
1121 * @arg @ref LL_PWR_GPIO_C
1122 * @arg @ref LL_PWR_GPIO_D
1123 * @arg @ref LL_PWR_GPIO_E
1124 * @arg @ref LL_PWR_GPIO_F (*)
1125 * @arg @ref LL_PWR_GPIO_G (*)
1126 * @arg @ref LL_PWR_GPIO_H
1127 * @arg @ref LL_PWR_GPIO_I (*)
1128 *
1129 * (*) value not defined in all devices
1130 * @param GPIONumber This parameter can be one of the following values:
1131 * @arg @ref LL_PWR_GPIO_BIT_0
1132 * @arg @ref LL_PWR_GPIO_BIT_1
1133 * @arg @ref LL_PWR_GPIO_BIT_2
1134 * @arg @ref LL_PWR_GPIO_BIT_3
1135 * @arg @ref LL_PWR_GPIO_BIT_4
1136 * @arg @ref LL_PWR_GPIO_BIT_5
1137 * @arg @ref LL_PWR_GPIO_BIT_6
1138 * @arg @ref LL_PWR_GPIO_BIT_7
1139 * @arg @ref LL_PWR_GPIO_BIT_8
1140 * @arg @ref LL_PWR_GPIO_BIT_9
1141 * @arg @ref LL_PWR_GPIO_BIT_10
1142 * @arg @ref LL_PWR_GPIO_BIT_11
1143 * @arg @ref LL_PWR_GPIO_BIT_12
1144 * @arg @ref LL_PWR_GPIO_BIT_13
1145 * @arg @ref LL_PWR_GPIO_BIT_14
1146 * @arg @ref LL_PWR_GPIO_BIT_15
1147 * @retval None
1148 */
LL_PWR_EnableGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)1149 __STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
1150 {
1151 SET_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
1152 }
1153
1154 /**
1155 * @brief Disable GPIO pull-up state in Standby and Shutdown modes
1156 * @rmtoll PUCRA PU0-15 LL_PWR_DisableGPIOPullUp\n
1157 * PUCRB PU0-15 LL_PWR_DisableGPIOPullUp\n
1158 * PUCRC PU0-15 LL_PWR_DisableGPIOPullUp\n
1159 * PUCRD PU0-15 LL_PWR_DisableGPIOPullUp\n
1160 * PUCRE PU0-15 LL_PWR_DisableGPIOPullUp\n
1161 * PUCRF PU0-15 LL_PWR_DisableGPIOPullUp\n
1162 * PUCRG PU0-15 LL_PWR_DisableGPIOPullUp\n
1163 * PUCRH PU0-15 LL_PWR_DisableGPIOPullUp\n
1164 * PUCRI PU0-11 LL_PWR_DisableGPIOPullUp
1165 * @param GPIO This parameter can be one of the following values:
1166 * @arg @ref LL_PWR_GPIO_A
1167 * @arg @ref LL_PWR_GPIO_B
1168 * @arg @ref LL_PWR_GPIO_C
1169 * @arg @ref LL_PWR_GPIO_D
1170 * @arg @ref LL_PWR_GPIO_E
1171 * @arg @ref LL_PWR_GPIO_F (*)
1172 * @arg @ref LL_PWR_GPIO_G (*)
1173 * @arg @ref LL_PWR_GPIO_H
1174 * @arg @ref LL_PWR_GPIO_I (*)
1175 *
1176 * (*) value not defined in all devices
1177 * @param GPIONumber This parameter can be one of the following values:
1178 * @arg @ref LL_PWR_GPIO_BIT_0
1179 * @arg @ref LL_PWR_GPIO_BIT_1
1180 * @arg @ref LL_PWR_GPIO_BIT_2
1181 * @arg @ref LL_PWR_GPIO_BIT_3
1182 * @arg @ref LL_PWR_GPIO_BIT_4
1183 * @arg @ref LL_PWR_GPIO_BIT_5
1184 * @arg @ref LL_PWR_GPIO_BIT_6
1185 * @arg @ref LL_PWR_GPIO_BIT_7
1186 * @arg @ref LL_PWR_GPIO_BIT_8
1187 * @arg @ref LL_PWR_GPIO_BIT_9
1188 * @arg @ref LL_PWR_GPIO_BIT_10
1189 * @arg @ref LL_PWR_GPIO_BIT_11
1190 * @arg @ref LL_PWR_GPIO_BIT_12
1191 * @arg @ref LL_PWR_GPIO_BIT_13
1192 * @arg @ref LL_PWR_GPIO_BIT_14
1193 * @arg @ref LL_PWR_GPIO_BIT_15
1194 * @retval None
1195 */
LL_PWR_DisableGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)1196 __STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
1197 {
1198 CLEAR_BIT(*((__IO uint32_t *)GPIO), GPIONumber);
1199 }
1200
1201 /**
1202 * @brief Check if GPIO pull-up state is enabled
1203 * @rmtoll PUCRA PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1204 * PUCRB PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1205 * PUCRC PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1206 * PUCRD PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1207 * PUCRE PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1208 * PUCRF PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1209 * PUCRG PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1210 * PUCRH PU0-15 LL_PWR_IsEnabledGPIOPullUp\n
1211 * PUCRI PU0-11 LL_PWR_IsEnabledGPIOPullUp
1212 * @param GPIO This parameter can be one of the following values:
1213 * @arg @ref LL_PWR_GPIO_A
1214 * @arg @ref LL_PWR_GPIO_B
1215 * @arg @ref LL_PWR_GPIO_C
1216 * @arg @ref LL_PWR_GPIO_D
1217 * @arg @ref LL_PWR_GPIO_E
1218 * @arg @ref LL_PWR_GPIO_F (*)
1219 * @arg @ref LL_PWR_GPIO_G (*)
1220 * @arg @ref LL_PWR_GPIO_H
1221 * @arg @ref LL_PWR_GPIO_I (*)
1222 *
1223 * (*) value not defined in all devices
1224 * @param GPIONumber This parameter can be one of the following values:
1225 * @arg @ref LL_PWR_GPIO_BIT_0
1226 * @arg @ref LL_PWR_GPIO_BIT_1
1227 * @arg @ref LL_PWR_GPIO_BIT_2
1228 * @arg @ref LL_PWR_GPIO_BIT_3
1229 * @arg @ref LL_PWR_GPIO_BIT_4
1230 * @arg @ref LL_PWR_GPIO_BIT_5
1231 * @arg @ref LL_PWR_GPIO_BIT_6
1232 * @arg @ref LL_PWR_GPIO_BIT_7
1233 * @arg @ref LL_PWR_GPIO_BIT_8
1234 * @arg @ref LL_PWR_GPIO_BIT_9
1235 * @arg @ref LL_PWR_GPIO_BIT_10
1236 * @arg @ref LL_PWR_GPIO_BIT_11
1237 * @arg @ref LL_PWR_GPIO_BIT_12
1238 * @arg @ref LL_PWR_GPIO_BIT_13
1239 * @arg @ref LL_PWR_GPIO_BIT_14
1240 * @arg @ref LL_PWR_GPIO_BIT_15
1241 * @retval State of bit (1 or 0).
1242 */
LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO,uint32_t GPIONumber)1243 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
1244 {
1245 return ((READ_BIT(*((__IO uint32_t *)GPIO), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
1246 }
1247
1248 /**
1249 * @brief Enable GPIO pull-down state in Standby and Shutdown modes
1250 * @rmtoll PDCRA PD0-15 LL_PWR_EnableGPIOPullDown\n
1251 * PDCRB PD0-15 LL_PWR_EnableGPIOPullDown\n
1252 * PDCRC PD0-15 LL_PWR_EnableGPIOPullDown\n
1253 * PDCRD PD0-15 LL_PWR_EnableGPIOPullDown\n
1254 * PDCRE PD0-15 LL_PWR_EnableGPIOPullDown\n
1255 * PDCRF PD0-15 LL_PWR_EnableGPIOPullDown\n
1256 * PDCRG PD0-15 LL_PWR_EnableGPIOPullDown\n
1257 * PDCRH PD0-15 LL_PWR_EnableGPIOPullDown\n
1258 * PDCRI PD0-11 LL_PWR_EnableGPIOPullDown
1259 * @param GPIO This parameter can be one of the following values:
1260 * @arg @ref LL_PWR_GPIO_A
1261 * @arg @ref LL_PWR_GPIO_B
1262 * @arg @ref LL_PWR_GPIO_C
1263 * @arg @ref LL_PWR_GPIO_D
1264 * @arg @ref LL_PWR_GPIO_E
1265 * @arg @ref LL_PWR_GPIO_F (*)
1266 * @arg @ref LL_PWR_GPIO_G (*)
1267 * @arg @ref LL_PWR_GPIO_H
1268 * @arg @ref LL_PWR_GPIO_I (*)
1269 *
1270 * (*) value not defined in all devices
1271 * @param GPIONumber This parameter can be one of the following values:
1272 * @arg @ref LL_PWR_GPIO_BIT_0
1273 * @arg @ref LL_PWR_GPIO_BIT_1
1274 * @arg @ref LL_PWR_GPIO_BIT_2
1275 * @arg @ref LL_PWR_GPIO_BIT_3
1276 * @arg @ref LL_PWR_GPIO_BIT_4
1277 * @arg @ref LL_PWR_GPIO_BIT_5
1278 * @arg @ref LL_PWR_GPIO_BIT_6
1279 * @arg @ref LL_PWR_GPIO_BIT_7
1280 * @arg @ref LL_PWR_GPIO_BIT_8
1281 * @arg @ref LL_PWR_GPIO_BIT_9
1282 * @arg @ref LL_PWR_GPIO_BIT_10
1283 * @arg @ref LL_PWR_GPIO_BIT_11
1284 * @arg @ref LL_PWR_GPIO_BIT_12
1285 * @arg @ref LL_PWR_GPIO_BIT_13
1286 * @arg @ref LL_PWR_GPIO_BIT_14
1287 * @arg @ref LL_PWR_GPIO_BIT_15
1288 * @retval None
1289 */
LL_PWR_EnableGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)1290 __STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
1291 {
1292 SET_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
1293 }
1294
1295 /**
1296 * @brief Disable GPIO pull-down state in Standby and Shutdown modes
1297 * @rmtoll PDCRA PD0-15 LL_PWR_DisableGPIOPullDown\n
1298 * PDCRB PD0-15 LL_PWR_DisableGPIOPullDown\n
1299 * PDCRC PD0-15 LL_PWR_DisableGPIOPullDown\n
1300 * PDCRD PD0-15 LL_PWR_DisableGPIOPullDown\n
1301 * PDCRE PD0-15 LL_PWR_DisableGPIOPullDown\n
1302 * PDCRF PD0-15 LL_PWR_DisableGPIOPullDown\n
1303 * PDCRG PD0-15 LL_PWR_DisableGPIOPullDown\n
1304 * PDCRH PD0-15 LL_PWR_DisableGPIOPullDown\n
1305 * PDCRI PD0-11 LL_PWR_DisableGPIOPullDown
1306 * @param GPIO This parameter can be one of the following values:
1307 * @arg @ref LL_PWR_GPIO_A
1308 * @arg @ref LL_PWR_GPIO_B
1309 * @arg @ref LL_PWR_GPIO_C
1310 * @arg @ref LL_PWR_GPIO_D
1311 * @arg @ref LL_PWR_GPIO_E
1312 * @arg @ref LL_PWR_GPIO_F (*)
1313 * @arg @ref LL_PWR_GPIO_G (*)
1314 * @arg @ref LL_PWR_GPIO_H
1315 * @arg @ref LL_PWR_GPIO_I (*)
1316 *
1317 * (*) value not defined in all devices
1318 * @param GPIONumber This parameter can be one of the following values:
1319 * @arg @ref LL_PWR_GPIO_BIT_0
1320 * @arg @ref LL_PWR_GPIO_BIT_1
1321 * @arg @ref LL_PWR_GPIO_BIT_2
1322 * @arg @ref LL_PWR_GPIO_BIT_3
1323 * @arg @ref LL_PWR_GPIO_BIT_4
1324 * @arg @ref LL_PWR_GPIO_BIT_5
1325 * @arg @ref LL_PWR_GPIO_BIT_6
1326 * @arg @ref LL_PWR_GPIO_BIT_7
1327 * @arg @ref LL_PWR_GPIO_BIT_8
1328 * @arg @ref LL_PWR_GPIO_BIT_9
1329 * @arg @ref LL_PWR_GPIO_BIT_10
1330 * @arg @ref LL_PWR_GPIO_BIT_11
1331 * @arg @ref LL_PWR_GPIO_BIT_12
1332 * @arg @ref LL_PWR_GPIO_BIT_13
1333 * @arg @ref LL_PWR_GPIO_BIT_14
1334 * @arg @ref LL_PWR_GPIO_BIT_15
1335 * @retval None
1336 */
LL_PWR_DisableGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)1337 __STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
1338 {
1339 CLEAR_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber);
1340 }
1341
1342 /**
1343 * @brief Check if GPIO pull-down state is enabled
1344 * @rmtoll PDCRA PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1345 * PDCRB PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1346 * PDCRC PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1347 * PDCRD PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1348 * PDCRE PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1349 * PDCRF PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1350 * PDCRG PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1351 * PDCRH PD0-15 LL_PWR_IsEnabledGPIOPullDown\n
1352 * PDCRI PD0-11 LL_PWR_IsEnabledGPIOPullDown
1353 * @param GPIO This parameter can be one of the following values:
1354 * @arg @ref LL_PWR_GPIO_A
1355 * @arg @ref LL_PWR_GPIO_B
1356 * @arg @ref LL_PWR_GPIO_C
1357 * @arg @ref LL_PWR_GPIO_D
1358 * @arg @ref LL_PWR_GPIO_E
1359 * @arg @ref LL_PWR_GPIO_F (*)
1360 * @arg @ref LL_PWR_GPIO_G (*)
1361 * @arg @ref LL_PWR_GPIO_H
1362 * @arg @ref LL_PWR_GPIO_I (*)
1363 *
1364 * (*) value not defined in all devices
1365 * @param GPIONumber This parameter can be one of the following values:
1366 * @arg @ref LL_PWR_GPIO_BIT_0
1367 * @arg @ref LL_PWR_GPIO_BIT_1
1368 * @arg @ref LL_PWR_GPIO_BIT_2
1369 * @arg @ref LL_PWR_GPIO_BIT_3
1370 * @arg @ref LL_PWR_GPIO_BIT_4
1371 * @arg @ref LL_PWR_GPIO_BIT_5
1372 * @arg @ref LL_PWR_GPIO_BIT_6
1373 * @arg @ref LL_PWR_GPIO_BIT_7
1374 * @arg @ref LL_PWR_GPIO_BIT_8
1375 * @arg @ref LL_PWR_GPIO_BIT_9
1376 * @arg @ref LL_PWR_GPIO_BIT_10
1377 * @arg @ref LL_PWR_GPIO_BIT_11
1378 * @arg @ref LL_PWR_GPIO_BIT_12
1379 * @arg @ref LL_PWR_GPIO_BIT_13
1380 * @arg @ref LL_PWR_GPIO_BIT_14
1381 * @arg @ref LL_PWR_GPIO_BIT_15
1382 * @retval State of bit (1 or 0).
1383 */
LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO,uint32_t GPIONumber)1384 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber)
1385 {
1386 return ((READ_BIT(*((__IO uint32_t *)(GPIO + 4U)), GPIONumber) == (GPIONumber)) ? 1UL : 0UL);
1387 }
1388
1389 /**
1390 * @}
1391 */
1392
1393 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
1394 * @{
1395 */
1396
1397 /**
1398 * @brief Get Internal Wake-up line Flag
1399 * @rmtoll SR1 WUFI LL_PWR_IsActiveFlag_InternWU
1400 * @retval State of bit (1 or 0).
1401 */
LL_PWR_IsActiveFlag_InternWU(void)1402 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU(void)
1403 {
1404 return ((READ_BIT(PWR->SR1, PWR_SR1_WUFI) == (PWR_SR1_WUFI)) ? 1UL : 0UL);
1405 }
1406
1407 #if defined(PWR_SR1_EXT_SMPS_RDY)
1408 /**
1409 * @brief Get Ready Flag for switching to external SMPS
1410 * @rmtoll SR1 EXT_SMPS_RDY LL_PWR_IsActiveFlag_ExtSMPSReady
1411 * @retval State of bit (1 or 0).
1412 */
LL_PWR_IsActiveFlag_ExtSMPSReady(void)1413 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ExtSMPSReady(void)
1414 {
1415 return ((READ_BIT(PWR->SR1, PWR_SR1_EXT_SMPS_RDY) == (PWR_SR1_EXT_SMPS_RDY)) ? 1UL : 0UL);
1416 }
1417 #endif /* PWR_SR1_EXT_SMPS_RDY */
1418
1419 /**
1420 * @brief Get Stand-By Flag
1421 * @rmtoll SR1 SBF LL_PWR_IsActiveFlag_SB
1422 * @retval State of bit (1 or 0).
1423 */
LL_PWR_IsActiveFlag_SB(void)1424 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
1425 {
1426 return ((READ_BIT(PWR->SR1, PWR_SR1_SBF) == (PWR_SR1_SBF)) ? 1UL : 0UL);
1427 }
1428
1429 /**
1430 * @brief Get Wake-up Flag 5
1431 * @rmtoll SR1 WUF5 LL_PWR_IsActiveFlag_WU5
1432 * @retval State of bit (1 or 0).
1433 */
LL_PWR_IsActiveFlag_WU5(void)1434 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
1435 {
1436 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF5) == (PWR_SR1_WUF5)) ? 1UL : 0UL);
1437 }
1438
1439 /**
1440 * @brief Get Wake-up Flag 4
1441 * @rmtoll SR1 WUF4 LL_PWR_IsActiveFlag_WU4
1442 * @retval State of bit (1 or 0).
1443 */
LL_PWR_IsActiveFlag_WU4(void)1444 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
1445 {
1446 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF4) == (PWR_SR1_WUF4)) ? 1UL : 0UL);
1447 }
1448
1449 /**
1450 * @brief Get Wake-up Flag 3
1451 * @rmtoll SR1 WUF3 LL_PWR_IsActiveFlag_WU3
1452 * @retval State of bit (1 or 0).
1453 */
LL_PWR_IsActiveFlag_WU3(void)1454 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
1455 {
1456 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3)) ? 1UL : 0UL);
1457 }
1458
1459 /**
1460 * @brief Get Wake-up Flag 2
1461 * @rmtoll SR1 WUF2 LL_PWR_IsActiveFlag_WU2
1462 * @retval State of bit (1 or 0).
1463 */
LL_PWR_IsActiveFlag_WU2(void)1464 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
1465 {
1466 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2)) ? 1UL : 0UL);
1467 }
1468
1469 /**
1470 * @brief Get Wake-up Flag 1
1471 * @rmtoll SR1 WUF1 LL_PWR_IsActiveFlag_WU1
1472 * @retval State of bit (1 or 0).
1473 */
LL_PWR_IsActiveFlag_WU1(void)1474 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
1475 {
1476 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF1) == (PWR_SR1_WUF1)) ? 1UL : 0UL);
1477 }
1478
1479 /**
1480 * @brief Clear Stand-By Flag
1481 * @rmtoll SCR CSBF LL_PWR_ClearFlag_SB
1482 * @retval None
1483 */
LL_PWR_ClearFlag_SB(void)1484 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
1485 {
1486 WRITE_REG(PWR->SCR, PWR_SCR_CSBF);
1487 }
1488
1489 /**
1490 * @brief Clear Wake-up Flags
1491 * @rmtoll SCR CWUF LL_PWR_ClearFlag_WU
1492 * @retval None
1493 */
LL_PWR_ClearFlag_WU(void)1494 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
1495 {
1496 WRITE_REG(PWR->SCR, PWR_SCR_CWUF);
1497 }
1498
1499 /**
1500 * @brief Clear Wake-up Flag 5
1501 * @rmtoll SCR CWUF5 LL_PWR_ClearFlag_WU5
1502 * @retval None
1503 */
LL_PWR_ClearFlag_WU5(void)1504 __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
1505 {
1506 WRITE_REG(PWR->SCR, PWR_SCR_CWUF5);
1507 }
1508
1509 /**
1510 * @brief Clear Wake-up Flag 4
1511 * @rmtoll SCR CWUF4 LL_PWR_ClearFlag_WU4
1512 * @retval None
1513 */
LL_PWR_ClearFlag_WU4(void)1514 __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
1515 {
1516 WRITE_REG(PWR->SCR, PWR_SCR_CWUF4);
1517 }
1518
1519 /**
1520 * @brief Clear Wake-up Flag 3
1521 * @rmtoll SCR CWUF3 LL_PWR_ClearFlag_WU3
1522 * @retval None
1523 */
LL_PWR_ClearFlag_WU3(void)1524 __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
1525 {
1526 WRITE_REG(PWR->SCR, PWR_SCR_CWUF3);
1527 }
1528
1529 /**
1530 * @brief Clear Wake-up Flag 2
1531 * @rmtoll SCR CWUF2 LL_PWR_ClearFlag_WU2
1532 * @retval None
1533 */
LL_PWR_ClearFlag_WU2(void)1534 __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
1535 {
1536 WRITE_REG(PWR->SCR, PWR_SCR_CWUF2);
1537 }
1538
1539 /**
1540 * @brief Clear Wake-up Flag 1
1541 * @rmtoll SCR CWUF1 LL_PWR_ClearFlag_WU1
1542 * @retval None
1543 */
LL_PWR_ClearFlag_WU1(void)1544 __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
1545 {
1546 WRITE_REG(PWR->SCR, PWR_SCR_CWUF1);
1547 }
1548
1549 /**
1550 * @brief Indicate whether VDDA voltage is below or above PVM4 threshold
1551 * @rmtoll SR2 PVMO4 LL_PWR_IsActiveFlag_PVMO4
1552 * @retval State of bit (1 or 0).
1553 */
LL_PWR_IsActiveFlag_PVMO4(void)1554 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO4(void)
1555 {
1556 return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO4) == (PWR_SR2_PVMO4)) ? 1UL : 0UL);
1557 }
1558
1559 /**
1560 * @brief Indicate whether VDDA voltage is below or above PVM3 threshold
1561 * @rmtoll SR2 PVMO3 LL_PWR_IsActiveFlag_PVMO3
1562 * @retval State of bit (1 or 0).
1563 */
LL_PWR_IsActiveFlag_PVMO3(void)1564 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO3(void)
1565 {
1566 return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO3) == (PWR_SR2_PVMO3)) ? 1UL : 0UL);
1567 }
1568
1569 #if defined(PWR_SR2_PVMO2)
1570 /**
1571 * @brief Indicate whether VDDIO2 voltage is below or above PVM2 threshold
1572 * @rmtoll SR2 PVMO2 LL_PWR_IsActiveFlag_PVMO2
1573 * @retval State of bit (1 or 0).
1574 */
LL_PWR_IsActiveFlag_PVMO2(void)1575 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO2(void)
1576 {
1577 return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO2) == (PWR_SR2_PVMO2)) ? 1UL : 0UL);
1578 }
1579 #endif /* PWR_SR2_PVMO2 */
1580
1581 #if defined(PWR_SR2_PVMO1)
1582 /**
1583 * @brief Indicate whether VDDUSB voltage is below or above PVM1 threshold
1584 * @rmtoll SR2 PVMO1 LL_PWR_IsActiveFlag_PVMO1
1585 * @retval State of bit (1 or 0).
1586 */
LL_PWR_IsActiveFlag_PVMO1(void)1587 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO1(void)
1588 {
1589 return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO1) == (PWR_SR2_PVMO1)) ? 1UL : 0UL);
1590 }
1591 #endif /* PWR_SR2_PVMO1 */
1592
1593 /**
1594 * @brief Indicate whether VDD voltage is below or above the selected PVD threshold
1595 * @rmtoll SR2 PVDO LL_PWR_IsActiveFlag_PVDO
1596 * @retval State of bit (1 or 0).
1597 */
LL_PWR_IsActiveFlag_PVDO(void)1598 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
1599 {
1600 return ((READ_BIT(PWR->SR2, PWR_SR2_PVDO) == (PWR_SR2_PVDO)) ? 1UL : 0UL);
1601 }
1602
1603 /**
1604 * @brief Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level
1605 * @rmtoll SR2 VOSF LL_PWR_IsActiveFlag_VOS
1606 * @retval State of bit (1 or 0).
1607 */
LL_PWR_IsActiveFlag_VOS(void)1608 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
1609 {
1610 return ((READ_BIT(PWR->SR2, PWR_SR2_VOSF) == (PWR_SR2_VOSF)) ? 1UL : 0UL);
1611 }
1612
1613 /**
1614 * @brief Indicate whether the regulator is ready in main mode or is in low-power mode
1615 * @note Take care, return value "0" means the regulator is ready. Return value "1" means the output voltage range is still changing.
1616 * @rmtoll SR2 REGLPF LL_PWR_IsActiveFlag_REGLPF
1617 * @retval State of bit (1 or 0).
1618 */
LL_PWR_IsActiveFlag_REGLPF(void)1619 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void)
1620 {
1621 return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPF) == (PWR_SR2_REGLPF)) ? 1UL : 0UL);
1622 }
1623
1624 /**
1625 * @brief Indicate whether or not the low-power regulator is ready
1626 * @rmtoll SR2 REGLPS LL_PWR_IsActiveFlag_REGLPS
1627 * @retval State of bit (1 or 0).
1628 */
LL_PWR_IsActiveFlag_REGLPS(void)1629 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPS(void)
1630 {
1631 return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPS) == (PWR_SR2_REGLPS)) ? 1UL : 0UL);
1632 }
1633
1634 /**
1635 * @}
1636 */
1637
1638 #if defined(USE_FULL_LL_DRIVER)
1639 /** @defgroup PWR_LL_EF_Init De-initialization function
1640 * @{
1641 */
1642 ErrorStatus LL_PWR_DeInit(void);
1643 /**
1644 * @}
1645 */
1646 #endif /* USE_FULL_LL_DRIVER */
1647
1648 /** @defgroup PWR_LL_EF_Legacy_Functions Legacy functions name
1649 * @{
1650 */
1651 /* Old functions name kept for legacy purpose, to be replaced by the */
1652 /* current functions name. */
1653 #define LL_PWR_IsActiveFlag_VOSF LL_PWR_IsActiveFlag_VOS
1654 /**
1655 * @}
1656 */
1657
1658 /**
1659 * @}
1660 */
1661
1662 /**
1663 * @}
1664 */
1665
1666 #endif /* defined(PWR) */
1667
1668 /**
1669 * @}
1670 */
1671
1672 #ifdef __cplusplus
1673 }
1674 #endif
1675
1676 #endif /* STM32L4xx_LL_PWR_H */
1677
1678 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1679