1 /** 2 ****************************************************************************** 3 * @file stm32wbxx_hal.h 4 * @author MCD Application Team 5 * @brief This file contains all the functions prototypes for the HAL 6 * module driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2019 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef STM32WBxx_HAL_H 23 #define STM32WBxx_HAL_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include "stm32wbxx_hal_conf.h" 31 #include "stm32wbxx_ll_system.h" 32 33 /** @addtogroup STM32WBxx_HAL_Driver 34 * @{ 35 */ 36 37 /** @defgroup HAL HAL 38 * @{ 39 */ 40 41 /* Exported constants --------------------------------------------------------*/ 42 /** @defgroup HAL_Exported_Constants HAL Exported Constants 43 * @{ 44 */ 45 46 /** @defgroup HAL_TICK_FREQ Tick Frequency 47 * @{ 48 */ 49 #define HAL_TICK_FREQ_10HZ 100U 50 #define HAL_TICK_FREQ_100HZ 10U 51 #define HAL_TICK_FREQ_1KHZ 1U 52 #define HAL_TICK_FREQ_DEFAULT HAL_TICK_FREQ_1KHZ 53 54 /** 55 * @} 56 */ 57 58 /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants 59 * @{ 60 */ 61 62 /** @defgroup SYSCFG_BootMode BOOT Mode 63 * @{ 64 */ 65 #define SYSCFG_BOOT_MAINFLASH LL_SYSCFG_REMAP_FLASH /*!< Main Flash memory mapped at 0x00000000 */ 66 #define SYSCFG_BOOT_SYSTEMFLASH LL_SYSCFG_REMAP_SYSTEMFLASH /*!< System Flash memory mapped at 0x00000000 */ 67 #define SYSCFG_BOOT_SRAM LL_SYSCFG_REMAP_SRAM /*!< SRAM1 mapped at 0x00000000 */ 68 #if defined(LL_SYSCFG_REMAP_QUADSPI) 69 #define SYSCFG_BOOT_QUADSPI LL_SYSCFG_REMAP_QUADSPI /*!< QUADSPI memory mapped at 0x00000000 */ 70 #endif 71 /** 72 * @} 73 */ 74 75 /** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts 76 * @{ 77 */ 78 #define SYSCFG_IT_FPU_IOC SYSCFG_CFGR1_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */ 79 #define SYSCFG_IT_FPU_DZC SYSCFG_CFGR1_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */ 80 #define SYSCFG_IT_FPU_UFC SYSCFG_CFGR1_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */ 81 #define SYSCFG_IT_FPU_OFC SYSCFG_CFGR1_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */ 82 #define SYSCFG_IT_FPU_IDC SYSCFG_CFGR1_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */ 83 #define SYSCFG_IT_FPU_IXC SYSCFG_CFGR1_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */ 84 85 /** 86 * @} 87 */ 88 89 /** @defgroup SYSCFG_SRAM2WRP SRAM2 Page Write protection (0 to 31) 90 * @{ 91 */ 92 #define SYSCFG_SRAM2WRP_PAGE0 LL_SYSCFG_SRAM2WRP_PAGE0 /*!< SRAM2A Write protection page 0 */ 93 #define SYSCFG_SRAM2WRP_PAGE1 LL_SYSCFG_SRAM2WRP_PAGE1 /*!< SRAM2A Write protection page 1 */ 94 #define SYSCFG_SRAM2WRP_PAGE2 LL_SYSCFG_SRAM2WRP_PAGE2 /*!< SRAM2A Write protection page 2 */ 95 #define SYSCFG_SRAM2WRP_PAGE3 LL_SYSCFG_SRAM2WRP_PAGE3 /*!< SRAM2A Write protection page 3 */ 96 #define SYSCFG_SRAM2WRP_PAGE4 LL_SYSCFG_SRAM2WRP_PAGE4 /*!< SRAM2A Write protection page 4 */ 97 #define SYSCFG_SRAM2WRP_PAGE5 LL_SYSCFG_SRAM2WRP_PAGE5 /*!< SRAM2A Write protection page 5 */ 98 #define SYSCFG_SRAM2WRP_PAGE6 LL_SYSCFG_SRAM2WRP_PAGE6 /*!< SRAM2A Write protection page 6 */ 99 #define SYSCFG_SRAM2WRP_PAGE7 LL_SYSCFG_SRAM2WRP_PAGE7 /*!< SRAM2A Write protection page 7 */ 100 #define SYSCFG_SRAM2WRP_PAGE8 LL_SYSCFG_SRAM2WRP_PAGE8 /*!< SRAM2A Write protection page 8 */ 101 #define SYSCFG_SRAM2WRP_PAGE9 LL_SYSCFG_SRAM2WRP_PAGE9 /*!< SRAM2A Write protection page 9 */ 102 #define SYSCFG_SRAM2WRP_PAGE10 LL_SYSCFG_SRAM2WRP_PAGE10 /*!< SRAM2A Write protection page 10 */ 103 #define SYSCFG_SRAM2WRP_PAGE11 LL_SYSCFG_SRAM2WRP_PAGE11 /*!< SRAM2A Write protection page 11 */ 104 #define SYSCFG_SRAM2WRP_PAGE12 LL_SYSCFG_SRAM2WRP_PAGE12 /*!< SRAM2A Write protection page 12 */ 105 #define SYSCFG_SRAM2WRP_PAGE13 LL_SYSCFG_SRAM2WRP_PAGE13 /*!< SRAM2A Write protection page 13 */ 106 #define SYSCFG_SRAM2WRP_PAGE14 LL_SYSCFG_SRAM2WRP_PAGE14 /*!< SRAM2A Write protection page 14 */ 107 #define SYSCFG_SRAM2WRP_PAGE15 LL_SYSCFG_SRAM2WRP_PAGE15 /*!< SRAM2A Write protection page 15 */ 108 #define SYSCFG_SRAM2WRP_PAGE16 LL_SYSCFG_SRAM2WRP_PAGE16 /*!< SRAM2A Write protection page 16 */ 109 #define SYSCFG_SRAM2WRP_PAGE17 LL_SYSCFG_SRAM2WRP_PAGE17 /*!< SRAM2A Write protection page 17 */ 110 #define SYSCFG_SRAM2WRP_PAGE18 LL_SYSCFG_SRAM2WRP_PAGE18 /*!< SRAM2A Write protection page 18 */ 111 #define SYSCFG_SRAM2WRP_PAGE19 LL_SYSCFG_SRAM2WRP_PAGE19 /*!< SRAM2A Write protection page 19 */ 112 #define SYSCFG_SRAM2WRP_PAGE20 LL_SYSCFG_SRAM2WRP_PAGE20 /*!< SRAM2A Write protection page 20 */ 113 #define SYSCFG_SRAM2WRP_PAGE21 LL_SYSCFG_SRAM2WRP_PAGE21 /*!< SRAM2A Write protection page 21 */ 114 #define SYSCFG_SRAM2WRP_PAGE22 LL_SYSCFG_SRAM2WRP_PAGE22 /*!< SRAM2A Write protection page 22 */ 115 #define SYSCFG_SRAM2WRP_PAGE23 LL_SYSCFG_SRAM2WRP_PAGE23 /*!< SRAM2A Write protection page 23 */ 116 #define SYSCFG_SRAM2WRP_PAGE24 LL_SYSCFG_SRAM2WRP_PAGE24 /*!< SRAM2A Write protection page 24 */ 117 #define SYSCFG_SRAM2WRP_PAGE25 LL_SYSCFG_SRAM2WRP_PAGE25 /*!< SRAM2A Write protection page 25 */ 118 #define SYSCFG_SRAM2WRP_PAGE26 LL_SYSCFG_SRAM2WRP_PAGE26 /*!< SRAM2A Write protection page 26 */ 119 #define SYSCFG_SRAM2WRP_PAGE27 LL_SYSCFG_SRAM2WRP_PAGE27 /*!< SRAM2A Write protection page 27 */ 120 #define SYSCFG_SRAM2WRP_PAGE28 LL_SYSCFG_SRAM2WRP_PAGE28 /*!< SRAM2A Write protection page 28 */ 121 #define SYSCFG_SRAM2WRP_PAGE29 LL_SYSCFG_SRAM2WRP_PAGE29 /*!< SRAM2A Write protection page 29 */ 122 #define SYSCFG_SRAM2WRP_PAGE30 LL_SYSCFG_SRAM2WRP_PAGE30 /*!< SRAM2A Write protection page 30 */ 123 #define SYSCFG_SRAM2WRP_PAGE31 LL_SYSCFG_SRAM2WRP_PAGE31 /*!< SRAM2A Write protection page 31 */ 124 125 /** 126 * @} 127 */ 128 129 /** @defgroup SYSCFG_SRAM2WRP_32_63 SRAM2 Page Write protection (32 to 63) 130 * @{ 131 */ 132 #define SYSCFG_SRAM2WRP_PAGE32 LL_SYSCFG_SRAM2WRP_PAGE32 /*!< SRAM2B Write protection page 32 */ 133 #define SYSCFG_SRAM2WRP_PAGE33 LL_SYSCFG_SRAM2WRP_PAGE33 /*!< SRAM2B Write protection page 33 */ 134 #define SYSCFG_SRAM2WRP_PAGE34 LL_SYSCFG_SRAM2WRP_PAGE34 /*!< SRAM2B Write protection page 34 */ 135 #define SYSCFG_SRAM2WRP_PAGE35 LL_SYSCFG_SRAM2WRP_PAGE35 /*!< SRAM2B Write protection page 35 */ 136 #define SYSCFG_SRAM2WRP_PAGE36 LL_SYSCFG_SRAM2WRP_PAGE36 /*!< SRAM2B Write protection page 36 */ 137 #define SYSCFG_SRAM2WRP_PAGE37 LL_SYSCFG_SRAM2WRP_PAGE37 /*!< SRAM2B Write protection page 37 */ 138 #define SYSCFG_SRAM2WRP_PAGE38 LL_SYSCFG_SRAM2WRP_PAGE38 /*!< SRAM2B Write protection page 38 */ 139 #define SYSCFG_SRAM2WRP_PAGE39 LL_SYSCFG_SRAM2WRP_PAGE39 /*!< SRAM2B Write protection page 39 */ 140 #define SYSCFG_SRAM2WRP_PAGE40 LL_SYSCFG_SRAM2WRP_PAGE40 /*!< SRAM2B Write protection page 40 */ 141 #define SYSCFG_SRAM2WRP_PAGE41 LL_SYSCFG_SRAM2WRP_PAGE41 /*!< SRAM2B Write protection page 41 */ 142 #define SYSCFG_SRAM2WRP_PAGE42 LL_SYSCFG_SRAM2WRP_PAGE42 /*!< SRAM2B Write protection page 42 */ 143 #define SYSCFG_SRAM2WRP_PAGE43 LL_SYSCFG_SRAM2WRP_PAGE43 /*!< SRAM2B Write protection page 43 */ 144 #define SYSCFG_SRAM2WRP_PAGE44 LL_SYSCFG_SRAM2WRP_PAGE44 /*!< SRAM2B Write protection page 44 */ 145 #define SYSCFG_SRAM2WRP_PAGE45 LL_SYSCFG_SRAM2WRP_PAGE45 /*!< SRAM2B Write protection page 45 */ 146 #define SYSCFG_SRAM2WRP_PAGE46 LL_SYSCFG_SRAM2WRP_PAGE46 /*!< SRAM2B Write protection page 46 */ 147 #define SYSCFG_SRAM2WRP_PAGE47 LL_SYSCFG_SRAM2WRP_PAGE47 /*!< SRAM2B Write protection page 47 */ 148 #define SYSCFG_SRAM2WRP_PAGE48 LL_SYSCFG_SRAM2WRP_PAGE48 /*!< SRAM2B Write protection page 48 */ 149 #define SYSCFG_SRAM2WRP_PAGE49 LL_SYSCFG_SRAM2WRP_PAGE49 /*!< SRAM2B Write protection page 49 */ 150 #define SYSCFG_SRAM2WRP_PAGE50 LL_SYSCFG_SRAM2WRP_PAGE50 /*!< SRAM2B Write protection page 50 */ 151 #define SYSCFG_SRAM2WRP_PAGE51 LL_SYSCFG_SRAM2WRP_PAGE51 /*!< SRAM2B Write protection page 51 */ 152 #define SYSCFG_SRAM2WRP_PAGE52 LL_SYSCFG_SRAM2WRP_PAGE52 /*!< SRAM2B Write protection page 52 */ 153 #define SYSCFG_SRAM2WRP_PAGE53 LL_SYSCFG_SRAM2WRP_PAGE53 /*!< SRAM2B Write protection page 53 */ 154 #define SYSCFG_SRAM2WRP_PAGE54 LL_SYSCFG_SRAM2WRP_PAGE54 /*!< SRAM2B Write protection page 54 */ 155 #define SYSCFG_SRAM2WRP_PAGE55 LL_SYSCFG_SRAM2WRP_PAGE55 /*!< SRAM2B Write protection page 55 */ 156 #define SYSCFG_SRAM2WRP_PAGE56 LL_SYSCFG_SRAM2WRP_PAGE56 /*!< SRAM2B Write protection page 56 */ 157 #define SYSCFG_SRAM2WRP_PAGE57 LL_SYSCFG_SRAM2WRP_PAGE57 /*!< SRAM2B Write protection page 57 */ 158 #define SYSCFG_SRAM2WRP_PAGE58 LL_SYSCFG_SRAM2WRP_PAGE58 /*!< SRAM2B Write protection page 58 */ 159 #define SYSCFG_SRAM2WRP_PAGE59 LL_SYSCFG_SRAM2WRP_PAGE59 /*!< SRAM2B Write protection page 59 */ 160 #define SYSCFG_SRAM2WRP_PAGE60 LL_SYSCFG_SRAM2WRP_PAGE60 /*!< SRAM2B Write protection page 60 */ 161 #define SYSCFG_SRAM2WRP_PAGE61 LL_SYSCFG_SRAM2WRP_PAGE61 /*!< SRAM2B Write protection page 61 */ 162 #define SYSCFG_SRAM2WRP_PAGE62 LL_SYSCFG_SRAM2WRP_PAGE62 /*!< SRAM2B Write protection page 62 */ 163 #define SYSCFG_SRAM2WRP_PAGE63 LL_SYSCFG_SRAM2WRP_PAGE63 /*!< SRAM2B Write protection page 63 */ 164 165 /** 166 * @} 167 */ 168 169 #if defined(VREFBUF) 170 /** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale 171 * @{ 172 */ 173 #define SYSCFG_VREFBUF_VOLTAGE_SCALE0 LL_VREFBUF_VOLTAGE_SCALE0 /*!< Voltage reference scale 0 (VREF_OUT1) */ 174 #define SYSCFG_VREFBUF_VOLTAGE_SCALE1 LL_VREFBUF_VOLTAGE_SCALE1 /*!< Voltage reference scale 1 (VREF_OUT2) */ 175 176 /** 177 * @} 178 */ 179 180 /** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance 181 * @{ 182 */ 183 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0x00000000U /*!< VREF_plus pin is internally connected to Voltage reference buffer output */ 184 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ 185 186 /** 187 * @} 188 */ 189 #endif /* VREFBUF */ 190 191 /** @defgroup SYSCFG_SRAM_flags_definition SRAM Flags 192 * @{ 193 */ 194 195 #define SYSCFG_FLAG_SRAM2_PE SYSCFG_CFGR2_SPF /*!< SRAM2 parity error */ 196 #define SYSCFG_FLAG_SRAM2_BUSY SYSCFG_SCSR_SRAM2BSY /*!< SRAM2 busy by erase operation */ 197 198 /** 199 * @} 200 */ 201 202 /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO 203 * @{ 204 */ 205 206 /** @brief Fast-mode Plus driving capability on a specific GPIO 207 */ 208 #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */ 209 #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */ 210 #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */ 211 #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */ 212 213 /** 214 * @} 215 */ 216 217 /** @defgroup Secure_IP_Write_Access Secure IP Write Access 218 * @{ 219 */ 220 #if defined(LL_SYSCFG_SECURE_ACCESS_AES1) 221 #define HAL_SYSCFG_SECURE_ACCESS_AES1 LL_SYSCFG_SECURE_ACCESS_AES1 /*!< Enabling the security access of Advanced Encryption Standard 1 KEY[7:0] */ 222 #endif 223 #define HAL_SYSCFG_SECURE_ACCESS_AES2 LL_SYSCFG_SECURE_ACCESS_AES2 /*!< Enabling the security access of Advanced Encryption Standard 2 */ 224 #define HAL_SYSCFG_SECURE_ACCESS_PKA LL_SYSCFG_SECURE_ACCESS_PKA /*!< Enabling the security access of Public Key Accelerator */ 225 #define HAL_SYSCFG_SECURE_ACCESS_RNG LL_SYSCFG_SECURE_ACCESS_RNG /*!< Enabling the security access of Random Number Generator */ 226 /** 227 * @} 228 */ 229 230 /** 231 * @} 232 */ 233 234 /** 235 * @} 236 */ 237 238 /* Exported macros -----------------------------------------------------------*/ 239 /** @defgroup HAL_Exported_Macros HAL Exported Macros 240 * @{ 241 */ 242 243 /** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros 244 * @{ 245 */ 246 247 /** @brief Freeze and Unfreeze Peripherals in Debug mode 248 */ 249 250 /** @defgroup DBGMCU_APBx_GRPx_STOP_IP DBGMCU CPU1 APBx GRPx STOP IP 251 * @{ 252 */ 253 #if defined(LL_DBGMCU_APB1_GRP1_TIM2_STOP) 254 #define __HAL_DBGMCU_FREEZE_TIM2() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_TIM2_STOP) 255 #define __HAL_DBGMCU_UNFREEZE_TIM2() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_TIM2_STOP) 256 #endif 257 258 #if defined(LL_DBGMCU_APB1_GRP1_RTC_STOP) 259 #define __HAL_DBGMCU_FREEZE_RTC() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_RTC_STOP) 260 #define __HAL_DBGMCU_UNFREEZE_RTC() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_RTC_STOP) 261 #endif 262 263 #if defined(LL_DBGMCU_APB1_GRP1_WWDG_STOP) 264 #define __HAL_DBGMCU_FREEZE_WWDG() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_WWDG_STOP) 265 #define __HAL_DBGMCU_UNFREEZE_WWDG() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_WWDG_STOP) 266 #endif 267 268 #if defined(LL_DBGMCU_APB1_GRP1_IWDG_STOP) 269 #define __HAL_DBGMCU_FREEZE_IWDG() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_IWDG_STOP) 270 #define __HAL_DBGMCU_UNFREEZE_IWDG() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_IWDG_STOP) 271 #endif 272 273 #if defined(LL_DBGMCU_APB1_GRP1_I2C1_STOP) 274 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_I2C1_STOP) 275 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_I2C1_STOP) 276 #endif 277 278 #if defined(LL_DBGMCU_APB1_GRP1_I2C3_STOP) 279 #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_I2C3_STOP) 280 #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_I2C3_STOP) 281 #endif 282 283 #if defined(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP) 284 #define __HAL_DBGMCU_FREEZE_LPTIM1() LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP) 285 #define __HAL_DBGMCU_UNFREEZE_LPTIM1() LL_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP) 286 #endif 287 288 #if defined(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP) 289 #define __HAL_DBGMCU_FREEZE_LPTIM2() LL_DBGMCU_APB1_GRP2_FreezePeriph(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP) 290 #define __HAL_DBGMCU_UNFREEZE_LPTIM2() LL_DBGMCU_APB1_GRP2_UnFreezePeriph(LL_DBGMCU_APB1_GRP2_LPTIM2_STOP) 291 #endif 292 293 #if defined(LL_DBGMCU_APB2_GRP1_TIM1_STOP) 294 #define __HAL_DBGMCU_FREEZE_TIM1() LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM1_STOP) 295 #define __HAL_DBGMCU_UNFREEZE_TIM1() LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM1_STOP) 296 #endif 297 298 #if defined(LL_DBGMCU_APB2_GRP1_TIM16_STOP) 299 #define __HAL_DBGMCU_FREEZE_TIM16() LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM16_STOP) 300 #define __HAL_DBGMCU_UNFREEZE_TIM16() LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM16_STOP) 301 #endif 302 303 #if defined(LL_DBGMCU_APB2_GRP1_TIM17_STOP) 304 #define __HAL_DBGMCU_FREEZE_TIM17() LL_DBGMCU_APB2_GRP1_FreezePeriph(LL_DBGMCU_APB2_GRP1_TIM17_STOP) 305 #define __HAL_DBGMCU_UNFREEZE_TIM17() LL_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_DBGMCU_APB2_GRP1_TIM17_STOP) 306 #endif 307 308 /** 309 * @} 310 */ 311 312 /** @defgroup DBGMCU_C2_APBx_GRPx_STOP_IP DBGMCU CPU2 APBx GRPx STOP IP 313 * @{ 314 */ 315 #if defined(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP) 316 #define __HAL_C2_DBGMCU_FREEZE_TIM2() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP) 317 #define __HAL_C2_DBGMCU_UNFREEZE_TIM2() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_TIM2_STOP) 318 #endif 319 320 #if defined(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP) 321 #define __HAL_C2_DBGMCU_FREEZE_RTC() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP) 322 #define __HAL_C2_DBGMCU_UNFREEZE_RTC() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_RTC_STOP) 323 #endif 324 325 #if defined(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP) 326 #define __HAL_C2_DBGMCU_FREEZE_IWDG() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP) 327 #define __HAL_C2_DBGMCU_UNFREEZE_IWDG() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_IWDG_STOP) 328 #endif 329 330 #if defined(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP) 331 #define __HAL_C2_DBGMCU_FREEZE_I2C1_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP) 332 #define __HAL_C2_DBGMCU_UNFREEZE_I2C1_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C1_STOP) 333 #endif 334 335 #if defined(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP) 336 #define __HAL_C2_DBGMCU_FREEZE_I2C3_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP) 337 #define __HAL_C2_DBGMCU_UNFREEZE_I2C3_TIMEOUT() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_I2C3_STOP) 338 #endif 339 340 #if defined(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP) 341 #define __HAL_C2_DBGMCU_FREEZE_LPTIM1() LL_C2_DBGMCU_APB1_GRP1_FreezePeriph(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP) 342 #define __HAL_C2_DBGMCU_UNFREEZE_LPTIM1() LL_C2_DBGMCU_APB1_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP1_LPTIM1_STOP) 343 #endif 344 345 #if defined(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP) 346 #define __HAL_C2_DBGMCU_FREEZE_LPTIM2() LL_C2_DBGMCU_APB1_GRP2_FreezePeriph(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP) 347 #define __HAL_C2_DBGMCU_UNFREEZE_LPTIM2() LL_C2_DBGMCU_APB1_GRP2_UnFreezePeriph(LL_C2_DBGMCU_APB1_GRP2_LPTIM2_STOP) 348 #endif 349 350 #if defined(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP) 351 #define __HAL_C2_DBGMCU_FREEZE_TIM1() LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP) 352 #define __HAL_C2_DBGMCU_UNFREEZE_TIM1() LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM1_STOP) 353 #endif 354 355 #if defined(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP) 356 #define __HAL_C2_DBGMCU_FREEZE_TIM16() LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP) 357 #define __HAL_C2_DBGMCU_UNFREEZE_TIM16() LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM16_STOP) 358 #endif 359 360 #if defined(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP) 361 #define __HAL_C2_DBGMCU_FREEZE_TIM17() LL_C2_DBGMCU_APB2_GRP1_FreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP) 362 #define __HAL_C2_DBGMCU_UNFREEZE_TIM17() LL_C2_DBGMCU_APB2_GRP1_UnFreezePeriph(LL_C2_DBGMCU_APB2_GRP1_TIM17_STOP) 363 #endif 364 365 /** 366 * @} 367 */ 368 369 /** 370 * @} 371 */ 372 373 /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros 374 * @{ 375 */ 376 377 /** @brief Main Flash memory mapped at 0x00000000 378 */ 379 #define __HAL_SYSCFG_REMAPMEMORY_FLASH() LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_FLASH) 380 381 /** @brief System Flash memory mapped at 0x00000000 382 */ 383 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_SYSTEMFLASH) 384 385 /** @brief Embedded SRAM mapped at 0x00000000 386 */ 387 #define __HAL_SYSCFG_REMAPMEMORY_SRAM() LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_SRAM) 388 389 #if defined(LL_SYSCFG_REMAP_QUADSPI) 390 /** @brief QUADSPI mapped at 0x00000000. 391 */ 392 #define __HAL_SYSCFG_REMAPMEMORY_QUADSPI() LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_QUADSPI) 393 #endif 394 395 /** 396 * @brief Return the boot mode as configured by user. 397 * @retval The boot mode as configured by user. The returned value can be one 398 * of the following values: 399 * @arg @ref SYSCFG_BOOT_MAINFLASH 400 * @arg @ref SYSCFG_BOOT_SYSTEMFLASH 401 * @arg @ref SYSCFG_BOOT_SRAM 402 #if defined(LL_SYSCFG_REMAP_QUADSPI) 403 * @arg @ref SYSCFG_BOOT_QUADSPI 404 #endif 405 */ 406 #define __HAL_SYSCFG_GET_BOOT_MODE() LL_SYSCFG_GetRemapMemory() 407 408 /** @brief SRAM2 page 0 to 31 write protection enable macro 409 * @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP 410 * @note Write protection can only be disabled by a system reset 411 */ 412 /* Legacy define */ 413 #define __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE 414 #define __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\ 415 LL_SYSCFG_EnableSRAM2PageWRP_0_31(__SRAM2WRP__);\ 416 }while(0) 417 418 /** @brief SRAM2 page 32 to 63 write protection enable macro 419 * @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP_32_63 420 * @note Write protection can only be disabled by a system reset 421 */ 422 #define __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\ 423 LL_SYSCFG_EnableSRAM2PageWRP_32_63(__SRAM2WRP__);\ 424 }while(0) 425 426 /** @brief SRAM2 page write protection unlock prior to erase 427 * @note Writing a wrong key reactivates the write protection 428 */ 429 #define __HAL_SYSCFG_SRAM2_WRP_UNLOCK() LL_SYSCFG_UnlockSRAM2WRP() 430 431 /** @brief SRAM2 erase 432 * @note __SYSCFG_GET_FLAG(SYSCFG_FLAG_SRAM2_BUSY) may be used to check end of erase 433 */ 434 #define __HAL_SYSCFG_SRAM2_ERASE() LL_SYSCFG_EnableSRAM2Erase() 435 436 /** @brief Floating Point Unit interrupt enable/disable macros 437 * @param __INTERRUPT__ This parameter can be a value of @ref SYSCFG_FPU_Interrupts 438 */ 439 #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ 440 SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\ 441 }while(0) 442 443 #define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ 444 CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\ 445 }while(0) 446 447 /** @brief SYSCFG Break ECC lock. 448 * Enable and lock the connection of Flash ECC error connection to TIM1/16/17 Break input. 449 * @note The selected configuration is locked and can be unlocked only by system reset. 450 */ 451 #define __HAL_SYSCFG_BREAK_ECC_LOCK() LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_ECC) 452 453 /** @brief SYSCFG Break Cortex-M4 Lockup lock. 454 * Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/16/17 Break input. 455 * @note The selected configuration is locked and can be unlocked only by system reset. 456 */ 457 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_LOCKUP) 458 459 /** @brief SYSCFG Break PVD lock. 460 * Enable and lock the PVD connection to Timer1/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register. 461 * @note The selected configuration is locked and can be unlocked only by system reset. 462 */ 463 #define __HAL_SYSCFG_BREAK_PVD_LOCK() LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_PVD) 464 465 /** @brief SYSCFG Break SRAM2 parity lock. 466 * Enable and lock the SRAM2 parity error signal connection to TIM1/16/17 Break input. 467 * @note The selected configuration is locked and can be unlocked by system reset. 468 */ 469 #define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() LL_SYSCFG_SetTIMBreakInputs(LL_SYSCFG_TIMBREAK_SRAM2_PARITY) 470 471 /** @brief Check SYSCFG flag is set or not. 472 * @param __FLAG__ specifies the flag to check. 473 * This parameter can be one of the following values: 474 * @arg @ref SYSCFG_FLAG_SRAM2_PE SRAM2 Parity Error Flag 475 * @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing 476 * @retval The new state of __FLAG__ (TRUE or FALSE). 477 */ 478 #define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0U) ? 1U : 0U) 479 480 /** @brief Set the SPF bit to clear the SRAM Parity Error Flag. 481 */ 482 #define __HAL_SYSCFG_CLEAR_FLAG() LL_SYSCFG_ClearFlag_SP() 483 484 /** @brief Fast mode Plus driving capability enable/disable macros 485 * @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO 486 */ 487 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \ 488 LL_SYSCFG_EnableFastModePlus(__FASTMODEPLUS__); \ 489 }while(0) 490 491 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \ 492 LL_SYSCFG_DisableFastModePlus(__FASTMODEPLUS__); \ 493 }while(0) 494 495 /** 496 * @} 497 */ 498 499 /** 500 * @} 501 */ 502 503 /* Private macros ------------------------------------------------------------*/ 504 /** @defgroup HAL_Private_Macros HAL Private Macros 505 * @{ 506 */ 507 508 /** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros 509 * @{ 510 */ 511 512 #define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \ 513 (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \ 514 (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \ 515 (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \ 516 (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \ 517 (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC)) 518 519 #define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFU)) 520 521 #if defined(VREFBUF) 522 #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ 523 ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1)) 524 525 #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ 526 ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE)) 527 528 #define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) 529 #endif 530 531 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 532 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ 533 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ 534 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) 535 536 #if defined(LL_SYSCFG_SECURE_ACCESS_AES1) 537 #define IS_SYSCFG_SECURITY_ACCESS(__VALUE__) ((((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_AES1) == HAL_SYSCFG_SECURE_ACCESS_AES1) || \ 538 (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_AES2) == HAL_SYSCFG_SECURE_ACCESS_AES2) || \ 539 (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_PKA) == HAL_SYSCFG_SECURE_ACCESS_PKA) || \ 540 (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_RNG) == HAL_SYSCFG_SECURE_ACCESS_RNG)) 541 #else 542 #define IS_SYSCFG_SECURITY_ACCESS(__VALUE__) ((((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_AES2) == HAL_SYSCFG_SECURE_ACCESS_AES2) || \ 543 (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_PKA) == HAL_SYSCFG_SECURE_ACCESS_PKA) || \ 544 (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_RNG) == HAL_SYSCFG_SECURE_ACCESS_RNG)) 545 #endif 546 547 /** 548 * @} 549 */ 550 551 /** 552 * @} 553 */ 554 555 /** @defgroup HAL_Private_Macros HAL Private Macros 556 * @{ 557 */ 558 #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ 559 ((FREQ) == HAL_TICK_FREQ_100HZ) || \ 560 ((FREQ) == HAL_TICK_FREQ_1KHZ)) 561 /** 562 * @} 563 */ 564 565 566 /* Exported functions --------------------------------------------------------*/ 567 568 /** @defgroup HAL_Exported_Functions HAL Exported Functions 569 * @{ 570 */ 571 572 /** @defgroup HAL_Exported_Functions_Group1 HAL Initialization and Configuration functions 573 * @{ 574 */ 575 576 /* Initialization and Configuration functions ******************************/ 577 HAL_StatusTypeDef HAL_Init(void); 578 HAL_StatusTypeDef HAL_DeInit(void); 579 void HAL_MspInit(void); 580 void HAL_MspDeInit(void); 581 582 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); 583 584 /** 585 * @} 586 */ 587 588 /** @defgroup HAL_Exported_Functions_Group2 HAL Control functions 589 * @{ 590 */ 591 592 /* Peripheral Control functions ************************************************/ 593 void HAL_IncTick(void); 594 void HAL_Delay(uint32_t Delay); 595 uint32_t HAL_GetTick(void); 596 uint32_t HAL_GetTickPrio(void); 597 HAL_StatusTypeDef HAL_SetTickFreq(uint32_t Freq); 598 uint32_t HAL_GetTickFreq(void); 599 void HAL_SuspendTick(void); 600 void HAL_ResumeTick(void); 601 uint32_t HAL_GetHalVersion(void); 602 uint32_t HAL_GetREVID(void); 603 uint32_t HAL_GetDEVID(void); 604 uint32_t HAL_GetUIDw0(void); 605 uint32_t HAL_GetUIDw1(void); 606 uint32_t HAL_GetUIDw2(void); 607 608 /** 609 * @} 610 */ 611 612 /** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions 613 * @{ 614 */ 615 616 /* DBGMCU Peripheral Control functions *****************************************/ 617 void HAL_DBGMCU_EnableDBGSleepMode(void); 618 void HAL_DBGMCU_DisableDBGSleepMode(void); 619 void HAL_DBGMCU_EnableDBGStopMode(void); 620 void HAL_DBGMCU_DisableDBGStopMode(void); 621 void HAL_DBGMCU_EnableDBGStandbyMode(void); 622 void HAL_DBGMCU_DisableDBGStandbyMode(void); 623 /** 624 * @} 625 */ 626 627 /* Exported variables ---------------------------------------------------------*/ 628 /** @addtogroup HAL_Exported_Variables 629 * @{ 630 */ 631 extern __IO uint32_t uwTick; 632 extern uint32_t uwTickPrio; 633 extern uint32_t uwTickFreq; 634 /** 635 * @} 636 */ 637 638 /** @addtogroup HAL_Exported_Functions_Group4 HAL System Configuration functions 639 * @{ 640 */ 641 642 /* SYSCFG Control functions ****************************************************/ 643 void HAL_SYSCFG_SRAM2Erase(void); 644 void HAL_SYSCFG_DisableSRAMFetch(void); 645 uint32_t HAL_SYSCFG_IsEnabledSRAMFetch(void); 646 647 #if defined(VREFBUF) 648 void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); 649 void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); 650 void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); 651 HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); 652 void HAL_SYSCFG_DisableVREFBUF(void); 653 #endif 654 655 void HAL_SYSCFG_EnableIOBooster(void); 656 void HAL_SYSCFG_DisableIOBooster(void); 657 void HAL_SYSCFG_EnableIOVdd(void); 658 void HAL_SYSCFG_DisableIOVdd(void); 659 660 void HAL_SYSCFG_EnableSecurityAccess(uint32_t SecurityAccess); 661 void HAL_SYSCFG_DisableSecurityAccess(uint32_t SecurityAccess); 662 uint32_t HAL_SYSCFG_IsEnabledSecurityAccess(uint32_t SecurityAccess); 663 664 /** 665 * @} 666 */ 667 668 /** 669 * @} 670 */ 671 672 /** 673 * @} 674 */ 675 676 /** 677 * @} 678 */ 679 680 #ifdef __cplusplus 681 } 682 #endif 683 684 #endif /* STM32WBxx_HAL_H */ 685 686 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 687