1 /* Copyright 2020 The TensorFlow Authors. All Rights Reserved. 2 3 Licensed under the Apache License, Version 2.0 (the "License"); 4 you may not use this file except in compliance with the License. 5 You may obtain a copy of the License at 6 7 http://www.apache.org/licenses/LICENSE-2.0 8 9 Unless required by applicable law or agreed to in writing, software 10 distributed under the License is distributed on an "AS IS" BASIS, 11 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 See the License for the specific language governing permissions and 13 limitations under the License. 14 ==============================================================================*/ 15 #ifndef TENSORFLOW_COMPILER_XLA_SERVICE_GPU_TREE_REDUCTION_REWRITER_H_ 16 #define TENSORFLOW_COMPILER_XLA_SERVICE_GPU_TREE_REDUCTION_REWRITER_H_ 17 18 #include <utility> 19 20 #include "absl/strings/string_view.h" 21 #include "tensorflow/compiler/xla/service/hlo_module.h" 22 #include "tensorflow/compiler/xla/service/hlo_pass_interface.h" 23 #include "tensorflow/compiler/xla/statusor.h" 24 25 namespace xla { 26 namespace gpu { 27 28 // Rewrites reductions in a way they can be implemented without atomics. 29 // 30 // Rule application: rewrite a single HLO reduce operation into two. 31 // 32 // Case 1: Row reduction, batched dimension is present, larger than 33 // Z-tiling size. 34 // ----------------------------------------------------------------- 35 // 36 // Rewriting: 37 // 38 // f32[B] out = reduce(f32[A, B, C] input, dimensions={0, 2}) 39 // 40 // Into: 41 // 42 // f32[A, B] tmp = reduce(f32[A, B, C] input, dimensions={2}) 43 // f32[B] out = reduce(f32[A, B] tmp, dimensions={0}) 44 // 45 // Case 2: Row reduction 46 // ------------------------------------------------------------------ 47 // 48 // Let M be the thread tiling multiplied by the warp size. 49 // We go from (assuming C > M): 50 // 51 // f32[B] out = reduce(f32[A, B, C] input, dimensions={0, 2}) 52 // 53 // to: 54 // 55 // f32[A, B, P] padded = pad(input) // Let P = ceil(C/M) * M. 56 // f32[A, B, Q, M] reshaped = bitcast(padded) // Let Q = ceil(C/M) 57 // f32[B, Q] inner_reduce = reduce(reshaped, dimensions={0, 3}) 58 // f32[B] outer_reduce = reduce(inner_reduce, dimensions={1}) 59 // 60 // Case 3: Column reduction 61 // ------------------------------------------------------------------- 62 // 63 // Let T be the tiling size for the column reduction. 64 // 65 // We go from (assuming B > T): 66 // 67 // f32[A, C] out = reduce(f32[A, B, C] input, dimensions={1}) 68 // 69 // to: 70 // 71 // f32[A, P, C] padded = pad(input) // Let P = ceil(B/T) * T. 72 // f32[A, Q, T, C] reshaped = bitcast(padded) // Let Q = ceil(B/T) 73 // f32[A, Q, C] inner_reduce = reduce(reshaped, dimensions={2}) 74 // f32[A, C] outer_reduce = reduce(inner_reduce, dimensions={1}) 75 // 76 class GpuTreeReductionRewriter : public HloModulePass { 77 public: GpuTreeReductionRewriter(se::CudaComputeCapability cuda_compute_capability)78 explicit GpuTreeReductionRewriter( 79 se::CudaComputeCapability cuda_compute_capability) 80 : cuda_compute_capability_(cuda_compute_capability) {} 81 82 ~GpuTreeReductionRewriter() override = default; name()83 absl::string_view name() const override { 84 return "gpu-tree-reduction-rewriter"; 85 } 86 87 using HloPassInterface::Run; 88 StatusOr<bool> Run( 89 HloModule* module, 90 const absl::flat_hash_set<absl::string_view>& execution_threads) override; 91 92 private: 93 se::CudaComputeCapability cuda_compute_capability_; 94 }; 95 96 } // end namespace gpu 97 } // end namespace xla 98 99 #endif // TENSORFLOW_COMPILER_XLA_SERVICE_GPU_TREE_REDUCTION_REWRITER_H_ 100