1#include <openssl/asm_base.h> 2 3#if !defined(OPENSSL_NO_ASM) && defined(OPENSSL_ARM) && defined(__ELF__) 4 5# This implementation was taken from the public domain, neon2 version in 6# SUPERCOP by D. J. Bernstein and Peter Schwabe. 7 8# qhasm: int32 input_0 9 10# qhasm: int32 input_1 11 12# qhasm: int32 input_2 13 14# qhasm: int32 input_3 15 16# qhasm: stack32 input_4 17 18# qhasm: stack32 input_5 19 20# qhasm: stack32 input_6 21 22# qhasm: stack32 input_7 23 24# qhasm: int32 caller_r4 25 26# qhasm: int32 caller_r5 27 28# qhasm: int32 caller_r6 29 30# qhasm: int32 caller_r7 31 32# qhasm: int32 caller_r8 33 34# qhasm: int32 caller_r9 35 36# qhasm: int32 caller_r10 37 38# qhasm: int32 caller_r11 39 40# qhasm: int32 caller_r12 41 42# qhasm: int32 caller_r14 43 44# qhasm: reg128 caller_q4 45 46# qhasm: reg128 caller_q5 47 48# qhasm: reg128 caller_q6 49 50# qhasm: reg128 caller_q7 51 52# qhasm: startcode 53.fpu neon 54.text 55 56# qhasm: reg128 r0 57 58# qhasm: reg128 r1 59 60# qhasm: reg128 r2 61 62# qhasm: reg128 r3 63 64# qhasm: reg128 r4 65 66# qhasm: reg128 x01 67 68# qhasm: reg128 x23 69 70# qhasm: reg128 x4 71 72# qhasm: reg128 y0 73 74# qhasm: reg128 y12 75 76# qhasm: reg128 y34 77 78# qhasm: reg128 5y12 79 80# qhasm: reg128 5y34 81 82# qhasm: stack128 y0_stack 83 84# qhasm: stack128 y12_stack 85 86# qhasm: stack128 y34_stack 87 88# qhasm: stack128 5y12_stack 89 90# qhasm: stack128 5y34_stack 91 92# qhasm: reg128 z0 93 94# qhasm: reg128 z12 95 96# qhasm: reg128 z34 97 98# qhasm: reg128 5z12 99 100# qhasm: reg128 5z34 101 102# qhasm: stack128 z0_stack 103 104# qhasm: stack128 z12_stack 105 106# qhasm: stack128 z34_stack 107 108# qhasm: stack128 5z12_stack 109 110# qhasm: stack128 5z34_stack 111 112# qhasm: stack128 two24 113 114# qhasm: int32 ptr 115 116# qhasm: reg128 c01 117 118# qhasm: reg128 c23 119 120# qhasm: reg128 d01 121 122# qhasm: reg128 d23 123 124# qhasm: reg128 t0 125 126# qhasm: reg128 t1 127 128# qhasm: reg128 t2 129 130# qhasm: reg128 t3 131 132# qhasm: reg128 t4 133 134# qhasm: reg128 mask 135 136# qhasm: reg128 u0 137 138# qhasm: reg128 u1 139 140# qhasm: reg128 u2 141 142# qhasm: reg128 u3 143 144# qhasm: reg128 u4 145 146# qhasm: reg128 v01 147 148# qhasm: reg128 mid 149 150# qhasm: reg128 v23 151 152# qhasm: reg128 v4 153 154# qhasm: int32 len 155 156# qhasm: qpushenter crypto_onetimeauth_poly1305_neon2_blocks 157.align 4 158.global openssl_poly1305_neon2_blocks 159.hidden openssl_poly1305_neon2_blocks 160.type openssl_poly1305_neon2_blocks STT_FUNC 161openssl_poly1305_neon2_blocks: 162vpush {q4,q5,q6,q7} 163mov r12,sp 164sub sp,sp,#192 165bic sp,sp,#31 166 167# qhasm: len = input_3 168# asm 1: mov >len=int32#4,<input_3=int32#4 169# asm 2: mov >len=r3,<input_3=r3 170mov r3,r3 171 172# qhasm: new y0 173 174# qhasm: y0 = mem64[input_1]y0[1]; input_1 += 8 175# asm 1: vld1.8 {<y0=reg128#1%bot},[<input_1=int32#2]! 176# asm 2: vld1.8 {<y0=d0},[<input_1=r1]! 177vld1.8 {d0},[r1]! 178 179# qhasm: y12 = mem128[input_1]; input_1 += 16 180# asm 1: vld1.8 {>y12=reg128#2%bot->y12=reg128#2%top},[<input_1=int32#2]! 181# asm 2: vld1.8 {>y12=d2->y12=d3},[<input_1=r1]! 182vld1.8 {d2-d3},[r1]! 183 184# qhasm: y34 = mem128[input_1]; input_1 += 16 185# asm 1: vld1.8 {>y34=reg128#3%bot->y34=reg128#3%top},[<input_1=int32#2]! 186# asm 2: vld1.8 {>y34=d4->y34=d5},[<input_1=r1]! 187vld1.8 {d4-d5},[r1]! 188 189# qhasm: input_1 += 8 190# asm 1: add >input_1=int32#2,<input_1=int32#2,#8 191# asm 2: add >input_1=r1,<input_1=r1,#8 192add r1,r1,#8 193 194# qhasm: new z0 195 196# qhasm: z0 = mem64[input_1]z0[1]; input_1 += 8 197# asm 1: vld1.8 {<z0=reg128#4%bot},[<input_1=int32#2]! 198# asm 2: vld1.8 {<z0=d6},[<input_1=r1]! 199vld1.8 {d6},[r1]! 200 201# qhasm: z12 = mem128[input_1]; input_1 += 16 202# asm 1: vld1.8 {>z12=reg128#5%bot->z12=reg128#5%top},[<input_1=int32#2]! 203# asm 2: vld1.8 {>z12=d8->z12=d9},[<input_1=r1]! 204vld1.8 {d8-d9},[r1]! 205 206# qhasm: z34 = mem128[input_1]; input_1 += 16 207# asm 1: vld1.8 {>z34=reg128#6%bot->z34=reg128#6%top},[<input_1=int32#2]! 208# asm 2: vld1.8 {>z34=d10->z34=d11},[<input_1=r1]! 209vld1.8 {d10-d11},[r1]! 210 211# qhasm: 2x mask = 0xffffffff 212# asm 1: vmov.i64 >mask=reg128#7,#0xffffffff 213# asm 2: vmov.i64 >mask=q6,#0xffffffff 214vmov.i64 q6,#0xffffffff 215 216# qhasm: 2x u4 = 0xff 217# asm 1: vmov.i64 >u4=reg128#8,#0xff 218# asm 2: vmov.i64 >u4=q7,#0xff 219vmov.i64 q7,#0xff 220 221# qhasm: x01 aligned= mem128[input_0];input_0+=16 222# asm 1: vld1.8 {>x01=reg128#9%bot->x01=reg128#9%top},[<input_0=int32#1,: 128]! 223# asm 2: vld1.8 {>x01=d16->x01=d17},[<input_0=r0,: 128]! 224vld1.8 {d16-d17},[r0,: 128]! 225 226# qhasm: x23 aligned= mem128[input_0];input_0+=16 227# asm 1: vld1.8 {>x23=reg128#10%bot->x23=reg128#10%top},[<input_0=int32#1,: 128]! 228# asm 2: vld1.8 {>x23=d18->x23=d19},[<input_0=r0,: 128]! 229vld1.8 {d18-d19},[r0,: 128]! 230 231# qhasm: x4 aligned= mem64[input_0]x4[1] 232# asm 1: vld1.8 {<x4=reg128#11%bot},[<input_0=int32#1,: 64] 233# asm 2: vld1.8 {<x4=d20},[<input_0=r0,: 64] 234vld1.8 {d20},[r0,: 64] 235 236# qhasm: input_0 -= 32 237# asm 1: sub >input_0=int32#1,<input_0=int32#1,#32 238# asm 2: sub >input_0=r0,<input_0=r0,#32 239sub r0,r0,#32 240 241# qhasm: 2x mask unsigned>>=6 242# asm 1: vshr.u64 >mask=reg128#7,<mask=reg128#7,#6 243# asm 2: vshr.u64 >mask=q6,<mask=q6,#6 244vshr.u64 q6,q6,#6 245 246# qhasm: 2x u4 unsigned>>= 7 247# asm 1: vshr.u64 >u4=reg128#8,<u4=reg128#8,#7 248# asm 2: vshr.u64 >u4=q7,<u4=q7,#7 249vshr.u64 q7,q7,#7 250 251# qhasm: 4x 5y12 = y12 << 2 252# asm 1: vshl.i32 >5y12=reg128#12,<y12=reg128#2,#2 253# asm 2: vshl.i32 >5y12=q11,<y12=q1,#2 254vshl.i32 q11,q1,#2 255 256# qhasm: 4x 5y34 = y34 << 2 257# asm 1: vshl.i32 >5y34=reg128#13,<y34=reg128#3,#2 258# asm 2: vshl.i32 >5y34=q12,<y34=q2,#2 259vshl.i32 q12,q2,#2 260 261# qhasm: 4x 5y12 += y12 262# asm 1: vadd.i32 >5y12=reg128#12,<5y12=reg128#12,<y12=reg128#2 263# asm 2: vadd.i32 >5y12=q11,<5y12=q11,<y12=q1 264vadd.i32 q11,q11,q1 265 266# qhasm: 4x 5y34 += y34 267# asm 1: vadd.i32 >5y34=reg128#13,<5y34=reg128#13,<y34=reg128#3 268# asm 2: vadd.i32 >5y34=q12,<5y34=q12,<y34=q2 269vadd.i32 q12,q12,q2 270 271# qhasm: 2x u4 <<= 24 272# asm 1: vshl.i64 >u4=reg128#8,<u4=reg128#8,#24 273# asm 2: vshl.i64 >u4=q7,<u4=q7,#24 274vshl.i64 q7,q7,#24 275 276# qhasm: 4x 5z12 = z12 << 2 277# asm 1: vshl.i32 >5z12=reg128#14,<z12=reg128#5,#2 278# asm 2: vshl.i32 >5z12=q13,<z12=q4,#2 279vshl.i32 q13,q4,#2 280 281# qhasm: 4x 5z34 = z34 << 2 282# asm 1: vshl.i32 >5z34=reg128#15,<z34=reg128#6,#2 283# asm 2: vshl.i32 >5z34=q14,<z34=q5,#2 284vshl.i32 q14,q5,#2 285 286# qhasm: 4x 5z12 += z12 287# asm 1: vadd.i32 >5z12=reg128#14,<5z12=reg128#14,<z12=reg128#5 288# asm 2: vadd.i32 >5z12=q13,<5z12=q13,<z12=q4 289vadd.i32 q13,q13,q4 290 291# qhasm: 4x 5z34 += z34 292# asm 1: vadd.i32 >5z34=reg128#15,<5z34=reg128#15,<z34=reg128#6 293# asm 2: vadd.i32 >5z34=q14,<5z34=q14,<z34=q5 294vadd.i32 q14,q14,q5 295 296# qhasm: new two24 297 298# qhasm: new y0_stack 299 300# qhasm: new y12_stack 301 302# qhasm: new y34_stack 303 304# qhasm: new 5y12_stack 305 306# qhasm: new 5y34_stack 307 308# qhasm: new z0_stack 309 310# qhasm: new z12_stack 311 312# qhasm: new z34_stack 313 314# qhasm: new 5z12_stack 315 316# qhasm: new 5z34_stack 317 318# qhasm: ptr = &two24 319# asm 1: lea >ptr=int32#2,<two24=stack128#1 320# asm 2: lea >ptr=r1,<two24=[sp,#0] 321add r1,sp,#0 322 323# qhasm: mem128[ptr] aligned= u4 324# asm 1: vst1.8 {<u4=reg128#8%bot-<u4=reg128#8%top},[<ptr=int32#2,: 128] 325# asm 2: vst1.8 {<u4=d14-<u4=d15},[<ptr=r1,: 128] 326vst1.8 {d14-d15},[r1,: 128] 327 328# qhasm: r4 = u4 329# asm 1: vmov >r4=reg128#16,<u4=reg128#8 330# asm 2: vmov >r4=q15,<u4=q7 331vmov q15,q7 332 333# qhasm: r0 = u4 334# asm 1: vmov >r0=reg128#8,<u4=reg128#8 335# asm 2: vmov >r0=q7,<u4=q7 336vmov q7,q7 337 338# qhasm: ptr = &y0_stack 339# asm 1: lea >ptr=int32#2,<y0_stack=stack128#2 340# asm 2: lea >ptr=r1,<y0_stack=[sp,#16] 341add r1,sp,#16 342 343# qhasm: mem128[ptr] aligned= y0 344# asm 1: vst1.8 {<y0=reg128#1%bot-<y0=reg128#1%top},[<ptr=int32#2,: 128] 345# asm 2: vst1.8 {<y0=d0-<y0=d1},[<ptr=r1,: 128] 346vst1.8 {d0-d1},[r1,: 128] 347 348# qhasm: ptr = &y12_stack 349# asm 1: lea >ptr=int32#2,<y12_stack=stack128#3 350# asm 2: lea >ptr=r1,<y12_stack=[sp,#32] 351add r1,sp,#32 352 353# qhasm: mem128[ptr] aligned= y12 354# asm 1: vst1.8 {<y12=reg128#2%bot-<y12=reg128#2%top},[<ptr=int32#2,: 128] 355# asm 2: vst1.8 {<y12=d2-<y12=d3},[<ptr=r1,: 128] 356vst1.8 {d2-d3},[r1,: 128] 357 358# qhasm: ptr = &y34_stack 359# asm 1: lea >ptr=int32#2,<y34_stack=stack128#4 360# asm 2: lea >ptr=r1,<y34_stack=[sp,#48] 361add r1,sp,#48 362 363# qhasm: mem128[ptr] aligned= y34 364# asm 1: vst1.8 {<y34=reg128#3%bot-<y34=reg128#3%top},[<ptr=int32#2,: 128] 365# asm 2: vst1.8 {<y34=d4-<y34=d5},[<ptr=r1,: 128] 366vst1.8 {d4-d5},[r1,: 128] 367 368# qhasm: ptr = &z0_stack 369# asm 1: lea >ptr=int32#2,<z0_stack=stack128#7 370# asm 2: lea >ptr=r1,<z0_stack=[sp,#96] 371add r1,sp,#96 372 373# qhasm: mem128[ptr] aligned= z0 374# asm 1: vst1.8 {<z0=reg128#4%bot-<z0=reg128#4%top},[<ptr=int32#2,: 128] 375# asm 2: vst1.8 {<z0=d6-<z0=d7},[<ptr=r1,: 128] 376vst1.8 {d6-d7},[r1,: 128] 377 378# qhasm: ptr = &z12_stack 379# asm 1: lea >ptr=int32#2,<z12_stack=stack128#8 380# asm 2: lea >ptr=r1,<z12_stack=[sp,#112] 381add r1,sp,#112 382 383# qhasm: mem128[ptr] aligned= z12 384# asm 1: vst1.8 {<z12=reg128#5%bot-<z12=reg128#5%top},[<ptr=int32#2,: 128] 385# asm 2: vst1.8 {<z12=d8-<z12=d9},[<ptr=r1,: 128] 386vst1.8 {d8-d9},[r1,: 128] 387 388# qhasm: ptr = &z34_stack 389# asm 1: lea >ptr=int32#2,<z34_stack=stack128#9 390# asm 2: lea >ptr=r1,<z34_stack=[sp,#128] 391add r1,sp,#128 392 393# qhasm: mem128[ptr] aligned= z34 394# asm 1: vst1.8 {<z34=reg128#6%bot-<z34=reg128#6%top},[<ptr=int32#2,: 128] 395# asm 2: vst1.8 {<z34=d10-<z34=d11},[<ptr=r1,: 128] 396vst1.8 {d10-d11},[r1,: 128] 397 398# qhasm: ptr = &5y12_stack 399# asm 1: lea >ptr=int32#2,<5y12_stack=stack128#5 400# asm 2: lea >ptr=r1,<5y12_stack=[sp,#64] 401add r1,sp,#64 402 403# qhasm: mem128[ptr] aligned= 5y12 404# asm 1: vst1.8 {<5y12=reg128#12%bot-<5y12=reg128#12%top},[<ptr=int32#2,: 128] 405# asm 2: vst1.8 {<5y12=d22-<5y12=d23},[<ptr=r1,: 128] 406vst1.8 {d22-d23},[r1,: 128] 407 408# qhasm: ptr = &5y34_stack 409# asm 1: lea >ptr=int32#2,<5y34_stack=stack128#6 410# asm 2: lea >ptr=r1,<5y34_stack=[sp,#80] 411add r1,sp,#80 412 413# qhasm: mem128[ptr] aligned= 5y34 414# asm 1: vst1.8 {<5y34=reg128#13%bot-<5y34=reg128#13%top},[<ptr=int32#2,: 128] 415# asm 2: vst1.8 {<5y34=d24-<5y34=d25},[<ptr=r1,: 128] 416vst1.8 {d24-d25},[r1,: 128] 417 418# qhasm: ptr = &5z12_stack 419# asm 1: lea >ptr=int32#2,<5z12_stack=stack128#10 420# asm 2: lea >ptr=r1,<5z12_stack=[sp,#144] 421add r1,sp,#144 422 423# qhasm: mem128[ptr] aligned= 5z12 424# asm 1: vst1.8 {<5z12=reg128#14%bot-<5z12=reg128#14%top},[<ptr=int32#2,: 128] 425# asm 2: vst1.8 {<5z12=d26-<5z12=d27},[<ptr=r1,: 128] 426vst1.8 {d26-d27},[r1,: 128] 427 428# qhasm: ptr = &5z34_stack 429# asm 1: lea >ptr=int32#2,<5z34_stack=stack128#11 430# asm 2: lea >ptr=r1,<5z34_stack=[sp,#160] 431add r1,sp,#160 432 433# qhasm: mem128[ptr] aligned= 5z34 434# asm 1: vst1.8 {<5z34=reg128#15%bot-<5z34=reg128#15%top},[<ptr=int32#2,: 128] 435# asm 2: vst1.8 {<5z34=d28-<5z34=d29},[<ptr=r1,: 128] 436vst1.8 {d28-d29},[r1,: 128] 437 438# qhasm: unsigned>? len - 64 439# asm 1: cmp <len=int32#4,#64 440# asm 2: cmp <len=r3,#64 441cmp r3,#64 442 443# qhasm: goto below64bytes if !unsigned> 444bls ._below64bytes 445 446# qhasm: input_2 += 32 447# asm 1: add >input_2=int32#2,<input_2=int32#3,#32 448# asm 2: add >input_2=r1,<input_2=r2,#32 449add r1,r2,#32 450 451# qhasm: mainloop2: 452._mainloop2: 453 454# qhasm: c01 = mem128[input_2];input_2+=16 455# asm 1: vld1.8 {>c01=reg128#1%bot->c01=reg128#1%top},[<input_2=int32#2]! 456# asm 2: vld1.8 {>c01=d0->c01=d1},[<input_2=r1]! 457vld1.8 {d0-d1},[r1]! 458 459# qhasm: c23 = mem128[input_2];input_2+=16 460# asm 1: vld1.8 {>c23=reg128#2%bot->c23=reg128#2%top},[<input_2=int32#2]! 461# asm 2: vld1.8 {>c23=d2->c23=d3},[<input_2=r1]! 462vld1.8 {d2-d3},[r1]! 463 464# qhasm: r4[0,1] += x01[0] unsigned* z34[2]; r4[2,3] += x01[1] unsigned* z34[3] 465# asm 1: vmlal.u32 <r4=reg128#16,<x01=reg128#9%bot,<z34=reg128#6%top 466# asm 2: vmlal.u32 <r4=q15,<x01=d16,<z34=d11 467vmlal.u32 q15,d16,d11 468 469# qhasm: ptr = &z12_stack 470# asm 1: lea >ptr=int32#3,<z12_stack=stack128#8 471# asm 2: lea >ptr=r2,<z12_stack=[sp,#112] 472add r2,sp,#112 473 474# qhasm: z12 aligned= mem128[ptr] 475# asm 1: vld1.8 {>z12=reg128#3%bot->z12=reg128#3%top},[<ptr=int32#3,: 128] 476# asm 2: vld1.8 {>z12=d4->z12=d5},[<ptr=r2,: 128] 477vld1.8 {d4-d5},[r2,: 128] 478 479# qhasm: r4[0,1] += x01[2] unsigned* z34[0]; r4[2,3] += x01[3] unsigned* z34[1] 480# asm 1: vmlal.u32 <r4=reg128#16,<x01=reg128#9%top,<z34=reg128#6%bot 481# asm 2: vmlal.u32 <r4=q15,<x01=d17,<z34=d10 482vmlal.u32 q15,d17,d10 483 484# qhasm: ptr = &z0_stack 485# asm 1: lea >ptr=int32#3,<z0_stack=stack128#7 486# asm 2: lea >ptr=r2,<z0_stack=[sp,#96] 487add r2,sp,#96 488 489# qhasm: z0 aligned= mem128[ptr] 490# asm 1: vld1.8 {>z0=reg128#4%bot->z0=reg128#4%top},[<ptr=int32#3,: 128] 491# asm 2: vld1.8 {>z0=d6->z0=d7},[<ptr=r2,: 128] 492vld1.8 {d6-d7},[r2,: 128] 493 494# qhasm: r4[0,1] += x23[0] unsigned* z12[2]; r4[2,3] += x23[1] unsigned* z12[3] 495# asm 1: vmlal.u32 <r4=reg128#16,<x23=reg128#10%bot,<z12=reg128#3%top 496# asm 2: vmlal.u32 <r4=q15,<x23=d18,<z12=d5 497vmlal.u32 q15,d18,d5 498 499# qhasm: c01 c23 = c01[0]c01[1]c01[2]c23[2]c23[0]c23[1]c01[3]c23[3] 500# asm 1: vtrn.32 <c01=reg128#1%top,<c23=reg128#2%top 501# asm 2: vtrn.32 <c01=d1,<c23=d3 502vtrn.32 d1,d3 503 504# qhasm: r4[0,1] += x23[2] unsigned* z12[0]; r4[2,3] += x23[3] unsigned* z12[1] 505# asm 1: vmlal.u32 <r4=reg128#16,<x23=reg128#10%top,<z12=reg128#3%bot 506# asm 2: vmlal.u32 <r4=q15,<x23=d19,<z12=d4 507vmlal.u32 q15,d19,d4 508 509# qhasm: r4[0,1] += x4[0] unsigned* z0[0]; r4[2,3] += x4[1] unsigned* z0[1] 510# asm 1: vmlal.u32 <r4=reg128#16,<x4=reg128#11%bot,<z0=reg128#4%bot 511# asm 2: vmlal.u32 <r4=q15,<x4=d20,<z0=d6 512vmlal.u32 q15,d20,d6 513 514# qhasm: r3[0,1] = c23[2]<<18; r3[2,3] = c23[3]<<18 515# asm 1: vshll.u32 >r3=reg128#5,<c23=reg128#2%top,#18 516# asm 2: vshll.u32 >r3=q4,<c23=d3,#18 517vshll.u32 q4,d3,#18 518 519# qhasm: c01 c23 = c01[0]c23[0]c01[2]c01[3]c01[1]c23[1]c23[2]c23[3] 520# asm 1: vtrn.32 <c01=reg128#1%bot,<c23=reg128#2%bot 521# asm 2: vtrn.32 <c01=d0,<c23=d2 522vtrn.32 d0,d2 523 524# qhasm: r3[0,1] += x01[0] unsigned* z34[0]; r3[2,3] += x01[1] unsigned* z34[1] 525# asm 1: vmlal.u32 <r3=reg128#5,<x01=reg128#9%bot,<z34=reg128#6%bot 526# asm 2: vmlal.u32 <r3=q4,<x01=d16,<z34=d10 527vmlal.u32 q4,d16,d10 528 529# qhasm: r3[0,1] += x01[2] unsigned* z12[2]; r3[2,3] += x01[3] unsigned* z12[3] 530# asm 1: vmlal.u32 <r3=reg128#5,<x01=reg128#9%top,<z12=reg128#3%top 531# asm 2: vmlal.u32 <r3=q4,<x01=d17,<z12=d5 532vmlal.u32 q4,d17,d5 533 534# qhasm: r0 = r0[1]c01[0]r0[2,3] 535# asm 1: vext.32 <r0=reg128#8%bot,<r0=reg128#8%bot,<c01=reg128#1%bot,#1 536# asm 2: vext.32 <r0=d14,<r0=d14,<c01=d0,#1 537vext.32 d14,d14,d0,#1 538 539# qhasm: r3[0,1] += x23[0] unsigned* z12[0]; r3[2,3] += x23[1] unsigned* z12[1] 540# asm 1: vmlal.u32 <r3=reg128#5,<x23=reg128#10%bot,<z12=reg128#3%bot 541# asm 2: vmlal.u32 <r3=q4,<x23=d18,<z12=d4 542vmlal.u32 q4,d18,d4 543 544# qhasm: input_2 -= 64 545# asm 1: sub >input_2=int32#2,<input_2=int32#2,#64 546# asm 2: sub >input_2=r1,<input_2=r1,#64 547sub r1,r1,#64 548 549# qhasm: r3[0,1] += x23[2] unsigned* z0[0]; r3[2,3] += x23[3] unsigned* z0[1] 550# asm 1: vmlal.u32 <r3=reg128#5,<x23=reg128#10%top,<z0=reg128#4%bot 551# asm 2: vmlal.u32 <r3=q4,<x23=d19,<z0=d6 552vmlal.u32 q4,d19,d6 553 554# qhasm: ptr = &5z34_stack 555# asm 1: lea >ptr=int32#3,<5z34_stack=stack128#11 556# asm 2: lea >ptr=r2,<5z34_stack=[sp,#160] 557add r2,sp,#160 558 559# qhasm: 5z34 aligned= mem128[ptr] 560# asm 1: vld1.8 {>5z34=reg128#6%bot->5z34=reg128#6%top},[<ptr=int32#3,: 128] 561# asm 2: vld1.8 {>5z34=d10->5z34=d11},[<ptr=r2,: 128] 562vld1.8 {d10-d11},[r2,: 128] 563 564# qhasm: r3[0,1] += x4[0] unsigned* 5z34[2]; r3[2,3] += x4[1] unsigned* 5z34[3] 565# asm 1: vmlal.u32 <r3=reg128#5,<x4=reg128#11%bot,<5z34=reg128#6%top 566# asm 2: vmlal.u32 <r3=q4,<x4=d20,<5z34=d11 567vmlal.u32 q4,d20,d11 568 569# qhasm: r0 = r0[1]r0[0]r0[3]r0[2] 570# asm 1: vrev64.i32 >r0=reg128#8,<r0=reg128#8 571# asm 2: vrev64.i32 >r0=q7,<r0=q7 572vrev64.i32 q7,q7 573 574# qhasm: r2[0,1] = c01[2]<<12; r2[2,3] = c01[3]<<12 575# asm 1: vshll.u32 >r2=reg128#14,<c01=reg128#1%top,#12 576# asm 2: vshll.u32 >r2=q13,<c01=d1,#12 577vshll.u32 q13,d1,#12 578 579# qhasm: d01 = mem128[input_2];input_2+=16 580# asm 1: vld1.8 {>d01=reg128#12%bot->d01=reg128#12%top},[<input_2=int32#2]! 581# asm 2: vld1.8 {>d01=d22->d01=d23},[<input_2=r1]! 582vld1.8 {d22-d23},[r1]! 583 584# qhasm: r2[0,1] += x01[0] unsigned* z12[2]; r2[2,3] += x01[1] unsigned* z12[3] 585# asm 1: vmlal.u32 <r2=reg128#14,<x01=reg128#9%bot,<z12=reg128#3%top 586# asm 2: vmlal.u32 <r2=q13,<x01=d16,<z12=d5 587vmlal.u32 q13,d16,d5 588 589# qhasm: r2[0,1] += x01[2] unsigned* z12[0]; r2[2,3] += x01[3] unsigned* z12[1] 590# asm 1: vmlal.u32 <r2=reg128#14,<x01=reg128#9%top,<z12=reg128#3%bot 591# asm 2: vmlal.u32 <r2=q13,<x01=d17,<z12=d4 592vmlal.u32 q13,d17,d4 593 594# qhasm: r2[0,1] += x23[0] unsigned* z0[0]; r2[2,3] += x23[1] unsigned* z0[1] 595# asm 1: vmlal.u32 <r2=reg128#14,<x23=reg128#10%bot,<z0=reg128#4%bot 596# asm 2: vmlal.u32 <r2=q13,<x23=d18,<z0=d6 597vmlal.u32 q13,d18,d6 598 599# qhasm: r2[0,1] += x23[2] unsigned* 5z34[2]; r2[2,3] += x23[3] unsigned* 5z34[3] 600# asm 1: vmlal.u32 <r2=reg128#14,<x23=reg128#10%top,<5z34=reg128#6%top 601# asm 2: vmlal.u32 <r2=q13,<x23=d19,<5z34=d11 602vmlal.u32 q13,d19,d11 603 604# qhasm: r2[0,1] += x4[0] unsigned* 5z34[0]; r2[2,3] += x4[1] unsigned* 5z34[1] 605# asm 1: vmlal.u32 <r2=reg128#14,<x4=reg128#11%bot,<5z34=reg128#6%bot 606# asm 2: vmlal.u32 <r2=q13,<x4=d20,<5z34=d10 607vmlal.u32 q13,d20,d10 608 609# qhasm: r0 = r0[0,1]c01[1]r0[2] 610# asm 1: vext.32 <r0=reg128#8%top,<c01=reg128#1%bot,<r0=reg128#8%top,#1 611# asm 2: vext.32 <r0=d15,<c01=d0,<r0=d15,#1 612vext.32 d15,d0,d15,#1 613 614# qhasm: r1[0,1] = c23[0]<<6; r1[2,3] = c23[1]<<6 615# asm 1: vshll.u32 >r1=reg128#15,<c23=reg128#2%bot,#6 616# asm 2: vshll.u32 >r1=q14,<c23=d2,#6 617vshll.u32 q14,d2,#6 618 619# qhasm: r1[0,1] += x01[0] unsigned* z12[0]; r1[2,3] += x01[1] unsigned* z12[1] 620# asm 1: vmlal.u32 <r1=reg128#15,<x01=reg128#9%bot,<z12=reg128#3%bot 621# asm 2: vmlal.u32 <r1=q14,<x01=d16,<z12=d4 622vmlal.u32 q14,d16,d4 623 624# qhasm: r1[0,1] += x01[2] unsigned* z0[0]; r1[2,3] += x01[3] unsigned* z0[1] 625# asm 1: vmlal.u32 <r1=reg128#15,<x01=reg128#9%top,<z0=reg128#4%bot 626# asm 2: vmlal.u32 <r1=q14,<x01=d17,<z0=d6 627vmlal.u32 q14,d17,d6 628 629# qhasm: r1[0,1] += x23[0] unsigned* 5z34[2]; r1[2,3] += x23[1] unsigned* 5z34[3] 630# asm 1: vmlal.u32 <r1=reg128#15,<x23=reg128#10%bot,<5z34=reg128#6%top 631# asm 2: vmlal.u32 <r1=q14,<x23=d18,<5z34=d11 632vmlal.u32 q14,d18,d11 633 634# qhasm: r1[0,1] += x23[2] unsigned* 5z34[0]; r1[2,3] += x23[3] unsigned* 5z34[1] 635# asm 1: vmlal.u32 <r1=reg128#15,<x23=reg128#10%top,<5z34=reg128#6%bot 636# asm 2: vmlal.u32 <r1=q14,<x23=d19,<5z34=d10 637vmlal.u32 q14,d19,d10 638 639# qhasm: ptr = &5z12_stack 640# asm 1: lea >ptr=int32#3,<5z12_stack=stack128#10 641# asm 2: lea >ptr=r2,<5z12_stack=[sp,#144] 642add r2,sp,#144 643 644# qhasm: 5z12 aligned= mem128[ptr] 645# asm 1: vld1.8 {>5z12=reg128#1%bot->5z12=reg128#1%top},[<ptr=int32#3,: 128] 646# asm 2: vld1.8 {>5z12=d0->5z12=d1},[<ptr=r2,: 128] 647vld1.8 {d0-d1},[r2,: 128] 648 649# qhasm: r1[0,1] += x4[0] unsigned* 5z12[2]; r1[2,3] += x4[1] unsigned* 5z12[3] 650# asm 1: vmlal.u32 <r1=reg128#15,<x4=reg128#11%bot,<5z12=reg128#1%top 651# asm 2: vmlal.u32 <r1=q14,<x4=d20,<5z12=d1 652vmlal.u32 q14,d20,d1 653 654# qhasm: d23 = mem128[input_2];input_2+=16 655# asm 1: vld1.8 {>d23=reg128#2%bot->d23=reg128#2%top},[<input_2=int32#2]! 656# asm 2: vld1.8 {>d23=d2->d23=d3},[<input_2=r1]! 657vld1.8 {d2-d3},[r1]! 658 659# qhasm: input_2 += 32 660# asm 1: add >input_2=int32#2,<input_2=int32#2,#32 661# asm 2: add >input_2=r1,<input_2=r1,#32 662add r1,r1,#32 663 664# qhasm: r0[0,1] += x4[0] unsigned* 5z12[0]; r0[2,3] += x4[1] unsigned* 5z12[1] 665# asm 1: vmlal.u32 <r0=reg128#8,<x4=reg128#11%bot,<5z12=reg128#1%bot 666# asm 2: vmlal.u32 <r0=q7,<x4=d20,<5z12=d0 667vmlal.u32 q7,d20,d0 668 669# qhasm: r0[0,1] += x23[0] unsigned* 5z34[0]; r0[2,3] += x23[1] unsigned* 5z34[1] 670# asm 1: vmlal.u32 <r0=reg128#8,<x23=reg128#10%bot,<5z34=reg128#6%bot 671# asm 2: vmlal.u32 <r0=q7,<x23=d18,<5z34=d10 672vmlal.u32 q7,d18,d10 673 674# qhasm: d01 d23 = d01[0] d23[0] d01[1] d23[1] 675# asm 1: vswp <d23=reg128#2%bot,<d01=reg128#12%top 676# asm 2: vswp <d23=d2,<d01=d23 677vswp d2,d23 678 679# qhasm: r0[0,1] += x23[2] unsigned* 5z12[2]; r0[2,3] += x23[3] unsigned* 5z12[3] 680# asm 1: vmlal.u32 <r0=reg128#8,<x23=reg128#10%top,<5z12=reg128#1%top 681# asm 2: vmlal.u32 <r0=q7,<x23=d19,<5z12=d1 682vmlal.u32 q7,d19,d1 683 684# qhasm: r0[0,1] += x01[0] unsigned* z0[0]; r0[2,3] += x01[1] unsigned* z0[1] 685# asm 1: vmlal.u32 <r0=reg128#8,<x01=reg128#9%bot,<z0=reg128#4%bot 686# asm 2: vmlal.u32 <r0=q7,<x01=d16,<z0=d6 687vmlal.u32 q7,d16,d6 688 689# qhasm: new mid 690 691# qhasm: 2x v4 = d23 unsigned>> 40 692# asm 1: vshr.u64 >v4=reg128#4,<d23=reg128#2,#40 693# asm 2: vshr.u64 >v4=q3,<d23=q1,#40 694vshr.u64 q3,q1,#40 695 696# qhasm: mid = d01[1]d23[0] mid[2,3] 697# asm 1: vext.32 <mid=reg128#1%bot,<d01=reg128#12%bot,<d23=reg128#2%bot,#1 698# asm 2: vext.32 <mid=d0,<d01=d22,<d23=d2,#1 699vext.32 d0,d22,d2,#1 700 701# qhasm: new v23 702 703# qhasm: v23[2] = d23[0,1] unsigned>> 14; v23[3] = d23[2,3] unsigned>> 14 704# asm 1: vshrn.u64 <v23=reg128#10%top,<d23=reg128#2,#14 705# asm 2: vshrn.u64 <v23=d19,<d23=q1,#14 706vshrn.u64 d19,q1,#14 707 708# qhasm: mid = mid[0,1] d01[3]d23[2] 709# asm 1: vext.32 <mid=reg128#1%top,<d01=reg128#12%top,<d23=reg128#2%top,#1 710# asm 2: vext.32 <mid=d1,<d01=d23,<d23=d3,#1 711vext.32 d1,d23,d3,#1 712 713# qhasm: new v01 714 715# qhasm: v01[2] = d01[0,1] unsigned>> 26; v01[3] = d01[2,3] unsigned>> 26 716# asm 1: vshrn.u64 <v01=reg128#11%top,<d01=reg128#12,#26 717# asm 2: vshrn.u64 <v01=d21,<d01=q11,#26 718vshrn.u64 d21,q11,#26 719 720# qhasm: v01 = d01[1]d01[0] v01[2,3] 721# asm 1: vext.32 <v01=reg128#11%bot,<d01=reg128#12%bot,<d01=reg128#12%bot,#1 722# asm 2: vext.32 <v01=d20,<d01=d22,<d01=d22,#1 723vext.32 d20,d22,d22,#1 724 725# qhasm: r0[0,1] += x01[2] unsigned* 5z34[2]; r0[2,3] += x01[3] unsigned* 5z34[3] 726# asm 1: vmlal.u32 <r0=reg128#8,<x01=reg128#9%top,<5z34=reg128#6%top 727# asm 2: vmlal.u32 <r0=q7,<x01=d17,<5z34=d11 728vmlal.u32 q7,d17,d11 729 730# qhasm: v01 = v01[1]d01[2] v01[2,3] 731# asm 1: vext.32 <v01=reg128#11%bot,<v01=reg128#11%bot,<d01=reg128#12%top,#1 732# asm 2: vext.32 <v01=d20,<v01=d20,<d01=d23,#1 733vext.32 d20,d20,d23,#1 734 735# qhasm: v23[0] = mid[0,1] unsigned>> 20; v23[1] = mid[2,3] unsigned>> 20 736# asm 1: vshrn.u64 <v23=reg128#10%bot,<mid=reg128#1,#20 737# asm 2: vshrn.u64 <v23=d18,<mid=q0,#20 738vshrn.u64 d18,q0,#20 739 740# qhasm: v4 = v4[0]v4[2]v4[1]v4[3] 741# asm 1: vtrn.32 <v4=reg128#4%bot,<v4=reg128#4%top 742# asm 2: vtrn.32 <v4=d6,<v4=d7 743vtrn.32 d6,d7 744 745# qhasm: 4x v01 &= 0x03ffffff 746# asm 1: vand.i32 <v01=reg128#11,#0x03ffffff 747# asm 2: vand.i32 <v01=q10,#0x03ffffff 748vand.i32 q10,#0x03ffffff 749 750# qhasm: ptr = &y34_stack 751# asm 1: lea >ptr=int32#3,<y34_stack=stack128#4 752# asm 2: lea >ptr=r2,<y34_stack=[sp,#48] 753add r2,sp,#48 754 755# qhasm: y34 aligned= mem128[ptr] 756# asm 1: vld1.8 {>y34=reg128#3%bot->y34=reg128#3%top},[<ptr=int32#3,: 128] 757# asm 2: vld1.8 {>y34=d4->y34=d5},[<ptr=r2,: 128] 758vld1.8 {d4-d5},[r2,: 128] 759 760# qhasm: 4x v23 &= 0x03ffffff 761# asm 1: vand.i32 <v23=reg128#10,#0x03ffffff 762# asm 2: vand.i32 <v23=q9,#0x03ffffff 763vand.i32 q9,#0x03ffffff 764 765# qhasm: ptr = &y12_stack 766# asm 1: lea >ptr=int32#3,<y12_stack=stack128#3 767# asm 2: lea >ptr=r2,<y12_stack=[sp,#32] 768add r2,sp,#32 769 770# qhasm: y12 aligned= mem128[ptr] 771# asm 1: vld1.8 {>y12=reg128#2%bot->y12=reg128#2%top},[<ptr=int32#3,: 128] 772# asm 2: vld1.8 {>y12=d2->y12=d3},[<ptr=r2,: 128] 773vld1.8 {d2-d3},[r2,: 128] 774 775# qhasm: 4x v4 |= 0x01000000 776# asm 1: vorr.i32 <v4=reg128#4,#0x01000000 777# asm 2: vorr.i32 <v4=q3,#0x01000000 778vorr.i32 q3,#0x01000000 779 780# qhasm: ptr = &y0_stack 781# asm 1: lea >ptr=int32#3,<y0_stack=stack128#2 782# asm 2: lea >ptr=r2,<y0_stack=[sp,#16] 783add r2,sp,#16 784 785# qhasm: y0 aligned= mem128[ptr] 786# asm 1: vld1.8 {>y0=reg128#1%bot->y0=reg128#1%top},[<ptr=int32#3,: 128] 787# asm 2: vld1.8 {>y0=d0->y0=d1},[<ptr=r2,: 128] 788vld1.8 {d0-d1},[r2,: 128] 789 790# qhasm: r4[0,1] += v01[0] unsigned* y34[2]; r4[2,3] += v01[1] unsigned* y34[3] 791# asm 1: vmlal.u32 <r4=reg128#16,<v01=reg128#11%bot,<y34=reg128#3%top 792# asm 2: vmlal.u32 <r4=q15,<v01=d20,<y34=d5 793vmlal.u32 q15,d20,d5 794 795# qhasm: r4[0,1] += v01[2] unsigned* y34[0]; r4[2,3] += v01[3] unsigned* y34[1] 796# asm 1: vmlal.u32 <r4=reg128#16,<v01=reg128#11%top,<y34=reg128#3%bot 797# asm 2: vmlal.u32 <r4=q15,<v01=d21,<y34=d4 798vmlal.u32 q15,d21,d4 799 800# qhasm: r4[0,1] += v23[0] unsigned* y12[2]; r4[2,3] += v23[1] unsigned* y12[3] 801# asm 1: vmlal.u32 <r4=reg128#16,<v23=reg128#10%bot,<y12=reg128#2%top 802# asm 2: vmlal.u32 <r4=q15,<v23=d18,<y12=d3 803vmlal.u32 q15,d18,d3 804 805# qhasm: r4[0,1] += v23[2] unsigned* y12[0]; r4[2,3] += v23[3] unsigned* y12[1] 806# asm 1: vmlal.u32 <r4=reg128#16,<v23=reg128#10%top,<y12=reg128#2%bot 807# asm 2: vmlal.u32 <r4=q15,<v23=d19,<y12=d2 808vmlal.u32 q15,d19,d2 809 810# qhasm: r4[0,1] += v4[0] unsigned* y0[0]; r4[2,3] += v4[1] unsigned* y0[1] 811# asm 1: vmlal.u32 <r4=reg128#16,<v4=reg128#4%bot,<y0=reg128#1%bot 812# asm 2: vmlal.u32 <r4=q15,<v4=d6,<y0=d0 813vmlal.u32 q15,d6,d0 814 815# qhasm: ptr = &5y34_stack 816# asm 1: lea >ptr=int32#3,<5y34_stack=stack128#6 817# asm 2: lea >ptr=r2,<5y34_stack=[sp,#80] 818add r2,sp,#80 819 820# qhasm: 5y34 aligned= mem128[ptr] 821# asm 1: vld1.8 {>5y34=reg128#13%bot->5y34=reg128#13%top},[<ptr=int32#3,: 128] 822# asm 2: vld1.8 {>5y34=d24->5y34=d25},[<ptr=r2,: 128] 823vld1.8 {d24-d25},[r2,: 128] 824 825# qhasm: r3[0,1] += v01[0] unsigned* y34[0]; r3[2,3] += v01[1] unsigned* y34[1] 826# asm 1: vmlal.u32 <r3=reg128#5,<v01=reg128#11%bot,<y34=reg128#3%bot 827# asm 2: vmlal.u32 <r3=q4,<v01=d20,<y34=d4 828vmlal.u32 q4,d20,d4 829 830# qhasm: r3[0,1] += v01[2] unsigned* y12[2]; r3[2,3] += v01[3] unsigned* y12[3] 831# asm 1: vmlal.u32 <r3=reg128#5,<v01=reg128#11%top,<y12=reg128#2%top 832# asm 2: vmlal.u32 <r3=q4,<v01=d21,<y12=d3 833vmlal.u32 q4,d21,d3 834 835# qhasm: r3[0,1] += v23[0] unsigned* y12[0]; r3[2,3] += v23[1] unsigned* y12[1] 836# asm 1: vmlal.u32 <r3=reg128#5,<v23=reg128#10%bot,<y12=reg128#2%bot 837# asm 2: vmlal.u32 <r3=q4,<v23=d18,<y12=d2 838vmlal.u32 q4,d18,d2 839 840# qhasm: r3[0,1] += v23[2] unsigned* y0[0]; r3[2,3] += v23[3] unsigned* y0[1] 841# asm 1: vmlal.u32 <r3=reg128#5,<v23=reg128#10%top,<y0=reg128#1%bot 842# asm 2: vmlal.u32 <r3=q4,<v23=d19,<y0=d0 843vmlal.u32 q4,d19,d0 844 845# qhasm: r3[0,1] += v4[0] unsigned* 5y34[2]; r3[2,3] += v4[1] unsigned* 5y34[3] 846# asm 1: vmlal.u32 <r3=reg128#5,<v4=reg128#4%bot,<5y34=reg128#13%top 847# asm 2: vmlal.u32 <r3=q4,<v4=d6,<5y34=d25 848vmlal.u32 q4,d6,d25 849 850# qhasm: ptr = &5y12_stack 851# asm 1: lea >ptr=int32#3,<5y12_stack=stack128#5 852# asm 2: lea >ptr=r2,<5y12_stack=[sp,#64] 853add r2,sp,#64 854 855# qhasm: 5y12 aligned= mem128[ptr] 856# asm 1: vld1.8 {>5y12=reg128#12%bot->5y12=reg128#12%top},[<ptr=int32#3,: 128] 857# asm 2: vld1.8 {>5y12=d22->5y12=d23},[<ptr=r2,: 128] 858vld1.8 {d22-d23},[r2,: 128] 859 860# qhasm: r0[0,1] += v4[0] unsigned* 5y12[0]; r0[2,3] += v4[1] unsigned* 5y12[1] 861# asm 1: vmlal.u32 <r0=reg128#8,<v4=reg128#4%bot,<5y12=reg128#12%bot 862# asm 2: vmlal.u32 <r0=q7,<v4=d6,<5y12=d22 863vmlal.u32 q7,d6,d22 864 865# qhasm: r0[0,1] += v23[0] unsigned* 5y34[0]; r0[2,3] += v23[1] unsigned* 5y34[1] 866# asm 1: vmlal.u32 <r0=reg128#8,<v23=reg128#10%bot,<5y34=reg128#13%bot 867# asm 2: vmlal.u32 <r0=q7,<v23=d18,<5y34=d24 868vmlal.u32 q7,d18,d24 869 870# qhasm: r0[0,1] += v23[2] unsigned* 5y12[2]; r0[2,3] += v23[3] unsigned* 5y12[3] 871# asm 1: vmlal.u32 <r0=reg128#8,<v23=reg128#10%top,<5y12=reg128#12%top 872# asm 2: vmlal.u32 <r0=q7,<v23=d19,<5y12=d23 873vmlal.u32 q7,d19,d23 874 875# qhasm: r0[0,1] += v01[0] unsigned* y0[0]; r0[2,3] += v01[1] unsigned* y0[1] 876# asm 1: vmlal.u32 <r0=reg128#8,<v01=reg128#11%bot,<y0=reg128#1%bot 877# asm 2: vmlal.u32 <r0=q7,<v01=d20,<y0=d0 878vmlal.u32 q7,d20,d0 879 880# qhasm: r0[0,1] += v01[2] unsigned* 5y34[2]; r0[2,3] += v01[3] unsigned* 5y34[3] 881# asm 1: vmlal.u32 <r0=reg128#8,<v01=reg128#11%top,<5y34=reg128#13%top 882# asm 2: vmlal.u32 <r0=q7,<v01=d21,<5y34=d25 883vmlal.u32 q7,d21,d25 884 885# qhasm: r1[0,1] += v01[0] unsigned* y12[0]; r1[2,3] += v01[1] unsigned* y12[1] 886# asm 1: vmlal.u32 <r1=reg128#15,<v01=reg128#11%bot,<y12=reg128#2%bot 887# asm 2: vmlal.u32 <r1=q14,<v01=d20,<y12=d2 888vmlal.u32 q14,d20,d2 889 890# qhasm: r1[0,1] += v01[2] unsigned* y0[0]; r1[2,3] += v01[3] unsigned* y0[1] 891# asm 1: vmlal.u32 <r1=reg128#15,<v01=reg128#11%top,<y0=reg128#1%bot 892# asm 2: vmlal.u32 <r1=q14,<v01=d21,<y0=d0 893vmlal.u32 q14,d21,d0 894 895# qhasm: r1[0,1] += v23[0] unsigned* 5y34[2]; r1[2,3] += v23[1] unsigned* 5y34[3] 896# asm 1: vmlal.u32 <r1=reg128#15,<v23=reg128#10%bot,<5y34=reg128#13%top 897# asm 2: vmlal.u32 <r1=q14,<v23=d18,<5y34=d25 898vmlal.u32 q14,d18,d25 899 900# qhasm: r1[0,1] += v23[2] unsigned* 5y34[0]; r1[2,3] += v23[3] unsigned* 5y34[1] 901# asm 1: vmlal.u32 <r1=reg128#15,<v23=reg128#10%top,<5y34=reg128#13%bot 902# asm 2: vmlal.u32 <r1=q14,<v23=d19,<5y34=d24 903vmlal.u32 q14,d19,d24 904 905# qhasm: r1[0,1] += v4[0] unsigned* 5y12[2]; r1[2,3] += v4[1] unsigned* 5y12[3] 906# asm 1: vmlal.u32 <r1=reg128#15,<v4=reg128#4%bot,<5y12=reg128#12%top 907# asm 2: vmlal.u32 <r1=q14,<v4=d6,<5y12=d23 908vmlal.u32 q14,d6,d23 909 910# qhasm: r2[0,1] += v01[0] unsigned* y12[2]; r2[2,3] += v01[1] unsigned* y12[3] 911# asm 1: vmlal.u32 <r2=reg128#14,<v01=reg128#11%bot,<y12=reg128#2%top 912# asm 2: vmlal.u32 <r2=q13,<v01=d20,<y12=d3 913vmlal.u32 q13,d20,d3 914 915# qhasm: r2[0,1] += v01[2] unsigned* y12[0]; r2[2,3] += v01[3] unsigned* y12[1] 916# asm 1: vmlal.u32 <r2=reg128#14,<v01=reg128#11%top,<y12=reg128#2%bot 917# asm 2: vmlal.u32 <r2=q13,<v01=d21,<y12=d2 918vmlal.u32 q13,d21,d2 919 920# qhasm: r2[0,1] += v23[0] unsigned* y0[0]; r2[2,3] += v23[1] unsigned* y0[1] 921# asm 1: vmlal.u32 <r2=reg128#14,<v23=reg128#10%bot,<y0=reg128#1%bot 922# asm 2: vmlal.u32 <r2=q13,<v23=d18,<y0=d0 923vmlal.u32 q13,d18,d0 924 925# qhasm: r2[0,1] += v23[2] unsigned* 5y34[2]; r2[2,3] += v23[3] unsigned* 5y34[3] 926# asm 1: vmlal.u32 <r2=reg128#14,<v23=reg128#10%top,<5y34=reg128#13%top 927# asm 2: vmlal.u32 <r2=q13,<v23=d19,<5y34=d25 928vmlal.u32 q13,d19,d25 929 930# qhasm: r2[0,1] += v4[0] unsigned* 5y34[0]; r2[2,3] += v4[1] unsigned* 5y34[1] 931# asm 1: vmlal.u32 <r2=reg128#14,<v4=reg128#4%bot,<5y34=reg128#13%bot 932# asm 2: vmlal.u32 <r2=q13,<v4=d6,<5y34=d24 933vmlal.u32 q13,d6,d24 934 935# qhasm: ptr = &two24 936# asm 1: lea >ptr=int32#3,<two24=stack128#1 937# asm 2: lea >ptr=r2,<two24=[sp,#0] 938add r2,sp,#0 939 940# qhasm: 2x t1 = r0 unsigned>> 26 941# asm 1: vshr.u64 >t1=reg128#4,<r0=reg128#8,#26 942# asm 2: vshr.u64 >t1=q3,<r0=q7,#26 943vshr.u64 q3,q7,#26 944 945# qhasm: len -= 64 946# asm 1: sub >len=int32#4,<len=int32#4,#64 947# asm 2: sub >len=r3,<len=r3,#64 948sub r3,r3,#64 949 950# qhasm: r0 &= mask 951# asm 1: vand >r0=reg128#6,<r0=reg128#8,<mask=reg128#7 952# asm 2: vand >r0=q5,<r0=q7,<mask=q6 953vand q5,q7,q6 954 955# qhasm: 2x r1 += t1 956# asm 1: vadd.i64 >r1=reg128#4,<r1=reg128#15,<t1=reg128#4 957# asm 2: vadd.i64 >r1=q3,<r1=q14,<t1=q3 958vadd.i64 q3,q14,q3 959 960# qhasm: 2x t4 = r3 unsigned>> 26 961# asm 1: vshr.u64 >t4=reg128#8,<r3=reg128#5,#26 962# asm 2: vshr.u64 >t4=q7,<r3=q4,#26 963vshr.u64 q7,q4,#26 964 965# qhasm: r3 &= mask 966# asm 1: vand >r3=reg128#5,<r3=reg128#5,<mask=reg128#7 967# asm 2: vand >r3=q4,<r3=q4,<mask=q6 968vand q4,q4,q6 969 970# qhasm: 2x x4 = r4 + t4 971# asm 1: vadd.i64 >x4=reg128#8,<r4=reg128#16,<t4=reg128#8 972# asm 2: vadd.i64 >x4=q7,<r4=q15,<t4=q7 973vadd.i64 q7,q15,q7 974 975# qhasm: r4 aligned= mem128[ptr] 976# asm 1: vld1.8 {>r4=reg128#16%bot->r4=reg128#16%top},[<ptr=int32#3,: 128] 977# asm 2: vld1.8 {>r4=d30->r4=d31},[<ptr=r2,: 128] 978vld1.8 {d30-d31},[r2,: 128] 979 980# qhasm: 2x t2 = r1 unsigned>> 26 981# asm 1: vshr.u64 >t2=reg128#9,<r1=reg128#4,#26 982# asm 2: vshr.u64 >t2=q8,<r1=q3,#26 983vshr.u64 q8,q3,#26 984 985# qhasm: r1 &= mask 986# asm 1: vand >r1=reg128#4,<r1=reg128#4,<mask=reg128#7 987# asm 2: vand >r1=q3,<r1=q3,<mask=q6 988vand q3,q3,q6 989 990# qhasm: 2x t0 = x4 unsigned>> 26 991# asm 1: vshr.u64 >t0=reg128#10,<x4=reg128#8,#26 992# asm 2: vshr.u64 >t0=q9,<x4=q7,#26 993vshr.u64 q9,q7,#26 994 995# qhasm: 2x r2 += t2 996# asm 1: vadd.i64 >r2=reg128#9,<r2=reg128#14,<t2=reg128#9 997# asm 2: vadd.i64 >r2=q8,<r2=q13,<t2=q8 998vadd.i64 q8,q13,q8 999 1000# qhasm: x4 &= mask 1001# asm 1: vand >x4=reg128#11,<x4=reg128#8,<mask=reg128#7 1002# asm 2: vand >x4=q10,<x4=q7,<mask=q6 1003vand q10,q7,q6 1004 1005# qhasm: 2x x01 = r0 + t0 1006# asm 1: vadd.i64 >x01=reg128#6,<r0=reg128#6,<t0=reg128#10 1007# asm 2: vadd.i64 >x01=q5,<r0=q5,<t0=q9 1008vadd.i64 q5,q5,q9 1009 1010# qhasm: r0 aligned= mem128[ptr] 1011# asm 1: vld1.8 {>r0=reg128#8%bot->r0=reg128#8%top},[<ptr=int32#3,: 128] 1012# asm 2: vld1.8 {>r0=d14->r0=d15},[<ptr=r2,: 128] 1013vld1.8 {d14-d15},[r2,: 128] 1014 1015# qhasm: ptr = &z34_stack 1016# asm 1: lea >ptr=int32#3,<z34_stack=stack128#9 1017# asm 2: lea >ptr=r2,<z34_stack=[sp,#128] 1018add r2,sp,#128 1019 1020# qhasm: 2x t0 <<= 2 1021# asm 1: vshl.i64 >t0=reg128#10,<t0=reg128#10,#2 1022# asm 2: vshl.i64 >t0=q9,<t0=q9,#2 1023vshl.i64 q9,q9,#2 1024 1025# qhasm: 2x t3 = r2 unsigned>> 26 1026# asm 1: vshr.u64 >t3=reg128#14,<r2=reg128#9,#26 1027# asm 2: vshr.u64 >t3=q13,<r2=q8,#26 1028vshr.u64 q13,q8,#26 1029 1030# qhasm: 2x x01 += t0 1031# asm 1: vadd.i64 >x01=reg128#15,<x01=reg128#6,<t0=reg128#10 1032# asm 2: vadd.i64 >x01=q14,<x01=q5,<t0=q9 1033vadd.i64 q14,q5,q9 1034 1035# qhasm: z34 aligned= mem128[ptr] 1036# asm 1: vld1.8 {>z34=reg128#6%bot->z34=reg128#6%top},[<ptr=int32#3,: 128] 1037# asm 2: vld1.8 {>z34=d10->z34=d11},[<ptr=r2,: 128] 1038vld1.8 {d10-d11},[r2,: 128] 1039 1040# qhasm: x23 = r2 & mask 1041# asm 1: vand >x23=reg128#10,<r2=reg128#9,<mask=reg128#7 1042# asm 2: vand >x23=q9,<r2=q8,<mask=q6 1043vand q9,q8,q6 1044 1045# qhasm: 2x r3 += t3 1046# asm 1: vadd.i64 >r3=reg128#5,<r3=reg128#5,<t3=reg128#14 1047# asm 2: vadd.i64 >r3=q4,<r3=q4,<t3=q13 1048vadd.i64 q4,q4,q13 1049 1050# qhasm: input_2 += 32 1051# asm 1: add >input_2=int32#2,<input_2=int32#2,#32 1052# asm 2: add >input_2=r1,<input_2=r1,#32 1053add r1,r1,#32 1054 1055# qhasm: 2x t1 = x01 unsigned>> 26 1056# asm 1: vshr.u64 >t1=reg128#14,<x01=reg128#15,#26 1057# asm 2: vshr.u64 >t1=q13,<x01=q14,#26 1058vshr.u64 q13,q14,#26 1059 1060# qhasm: x23 = x23[0,2,1,3] 1061# asm 1: vtrn.32 <x23=reg128#10%bot,<x23=reg128#10%top 1062# asm 2: vtrn.32 <x23=d18,<x23=d19 1063vtrn.32 d18,d19 1064 1065# qhasm: x01 = x01 & mask 1066# asm 1: vand >x01=reg128#9,<x01=reg128#15,<mask=reg128#7 1067# asm 2: vand >x01=q8,<x01=q14,<mask=q6 1068vand q8,q14,q6 1069 1070# qhasm: 2x r1 += t1 1071# asm 1: vadd.i64 >r1=reg128#4,<r1=reg128#4,<t1=reg128#14 1072# asm 2: vadd.i64 >r1=q3,<r1=q3,<t1=q13 1073vadd.i64 q3,q3,q13 1074 1075# qhasm: 2x t4 = r3 unsigned>> 26 1076# asm 1: vshr.u64 >t4=reg128#14,<r3=reg128#5,#26 1077# asm 2: vshr.u64 >t4=q13,<r3=q4,#26 1078vshr.u64 q13,q4,#26 1079 1080# qhasm: x01 = x01[0,2,1,3] 1081# asm 1: vtrn.32 <x01=reg128#9%bot,<x01=reg128#9%top 1082# asm 2: vtrn.32 <x01=d16,<x01=d17 1083vtrn.32 d16,d17 1084 1085# qhasm: r3 &= mask 1086# asm 1: vand >r3=reg128#5,<r3=reg128#5,<mask=reg128#7 1087# asm 2: vand >r3=q4,<r3=q4,<mask=q6 1088vand q4,q4,q6 1089 1090# qhasm: r1 = r1[0,2,1,3] 1091# asm 1: vtrn.32 <r1=reg128#4%bot,<r1=reg128#4%top 1092# asm 2: vtrn.32 <r1=d6,<r1=d7 1093vtrn.32 d6,d7 1094 1095# qhasm: 2x x4 += t4 1096# asm 1: vadd.i64 >x4=reg128#11,<x4=reg128#11,<t4=reg128#14 1097# asm 2: vadd.i64 >x4=q10,<x4=q10,<t4=q13 1098vadd.i64 q10,q10,q13 1099 1100# qhasm: r3 = r3[0,2,1,3] 1101# asm 1: vtrn.32 <r3=reg128#5%bot,<r3=reg128#5%top 1102# asm 2: vtrn.32 <r3=d8,<r3=d9 1103vtrn.32 d8,d9 1104 1105# qhasm: x01 = x01[0,1] r1[0,1] 1106# asm 1: vext.32 <x01=reg128#9%top,<r1=reg128#4%bot,<r1=reg128#4%bot,#0 1107# asm 2: vext.32 <x01=d17,<r1=d6,<r1=d6,#0 1108vext.32 d17,d6,d6,#0 1109 1110# qhasm: x23 = x23[0,1] r3[0,1] 1111# asm 1: vext.32 <x23=reg128#10%top,<r3=reg128#5%bot,<r3=reg128#5%bot,#0 1112# asm 2: vext.32 <x23=d19,<r3=d8,<r3=d8,#0 1113vext.32 d19,d8,d8,#0 1114 1115# qhasm: x4 = x4[0,2,1,3] 1116# asm 1: vtrn.32 <x4=reg128#11%bot,<x4=reg128#11%top 1117# asm 2: vtrn.32 <x4=d20,<x4=d21 1118vtrn.32 d20,d21 1119 1120# qhasm: unsigned>? len - 64 1121# asm 1: cmp <len=int32#4,#64 1122# asm 2: cmp <len=r3,#64 1123cmp r3,#64 1124 1125# qhasm: goto mainloop2 if unsigned> 1126bhi ._mainloop2 1127 1128# qhasm: input_2 -= 32 1129# asm 1: sub >input_2=int32#3,<input_2=int32#2,#32 1130# asm 2: sub >input_2=r2,<input_2=r1,#32 1131sub r2,r1,#32 1132 1133# qhasm: below64bytes: 1134._below64bytes: 1135 1136# qhasm: unsigned>? len - 32 1137# asm 1: cmp <len=int32#4,#32 1138# asm 2: cmp <len=r3,#32 1139cmp r3,#32 1140 1141# qhasm: goto end if !unsigned> 1142bls ._end 1143 1144# qhasm: mainloop: 1145._mainloop: 1146 1147# qhasm: new r0 1148 1149# qhasm: ptr = &two24 1150# asm 1: lea >ptr=int32#2,<two24=stack128#1 1151# asm 2: lea >ptr=r1,<two24=[sp,#0] 1152add r1,sp,#0 1153 1154# qhasm: r4 aligned= mem128[ptr] 1155# asm 1: vld1.8 {>r4=reg128#5%bot->r4=reg128#5%top},[<ptr=int32#2,: 128] 1156# asm 2: vld1.8 {>r4=d8->r4=d9},[<ptr=r1,: 128] 1157vld1.8 {d8-d9},[r1,: 128] 1158 1159# qhasm: u4 aligned= mem128[ptr] 1160# asm 1: vld1.8 {>u4=reg128#6%bot->u4=reg128#6%top},[<ptr=int32#2,: 128] 1161# asm 2: vld1.8 {>u4=d10->u4=d11},[<ptr=r1,: 128] 1162vld1.8 {d10-d11},[r1,: 128] 1163 1164# qhasm: c01 = mem128[input_2];input_2+=16 1165# asm 1: vld1.8 {>c01=reg128#8%bot->c01=reg128#8%top},[<input_2=int32#3]! 1166# asm 2: vld1.8 {>c01=d14->c01=d15},[<input_2=r2]! 1167vld1.8 {d14-d15},[r2]! 1168 1169# qhasm: r4[0,1] += x01[0] unsigned* y34[2]; r4[2,3] += x01[1] unsigned* y34[3] 1170# asm 1: vmlal.u32 <r4=reg128#5,<x01=reg128#9%bot,<y34=reg128#3%top 1171# asm 2: vmlal.u32 <r4=q4,<x01=d16,<y34=d5 1172vmlal.u32 q4,d16,d5 1173 1174# qhasm: c23 = mem128[input_2];input_2+=16 1175# asm 1: vld1.8 {>c23=reg128#14%bot->c23=reg128#14%top},[<input_2=int32#3]! 1176# asm 2: vld1.8 {>c23=d26->c23=d27},[<input_2=r2]! 1177vld1.8 {d26-d27},[r2]! 1178 1179# qhasm: r4[0,1] += x01[2] unsigned* y34[0]; r4[2,3] += x01[3] unsigned* y34[1] 1180# asm 1: vmlal.u32 <r4=reg128#5,<x01=reg128#9%top,<y34=reg128#3%bot 1181# asm 2: vmlal.u32 <r4=q4,<x01=d17,<y34=d4 1182vmlal.u32 q4,d17,d4 1183 1184# qhasm: r0 = u4[1]c01[0]r0[2,3] 1185# asm 1: vext.32 <r0=reg128#4%bot,<u4=reg128#6%bot,<c01=reg128#8%bot,#1 1186# asm 2: vext.32 <r0=d6,<u4=d10,<c01=d14,#1 1187vext.32 d6,d10,d14,#1 1188 1189# qhasm: r4[0,1] += x23[0] unsigned* y12[2]; r4[2,3] += x23[1] unsigned* y12[3] 1190# asm 1: vmlal.u32 <r4=reg128#5,<x23=reg128#10%bot,<y12=reg128#2%top 1191# asm 2: vmlal.u32 <r4=q4,<x23=d18,<y12=d3 1192vmlal.u32 q4,d18,d3 1193 1194# qhasm: r0 = r0[0,1]u4[1]c23[0] 1195# asm 1: vext.32 <r0=reg128#4%top,<u4=reg128#6%bot,<c23=reg128#14%bot,#1 1196# asm 2: vext.32 <r0=d7,<u4=d10,<c23=d26,#1 1197vext.32 d7,d10,d26,#1 1198 1199# qhasm: r4[0,1] += x23[2] unsigned* y12[0]; r4[2,3] += x23[3] unsigned* y12[1] 1200# asm 1: vmlal.u32 <r4=reg128#5,<x23=reg128#10%top,<y12=reg128#2%bot 1201# asm 2: vmlal.u32 <r4=q4,<x23=d19,<y12=d2 1202vmlal.u32 q4,d19,d2 1203 1204# qhasm: r0 = r0[1]r0[0]r0[3]r0[2] 1205# asm 1: vrev64.i32 >r0=reg128#4,<r0=reg128#4 1206# asm 2: vrev64.i32 >r0=q3,<r0=q3 1207vrev64.i32 q3,q3 1208 1209# qhasm: r4[0,1] += x4[0] unsigned* y0[0]; r4[2,3] += x4[1] unsigned* y0[1] 1210# asm 1: vmlal.u32 <r4=reg128#5,<x4=reg128#11%bot,<y0=reg128#1%bot 1211# asm 2: vmlal.u32 <r4=q4,<x4=d20,<y0=d0 1212vmlal.u32 q4,d20,d0 1213 1214# qhasm: r0[0,1] += x4[0] unsigned* 5y12[0]; r0[2,3] += x4[1] unsigned* 5y12[1] 1215# asm 1: vmlal.u32 <r0=reg128#4,<x4=reg128#11%bot,<5y12=reg128#12%bot 1216# asm 2: vmlal.u32 <r0=q3,<x4=d20,<5y12=d22 1217vmlal.u32 q3,d20,d22 1218 1219# qhasm: r0[0,1] += x23[0] unsigned* 5y34[0]; r0[2,3] += x23[1] unsigned* 5y34[1] 1220# asm 1: vmlal.u32 <r0=reg128#4,<x23=reg128#10%bot,<5y34=reg128#13%bot 1221# asm 2: vmlal.u32 <r0=q3,<x23=d18,<5y34=d24 1222vmlal.u32 q3,d18,d24 1223 1224# qhasm: r0[0,1] += x23[2] unsigned* 5y12[2]; r0[2,3] += x23[3] unsigned* 5y12[3] 1225# asm 1: vmlal.u32 <r0=reg128#4,<x23=reg128#10%top,<5y12=reg128#12%top 1226# asm 2: vmlal.u32 <r0=q3,<x23=d19,<5y12=d23 1227vmlal.u32 q3,d19,d23 1228 1229# qhasm: c01 c23 = c01[0]c23[0]c01[2]c23[2]c01[1]c23[1]c01[3]c23[3] 1230# asm 1: vtrn.32 <c01=reg128#8,<c23=reg128#14 1231# asm 2: vtrn.32 <c01=q7,<c23=q13 1232vtrn.32 q7,q13 1233 1234# qhasm: r0[0,1] += x01[0] unsigned* y0[0]; r0[2,3] += x01[1] unsigned* y0[1] 1235# asm 1: vmlal.u32 <r0=reg128#4,<x01=reg128#9%bot,<y0=reg128#1%bot 1236# asm 2: vmlal.u32 <r0=q3,<x01=d16,<y0=d0 1237vmlal.u32 q3,d16,d0 1238 1239# qhasm: r3[0,1] = c23[2]<<18; r3[2,3] = c23[3]<<18 1240# asm 1: vshll.u32 >r3=reg128#6,<c23=reg128#14%top,#18 1241# asm 2: vshll.u32 >r3=q5,<c23=d27,#18 1242vshll.u32 q5,d27,#18 1243 1244# qhasm: r0[0,1] += x01[2] unsigned* 5y34[2]; r0[2,3] += x01[3] unsigned* 5y34[3] 1245# asm 1: vmlal.u32 <r0=reg128#4,<x01=reg128#9%top,<5y34=reg128#13%top 1246# asm 2: vmlal.u32 <r0=q3,<x01=d17,<5y34=d25 1247vmlal.u32 q3,d17,d25 1248 1249# qhasm: r3[0,1] += x01[0] unsigned* y34[0]; r3[2,3] += x01[1] unsigned* y34[1] 1250# asm 1: vmlal.u32 <r3=reg128#6,<x01=reg128#9%bot,<y34=reg128#3%bot 1251# asm 2: vmlal.u32 <r3=q5,<x01=d16,<y34=d4 1252vmlal.u32 q5,d16,d4 1253 1254# qhasm: r3[0,1] += x01[2] unsigned* y12[2]; r3[2,3] += x01[3] unsigned* y12[3] 1255# asm 1: vmlal.u32 <r3=reg128#6,<x01=reg128#9%top,<y12=reg128#2%top 1256# asm 2: vmlal.u32 <r3=q5,<x01=d17,<y12=d3 1257vmlal.u32 q5,d17,d3 1258 1259# qhasm: r3[0,1] += x23[0] unsigned* y12[0]; r3[2,3] += x23[1] unsigned* y12[1] 1260# asm 1: vmlal.u32 <r3=reg128#6,<x23=reg128#10%bot,<y12=reg128#2%bot 1261# asm 2: vmlal.u32 <r3=q5,<x23=d18,<y12=d2 1262vmlal.u32 q5,d18,d2 1263 1264# qhasm: r3[0,1] += x23[2] unsigned* y0[0]; r3[2,3] += x23[3] unsigned* y0[1] 1265# asm 1: vmlal.u32 <r3=reg128#6,<x23=reg128#10%top,<y0=reg128#1%bot 1266# asm 2: vmlal.u32 <r3=q5,<x23=d19,<y0=d0 1267vmlal.u32 q5,d19,d0 1268 1269# qhasm: r1[0,1] = c23[0]<<6; r1[2,3] = c23[1]<<6 1270# asm 1: vshll.u32 >r1=reg128#14,<c23=reg128#14%bot,#6 1271# asm 2: vshll.u32 >r1=q13,<c23=d26,#6 1272vshll.u32 q13,d26,#6 1273 1274# qhasm: r3[0,1] += x4[0] unsigned* 5y34[2]; r3[2,3] += x4[1] unsigned* 5y34[3] 1275# asm 1: vmlal.u32 <r3=reg128#6,<x4=reg128#11%bot,<5y34=reg128#13%top 1276# asm 2: vmlal.u32 <r3=q5,<x4=d20,<5y34=d25 1277vmlal.u32 q5,d20,d25 1278 1279# qhasm: r1[0,1] += x01[0] unsigned* y12[0]; r1[2,3] += x01[1] unsigned* y12[1] 1280# asm 1: vmlal.u32 <r1=reg128#14,<x01=reg128#9%bot,<y12=reg128#2%bot 1281# asm 2: vmlal.u32 <r1=q13,<x01=d16,<y12=d2 1282vmlal.u32 q13,d16,d2 1283 1284# qhasm: r1[0,1] += x01[2] unsigned* y0[0]; r1[2,3] += x01[3] unsigned* y0[1] 1285# asm 1: vmlal.u32 <r1=reg128#14,<x01=reg128#9%top,<y0=reg128#1%bot 1286# asm 2: vmlal.u32 <r1=q13,<x01=d17,<y0=d0 1287vmlal.u32 q13,d17,d0 1288 1289# qhasm: r1[0,1] += x23[0] unsigned* 5y34[2]; r1[2,3] += x23[1] unsigned* 5y34[3] 1290# asm 1: vmlal.u32 <r1=reg128#14,<x23=reg128#10%bot,<5y34=reg128#13%top 1291# asm 2: vmlal.u32 <r1=q13,<x23=d18,<5y34=d25 1292vmlal.u32 q13,d18,d25 1293 1294# qhasm: r1[0,1] += x23[2] unsigned* 5y34[0]; r1[2,3] += x23[3] unsigned* 5y34[1] 1295# asm 1: vmlal.u32 <r1=reg128#14,<x23=reg128#10%top,<5y34=reg128#13%bot 1296# asm 2: vmlal.u32 <r1=q13,<x23=d19,<5y34=d24 1297vmlal.u32 q13,d19,d24 1298 1299# qhasm: r2[0,1] = c01[2]<<12; r2[2,3] = c01[3]<<12 1300# asm 1: vshll.u32 >r2=reg128#8,<c01=reg128#8%top,#12 1301# asm 2: vshll.u32 >r2=q7,<c01=d15,#12 1302vshll.u32 q7,d15,#12 1303 1304# qhasm: r1[0,1] += x4[0] unsigned* 5y12[2]; r1[2,3] += x4[1] unsigned* 5y12[3] 1305# asm 1: vmlal.u32 <r1=reg128#14,<x4=reg128#11%bot,<5y12=reg128#12%top 1306# asm 2: vmlal.u32 <r1=q13,<x4=d20,<5y12=d23 1307vmlal.u32 q13,d20,d23 1308 1309# qhasm: r2[0,1] += x01[0] unsigned* y12[2]; r2[2,3] += x01[1] unsigned* y12[3] 1310# asm 1: vmlal.u32 <r2=reg128#8,<x01=reg128#9%bot,<y12=reg128#2%top 1311# asm 2: vmlal.u32 <r2=q7,<x01=d16,<y12=d3 1312vmlal.u32 q7,d16,d3 1313 1314# qhasm: r2[0,1] += x01[2] unsigned* y12[0]; r2[2,3] += x01[3] unsigned* y12[1] 1315# asm 1: vmlal.u32 <r2=reg128#8,<x01=reg128#9%top,<y12=reg128#2%bot 1316# asm 2: vmlal.u32 <r2=q7,<x01=d17,<y12=d2 1317vmlal.u32 q7,d17,d2 1318 1319# qhasm: r2[0,1] += x23[0] unsigned* y0[0]; r2[2,3] += x23[1] unsigned* y0[1] 1320# asm 1: vmlal.u32 <r2=reg128#8,<x23=reg128#10%bot,<y0=reg128#1%bot 1321# asm 2: vmlal.u32 <r2=q7,<x23=d18,<y0=d0 1322vmlal.u32 q7,d18,d0 1323 1324# qhasm: r2[0,1] += x23[2] unsigned* 5y34[2]; r2[2,3] += x23[3] unsigned* 5y34[3] 1325# asm 1: vmlal.u32 <r2=reg128#8,<x23=reg128#10%top,<5y34=reg128#13%top 1326# asm 2: vmlal.u32 <r2=q7,<x23=d19,<5y34=d25 1327vmlal.u32 q7,d19,d25 1328 1329# qhasm: r2[0,1] += x4[0] unsigned* 5y34[0]; r2[2,3] += x4[1] unsigned* 5y34[1] 1330# asm 1: vmlal.u32 <r2=reg128#8,<x4=reg128#11%bot,<5y34=reg128#13%bot 1331# asm 2: vmlal.u32 <r2=q7,<x4=d20,<5y34=d24 1332vmlal.u32 q7,d20,d24 1333 1334# qhasm: 2x t1 = r0 unsigned>> 26 1335# asm 1: vshr.u64 >t1=reg128#9,<r0=reg128#4,#26 1336# asm 2: vshr.u64 >t1=q8,<r0=q3,#26 1337vshr.u64 q8,q3,#26 1338 1339# qhasm: r0 &= mask 1340# asm 1: vand >r0=reg128#4,<r0=reg128#4,<mask=reg128#7 1341# asm 2: vand >r0=q3,<r0=q3,<mask=q6 1342vand q3,q3,q6 1343 1344# qhasm: 2x r1 += t1 1345# asm 1: vadd.i64 >r1=reg128#9,<r1=reg128#14,<t1=reg128#9 1346# asm 2: vadd.i64 >r1=q8,<r1=q13,<t1=q8 1347vadd.i64 q8,q13,q8 1348 1349# qhasm: 2x t4 = r3 unsigned>> 26 1350# asm 1: vshr.u64 >t4=reg128#10,<r3=reg128#6,#26 1351# asm 2: vshr.u64 >t4=q9,<r3=q5,#26 1352vshr.u64 q9,q5,#26 1353 1354# qhasm: r3 &= mask 1355# asm 1: vand >r3=reg128#6,<r3=reg128#6,<mask=reg128#7 1356# asm 2: vand >r3=q5,<r3=q5,<mask=q6 1357vand q5,q5,q6 1358 1359# qhasm: 2x r4 += t4 1360# asm 1: vadd.i64 >r4=reg128#5,<r4=reg128#5,<t4=reg128#10 1361# asm 2: vadd.i64 >r4=q4,<r4=q4,<t4=q9 1362vadd.i64 q4,q4,q9 1363 1364# qhasm: 2x t2 = r1 unsigned>> 26 1365# asm 1: vshr.u64 >t2=reg128#10,<r1=reg128#9,#26 1366# asm 2: vshr.u64 >t2=q9,<r1=q8,#26 1367vshr.u64 q9,q8,#26 1368 1369# qhasm: r1 &= mask 1370# asm 1: vand >r1=reg128#11,<r1=reg128#9,<mask=reg128#7 1371# asm 2: vand >r1=q10,<r1=q8,<mask=q6 1372vand q10,q8,q6 1373 1374# qhasm: 2x t0 = r4 unsigned>> 26 1375# asm 1: vshr.u64 >t0=reg128#9,<r4=reg128#5,#26 1376# asm 2: vshr.u64 >t0=q8,<r4=q4,#26 1377vshr.u64 q8,q4,#26 1378 1379# qhasm: 2x r2 += t2 1380# asm 1: vadd.i64 >r2=reg128#8,<r2=reg128#8,<t2=reg128#10 1381# asm 2: vadd.i64 >r2=q7,<r2=q7,<t2=q9 1382vadd.i64 q7,q7,q9 1383 1384# qhasm: r4 &= mask 1385# asm 1: vand >r4=reg128#5,<r4=reg128#5,<mask=reg128#7 1386# asm 2: vand >r4=q4,<r4=q4,<mask=q6 1387vand q4,q4,q6 1388 1389# qhasm: 2x r0 += t0 1390# asm 1: vadd.i64 >r0=reg128#4,<r0=reg128#4,<t0=reg128#9 1391# asm 2: vadd.i64 >r0=q3,<r0=q3,<t0=q8 1392vadd.i64 q3,q3,q8 1393 1394# qhasm: 2x t0 <<= 2 1395# asm 1: vshl.i64 >t0=reg128#9,<t0=reg128#9,#2 1396# asm 2: vshl.i64 >t0=q8,<t0=q8,#2 1397vshl.i64 q8,q8,#2 1398 1399# qhasm: 2x t3 = r2 unsigned>> 26 1400# asm 1: vshr.u64 >t3=reg128#14,<r2=reg128#8,#26 1401# asm 2: vshr.u64 >t3=q13,<r2=q7,#26 1402vshr.u64 q13,q7,#26 1403 1404# qhasm: 2x r0 += t0 1405# asm 1: vadd.i64 >r0=reg128#4,<r0=reg128#4,<t0=reg128#9 1406# asm 2: vadd.i64 >r0=q3,<r0=q3,<t0=q8 1407vadd.i64 q3,q3,q8 1408 1409# qhasm: x23 = r2 & mask 1410# asm 1: vand >x23=reg128#10,<r2=reg128#8,<mask=reg128#7 1411# asm 2: vand >x23=q9,<r2=q7,<mask=q6 1412vand q9,q7,q6 1413 1414# qhasm: 2x r3 += t3 1415# asm 1: vadd.i64 >r3=reg128#6,<r3=reg128#6,<t3=reg128#14 1416# asm 2: vadd.i64 >r3=q5,<r3=q5,<t3=q13 1417vadd.i64 q5,q5,q13 1418 1419# qhasm: 2x t1 = r0 unsigned>> 26 1420# asm 1: vshr.u64 >t1=reg128#8,<r0=reg128#4,#26 1421# asm 2: vshr.u64 >t1=q7,<r0=q3,#26 1422vshr.u64 q7,q3,#26 1423 1424# qhasm: x01 = r0 & mask 1425# asm 1: vand >x01=reg128#9,<r0=reg128#4,<mask=reg128#7 1426# asm 2: vand >x01=q8,<r0=q3,<mask=q6 1427vand q8,q3,q6 1428 1429# qhasm: 2x r1 += t1 1430# asm 1: vadd.i64 >r1=reg128#4,<r1=reg128#11,<t1=reg128#8 1431# asm 2: vadd.i64 >r1=q3,<r1=q10,<t1=q7 1432vadd.i64 q3,q10,q7 1433 1434# qhasm: 2x t4 = r3 unsigned>> 26 1435# asm 1: vshr.u64 >t4=reg128#8,<r3=reg128#6,#26 1436# asm 2: vshr.u64 >t4=q7,<r3=q5,#26 1437vshr.u64 q7,q5,#26 1438 1439# qhasm: r3 &= mask 1440# asm 1: vand >r3=reg128#6,<r3=reg128#6,<mask=reg128#7 1441# asm 2: vand >r3=q5,<r3=q5,<mask=q6 1442vand q5,q5,q6 1443 1444# qhasm: 2x x4 = r4 + t4 1445# asm 1: vadd.i64 >x4=reg128#11,<r4=reg128#5,<t4=reg128#8 1446# asm 2: vadd.i64 >x4=q10,<r4=q4,<t4=q7 1447vadd.i64 q10,q4,q7 1448 1449# qhasm: len -= 32 1450# asm 1: sub >len=int32#4,<len=int32#4,#32 1451# asm 2: sub >len=r3,<len=r3,#32 1452sub r3,r3,#32 1453 1454# qhasm: x01 = x01[0,2,1,3] 1455# asm 1: vtrn.32 <x01=reg128#9%bot,<x01=reg128#9%top 1456# asm 2: vtrn.32 <x01=d16,<x01=d17 1457vtrn.32 d16,d17 1458 1459# qhasm: x23 = x23[0,2,1,3] 1460# asm 1: vtrn.32 <x23=reg128#10%bot,<x23=reg128#10%top 1461# asm 2: vtrn.32 <x23=d18,<x23=d19 1462vtrn.32 d18,d19 1463 1464# qhasm: r1 = r1[0,2,1,3] 1465# asm 1: vtrn.32 <r1=reg128#4%bot,<r1=reg128#4%top 1466# asm 2: vtrn.32 <r1=d6,<r1=d7 1467vtrn.32 d6,d7 1468 1469# qhasm: r3 = r3[0,2,1,3] 1470# asm 1: vtrn.32 <r3=reg128#6%bot,<r3=reg128#6%top 1471# asm 2: vtrn.32 <r3=d10,<r3=d11 1472vtrn.32 d10,d11 1473 1474# qhasm: x4 = x4[0,2,1,3] 1475# asm 1: vtrn.32 <x4=reg128#11%bot,<x4=reg128#11%top 1476# asm 2: vtrn.32 <x4=d20,<x4=d21 1477vtrn.32 d20,d21 1478 1479# qhasm: x01 = x01[0,1] r1[0,1] 1480# asm 1: vext.32 <x01=reg128#9%top,<r1=reg128#4%bot,<r1=reg128#4%bot,#0 1481# asm 2: vext.32 <x01=d17,<r1=d6,<r1=d6,#0 1482vext.32 d17,d6,d6,#0 1483 1484# qhasm: x23 = x23[0,1] r3[0,1] 1485# asm 1: vext.32 <x23=reg128#10%top,<r3=reg128#6%bot,<r3=reg128#6%bot,#0 1486# asm 2: vext.32 <x23=d19,<r3=d10,<r3=d10,#0 1487vext.32 d19,d10,d10,#0 1488 1489# qhasm: unsigned>? len - 32 1490# asm 1: cmp <len=int32#4,#32 1491# asm 2: cmp <len=r3,#32 1492cmp r3,#32 1493 1494# qhasm: goto mainloop if unsigned> 1495bhi ._mainloop 1496 1497# qhasm: end: 1498._end: 1499 1500# qhasm: mem128[input_0] = x01;input_0+=16 1501# asm 1: vst1.8 {<x01=reg128#9%bot-<x01=reg128#9%top},[<input_0=int32#1]! 1502# asm 2: vst1.8 {<x01=d16-<x01=d17},[<input_0=r0]! 1503vst1.8 {d16-d17},[r0]! 1504 1505# qhasm: mem128[input_0] = x23;input_0+=16 1506# asm 1: vst1.8 {<x23=reg128#10%bot-<x23=reg128#10%top},[<input_0=int32#1]! 1507# asm 2: vst1.8 {<x23=d18-<x23=d19},[<input_0=r0]! 1508vst1.8 {d18-d19},[r0]! 1509 1510# qhasm: mem64[input_0] = x4[0] 1511# asm 1: vst1.8 <x4=reg128#11%bot,[<input_0=int32#1] 1512# asm 2: vst1.8 <x4=d20,[<input_0=r0] 1513vst1.8 d20,[r0] 1514 1515# qhasm: len = len 1516# asm 1: mov >len=int32#1,<len=int32#4 1517# asm 2: mov >len=r0,<len=r3 1518mov r0,r3 1519 1520# qhasm: qpopreturn len 1521mov sp,r12 1522vpop {q4,q5,q6,q7} 1523bx lr 1524 1525# qhasm: int32 input_0 1526 1527# qhasm: int32 input_1 1528 1529# qhasm: int32 input_2 1530 1531# qhasm: int32 input_3 1532 1533# qhasm: stack32 input_4 1534 1535# qhasm: stack32 input_5 1536 1537# qhasm: stack32 input_6 1538 1539# qhasm: stack32 input_7 1540 1541# qhasm: int32 caller_r4 1542 1543# qhasm: int32 caller_r5 1544 1545# qhasm: int32 caller_r6 1546 1547# qhasm: int32 caller_r7 1548 1549# qhasm: int32 caller_r8 1550 1551# qhasm: int32 caller_r9 1552 1553# qhasm: int32 caller_r10 1554 1555# qhasm: int32 caller_r11 1556 1557# qhasm: int32 caller_r12 1558 1559# qhasm: int32 caller_r14 1560 1561# qhasm: reg128 caller_q4 1562 1563# qhasm: reg128 caller_q5 1564 1565# qhasm: reg128 caller_q6 1566 1567# qhasm: reg128 caller_q7 1568 1569# qhasm: reg128 r0 1570 1571# qhasm: reg128 r1 1572 1573# qhasm: reg128 r2 1574 1575# qhasm: reg128 r3 1576 1577# qhasm: reg128 r4 1578 1579# qhasm: reg128 x01 1580 1581# qhasm: reg128 x23 1582 1583# qhasm: reg128 x4 1584 1585# qhasm: reg128 y01 1586 1587# qhasm: reg128 y23 1588 1589# qhasm: reg128 y4 1590 1591# qhasm: reg128 _5y01 1592 1593# qhasm: reg128 _5y23 1594 1595# qhasm: reg128 _5y4 1596 1597# qhasm: reg128 c01 1598 1599# qhasm: reg128 c23 1600 1601# qhasm: reg128 c4 1602 1603# qhasm: reg128 t0 1604 1605# qhasm: reg128 t1 1606 1607# qhasm: reg128 t2 1608 1609# qhasm: reg128 t3 1610 1611# qhasm: reg128 t4 1612 1613# qhasm: reg128 mask 1614 1615# qhasm: enter crypto_onetimeauth_poly1305_neon2_addmulmod 1616.align 2 1617.global openssl_poly1305_neon2_addmulmod 1618.hidden openssl_poly1305_neon2_addmulmod 1619.type openssl_poly1305_neon2_addmulmod STT_FUNC 1620openssl_poly1305_neon2_addmulmod: 1621sub sp,sp,#0 1622 1623# qhasm: 2x mask = 0xffffffff 1624# asm 1: vmov.i64 >mask=reg128#1,#0xffffffff 1625# asm 2: vmov.i64 >mask=q0,#0xffffffff 1626vmov.i64 q0,#0xffffffff 1627 1628# qhasm: y01 aligned= mem128[input_2];input_2+=16 1629# asm 1: vld1.8 {>y01=reg128#2%bot->y01=reg128#2%top},[<input_2=int32#3,: 128]! 1630# asm 2: vld1.8 {>y01=d2->y01=d3},[<input_2=r2,: 128]! 1631vld1.8 {d2-d3},[r2,: 128]! 1632 1633# qhasm: 4x _5y01 = y01 << 2 1634# asm 1: vshl.i32 >_5y01=reg128#3,<y01=reg128#2,#2 1635# asm 2: vshl.i32 >_5y01=q2,<y01=q1,#2 1636vshl.i32 q2,q1,#2 1637 1638# qhasm: y23 aligned= mem128[input_2];input_2+=16 1639# asm 1: vld1.8 {>y23=reg128#4%bot->y23=reg128#4%top},[<input_2=int32#3,: 128]! 1640# asm 2: vld1.8 {>y23=d6->y23=d7},[<input_2=r2,: 128]! 1641vld1.8 {d6-d7},[r2,: 128]! 1642 1643# qhasm: 4x _5y23 = y23 << 2 1644# asm 1: vshl.i32 >_5y23=reg128#9,<y23=reg128#4,#2 1645# asm 2: vshl.i32 >_5y23=q8,<y23=q3,#2 1646vshl.i32 q8,q3,#2 1647 1648# qhasm: y4 aligned= mem64[input_2]y4[1] 1649# asm 1: vld1.8 {<y4=reg128#10%bot},[<input_2=int32#3,: 64] 1650# asm 2: vld1.8 {<y4=d18},[<input_2=r2,: 64] 1651vld1.8 {d18},[r2,: 64] 1652 1653# qhasm: 4x _5y4 = y4 << 2 1654# asm 1: vshl.i32 >_5y4=reg128#11,<y4=reg128#10,#2 1655# asm 2: vshl.i32 >_5y4=q10,<y4=q9,#2 1656vshl.i32 q10,q9,#2 1657 1658# qhasm: x01 aligned= mem128[input_1];input_1+=16 1659# asm 1: vld1.8 {>x01=reg128#12%bot->x01=reg128#12%top},[<input_1=int32#2,: 128]! 1660# asm 2: vld1.8 {>x01=d22->x01=d23},[<input_1=r1,: 128]! 1661vld1.8 {d22-d23},[r1,: 128]! 1662 1663# qhasm: 4x _5y01 += y01 1664# asm 1: vadd.i32 >_5y01=reg128#3,<_5y01=reg128#3,<y01=reg128#2 1665# asm 2: vadd.i32 >_5y01=q2,<_5y01=q2,<y01=q1 1666vadd.i32 q2,q2,q1 1667 1668# qhasm: x23 aligned= mem128[input_1];input_1+=16 1669# asm 1: vld1.8 {>x23=reg128#13%bot->x23=reg128#13%top},[<input_1=int32#2,: 128]! 1670# asm 2: vld1.8 {>x23=d24->x23=d25},[<input_1=r1,: 128]! 1671vld1.8 {d24-d25},[r1,: 128]! 1672 1673# qhasm: 4x _5y23 += y23 1674# asm 1: vadd.i32 >_5y23=reg128#9,<_5y23=reg128#9,<y23=reg128#4 1675# asm 2: vadd.i32 >_5y23=q8,<_5y23=q8,<y23=q3 1676vadd.i32 q8,q8,q3 1677 1678# qhasm: 4x _5y4 += y4 1679# asm 1: vadd.i32 >_5y4=reg128#11,<_5y4=reg128#11,<y4=reg128#10 1680# asm 2: vadd.i32 >_5y4=q10,<_5y4=q10,<y4=q9 1681vadd.i32 q10,q10,q9 1682 1683# qhasm: c01 aligned= mem128[input_3];input_3+=16 1684# asm 1: vld1.8 {>c01=reg128#14%bot->c01=reg128#14%top},[<input_3=int32#4,: 128]! 1685# asm 2: vld1.8 {>c01=d26->c01=d27},[<input_3=r3,: 128]! 1686vld1.8 {d26-d27},[r3,: 128]! 1687 1688# qhasm: 4x x01 += c01 1689# asm 1: vadd.i32 >x01=reg128#12,<x01=reg128#12,<c01=reg128#14 1690# asm 2: vadd.i32 >x01=q11,<x01=q11,<c01=q13 1691vadd.i32 q11,q11,q13 1692 1693# qhasm: c23 aligned= mem128[input_3];input_3+=16 1694# asm 1: vld1.8 {>c23=reg128#14%bot->c23=reg128#14%top},[<input_3=int32#4,: 128]! 1695# asm 2: vld1.8 {>c23=d26->c23=d27},[<input_3=r3,: 128]! 1696vld1.8 {d26-d27},[r3,: 128]! 1697 1698# qhasm: 4x x23 += c23 1699# asm 1: vadd.i32 >x23=reg128#13,<x23=reg128#13,<c23=reg128#14 1700# asm 2: vadd.i32 >x23=q12,<x23=q12,<c23=q13 1701vadd.i32 q12,q12,q13 1702 1703# qhasm: x4 aligned= mem64[input_1]x4[1] 1704# asm 1: vld1.8 {<x4=reg128#14%bot},[<input_1=int32#2,: 64] 1705# asm 2: vld1.8 {<x4=d26},[<input_1=r1,: 64] 1706vld1.8 {d26},[r1,: 64] 1707 1708# qhasm: 2x mask unsigned>>=6 1709# asm 1: vshr.u64 >mask=reg128#1,<mask=reg128#1,#6 1710# asm 2: vshr.u64 >mask=q0,<mask=q0,#6 1711vshr.u64 q0,q0,#6 1712 1713# qhasm: c4 aligned= mem64[input_3]c4[1] 1714# asm 1: vld1.8 {<c4=reg128#15%bot},[<input_3=int32#4,: 64] 1715# asm 2: vld1.8 {<c4=d28},[<input_3=r3,: 64] 1716vld1.8 {d28},[r3,: 64] 1717 1718# qhasm: 4x x4 += c4 1719# asm 1: vadd.i32 >x4=reg128#14,<x4=reg128#14,<c4=reg128#15 1720# asm 2: vadd.i32 >x4=q13,<x4=q13,<c4=q14 1721vadd.i32 q13,q13,q14 1722 1723# qhasm: r0[0,1] = x01[0] unsigned* y01[0]; r0[2,3] = x01[1] unsigned* y01[1] 1724# asm 1: vmull.u32 >r0=reg128#15,<x01=reg128#12%bot,<y01=reg128#2%bot 1725# asm 2: vmull.u32 >r0=q14,<x01=d22,<y01=d2 1726vmull.u32 q14,d22,d2 1727 1728# qhasm: r0[0,1] += x01[2] unsigned* _5y4[0]; r0[2,3] += x01[3] unsigned* _5y4[1] 1729# asm 1: vmlal.u32 <r0=reg128#15,<x01=reg128#12%top,<_5y4=reg128#11%bot 1730# asm 2: vmlal.u32 <r0=q14,<x01=d23,<_5y4=d20 1731vmlal.u32 q14,d23,d20 1732 1733# qhasm: r0[0,1] += x23[0] unsigned* _5y23[2]; r0[2,3] += x23[1] unsigned* _5y23[3] 1734# asm 1: vmlal.u32 <r0=reg128#15,<x23=reg128#13%bot,<_5y23=reg128#9%top 1735# asm 2: vmlal.u32 <r0=q14,<x23=d24,<_5y23=d17 1736vmlal.u32 q14,d24,d17 1737 1738# qhasm: r0[0,1] += x23[2] unsigned* _5y23[0]; r0[2,3] += x23[3] unsigned* _5y23[1] 1739# asm 1: vmlal.u32 <r0=reg128#15,<x23=reg128#13%top,<_5y23=reg128#9%bot 1740# asm 2: vmlal.u32 <r0=q14,<x23=d25,<_5y23=d16 1741vmlal.u32 q14,d25,d16 1742 1743# qhasm: r0[0,1] += x4[0] unsigned* _5y01[2]; r0[2,3] += x4[1] unsigned* _5y01[3] 1744# asm 1: vmlal.u32 <r0=reg128#15,<x4=reg128#14%bot,<_5y01=reg128#3%top 1745# asm 2: vmlal.u32 <r0=q14,<x4=d26,<_5y01=d5 1746vmlal.u32 q14,d26,d5 1747 1748# qhasm: r1[0,1] = x01[0] unsigned* y01[2]; r1[2,3] = x01[1] unsigned* y01[3] 1749# asm 1: vmull.u32 >r1=reg128#3,<x01=reg128#12%bot,<y01=reg128#2%top 1750# asm 2: vmull.u32 >r1=q2,<x01=d22,<y01=d3 1751vmull.u32 q2,d22,d3 1752 1753# qhasm: r1[0,1] += x01[2] unsigned* y01[0]; r1[2,3] += x01[3] unsigned* y01[1] 1754# asm 1: vmlal.u32 <r1=reg128#3,<x01=reg128#12%top,<y01=reg128#2%bot 1755# asm 2: vmlal.u32 <r1=q2,<x01=d23,<y01=d2 1756vmlal.u32 q2,d23,d2 1757 1758# qhasm: r1[0,1] += x23[0] unsigned* _5y4[0]; r1[2,3] += x23[1] unsigned* _5y4[1] 1759# asm 1: vmlal.u32 <r1=reg128#3,<x23=reg128#13%bot,<_5y4=reg128#11%bot 1760# asm 2: vmlal.u32 <r1=q2,<x23=d24,<_5y4=d20 1761vmlal.u32 q2,d24,d20 1762 1763# qhasm: r1[0,1] += x23[2] unsigned* _5y23[2]; r1[2,3] += x23[3] unsigned* _5y23[3] 1764# asm 1: vmlal.u32 <r1=reg128#3,<x23=reg128#13%top,<_5y23=reg128#9%top 1765# asm 2: vmlal.u32 <r1=q2,<x23=d25,<_5y23=d17 1766vmlal.u32 q2,d25,d17 1767 1768# qhasm: r1[0,1] += x4[0] unsigned* _5y23[0]; r1[2,3] += x4[1] unsigned* _5y23[1] 1769# asm 1: vmlal.u32 <r1=reg128#3,<x4=reg128#14%bot,<_5y23=reg128#9%bot 1770# asm 2: vmlal.u32 <r1=q2,<x4=d26,<_5y23=d16 1771vmlal.u32 q2,d26,d16 1772 1773# qhasm: r2[0,1] = x01[0] unsigned* y23[0]; r2[2,3] = x01[1] unsigned* y23[1] 1774# asm 1: vmull.u32 >r2=reg128#16,<x01=reg128#12%bot,<y23=reg128#4%bot 1775# asm 2: vmull.u32 >r2=q15,<x01=d22,<y23=d6 1776vmull.u32 q15,d22,d6 1777 1778# qhasm: r2[0,1] += x01[2] unsigned* y01[2]; r2[2,3] += x01[3] unsigned* y01[3] 1779# asm 1: vmlal.u32 <r2=reg128#16,<x01=reg128#12%top,<y01=reg128#2%top 1780# asm 2: vmlal.u32 <r2=q15,<x01=d23,<y01=d3 1781vmlal.u32 q15,d23,d3 1782 1783# qhasm: r2[0,1] += x23[0] unsigned* y01[0]; r2[2,3] += x23[1] unsigned* y01[1] 1784# asm 1: vmlal.u32 <r2=reg128#16,<x23=reg128#13%bot,<y01=reg128#2%bot 1785# asm 2: vmlal.u32 <r2=q15,<x23=d24,<y01=d2 1786vmlal.u32 q15,d24,d2 1787 1788# qhasm: r2[0,1] += x23[2] unsigned* _5y4[0]; r2[2,3] += x23[3] unsigned* _5y4[1] 1789# asm 1: vmlal.u32 <r2=reg128#16,<x23=reg128#13%top,<_5y4=reg128#11%bot 1790# asm 2: vmlal.u32 <r2=q15,<x23=d25,<_5y4=d20 1791vmlal.u32 q15,d25,d20 1792 1793# qhasm: r2[0,1] += x4[0] unsigned* _5y23[2]; r2[2,3] += x4[1] unsigned* _5y23[3] 1794# asm 1: vmlal.u32 <r2=reg128#16,<x4=reg128#14%bot,<_5y23=reg128#9%top 1795# asm 2: vmlal.u32 <r2=q15,<x4=d26,<_5y23=d17 1796vmlal.u32 q15,d26,d17 1797 1798# qhasm: r3[0,1] = x01[0] unsigned* y23[2]; r3[2,3] = x01[1] unsigned* y23[3] 1799# asm 1: vmull.u32 >r3=reg128#9,<x01=reg128#12%bot,<y23=reg128#4%top 1800# asm 2: vmull.u32 >r3=q8,<x01=d22,<y23=d7 1801vmull.u32 q8,d22,d7 1802 1803# qhasm: r3[0,1] += x01[2] unsigned* y23[0]; r3[2,3] += x01[3] unsigned* y23[1] 1804# asm 1: vmlal.u32 <r3=reg128#9,<x01=reg128#12%top,<y23=reg128#4%bot 1805# asm 2: vmlal.u32 <r3=q8,<x01=d23,<y23=d6 1806vmlal.u32 q8,d23,d6 1807 1808# qhasm: r3[0,1] += x23[0] unsigned* y01[2]; r3[2,3] += x23[1] unsigned* y01[3] 1809# asm 1: vmlal.u32 <r3=reg128#9,<x23=reg128#13%bot,<y01=reg128#2%top 1810# asm 2: vmlal.u32 <r3=q8,<x23=d24,<y01=d3 1811vmlal.u32 q8,d24,d3 1812 1813# qhasm: r3[0,1] += x23[2] unsigned* y01[0]; r3[2,3] += x23[3] unsigned* y01[1] 1814# asm 1: vmlal.u32 <r3=reg128#9,<x23=reg128#13%top,<y01=reg128#2%bot 1815# asm 2: vmlal.u32 <r3=q8,<x23=d25,<y01=d2 1816vmlal.u32 q8,d25,d2 1817 1818# qhasm: r3[0,1] += x4[0] unsigned* _5y4[0]; r3[2,3] += x4[1] unsigned* _5y4[1] 1819# asm 1: vmlal.u32 <r3=reg128#9,<x4=reg128#14%bot,<_5y4=reg128#11%bot 1820# asm 2: vmlal.u32 <r3=q8,<x4=d26,<_5y4=d20 1821vmlal.u32 q8,d26,d20 1822 1823# qhasm: r4[0,1] = x01[0] unsigned* y4[0]; r4[2,3] = x01[1] unsigned* y4[1] 1824# asm 1: vmull.u32 >r4=reg128#10,<x01=reg128#12%bot,<y4=reg128#10%bot 1825# asm 2: vmull.u32 >r4=q9,<x01=d22,<y4=d18 1826vmull.u32 q9,d22,d18 1827 1828# qhasm: r4[0,1] += x01[2] unsigned* y23[2]; r4[2,3] += x01[3] unsigned* y23[3] 1829# asm 1: vmlal.u32 <r4=reg128#10,<x01=reg128#12%top,<y23=reg128#4%top 1830# asm 2: vmlal.u32 <r4=q9,<x01=d23,<y23=d7 1831vmlal.u32 q9,d23,d7 1832 1833# qhasm: r4[0,1] += x23[0] unsigned* y23[0]; r4[2,3] += x23[1] unsigned* y23[1] 1834# asm 1: vmlal.u32 <r4=reg128#10,<x23=reg128#13%bot,<y23=reg128#4%bot 1835# asm 2: vmlal.u32 <r4=q9,<x23=d24,<y23=d6 1836vmlal.u32 q9,d24,d6 1837 1838# qhasm: r4[0,1] += x23[2] unsigned* y01[2]; r4[2,3] += x23[3] unsigned* y01[3] 1839# asm 1: vmlal.u32 <r4=reg128#10,<x23=reg128#13%top,<y01=reg128#2%top 1840# asm 2: vmlal.u32 <r4=q9,<x23=d25,<y01=d3 1841vmlal.u32 q9,d25,d3 1842 1843# qhasm: r4[0,1] += x4[0] unsigned* y01[0]; r4[2,3] += x4[1] unsigned* y01[1] 1844# asm 1: vmlal.u32 <r4=reg128#10,<x4=reg128#14%bot,<y01=reg128#2%bot 1845# asm 2: vmlal.u32 <r4=q9,<x4=d26,<y01=d2 1846vmlal.u32 q9,d26,d2 1847 1848# qhasm: 2x t1 = r0 unsigned>> 26 1849# asm 1: vshr.u64 >t1=reg128#2,<r0=reg128#15,#26 1850# asm 2: vshr.u64 >t1=q1,<r0=q14,#26 1851vshr.u64 q1,q14,#26 1852 1853# qhasm: r0 &= mask 1854# asm 1: vand >r0=reg128#4,<r0=reg128#15,<mask=reg128#1 1855# asm 2: vand >r0=q3,<r0=q14,<mask=q0 1856vand q3,q14,q0 1857 1858# qhasm: 2x r1 += t1 1859# asm 1: vadd.i64 >r1=reg128#2,<r1=reg128#3,<t1=reg128#2 1860# asm 2: vadd.i64 >r1=q1,<r1=q2,<t1=q1 1861vadd.i64 q1,q2,q1 1862 1863# qhasm: 2x t4 = r3 unsigned>> 26 1864# asm 1: vshr.u64 >t4=reg128#3,<r3=reg128#9,#26 1865# asm 2: vshr.u64 >t4=q2,<r3=q8,#26 1866vshr.u64 q2,q8,#26 1867 1868# qhasm: r3 &= mask 1869# asm 1: vand >r3=reg128#9,<r3=reg128#9,<mask=reg128#1 1870# asm 2: vand >r3=q8,<r3=q8,<mask=q0 1871vand q8,q8,q0 1872 1873# qhasm: 2x r4 += t4 1874# asm 1: vadd.i64 >r4=reg128#3,<r4=reg128#10,<t4=reg128#3 1875# asm 2: vadd.i64 >r4=q2,<r4=q9,<t4=q2 1876vadd.i64 q2,q9,q2 1877 1878# qhasm: 2x t2 = r1 unsigned>> 26 1879# asm 1: vshr.u64 >t2=reg128#10,<r1=reg128#2,#26 1880# asm 2: vshr.u64 >t2=q9,<r1=q1,#26 1881vshr.u64 q9,q1,#26 1882 1883# qhasm: r1 &= mask 1884# asm 1: vand >r1=reg128#2,<r1=reg128#2,<mask=reg128#1 1885# asm 2: vand >r1=q1,<r1=q1,<mask=q0 1886vand q1,q1,q0 1887 1888# qhasm: 2x t0 = r4 unsigned>> 26 1889# asm 1: vshr.u64 >t0=reg128#11,<r4=reg128#3,#26 1890# asm 2: vshr.u64 >t0=q10,<r4=q2,#26 1891vshr.u64 q10,q2,#26 1892 1893# qhasm: 2x r2 += t2 1894# asm 1: vadd.i64 >r2=reg128#10,<r2=reg128#16,<t2=reg128#10 1895# asm 2: vadd.i64 >r2=q9,<r2=q15,<t2=q9 1896vadd.i64 q9,q15,q9 1897 1898# qhasm: r4 &= mask 1899# asm 1: vand >r4=reg128#3,<r4=reg128#3,<mask=reg128#1 1900# asm 2: vand >r4=q2,<r4=q2,<mask=q0 1901vand q2,q2,q0 1902 1903# qhasm: 2x r0 += t0 1904# asm 1: vadd.i64 >r0=reg128#4,<r0=reg128#4,<t0=reg128#11 1905# asm 2: vadd.i64 >r0=q3,<r0=q3,<t0=q10 1906vadd.i64 q3,q3,q10 1907 1908# qhasm: 2x t0 <<= 2 1909# asm 1: vshl.i64 >t0=reg128#11,<t0=reg128#11,#2 1910# asm 2: vshl.i64 >t0=q10,<t0=q10,#2 1911vshl.i64 q10,q10,#2 1912 1913# qhasm: 2x t3 = r2 unsigned>> 26 1914# asm 1: vshr.u64 >t3=reg128#12,<r2=reg128#10,#26 1915# asm 2: vshr.u64 >t3=q11,<r2=q9,#26 1916vshr.u64 q11,q9,#26 1917 1918# qhasm: 2x r0 += t0 1919# asm 1: vadd.i64 >r0=reg128#4,<r0=reg128#4,<t0=reg128#11 1920# asm 2: vadd.i64 >r0=q3,<r0=q3,<t0=q10 1921vadd.i64 q3,q3,q10 1922 1923# qhasm: x23 = r2 & mask 1924# asm 1: vand >x23=reg128#10,<r2=reg128#10,<mask=reg128#1 1925# asm 2: vand >x23=q9,<r2=q9,<mask=q0 1926vand q9,q9,q0 1927 1928# qhasm: 2x r3 += t3 1929# asm 1: vadd.i64 >r3=reg128#9,<r3=reg128#9,<t3=reg128#12 1930# asm 2: vadd.i64 >r3=q8,<r3=q8,<t3=q11 1931vadd.i64 q8,q8,q11 1932 1933# qhasm: 2x t1 = r0 unsigned>> 26 1934# asm 1: vshr.u64 >t1=reg128#11,<r0=reg128#4,#26 1935# asm 2: vshr.u64 >t1=q10,<r0=q3,#26 1936vshr.u64 q10,q3,#26 1937 1938# qhasm: x23 = x23[0,2,1,3] 1939# asm 1: vtrn.32 <x23=reg128#10%bot,<x23=reg128#10%top 1940# asm 2: vtrn.32 <x23=d18,<x23=d19 1941vtrn.32 d18,d19 1942 1943# qhasm: x01 = r0 & mask 1944# asm 1: vand >x01=reg128#4,<r0=reg128#4,<mask=reg128#1 1945# asm 2: vand >x01=q3,<r0=q3,<mask=q0 1946vand q3,q3,q0 1947 1948# qhasm: 2x r1 += t1 1949# asm 1: vadd.i64 >r1=reg128#2,<r1=reg128#2,<t1=reg128#11 1950# asm 2: vadd.i64 >r1=q1,<r1=q1,<t1=q10 1951vadd.i64 q1,q1,q10 1952 1953# qhasm: 2x t4 = r3 unsigned>> 26 1954# asm 1: vshr.u64 >t4=reg128#11,<r3=reg128#9,#26 1955# asm 2: vshr.u64 >t4=q10,<r3=q8,#26 1956vshr.u64 q10,q8,#26 1957 1958# qhasm: x01 = x01[0,2,1,3] 1959# asm 1: vtrn.32 <x01=reg128#4%bot,<x01=reg128#4%top 1960# asm 2: vtrn.32 <x01=d6,<x01=d7 1961vtrn.32 d6,d7 1962 1963# qhasm: r3 &= mask 1964# asm 1: vand >r3=reg128#1,<r3=reg128#9,<mask=reg128#1 1965# asm 2: vand >r3=q0,<r3=q8,<mask=q0 1966vand q0,q8,q0 1967 1968# qhasm: r1 = r1[0,2,1,3] 1969# asm 1: vtrn.32 <r1=reg128#2%bot,<r1=reg128#2%top 1970# asm 2: vtrn.32 <r1=d2,<r1=d3 1971vtrn.32 d2,d3 1972 1973# qhasm: 2x x4 = r4 + t4 1974# asm 1: vadd.i64 >x4=reg128#3,<r4=reg128#3,<t4=reg128#11 1975# asm 2: vadd.i64 >x4=q2,<r4=q2,<t4=q10 1976vadd.i64 q2,q2,q10 1977 1978# qhasm: r3 = r3[0,2,1,3] 1979# asm 1: vtrn.32 <r3=reg128#1%bot,<r3=reg128#1%top 1980# asm 2: vtrn.32 <r3=d0,<r3=d1 1981vtrn.32 d0,d1 1982 1983# qhasm: x01 = x01[0,1] r1[0,1] 1984# asm 1: vext.32 <x01=reg128#4%top,<r1=reg128#2%bot,<r1=reg128#2%bot,#0 1985# asm 2: vext.32 <x01=d7,<r1=d2,<r1=d2,#0 1986vext.32 d7,d2,d2,#0 1987 1988# qhasm: x23 = x23[0,1] r3[0,1] 1989# asm 1: vext.32 <x23=reg128#10%top,<r3=reg128#1%bot,<r3=reg128#1%bot,#0 1990# asm 2: vext.32 <x23=d19,<r3=d0,<r3=d0,#0 1991vext.32 d19,d0,d0,#0 1992 1993# qhasm: x4 = x4[0,2,1,3] 1994# asm 1: vtrn.32 <x4=reg128#3%bot,<x4=reg128#3%top 1995# asm 2: vtrn.32 <x4=d4,<x4=d5 1996vtrn.32 d4,d5 1997 1998# qhasm: mem128[input_0] aligned= x01;input_0+=16 1999# asm 1: vst1.8 {<x01=reg128#4%bot-<x01=reg128#4%top},[<input_0=int32#1,: 128]! 2000# asm 2: vst1.8 {<x01=d6-<x01=d7},[<input_0=r0,: 128]! 2001vst1.8 {d6-d7},[r0,: 128]! 2002 2003# qhasm: mem128[input_0] aligned= x23;input_0+=16 2004# asm 1: vst1.8 {<x23=reg128#10%bot-<x23=reg128#10%top},[<input_0=int32#1,: 128]! 2005# asm 2: vst1.8 {<x23=d18-<x23=d19},[<input_0=r0,: 128]! 2006vst1.8 {d18-d19},[r0,: 128]! 2007 2008# qhasm: mem64[input_0] aligned= x4[0] 2009# asm 1: vst1.8 <x4=reg128#3%bot,[<input_0=int32#1,: 64] 2010# asm 2: vst1.8 <x4=d4,[<input_0=r0,: 64] 2011vst1.8 d4,[r0,: 64] 2012 2013# qhasm: return 2014add sp,sp,#0 2015bx lr 2016 2017#endif /* !OPENSSL_NO_ASM && OPENSSL_ARM && __ELF__ */ 2018