1 // Copyright 2017 Google LLC
2 //
3 // Licensed under the Apache License, Version 2.0 (the "License");
4 // you may not use this file except in compliance with the License.
5 // You may obtain a copy of the License at
6 //
7 // http://www.apache.org/licenses/LICENSE-2.0
8 //
9 // Unless required by applicable law or agreed to in writing, software
10 // distributed under the License is distributed on an "AS IS" BASIS,
11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 // See the License for the specific language governing permissions and
13 // limitations under the License.
14
15 #include "cpu_features_macros.h"
16
17 #ifdef CPU_FEATURES_ARCH_AARCH64
18 #if defined(CPU_FEATURES_OS_LINUX) || defined(CPU_FEATURES_OS_ANDROID)
19
20 #include "cpuinfo_aarch64.h"
21
22 ////////////////////////////////////////////////////////////////////////////////
23 // Definitions for introspection.
24 ////////////////////////////////////////////////////////////////////////////////
25 #define INTROSPECTION_TABLE \
26 LINE(AARCH64_FP, fp, "fp", AARCH64_HWCAP_FP, 0) \
27 LINE(AARCH64_ASIMD, asimd, "asimd", AARCH64_HWCAP_ASIMD, 0) \
28 LINE(AARCH64_EVTSTRM, evtstrm, "evtstrm", AARCH64_HWCAP_EVTSTRM, 0) \
29 LINE(AARCH64_AES, aes, "aes", AARCH64_HWCAP_AES, 0) \
30 LINE(AARCH64_PMULL, pmull, "pmull", AARCH64_HWCAP_PMULL, 0) \
31 LINE(AARCH64_SHA1, sha1, "sha1", AARCH64_HWCAP_SHA1, 0) \
32 LINE(AARCH64_SHA2, sha2, "sha2", AARCH64_HWCAP_SHA2, 0) \
33 LINE(AARCH64_CRC32, crc32, "crc32", AARCH64_HWCAP_CRC32, 0) \
34 LINE(AARCH64_ATOMICS, atomics, "atomics", AARCH64_HWCAP_ATOMICS, 0) \
35 LINE(AARCH64_FPHP, fphp, "fphp", AARCH64_HWCAP_FPHP, 0) \
36 LINE(AARCH64_ASIMDHP, asimdhp, "asimdhp", AARCH64_HWCAP_ASIMDHP, 0) \
37 LINE(AARCH64_CPUID, cpuid, "cpuid", AARCH64_HWCAP_CPUID, 0) \
38 LINE(AARCH64_ASIMDRDM, asimdrdm, "asimdrdm", AARCH64_HWCAP_ASIMDRDM, 0) \
39 LINE(AARCH64_JSCVT, jscvt, "jscvt", AARCH64_HWCAP_JSCVT, 0) \
40 LINE(AARCH64_FCMA, fcma, "fcma", AARCH64_HWCAP_FCMA, 0) \
41 LINE(AARCH64_LRCPC, lrcpc, "lrcpc", AARCH64_HWCAP_LRCPC, 0) \
42 LINE(AARCH64_DCPOP, dcpop, "dcpop", AARCH64_HWCAP_DCPOP, 0) \
43 LINE(AARCH64_SHA3, sha3, "sha3", AARCH64_HWCAP_SHA3, 0) \
44 LINE(AARCH64_SM3, sm3, "sm3", AARCH64_HWCAP_SM3, 0) \
45 LINE(AARCH64_SM4, sm4, "sm4", AARCH64_HWCAP_SM4, 0) \
46 LINE(AARCH64_ASIMDDP, asimddp, "asimddp", AARCH64_HWCAP_ASIMDDP, 0) \
47 LINE(AARCH64_SHA512, sha512, "sha512", AARCH64_HWCAP_SHA512, 0) \
48 LINE(AARCH64_SVE, sve, "sve", AARCH64_HWCAP_SVE, 0) \
49 LINE(AARCH64_ASIMDFHM, asimdfhm, "asimdfhm", AARCH64_HWCAP_ASIMDFHM, 0) \
50 LINE(AARCH64_DIT, dit, "dit", AARCH64_HWCAP_DIT, 0) \
51 LINE(AARCH64_USCAT, uscat, "uscat", AARCH64_HWCAP_USCAT, 0) \
52 LINE(AARCH64_ILRCPC, ilrcpc, "ilrcpc", AARCH64_HWCAP_ILRCPC, 0) \
53 LINE(AARCH64_FLAGM, flagm, "flagm", AARCH64_HWCAP_FLAGM, 0) \
54 LINE(AARCH64_SSBS, ssbs, "ssbs", AARCH64_HWCAP_SSBS, 0) \
55 LINE(AARCH64_SB, sb, "sb", AARCH64_HWCAP_SB, 0) \
56 LINE(AARCH64_PACA, paca, "paca", AARCH64_HWCAP_PACA, 0) \
57 LINE(AARCH64_PACG, pacg, "pacg", AARCH64_HWCAP_PACG, 0) \
58 LINE(AARCH64_DCPODP, dcpodp, "dcpodp", 0, AARCH64_HWCAP2_DCPODP) \
59 LINE(AARCH64_SVE2, sve2, "sve2", 0, AARCH64_HWCAP2_SVE2) \
60 LINE(AARCH64_SVEAES, sveaes, "sveaes", 0, AARCH64_HWCAP2_SVEAES) \
61 LINE(AARCH64_SVEPMULL, svepmull, "svepmull", 0, AARCH64_HWCAP2_SVEPMULL) \
62 LINE(AARCH64_SVEBITPERM, svebitperm, "svebitperm", 0, \
63 AARCH64_HWCAP2_SVEBITPERM) \
64 LINE(AARCH64_SVESHA3, svesha3, "svesha3", 0, AARCH64_HWCAP2_SVESHA3) \
65 LINE(AARCH64_SVESM4, svesm4, "svesm4", 0, AARCH64_HWCAP2_SVESM4) \
66 LINE(AARCH64_FLAGM2, flagm2, "flagm2", 0, AARCH64_HWCAP2_FLAGM2) \
67 LINE(AARCH64_FRINT, frint, "frint", 0, AARCH64_HWCAP2_FRINT) \
68 LINE(AARCH64_SVEI8MM, svei8mm, "svei8mm", 0, AARCH64_HWCAP2_SVEI8MM) \
69 LINE(AARCH64_SVEF32MM, svef32mm, "svef32mm", 0, AARCH64_HWCAP2_SVEF32MM) \
70 LINE(AARCH64_SVEF64MM, svef64mm, "svef64mm", 0, AARCH64_HWCAP2_SVEF64MM) \
71 LINE(AARCH64_SVEBF16, svebf16, "svebf16", 0, AARCH64_HWCAP2_SVEBF16) \
72 LINE(AARCH64_I8MM, i8mm, "i8mm", 0, AARCH64_HWCAP2_I8MM) \
73 LINE(AARCH64_BF16, bf16, "bf16", 0, AARCH64_HWCAP2_BF16) \
74 LINE(AARCH64_DGH, dgh, "dgh", 0, AARCH64_HWCAP2_DGH) \
75 LINE(AARCH64_RNG, rng, "rng", 0, AARCH64_HWCAP2_RNG) \
76 LINE(AARCH64_BTI, bti, "bti", 0, AARCH64_HWCAP2_BTI) \
77 LINE(AARCH64_MTE, mte, "mte", 0, AARCH64_HWCAP2_MTE) \
78 LINE(AARCH64_ECV, ecv, "ecv", 0, AARCH64_HWCAP2_ECV) \
79 LINE(AARCH64_AFP, afp, "afp", 0, AARCH64_HWCAP2_AFP) \
80 LINE(AARCH64_RPRES, rpres, "rpres", 0, AARCH64_HWCAP2_RPRES)
81 #define INTROSPECTION_PREFIX Aarch64
82 #define INTROSPECTION_ENUM_PREFIX AARCH64
83 #include "define_introspection_and_hwcaps.inl"
84
85 ////////////////////////////////////////////////////////////////////////////////
86 // Implementation.
87 ////////////////////////////////////////////////////////////////////////////////
88
89 #include <stdbool.h>
90
91 #include "internal/bit_utils.h"
92 #include "internal/filesystem.h"
93 #include "internal/stack_line_reader.h"
94 #include "internal/string_view.h"
95
HandleAarch64Line(const LineResult result,Aarch64Info * const info)96 static bool HandleAarch64Line(const LineResult result,
97 Aarch64Info* const info) {
98 StringView line = result.line;
99 StringView key, value;
100 if (CpuFeatures_StringView_GetAttributeKeyValue(line, &key, &value)) {
101 if (CpuFeatures_StringView_IsEquals(key, str("Features"))) {
102 for (size_t i = 0; i < AARCH64_LAST_; ++i) {
103 kSetters[i](&info->features, CpuFeatures_StringView_HasWord(
104 value, kCpuInfoFlags[i], ' '));
105 }
106 } else if (CpuFeatures_StringView_IsEquals(key, str("CPU implementer"))) {
107 info->implementer = CpuFeatures_StringView_ParsePositiveNumber(value);
108 } else if (CpuFeatures_StringView_IsEquals(key, str("CPU variant"))) {
109 info->variant = CpuFeatures_StringView_ParsePositiveNumber(value);
110 } else if (CpuFeatures_StringView_IsEquals(key, str("CPU part"))) {
111 info->part = CpuFeatures_StringView_ParsePositiveNumber(value);
112 } else if (CpuFeatures_StringView_IsEquals(key, str("CPU revision"))) {
113 info->revision = CpuFeatures_StringView_ParsePositiveNumber(value);
114 }
115 }
116 return !result.eof;
117 }
118
FillProcCpuInfoData(Aarch64Info * const info)119 static void FillProcCpuInfoData(Aarch64Info* const info) {
120 const int fd = CpuFeatures_OpenFile("/proc/cpuinfo");
121 if (fd >= 0) {
122 StackLineReader reader;
123 StackLineReader_Initialize(&reader, fd);
124 for (;;) {
125 if (!HandleAarch64Line(StackLineReader_NextLine(&reader), info)) {
126 break;
127 }
128 }
129 CpuFeatures_CloseFile(fd);
130 }
131 }
132
133 static const Aarch64Info kEmptyAarch64Info;
134
GetAarch64Info(void)135 Aarch64Info GetAarch64Info(void) {
136 // capabilities are fetched from both getauxval and /proc/cpuinfo so we can
137 // have some information if the executable is sandboxed (aka no access to
138 // /proc/cpuinfo).
139 Aarch64Info info = kEmptyAarch64Info;
140
141 FillProcCpuInfoData(&info);
142 const HardwareCapabilities hwcaps = CpuFeatures_GetHardwareCapabilities();
143 for (size_t i = 0; i < AARCH64_LAST_; ++i) {
144 if (CpuFeatures_IsHwCapsSet(kHardwareCapabilities[i], hwcaps)) {
145 kSetters[i](&info.features, true);
146 }
147 }
148
149 return info;
150 }
151
152 #endif // defined(CPU_FEATURES_OS_LINUX) || defined(CPU_FEATURES_OS_ANDROID)
153 #endif // CPU_FEATURES_ARCH_AARCH64
154