1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef UART8250REG_H 4 #define UART8250REG_H 5 6 #include <types.h> 7 8 /* Data */ 9 #define UART8250_RBR 0x00 10 #define UART8250_TBR 0x00 11 12 /* Control */ 13 #define UART8250_IER 0x01 14 #define UART8250_IER_MSI BIT(3) /* Enable Modem status interrupt */ 15 #define UART8250_IER_RLSI BIT(2) /* Enable receiver line status interrupt */ 16 #define UART8250_IER_THRI BIT(1) /* Enable Transmitter holding register int. */ 17 #define UART8250_IER_RDI BIT(0) /* Enable receiver data interrupt */ 18 19 #define UART8250_IIR 0x02 20 #define UART8250_IIR_NO_INT 0x01 /* No interrupts pending */ 21 #define UART8250_IIR_ID 0x06 /* Mask for the interrupt ID */ 22 23 #define UART8250_IIR_MSI 0x00 /* Modem status interrupt */ 24 #define UART8250_IIR_THRI 0x02 /* Transmitter holding register empty */ 25 #define UART8250_IIR_RDI 0x04 /* Receiver data interrupt */ 26 #define UART8250_IIR_RLSI 0x06 /* Receiver line status interrupt */ 27 #define UART8250_IIR_FIFO_EN 0xC0 /* FIFO enabled */ 28 29 #define UART8250_FCR 0x02 30 #define UART8250_FCR_FIFO_EN BIT(0) /* Fifo enable */ 31 #define UART8250_FCR_CLEAR_RCVR BIT(1) /* Clear the RCVR FIFO */ 32 #define UART8250_FCR_CLEAR_XMIT BIT(2) /* Clear the XMIT FIFO */ 33 #define UART8250_FCR_DMA_SELECT BIT(3) /* For DMA applications */ 34 #define UART8250_FCR_TRIGGER_MASK (3 << 6) /* Mask for the FIFO trigger range */ 35 #define UART8250_FCR_TRIGGER_1 (0 << 6) /* Mask for trigger set at 1 */ 36 #define UART8250_FCR_TRIGGER_4 (1 << 6) /* Mask for trigger set at 4 */ 37 #define UART8250_FCR_TRIGGER_8 (2 << 6) /* Mask for trigger set at 8 */ 38 #define UART8250_FCR_TRIGGER_14 (3 << 6) /* Mask for trigger set at 14 */ 39 40 #define UART8250_LCR 0x03 41 #define UART8250_LCR_WLS_MSK 0x03 /* character length select mask */ 42 #define UART8250_LCR_WLS_5 0x00 /* 5 bit character length */ 43 #define UART8250_LCR_WLS_6 0x01 /* 6 bit character length */ 44 #define UART8250_LCR_WLS_7 0x02 /* 7 bit character length */ 45 #define UART8250_LCR_WLS_8 0x03 /* 8 bit character length */ 46 #define UART8250_LCR_STB BIT(2) /* Number of stop Bits, off = 1, on = 1.5 or 2) */ 47 #define UART8250_LCR_PEN BIT(3) /* Parity enable */ 48 #define UART8250_LCR_EPS BIT(4) /* Even Parity Select */ 49 #define UART8250_LCR_STKP BIT(5) /* Stick Parity */ 50 #define UART8250_LCR_SBRK BIT(6) /* Set Break */ 51 #define UART8250_LCR_DLAB BIT(7) /* Divisor latch access bit */ 52 53 #define UART8250_MCR 0x04 54 #define UART8250_MCR_DTR BIT(0) /* DTR */ 55 #define UART8250_MCR_RTS BIT(1) /* RTS */ 56 #define UART8250_MCR_OUT1 BIT(2) /* Out 1 */ 57 #define UART8250_MCR_OUT2 BIT(3) /* Out 2 */ 58 #define UART8250_MCR_LOOP BIT(4) /* Enable loopback test mode */ 59 60 #define UART8250_MCR_DMA_EN 0x04 61 #define UART8250_MCR_TX_DFR 0x08 62 63 #define UART8250_DLL 0x00 64 #define UART8250_DLM 0x01 65 66 /* Status */ 67 #define UART8250_LSR 0x05 68 #define UART8250_LSR_DR BIT(0) /* Data ready */ 69 #define UART8250_LSR_OE BIT(1) /* Overrun */ 70 #define UART8250_LSR_PE BIT(2) /* Parity error */ 71 #define UART8250_LSR_FE BIT(3) /* Framing error */ 72 #define UART8250_LSR_BI BIT(4) /* Break */ 73 #define UART8250_LSR_THRE BIT(5) /* Xmit holding register empty */ 74 #define UART8250_LSR_TEMT BIT(6) /* Xmitter empty */ 75 #define UART8250_LSR_ERR BIT(7) /* Error */ 76 77 #define UART8250_MSR 0x06 78 #define UART8250_MSR_DCD BIT(7) /* Data Carrier Detect */ 79 #define UART8250_MSR_RI BIT(6) /* Ring Indicator */ 80 #define UART8250_MSR_DSR BIT(5) /* Data Set Ready */ 81 #define UART8250_MSR_CTS BIT(4) /* Clear to Send */ 82 #define UART8250_MSR_DDCD BIT(3) /* Delta DCD */ 83 #define UART8250_MSR_TERI BIT(2) /* Trailing edge ring indicator */ 84 #define UART8250_MSR_DDSR BIT(1) /* Delta DSR */ 85 #define UART8250_MSR_DCTS BIT(0) /* Delta CTS */ 86 87 #define UART8250_SCR 0x07 88 #define UART8250_SPR 0x07 89 90 #endif /* UART8250REG_H */ 91