1# Measured Boot 2Measured boot feature was initially implemented as an extension of Google 3Verified Boot. However, the two features were decoupled since then and use of 4measured boot no longer requires enabling vboot. 5 6In most cases TPM eventlog is initialized during bootblock before TPM gets set 7up, hence digests are not measured into TPM immediately, but are only cached in 8the event log. Later, as part of TPM setup, the cached events are applied onto 9TPM device. The behaviour is different if TPM_MEASURED_BOOT_INIT_BOOTBLOCK 10kconfig is set, which moves TPM initialization into bootblock. 11 12## SRTM 13A measured-based trust chain is one that begins with an initial entity that 14takes the first measurement, referred to as the "Core Root of Trust for 15Measurement" (CRTM), before control is granted to the measured entity. This 16process of measurement and then passing control is referred to as a transitive 17trust. When the CRTM can only ever be executed once during the power life-cycle 18of the system, it is referred to as a "Static CRTM" (S-CRTM). Thus the trust 19chain constructed from the S-CRTM is referred to as the Static Root of Trust for 20Measurement (SRTM) trust chain. The theory is that as long as a proper 21transitive trust is conducted as more code is allowed to execute, a trustworthy 22record showing the provenance of the executing system may be provided to 23establish the trustworthiness of the system. 24 25## IBB/CRTM 26The "Initial Boot Block" (IBB) is a one-time executed code block loaded at the 27reset vector. Under measured boot mode, the IBB measures itself before measuring 28the next code block making it an S-CRTM for the measured boot trust chain, an 29SRTM trust chain. Since the IBB measures itself and executes out of DRAM, it is 30said to have a "Root of Trust" (RoT) that is rooted in software. 31 32## S-CRTM Hardening 33To address attacks that took advantage of the IBB being self-referential with 34both the "Root of Trust for Verification" (RTV) and "Root of Trust for 35Measurement" (RTM) being rooted in software, hardening was implemented by CPU 36manufactures. This was accomplished by introducing RoT, typically an RTV, to an 37external entity provided by the manufacture that could be validated by the CPU 38at boot. Examples of this are Intel's BootGuard and AMD's Hardware Validated 39Boot (also known as Platform Secure Boot). These solutions work by having the 40IBB invoke the manufacture provided RoT as early as possible, for which the CPU 41has already validated or validates when invoked. The RoT will then validate the 42IBB, thus moving the root for the respective trust chain, typically the 43verification trust chain, into hardware. 44 45It should be noted that when Intel BootGuard was originally designed, it 46provided a measurement mode that resulted in the ACM (Authenticated Code 47Module) becoming the S-CRTM for the SRTM trust chain. Unfortunately, this was 48never deployed and thus relying on "Root of Trust for Verification" (RTV) 49signature check as the only assertion rooted in hardware. 50 51## Known Limitations 52At the moment measuring IBB dynamically and FMAP partitions are not possible but 53will be added later to the implementation. 54 55Also SoCs making use of VBOOT_RETURN_FROM_VERSTAGE are not able to use the 56measured boot extension because of platform constraints. 57 58### Measurements 59To construct the coreboot SRTM trust chain, the CBFS files which are part of the 60IBB, are identified by a metadata tag. This makes it possible to have platform 61specific IBB measurements without hard-coding them. 62 63#### CBFS files (stages, blobs) 64* CBFS data is measured as raw data before decompression happens. 65* CBFS header is excluded from measurements. 66* Measurements are stored in PCR 2 (by default, use PCR_SRTM kconfig option to 67 change). 68 69#### Runtime Data 70* CBFS data which changes by external input dynamically. Never stays the same. 71* It is identified by TPM_MEASURED_BOOT_RUNTIME_DATA kconfig option and 72 measured into a different PCR (PCR_RUNTIME_DATA kconfig option, 3 by default) 73 in order to avoid PCR pre-calculation issues. 74 75![][srtm] 76 77[srtm]: srtm.png 78 79### TPM eventlog 80There are three supported formats of event logs: 81* coreboot-specific format. 82* [TPM1.2 Specification][TPM12] (chapter 11). 83* [TPM2.0 Specification][TPM20] (chapter 10). 84 85#### coreboot-specific format 86```c 87struct tcpa_entry { 88 uint32_t pcr; /* PCR number. */ 89 char digest_type[10]; /* Hash algorithm name. */ 90 uint8_t digest[64]; /* Digest (tail can be unused). */ 91 uint32_t digest_length; /* Number of digest bytes used. */ 92 char name[50]; /* Description of what was hashed. */ 93} __packed; 94 95struct tcpa_table { 96 uint16_t max_entries; 97 uint16_t num_entries; 98 struct tcpa_entry entries[0]; 99} __packed; 100``` 101 102Single hash per PCR. No magic number or any other way of recognizing it. 103Endianness isn't specified. 104 105In principle can hold any hash with 512 bits or less. In practice, 106SHA-1 (for TPM1) and SHA-256 (TPM2) are used. 107 108Can be parsed by `cbmem`. 109 110##### Console dump format 111The first column describes the PCR index used for measurement. 112The second column is the hash of the raw data. The third column contains 113the hash algorithm used in the operation. The last column provides 114information about what is measured. First the namespace from where the data 115came from, CBFS or FMAP, then the name used to look up the data 116(region or file name). 117 118#### TPM 1.2 format 119Single hash per PCR (always SHA-1). First entry serves as a header, provides 120ID and version. Always little endian. Event data describes what is being hashed 121as a NUL-terminated string instead of providing the actual raw data. 122 123Can be parsed by at least `cbmem` and Linux (exports in both text and binary 124forms). 125 126Packed data in vendor info section of the header: 127```c 128uint8_t reserved; /* 0 */ 129uint8_t version_major; /* 1 */ 130uint8_t version_minor; /* 0 */ 131uint32_t magic; /* 0x31544243 ("CBT1" in LE) */ 132uint16_t max_entries; 133uint16_t num_entries; 134uint32_t entry_size; 135``` 136All fields are little endian. 137 138#### TPM 2.0 format 139One or more hashes per PCR, but implementation is limited to single hash (SHA-1, 140SHA-256, SHA-384 or SHA-512). First entry is overall compatible with TPM 1.2 and 141serves as a header with ID, version and number of hashing algorithms used. 142Always little endian. Event data describes what is being hashed as a 143NUL-terminated string instead of providing the actual raw data. 144 145By default SHA-1 is used for TPM1 and SHA-256 for TPM2. Other options are 146selectable via kconfig menu. 147 148Can be parsed by at least `cbmem`, Linux (exports only binary form) and 149[Skiboot][skiboot]. 150 151[skiboot]: https://github.com/open-power/skiboot/ 152 153Packed data in vendor info section of the header: 154```c 155uint8_t reserved; /* 0 */ 156uint8_t version_major; /* 1 */ 157uint8_t version_minor; /* 0 */ 158uint32_t magic; /* 0x32544243 ("CBT2" in LE) */ 159uint16_t max_entries; 160uint16_t num_entries; 161uint32_t entry_size; 162``` 163All fields are little endian. 164 165#### Example: 166```bash 167PCR-2 e8f2b57c9ec5ea06d1bbd3240a753974d4c3e7c8cd305c20a8ea26eed906dc89 SHA256 [FMAP: COREBOOT CBFS: bootblock] 168PCR-2 309a5fcb231d3a39127de2521792f332f9a69e05675ec52535d2dcded756dc19 SHA256 [FMAP: COREBOOT CBFS: fallback/verstage] 169PCR-2 0fbba07a833d4dcfc7024eaf313661a0ba8f80a05c6d29b8801c612e10e60dee SHA256 [FMAP: RO_VPD] 170PCR-2 431681113ed44cbf6f68a12c6e5687e901052f1d728a4777b2ad36e559962047 SHA256 [FMAP: GBB] 171PCR-2 f47a8ec3e9aff2318d896942282ad4fe37d6391c82914f54a5da8a37de1300c6 SHA256 [FMAP: SI_DESC] 172PCR-3 237f6f567f8597dbdff0a00690d34d21616af0dbe434b9a2d432b136c012765f SHA256 [FMAP: SI_ME] 173PCR-2 7d2c7ac4888bfd75cd5f56e8d61f69595121183afc81556c876732fd3782c62f SHA256 [FMAP: SI_GBE] 174PCR-0 62571891215b4efc1ceab744ce59dd0b66ea6f73 SHA1 [GBB flags] 175PCR-1 a66c8c2cda246d332d0c2025b6266e1e23c89410051002f46bfad1c9265f43d0 SHA256 [GBB HWID] 176PCR-2 ceca357524caf8fc73f5fa130f05a75293031962af884e18990d281eb259f5ff SHA256 [FMAP: FW_MAIN_B CBFS: fallback/romstage] 177PCR-2 548a097604e0a975de76f98b04c7f0b0ddec03883dd69179e47a784704a1c571 SHA256 [FMAP: FW_MAIN_B CBFS: fspm.bin] 178PCR-2 1e86b27008818244c221df2436b0113bd20a86ec6ec9d8259defe87f45d2f604 SHA256 [FMAP: FW_MAIN_B CBFS: spd2.bin] 179PCR-2 05d78005fcfc9edd4ca5625f11b1f49991d17bdb7cee33b72e722bc785db55ae SHA256 [FMAP: FW_MAIN_B CBFS: fallback/postcar] 180PCR-2 c13e95829af12a584046f1a6f3e1f6e4af691209324cfeeec573633399384141 SHA256 [FMAP: FW_MAIN_B CBFS: fallback/ramstage] 181PCR-2 a6ec2761b597abd252dba2a7237140ef4a5a8e0d47cad8afb65fa16314413401 SHA256 [FMAP: FW_MAIN_B CBFS: cpu_microcode_blob.bin] 182PCR-2 c81ffa40df0b6cd6cfde4f476d452a1f6f2217bc96a3b98a4fa4a037ee7039cf SHA256 [FMAP: FW_MAIN_B CBFS: fsps.bin] 183PCR-2 4e95f57bbf3c6627eb1c72be9c48df3aaa8e6da4f5f63d85e554cf6803505609 SHA256 [FMAP: FW_MAIN_B CBFS: vbt.bin] 184PCR-3 b7663f611ecf8637a59d72f623ae92a456c30377d4175e96021c85362f0323c8 SHA256 [FMAP: RW_NVRAM] 185PCR-2 178561f046e2adbc621b12b47d65be82756128e2a1fe5116b53ef3637da700e8 SHA256 [FMAP: FW_MAIN_B CBFS: fallback/dsdt.aml] 186PCR-2 091706f5fce3eb123dd9b96c15a9dcc459a694f5e5a86e7bf6064b819a8575c7 SHA256 [FMAP: FW_MAIN_B CBFS: fallback/payload] 187``` 188 189#### Dump TPM eventlog in the OS: 190```bash 191cbmem -L 192``` 193 194#### Get CBFS file and print the hash 195```bash 196cbfstool coreboot.rom extract -r COREBOOT -n fallback/romstage -U -f /dev/stdout | sha256sum 197``` 198 199#### Get FMAP partition and print the hash 200```bash 201cbfstool coreboot.rom read -n SI_ME -f /dev/stdout | sha256sum 202``` 203 204## DRTM 205Certain hardware platforms, for example those with Intel TXT or AMD-V, provide 206a mechanism to dynamically execute a CRTM, referred to as the "Dynamic 207CRTM" (D-CRTM), at any point and repeatedly during a single power life-cycle of 208a system. The trust chain constructed by this D-CRTM is referred to as the 209"Dynamic Root of Trust for Measurement" (DRTM) trust chain. On platforms with 210Intel TXT and AMD-V, the D-CRTM is the CPU itself, which is the reason for these 211capabilities being referred to as having a "Root of Trust" (RoT) rooted in 212hardware. 213 214To provide as an authority assertion and for the DRTM trust chain attestations 215to co-exist with the SRTM trust chain, the TPM provides localities, localities 2161 - 4, which restrict access to a subset of the Platform Configuration 217Registers (PCR), specifically the DRTM PCRs 17 - 22. The mechanism to assert 218authority for access to these localities is platform specific, though the 219intention was for it to be a hardware mechanism. On Intel x86 platforms this is 220controlled through communication between the CPU and the PCH to determine if 221the "Dynamic Launch" instruction, `GETSEC[SENTER]`, was executed and that the 222CPU is in SMX mode. For AMD x86 platforms, this controlled with the APU with a 223similar enforcement that the "Dynamic Launch" instruction, `SKINIT`, was 224executed. 225 226## Platform Configuration Registers 227PCRs are allocated as follows: 228* PCRs 0-15 are SRTM PCRs. 229 - PCRs 0-7 are reserved for firmware usage. 230* PCR 16 is the debug PCR. 231* PCRs 17-22 are DRTM PCRs (PCR 22 is resettable from locality 1). 232* PCR 23 is the application/user PCR and is resettable from locality 0. 233 234coreboot uses 3 or 4 PCRs in order to store the measurements. PCRs 4-7 are left 235empty. 236 237The firmware computes the hash and passes it to TPM. 238 239The bank used by the TPM depends on the selected eventlog format. CBFS hashes 240use the same algorithm as the bank. However, GBB flags are always hashed by 241SHA-1 and GBB HWID by SHA-256. This results in these hashes being truncated or 242extended with zeroes in eventlog and on passing them to TPM. 243 244### If CHROMEOS kconfig option is set 245vboot-specific (non-standard) PCR usage. 246 247* PCR-0 - SHA1 of Google vboot GBB flags. 248* PCR-1 - SHA256 of Google vboot GBB HWID. 249* PCR-2 - Hash of Root of Trust for Measurement which includes all stages, 250 data and blobs. 251* PCR-3 - Hash of runtime data like hwinfo.hex or MRC cache. 252 253### If CHROMEOS kconfig option is NOT set 254See [TPM1.2 Specification][TPM12] (section 3.3.3) and 255[TPM2.0 Specification][TPM20] (section 3.3.4) for PCR assignment information. 256 257* PCR-0 - Unused. 258* PCR-1 - SHA1 of Google vboot GBB flags, SHA256 of Google vboot GBB HWID. 259* PCR-2 - Hash of Root of Trust for Measurement which includes all stages, 260 data and blobs. 261* PCR-3 - Hash of runtime data like hwinfo.hex or MRC cache. 262 263[TPM12]: https://trustedcomputinggroup.org/wp-content/uploads/TCG_PCClientImplementation_1-21_1_00.pdf 264[TPM20]: https://trustedcomputinggroup.org/wp-content/uploads/TCG_PCClient_PFP_r1p05_v23_pub.pdf 265
