xref: /aosp_15_r20/external/mesa3d/src/gallium/winsys/svga/drm/vmw_screen.h (revision 6104692788411f58d303aa86923a9ff6ecaded22)
1 /*
2  * Copyright (c) 2009-2024 Broadcom. All Rights Reserved.
3  * The term “Broadcom” refers to Broadcom Inc.
4  * and/or its subsidiaries.
5  * SPDX-License-Identifier: MIT
6  */
7 
8 /**
9  * @file
10  * Common definitions for the VMware SVGA winsys.
11  *
12  * @author Jose Fonseca <[email protected]>
13  */
14 
15 
16 #ifndef VMW_SCREEN_H_
17 #define VMW_SCREEN_H_
18 
19 
20 #include "util/compiler.h"
21 #include "pipe/p_state.h"
22 
23 #include "svga_winsys.h"
24 #include "pipebuffer/pb_buffer_fenced.h"
25 #include "util/u_thread.h"
26 #include <sys/types.h>
27 
28 #define VMW_GMR_POOL_SIZE (16*1024*1024)
29 #define VMW_QUERY_POOL_SIZE (8192)
30 #define VMW_DEBUG_FLUSH_STACK 10
31 
32 /*
33  * Something big, but arbitrary. The kernel reports an error if it can't
34  * handle this, and the svga driver will resort to multiple partial
35  * uploads.
36  */
37 #define VMW_MAX_BUFFER_SIZE (512*1024*1024)
38 
39 struct pb_manager;
40 struct vmw_region;
41 
42 struct vmw_cap_3d {
43    bool has_cap;
44    SVGA3dDevCapResult result;
45 };
46 
47 struct vmw_winsys_screen
48 {
49    struct svga_winsys_screen base;
50 
51    struct {
52       int drm_fd;
53       uint32_t hwversion;
54       uint32_t num_cap_3d;
55       struct vmw_cap_3d *cap_3d;
56       uint64_t max_mob_memory;
57       uint64_t max_surface_memory;
58       uint64_t max_texture_size;
59       bool have_drm_2_6;
60       bool have_drm_2_9;
61       uint32_t drm_execbuf_version;
62       bool have_drm_2_15;
63       bool have_drm_2_16;
64       bool have_drm_2_17;
65       bool have_drm_2_18;
66       bool have_drm_2_19;
67       bool have_drm_2_20;
68    } ioctl;
69 
70    struct {
71       struct pb_manager *dma_base;
72       struct pb_manager *dma_mm;
73       struct pb_manager *query_mm;
74       struct pb_manager *query_fenced;
75       struct pb_manager *dma_fenced;
76       struct pb_manager *dma_cache;
77       struct pb_manager *dma_slab;
78       struct pb_manager *dma_slab_fenced;
79    } pools;
80 
81    struct pb_fence_ops *fence_ops;
82 
83 #ifdef VMX86_STATS
84    /*
85     * mksGuestStats TLS array; length must be power of two
86     */
87    struct {
88       void *     stat_pages;
89       uint64_t   stat_id;
90       uint32_t   pid;
91    } mksstat_tls[64];
92 
93 #endif
94    /*
95     * Screen instances
96     */
97    dev_t device;
98    int open_count;
99 
100    cnd_t cs_cond;
101    mtx_t cs_mutex;
102 
103    bool force_coherent;
104    bool cache_maps;
105 };
106 
107 
108 static inline struct vmw_winsys_screen *
vmw_winsys_screen(struct svga_winsys_screen * base)109 vmw_winsys_screen(struct svga_winsys_screen *base)
110 {
111    return (struct vmw_winsys_screen *)base;
112 }
113 
114 /*  */
115 uint32_t
116 vmw_region_size(struct vmw_region *region);
117 
118 uint32
119 vmw_ioctl_context_create(struct vmw_winsys_screen *vws);
120 
121 uint32
122 vmw_ioctl_extended_context_create(struct vmw_winsys_screen *vws,
123                                   bool vgpu10);
124 
125 void
126 vmw_ioctl_context_destroy(struct vmw_winsys_screen *vws,
127                           uint32 cid);
128 
129 uint32
130 vmw_ioctl_surface_create(struct vmw_winsys_screen *vws,
131                          SVGA3dSurface1Flags flags,
132                          SVGA3dSurfaceFormat format,
133                          unsigned usage,
134                          SVGA3dSize size,
135                          uint32 numFaces,
136                          uint32 numMipLevels,
137                          unsigned sampleCount);
138 uint32
139 vmw_ioctl_gb_surface_create(struct vmw_winsys_screen *vws,
140                             SVGA3dSurfaceAllFlags flags,
141                             SVGA3dSurfaceFormat format,
142                             unsigned usage,
143                             SVGA3dSize size,
144                             uint32 numFaces,
145                             uint32 numMipLevels,
146                             unsigned sampleCount,
147                             uint32 buffer_handle,
148                             SVGA3dMSPattern multisamplePattern,
149                             SVGA3dMSQualityLevel qualityLevel,
150                             struct vmw_region **p_region);
151 
152 int
153 vmw_ioctl_gb_surface_ref(struct vmw_winsys_screen *vws,
154                          const struct winsys_handle *whandle,
155                          SVGA3dSurfaceAllFlags *flags,
156                          SVGA3dSurfaceFormat *format,
157                          uint32_t *numMipLevels,
158                          uint32_t *handle,
159                          struct vmw_region **p_region);
160 
161 void
162 vmw_ioctl_surface_destroy(struct vmw_winsys_screen *vws,
163                           uint32 sid);
164 
165 void
166 vmw_ioctl_command(struct vmw_winsys_screen *vws,
167                   int32_t cid,
168                   uint32_t throttle_us,
169                   void *commands,
170                   uint32_t size,
171                   struct pipe_fence_handle **fence,
172                   int32_t imported_fence_fd,
173                   uint32_t flags);
174 
175 struct vmw_region *
176 vmw_ioctl_region_create(struct vmw_winsys_screen *vws, uint32_t size);
177 
178 void
179 vmw_ioctl_region_destroy(struct vmw_region *region);
180 
181 struct SVGAGuestPtr
182 vmw_ioctl_region_ptr(struct vmw_region *region);
183 
184 void *
185 vmw_ioctl_region_map(struct vmw_region *region);
186 void
187 vmw_ioctl_region_unmap(struct vmw_region *region);
188 
189 
190 int
191 vmw_ioctl_fence_finish(struct vmw_winsys_screen *vws,
192                        uint32_t handle, uint32_t flags);
193 
194 int
195 vmw_ioctl_fence_signalled(struct vmw_winsys_screen *vws,
196                           uint32_t handle, uint32_t flags);
197 
198 void
199 vmw_ioctl_fence_unref(struct vmw_winsys_screen *vws,
200 		      uint32_t handle);
201 
202 uint32
203 vmw_ioctl_shader_create(struct vmw_winsys_screen *vws,
204 			SVGA3dShaderType type,
205 			uint32 code_len);
206 void
207 vmw_ioctl_shader_destroy(struct vmw_winsys_screen *vws, uint32 shid);
208 
209 int
210 vmw_ioctl_syncforcpu(struct vmw_region *region,
211                      bool dont_block,
212                      bool readonly,
213                      bool allow_cs);
214 void
215 vmw_ioctl_releasefromcpu(struct vmw_region *region,
216                          bool readonly,
217                          bool allow_cs);
218 /* Initialize parts of vmw_winsys_screen at startup:
219  */
220 bool vmw_ioctl_init(struct vmw_winsys_screen *vws);
221 bool vmw_pools_init(struct vmw_winsys_screen *vws);
222 bool vmw_query_pools_init(struct vmw_winsys_screen *vws);
223 bool vmw_winsys_screen_init_svga(struct vmw_winsys_screen *vws);
224 
225 void vmw_ioctl_cleanup(struct vmw_winsys_screen *vws);
226 void vmw_pools_cleanup(struct vmw_winsys_screen *vws);
227 
228 struct vmw_winsys_screen *vmw_winsys_create(int fd);
229 void vmw_winsys_destroy(struct vmw_winsys_screen *sws);
230 void vmw_winsys_screen_set_throttling(struct pipe_screen *screen,
231 				      uint32_t throttle_us);
232 
233 struct pb_manager *
234 simple_fenced_bufmgr_create(struct pb_manager *provider,
235 			    struct pb_fence_ops *ops);
236 void
237 vmw_fences_signal(struct pb_fence_ops *fence_ops,
238                   uint32_t signaled,
239                   uint32_t emitted,
240                   bool has_emitted);
241 
242 struct svga_winsys_gb_shader *
243 vmw_svga_winsys_shader_create(struct svga_winsys_screen *sws,
244 			      SVGA3dShaderType type,
245 			      const uint32 *bytecode,
246 			      uint32 bytecodeLen);
247 void
248 vmw_svga_winsys_shader_destroy(struct svga_winsys_screen *sws,
249 			       struct svga_winsys_gb_shader *shader);
250 
251 size_t
252 vmw_svga_winsys_stats_len(void);
253 
254 #endif /* VMW_SCREEN_H_ */
255