1 /* Copyright 2022 Advanced Micro Devices, Inc. 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice shall be included in 11 * all copies or substantial portions of the Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 19 * OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * Authors: AMD 22 * 23 */ 24 #pragma once 25 26 #include "mpc.h" 27 #include "reg_helper.h" 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #define MPC_REG_LIST_VPE10_COMMON(id) \ 34 SRIDFVL1(VPMPC_CLOCK_CONTROL), SRIDFVL1(VPMPC_SOFT_RESET), SRIDFVL1(VPMPC_CRC_CTRL), \ 35 SRIDFVL1(VPMPC_CRC_SEL_CONTROL), SRIDFVL1(VPMPC_CRC_RESULT_AR), \ 36 SRIDFVL1(VPMPC_CRC_RESULT_GB), SRIDFVL1(VPMPC_CRC_RESULT_C), SRIDFVL1(VPMPC_BYPASS_BG_AR), \ 37 SRIDFVL1(VPMPC_BYPASS_BG_GB), SRIDFVL1(VPMPC_HOST_READ_CONTROL), \ 38 SRIDFVL1(VPMPC_PENDING_STATUS_MISC), \ 39 SRIDFVL2(MUX, VPMPC_OUT, id), \ 40 SRIDFVL2(FLOAT_CONTROL, VPMPC_OUT, id), SRIDFVL2(DENORM_CONTROL, VPMPC_OUT, id), \ 41 SRIDFVL2(DENORM_CLAMP_G_Y, VPMPC_OUT, id), SRIDFVL2(DENORM_CLAMP_B_CB, VPMPC_OUT, id), \ 42 SRIDFVL3(CSC_COEF_FORMAT, VPMPC_OUT, id), SRIDFVL2(CSC_MODE, VPMPC_OUT, id), \ 43 SRIDFVL2(CSC_C11_C12_A, VPMPC_OUT, id), SRIDFVL2(CSC_C13_C14_A, VPMPC_OUT, id), \ 44 SRIDFVL2(CSC_C21_C22_A, VPMPC_OUT, id), SRIDFVL2(CSC_C23_C24_A, VPMPC_OUT, id), \ 45 SRIDFVL2(CSC_C31_C32_A, VPMPC_OUT, id), SRIDFVL2(CSC_C33_C34_A, VPMPC_OUT, id), \ 46 SRIDFVL(VPMPCC_TOP_SEL, VPMPCC, id), \ 47 SRIDFVL(VPMPCC_BOT_SEL, VPMPCC, id), SRIDFVL(VPMPCC_VPOPP_ID, VPMPCC, id), \ 48 SRIDFVL(VPMPCC_CONTROL, VPMPCC, id), SRIDFVL(VPMPCC_TOP_GAIN, VPMPCC, id), \ 49 SRIDFVL(VPMPCC_BOT_GAIN_INSIDE, VPMPCC, id), SRIDFVL(VPMPCC_BOT_GAIN_OUTSIDE, VPMPCC, id), \ 50 SRIDFVL(VPMPCC_MOVABLE_CM_LOCATION_CONTROL, VPMPCC, id), \ 51 SRIDFVL(VPMPCC_BG_R_CR, VPMPCC, id), SRIDFVL(VPMPCC_BG_G_Y, VPMPCC, id), \ 52 SRIDFVL(VPMPCC_BG_B_CB, VPMPCC, id), SRIDFVL(VPMPCC_MEM_PWR_CTRL, VPMPCC, id), \ 53 SRIDFVL(VPMPCC_STATUS, VPMPCC, id), SRIDFVL(VPMPCC_OGAM_CONTROL, VPMPCC_OGAM, id), \ 54 SRIDFVL(VPMPCC_OGAM_LUT_INDEX, VPMPCC_OGAM, id), \ 55 SRIDFVL(VPMPCC_OGAM_LUT_DATA, VPMPCC_OGAM, id), \ 56 SRIDFVL(VPMPCC_OGAM_LUT_CONTROL, VPMPCC_OGAM, id), \ 57 SRIDFVL(VPMPCC_OGAM_RAMA_START_CNTL_B, VPMPCC_OGAM, id), \ 58 SRIDFVL(VPMPCC_OGAM_RAMA_START_CNTL_G, VPMPCC_OGAM, id), \ 59 SRIDFVL(VPMPCC_OGAM_RAMA_START_CNTL_R, VPMPCC_OGAM, id), \ 60 SRIDFVL(VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B, VPMPCC_OGAM, id), \ 61 SRIDFVL(VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G, VPMPCC_OGAM, id), \ 62 SRIDFVL(VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R, VPMPCC_OGAM, id), \ 63 SRIDFVL(VPMPCC_OGAM_RAMA_START_BASE_CNTL_B, VPMPCC_OGAM, id), \ 64 SRIDFVL(VPMPCC_OGAM_RAMA_START_BASE_CNTL_G, VPMPCC_OGAM, id), \ 65 SRIDFVL(VPMPCC_OGAM_RAMA_START_BASE_CNTL_R, VPMPCC_OGAM, id), \ 66 SRIDFVL(VPMPCC_OGAM_RAMA_END_CNTL1_B, VPMPCC_OGAM, id), \ 67 SRIDFVL(VPMPCC_OGAM_RAMA_END_CNTL2_B, VPMPCC_OGAM, id), \ 68 SRIDFVL(VPMPCC_OGAM_RAMA_END_CNTL1_G, VPMPCC_OGAM, id), \ 69 SRIDFVL(VPMPCC_OGAM_RAMA_END_CNTL2_G, VPMPCC_OGAM, id), \ 70 SRIDFVL(VPMPCC_OGAM_RAMA_END_CNTL1_R, VPMPCC_OGAM, id), \ 71 SRIDFVL(VPMPCC_OGAM_RAMA_END_CNTL2_R, VPMPCC_OGAM, id), \ 72 SRIDFVL(VPMPCC_OGAM_RAMA_OFFSET_B, VPMPCC_OGAM, id), \ 73 SRIDFVL(VPMPCC_OGAM_RAMA_OFFSET_G, VPMPCC_OGAM, id), \ 74 SRIDFVL(VPMPCC_OGAM_RAMA_OFFSET_R, VPMPCC_OGAM, id), \ 75 SRIDFVL(VPMPCC_OGAM_RAMA_REGION_0_1, VPMPCC_OGAM, id), \ 76 SRIDFVL(VPMPCC_OGAM_RAMA_REGION_2_3, VPMPCC_OGAM, id), \ 77 SRIDFVL(VPMPCC_OGAM_RAMA_REGION_4_5, VPMPCC_OGAM, id), \ 78 SRIDFVL(VPMPCC_OGAM_RAMA_REGION_6_7, VPMPCC_OGAM, id), \ 79 SRIDFVL(VPMPCC_OGAM_RAMA_REGION_8_9, VPMPCC_OGAM, id), \ 80 SRIDFVL(VPMPCC_OGAM_RAMA_REGION_10_11, VPMPCC_OGAM, id), \ 81 SRIDFVL(VPMPCC_OGAM_RAMA_REGION_12_13, VPMPCC_OGAM, id), \ 82 SRIDFVL(VPMPCC_OGAM_RAMA_REGION_14_15, VPMPCC_OGAM, id), \ 83 SRIDFVL(VPMPCC_OGAM_RAMA_REGION_16_17, VPMPCC_OGAM, id), \ 84 SRIDFVL(VPMPCC_OGAM_RAMA_REGION_18_19, VPMPCC_OGAM, id), \ 85 SRIDFVL(VPMPCC_OGAM_RAMA_REGION_20_21, VPMPCC_OGAM, id), \ 86 SRIDFVL(VPMPCC_OGAM_RAMA_REGION_22_23, VPMPCC_OGAM, id), \ 87 SRIDFVL(VPMPCC_OGAM_RAMA_REGION_24_25, VPMPCC_OGAM, id), \ 88 SRIDFVL(VPMPCC_OGAM_RAMA_REGION_26_27, VPMPCC_OGAM, id), \ 89 SRIDFVL(VPMPCC_OGAM_RAMA_REGION_28_29, VPMPCC_OGAM, id), \ 90 SRIDFVL(VPMPCC_OGAM_RAMA_REGION_30_31, VPMPCC_OGAM, id), \ 91 SRIDFVL(VPMPCC_OGAM_RAMA_REGION_32_33, VPMPCC_OGAM, id), \ 92 SRIDFVL(VPMPCC_GAMUT_REMAP_COEF_FORMAT, VPMPCC_OGAM, id), \ 93 SRIDFVL(VPMPCC_GAMUT_REMAP_MODE, VPMPCC_OGAM, id), \ 94 SRIDFVL(VPMPC_GAMUT_REMAP_C11_C12_A, VPMPCC_OGAM, id), \ 95 SRIDFVL(VPMPC_GAMUT_REMAP_C13_C14_A, VPMPCC_OGAM, id), \ 96 SRIDFVL(VPMPC_GAMUT_REMAP_C21_C22_A, VPMPCC_OGAM, id), \ 97 SRIDFVL(VPMPC_GAMUT_REMAP_C23_C24_A, VPMPCC_OGAM, id), \ 98 SRIDFVL(VPMPC_GAMUT_REMAP_C31_C32_A, VPMPCC_OGAM, id), \ 99 SRIDFVL(VPMPC_GAMUT_REMAP_C33_C34_A, VPMPCC_OGAM, id), \ 100 SRIDFVL(VPMPCC_MCM_1DLUT_CONTROL, VPMPCC_MCM, id), \ 101 SRIDFVL(VPMPCC_MCM_1DLUT_LUT_INDEX, VPMPCC_MCM, id), \ 102 SRIDFVL(VPMPCC_MCM_1DLUT_LUT_DATA, VPMPCC_MCM, id), \ 103 SRIDFVL(VPMPCC_MCM_1DLUT_LUT_CONTROL, VPMPCC_MCM, id), \ 104 SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B, VPMPCC_MCM, id), \ 105 SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G, VPMPCC_MCM, id), \ 106 SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R, VPMPCC_MCM, id), \ 107 SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B, VPMPCC_MCM, id), \ 108 SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G, VPMPCC_MCM, id), \ 109 SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R, VPMPCC_MCM, id), \ 110 SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B, VPMPCC_MCM, id), \ 111 SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G, VPMPCC_MCM, id), \ 112 SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R, VPMPCC_MCM, id), \ 113 SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B, VPMPCC_MCM, id), \ 114 SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B, VPMPCC_MCM, id), \ 115 SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G, VPMPCC_MCM, id), \ 116 SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G, VPMPCC_MCM, id), \ 117 SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R, VPMPCC_MCM, id), \ 118 SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R, VPMPCC_MCM, id), \ 119 SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_OFFSET_B, VPMPCC_MCM, id), \ 120 SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_OFFSET_G, VPMPCC_MCM, id), \ 121 SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_OFFSET_R, VPMPCC_MCM, id), \ 122 SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_REGION_0_1, VPMPCC_MCM, id), \ 123 SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_REGION_2_3, VPMPCC_MCM, id), \ 124 SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_REGION_4_5, VPMPCC_MCM, id), \ 125 SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_REGION_6_7, VPMPCC_MCM, id), \ 126 SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_REGION_8_9, VPMPCC_MCM, id), \ 127 SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_REGION_10_11, VPMPCC_MCM, id), \ 128 SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_REGION_12_13, VPMPCC_MCM, id), \ 129 SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_REGION_14_15, VPMPCC_MCM, id), \ 130 SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_REGION_16_17, VPMPCC_MCM, id), \ 131 SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_REGION_18_19, VPMPCC_MCM, id), \ 132 SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_REGION_20_21, VPMPCC_MCM, id), \ 133 SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_REGION_22_23, VPMPCC_MCM, id), \ 134 SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_REGION_24_25, VPMPCC_MCM, id), \ 135 SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_REGION_26_27, VPMPCC_MCM, id), \ 136 SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_REGION_28_29, VPMPCC_MCM, id), \ 137 SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_REGION_30_31, VPMPCC_MCM, id), \ 138 SRIDFVL(VPMPCC_MCM_1DLUT_RAMA_REGION_32_33, VPMPCC_MCM, id), \ 139 SRIDFVL(VPMPCC_MCM_MEM_PWR_CTRL, VPMPCC_MCM, id) 140 141 #define MPC_REG_LIST_VPE10(id) \ 142 MPC_REG_LIST_VPE10_COMMON(id), \ 143 SRIDFVL(VPMPCC_MCM_SHAPER_CONTROL, VPMPCC_MCM, id), \ 144 SRIDFVL(VPMPCC_MCM_SHAPER_OFFSET_R, VPMPCC_MCM, id), \ 145 SRIDFVL(VPMPCC_MCM_SHAPER_OFFSET_G, VPMPCC_MCM, id), \ 146 SRIDFVL(VPMPCC_MCM_SHAPER_OFFSET_B, VPMPCC_MCM, id), \ 147 SRIDFVL(VPMPCC_MCM_SHAPER_SCALE_R, VPMPCC_MCM, id), \ 148 SRIDFVL(VPMPCC_MCM_SHAPER_SCALE_G_B, VPMPCC_MCM, id), \ 149 SRIDFVL(VPMPCC_MCM_SHAPER_LUT_INDEX, VPMPCC_MCM, id), \ 150 SRIDFVL(VPMPCC_MCM_SHAPER_LUT_DATA, VPMPCC_MCM, id), \ 151 SRIDFVL(VPMPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, VPMPCC_MCM, id), \ 152 SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_START_CNTL_B, VPMPCC_MCM, id), \ 153 SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_START_CNTL_G, VPMPCC_MCM, id), \ 154 SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_START_CNTL_R, VPMPCC_MCM, id), \ 155 SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_END_CNTL_B, VPMPCC_MCM, id), \ 156 SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_END_CNTL_G, VPMPCC_MCM, id), \ 157 SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_END_CNTL_R, VPMPCC_MCM, id), \ 158 SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_REGION_0_1, VPMPCC_MCM, id), \ 159 SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_REGION_2_3, VPMPCC_MCM, id), \ 160 SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_REGION_4_5, VPMPCC_MCM, id), \ 161 SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_REGION_6_7, VPMPCC_MCM, id), \ 162 SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_REGION_8_9, VPMPCC_MCM, id), \ 163 SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_REGION_10_11, VPMPCC_MCM, id), \ 164 SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_REGION_12_13, VPMPCC_MCM, id), \ 165 SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_REGION_14_15, VPMPCC_MCM, id), \ 166 SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_REGION_16_17, VPMPCC_MCM, id), \ 167 SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_REGION_18_19, VPMPCC_MCM, id), \ 168 SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_REGION_20_21, VPMPCC_MCM, id), \ 169 SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_REGION_22_23, VPMPCC_MCM, id), \ 170 SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_REGION_24_25, VPMPCC_MCM, id), \ 171 SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_REGION_26_27, VPMPCC_MCM, id), \ 172 SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_REGION_28_29, VPMPCC_MCM, id), \ 173 SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_REGION_30_31, VPMPCC_MCM, id), \ 174 SRIDFVL(VPMPCC_MCM_SHAPER_RAMA_REGION_32_33, VPMPCC_MCM, id), \ 175 SRIDFVL(VPMPCC_MCM_3DLUT_MODE, VPMPCC_MCM, id), \ 176 SRIDFVL(VPMPCC_MCM_3DLUT_INDEX, VPMPCC_MCM, id), \ 177 SRIDFVL(VPMPCC_MCM_3DLUT_DATA, VPMPCC_MCM, id), \ 178 SRIDFVL(VPMPCC_MCM_3DLUT_DATA_30BIT, VPMPCC_MCM, id), \ 179 SRIDFVL(VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL, VPMPCC_MCM, id), \ 180 SRIDFVL(VPMPCC_MCM_3DLUT_OUT_NORM_FACTOR, VPMPCC_MCM, id), \ 181 SRIDFVL(VPMPCC_MCM_3DLUT_OUT_OFFSET_R, VPMPCC_MCM, id), \ 182 SRIDFVL(VPMPCC_MCM_3DLUT_OUT_OFFSET_G, VPMPCC_MCM, id), \ 183 SRIDFVL(VPMPCC_MCM_3DLUT_OUT_OFFSET_B, VPMPCC_MCM, id) 184 185 #define MPC_FIELD_LIST_VPE10_COMMON(post_fix) \ 186 SFRB(VPECLK_R_GATE_DISABLE, VPMPC_CLOCK_CONTROL, post_fix), \ 187 SFRB(VPMPC_TEST_CLK_SEL, VPMPC_CLOCK_CONTROL, post_fix), \ 188 SFRB(VPMPCC0_SOFT_RESET, VPMPC_SOFT_RESET, post_fix), \ 189 SFRB(VPMPC_SFR0_SOFT_RESET, VPMPC_SOFT_RESET, post_fix), \ 190 SFRB(VPMPC_SFT0_SOFT_RESET, VPMPC_SOFT_RESET, post_fix), \ 191 SFRB(VPMPC_SOFT_RESET, VPMPC_SOFT_RESET, post_fix), \ 192 SFRB(VPMPC_CRC_EN, VPMPC_CRC_CTRL, post_fix), \ 193 SFRB(VPMPC_CRC_CONT_EN, VPMPC_CRC_CTRL, post_fix), \ 194 SFRB(VPMPC_CRC_SRC_SEL, VPMPC_CRC_CTRL, post_fix), \ 195 SFRB(VPMPC_CRC_ONE_SHOT_PENDING, VPMPC_CRC_CTRL, post_fix), \ 196 SFRB(VPMPC_CRC_UPDATE_ENABLED, VPMPC_CRC_CTRL, post_fix), \ 197 SFRB(VPMPC_CRC_UPDATE_LOCK, VPMPC_CRC_CTRL, post_fix), \ 198 SFRB(VPMPC_CRC_VPDPP_SEL, VPMPC_CRC_SEL_CONTROL, post_fix), \ 199 SFRB(VPMPC_CRC_VPOPP_SEL, VPMPC_CRC_SEL_CONTROL, post_fix), \ 200 SFRB(VPMPC_CRC_MASK, VPMPC_CRC_SEL_CONTROL, post_fix), \ 201 SFRB(VPMPC_CRC_RESULT_A, VPMPC_CRC_RESULT_AR, post_fix), \ 202 SFRB(VPMPC_CRC_RESULT_R, VPMPC_CRC_RESULT_AR, post_fix), \ 203 SFRB(VPMPC_CRC_RESULT_G, VPMPC_CRC_RESULT_GB, post_fix), \ 204 SFRB(VPMPC_CRC_RESULT_B, VPMPC_CRC_RESULT_GB, post_fix), \ 205 SFRB(VPMPC_CRC_RESULT_C, VPMPC_CRC_RESULT_C, post_fix), \ 206 SFRB(VPMPC_BYPASS_BG_ALPHA, VPMPC_BYPASS_BG_AR, post_fix), \ 207 SFRB(VPMPC_BYPASS_BG_R_CR, VPMPC_BYPASS_BG_AR, post_fix), \ 208 SFRB(VPMPC_BYPASS_BG_G_Y, VPMPC_BYPASS_BG_GB, post_fix), \ 209 SFRB(VPMPC_BYPASS_BG_B_CB, VPMPC_BYPASS_BG_GB, post_fix), \ 210 SFRB(HOST_READ_RATE_CONTROL, VPMPC_HOST_READ_CONTROL, post_fix), \ 211 SFRB(VPMPCC0_CONFIG_UPDATE_PENDING, VPMPC_PENDING_STATUS_MISC, post_fix), \ 212 SFRB(VPMPC_OUT_MUX, VPMPC_OUT0_MUX, post_fix), \ 213 SFRB(VPMPC_OUT_FLOAT_EN, VPMPC_OUT0_FLOAT_CONTROL, post_fix), \ 214 SFRB(VPMPC_OUT_DENORM_CLAMP_MIN_R_CR, VPMPC_OUT0_DENORM_CONTROL, post_fix), \ 215 SFRB(VPMPC_OUT_DENORM_CLAMP_MAX_R_CR, VPMPC_OUT0_DENORM_CONTROL, post_fix), \ 216 SFRB(VPMPC_OUT_DENORM_MODE, VPMPC_OUT0_DENORM_CONTROL, post_fix), \ 217 SFRB(VPMPC_OUT_DENORM_CLAMP_MIN_G_Y, VPMPC_OUT0_DENORM_CLAMP_G_Y, post_fix), \ 218 SFRB(VPMPC_OUT_DENORM_CLAMP_MAX_G_Y, VPMPC_OUT0_DENORM_CLAMP_G_Y, post_fix), \ 219 SFRB(VPMPC_OUT_DENORM_CLAMP_MIN_B_CB, VPMPC_OUT0_DENORM_CLAMP_B_CB, post_fix), \ 220 SFRB(VPMPC_OUT_DENORM_CLAMP_MAX_B_CB, VPMPC_OUT0_DENORM_CLAMP_B_CB, post_fix), \ 221 SFRB(VPMPC_OCSC0_COEF_FORMAT, VPMPC_OUT_CSC_COEF_FORMAT, post_fix), \ 222 SFRB(VPMPC_OCSC_MODE, VPMPC_OUT0_CSC_MODE, post_fix), \ 223 SFRB(VPMPC_OCSC_MODE_CURRENT, VPMPC_OUT0_CSC_MODE, post_fix), \ 224 SFRB(VPMPC_OCSC_C11_A, VPMPC_OUT0_CSC_C11_C12_A, post_fix), \ 225 SFRB(VPMPC_OCSC_C12_A, VPMPC_OUT0_CSC_C11_C12_A, post_fix), \ 226 SFRB(VPMPC_OCSC_C13_A, VPMPC_OUT0_CSC_C13_C14_A, post_fix), \ 227 SFRB(VPMPC_OCSC_C14_A, VPMPC_OUT0_CSC_C13_C14_A, post_fix), \ 228 SFRB(VPMPC_OCSC_C21_A, VPMPC_OUT0_CSC_C21_C22_A, post_fix), \ 229 SFRB(VPMPC_OCSC_C22_A, VPMPC_OUT0_CSC_C21_C22_A, post_fix), \ 230 SFRB(VPMPC_OCSC_C23_A, VPMPC_OUT0_CSC_C23_C24_A, post_fix), \ 231 SFRB(VPMPC_OCSC_C24_A, VPMPC_OUT0_CSC_C23_C24_A, post_fix), \ 232 SFRB(VPMPC_OCSC_C31_A, VPMPC_OUT0_CSC_C31_C32_A, post_fix), \ 233 SFRB(VPMPC_OCSC_C32_A, VPMPC_OUT0_CSC_C31_C32_A, post_fix), \ 234 SFRB(VPMPC_OCSC_C33_A, VPMPC_OUT0_CSC_C33_C34_A, post_fix), \ 235 SFRB(VPMPC_OCSC_C34_A, VPMPC_OUT0_CSC_C33_C34_A, post_fix), \ 236 SFRB(VPMPCC_TOP_SEL, VPMPCC_TOP_SEL, post_fix), \ 237 SFRB(VPMPCC_BOT_SEL, VPMPCC_BOT_SEL, post_fix), \ 238 SFRB(VPMPCC_VPOPP_ID, VPMPCC_VPOPP_ID, post_fix), \ 239 SFRB(VPMPCC_MODE, VPMPCC_CONTROL, post_fix), \ 240 SFRB(VPMPCC_ALPHA_BLND_MODE, VPMPCC_CONTROL, post_fix), \ 241 SFRB(VPMPCC_ALPHA_MULTIPLIED_MODE, VPMPCC_CONTROL, post_fix), \ 242 SFRB(VPMPCC_BLND_ACTIVE_OVERLAP_ONLY, VPMPCC_CONTROL, post_fix), \ 243 SFRB(VPMPCC_BOT_GAIN_MODE, VPMPCC_CONTROL, post_fix), \ 244 SFRB(VPMPCC_TOP_GAIN, VPMPCC_TOP_GAIN, post_fix), \ 245 SFRB(VPMPCC_BOT_GAIN_INSIDE, VPMPCC_BOT_GAIN_INSIDE, post_fix), \ 246 SFRB(VPMPCC_BOT_GAIN_OUTSIDE, VPMPCC_BOT_GAIN_OUTSIDE, post_fix), \ 247 SFRB(VPMPCC_MOVABLE_CM_LOCATION_CNTL, VPMPCC_MOVABLE_CM_LOCATION_CONTROL, post_fix), \ 248 SFRB(VPMPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT, VPMPCC_MOVABLE_CM_LOCATION_CONTROL, \ 249 post_fix), \ 250 SFRB(VPMPCC_BG_R_CR, VPMPCC_BG_R_CR, post_fix), \ 251 SFRB(VPMPCC_BG_G_Y, VPMPCC_BG_G_Y, post_fix), \ 252 SFRB(VPMPCC_BG_B_CB, VPMPCC_BG_B_CB, post_fix), \ 253 SFRB(VPMPCC_OGAM_MEM_PWR_FORCE, VPMPCC_MEM_PWR_CTRL, post_fix), \ 254 SFRB(VPMPCC_OGAM_MEM_PWR_DIS, VPMPCC_MEM_PWR_CTRL, post_fix), \ 255 SFRB(VPMPCC_OGAM_MEM_LOW_PWR_MODE, VPMPCC_MEM_PWR_CTRL, post_fix), \ 256 SFRB(VPMPCC_OGAM_MEM_PWR_STATE, VPMPCC_MEM_PWR_CTRL, post_fix), \ 257 SFRB(VPMPCC_IDLE, VPMPCC_STATUS, post_fix), SFRB(VPMPCC_BUSY, VPMPCC_STATUS, post_fix), \ 258 SFRB(VPMPCC_DISABLED, VPMPCC_STATUS, post_fix), \ 259 SFRB(VPMPCC_OGAM_MODE, VPMPCC_OGAM_CONTROL, post_fix), \ 260 SFRB(VPMPCC_OGAM_PWL_DISABLE, VPMPCC_OGAM_CONTROL, post_fix), \ 261 SFRB(VPMPCC_OGAM_MODE_CURRENT, VPMPCC_OGAM_CONTROL, post_fix), \ 262 SFRB(VPMPCC_OGAM_SELECT_CURRENT, VPMPCC_OGAM_CONTROL, post_fix), \ 263 SFRB(VPMPCC_OGAM_LUT_INDEX, VPMPCC_OGAM_LUT_INDEX, post_fix), \ 264 SFRB(VPMPCC_OGAM_LUT_DATA, VPMPCC_OGAM_LUT_DATA, post_fix), \ 265 SFRB(VPMPCC_OGAM_LUT_WRITE_COLOR_MASK, VPMPCC_OGAM_LUT_CONTROL, post_fix), \ 266 SFRB(VPMPCC_OGAM_LUT_READ_COLOR_SEL, VPMPCC_OGAM_LUT_CONTROL, post_fix), \ 267 SFRB(VPMPCC_OGAM_LUT_READ_DBG, VPMPCC_OGAM_LUT_CONTROL, post_fix), \ 268 SFRB(VPMPCC_OGAM_LUT_HOST_SEL, VPMPCC_OGAM_LUT_CONTROL, post_fix), \ 269 SFRB(VPMPCC_OGAM_LUT_CONFIG_MODE, VPMPCC_OGAM_LUT_CONTROL, post_fix), \ 270 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION_START_B, VPMPCC_OGAM_RAMA_START_CNTL_B, post_fix), \ 271 SFRB( \ 272 VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B, VPMPCC_OGAM_RAMA_START_CNTL_B, post_fix), \ 273 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION_START_G, VPMPCC_OGAM_RAMA_START_CNTL_G, post_fix), \ 274 SFRB( \ 275 VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G, VPMPCC_OGAM_RAMA_START_CNTL_G, post_fix), \ 276 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION_START_R, VPMPCC_OGAM_RAMA_START_CNTL_R, post_fix), \ 277 SFRB( \ 278 VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R, VPMPCC_OGAM_RAMA_START_CNTL_R, post_fix), \ 279 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B, VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B, \ 280 post_fix), \ 281 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G, VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G, \ 282 post_fix), \ 283 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R, VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R, \ 284 post_fix), \ 285 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_B, VPMPCC_OGAM_RAMA_START_BASE_CNTL_B, \ 286 post_fix), \ 287 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_G, VPMPCC_OGAM_RAMA_START_BASE_CNTL_G, \ 288 post_fix), \ 289 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_R, VPMPCC_OGAM_RAMA_START_BASE_CNTL_R, \ 290 post_fix), \ 291 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_B, VPMPCC_OGAM_RAMA_END_CNTL1_B, post_fix), \ 292 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION_END_B, VPMPCC_OGAM_RAMA_END_CNTL2_B, post_fix), \ 293 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B, VPMPCC_OGAM_RAMA_END_CNTL2_B, post_fix), \ 294 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_G, VPMPCC_OGAM_RAMA_END_CNTL1_G, post_fix), \ 295 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION_END_G, VPMPCC_OGAM_RAMA_END_CNTL2_G, post_fix), \ 296 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G, VPMPCC_OGAM_RAMA_END_CNTL2_G, post_fix), \ 297 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_R, VPMPCC_OGAM_RAMA_END_CNTL1_R, post_fix), \ 298 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION_END_R, VPMPCC_OGAM_RAMA_END_CNTL2_R, post_fix), \ 299 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R, VPMPCC_OGAM_RAMA_END_CNTL2_R, post_fix), \ 300 SFRB(VPMPCC_OGAM_RAMA_OFFSET_B, VPMPCC_OGAM_RAMA_OFFSET_B, post_fix), \ 301 SFRB(VPMPCC_OGAM_RAMA_OFFSET_G, VPMPCC_OGAM_RAMA_OFFSET_G, post_fix), \ 302 SFRB(VPMPCC_OGAM_RAMA_OFFSET_R, VPMPCC_OGAM_RAMA_OFFSET_R, post_fix), \ 303 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_0_1, post_fix), \ 304 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_0_1, post_fix), \ 305 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_0_1, post_fix), \ 306 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_0_1, post_fix), \ 307 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_2_3, post_fix), \ 308 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_2_3, post_fix), \ 309 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_2_3, post_fix), \ 310 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_2_3, post_fix), \ 311 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_4_5, post_fix), \ 312 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_4_5, post_fix), \ 313 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_4_5, post_fix), \ 314 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_4_5, post_fix), \ 315 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_6_7, post_fix), \ 316 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_6_7, post_fix), \ 317 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_6_7, post_fix), \ 318 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_6_7, post_fix), \ 319 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_8_9, post_fix), \ 320 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_8_9, post_fix), \ 321 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_8_9, post_fix), \ 322 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_8_9, post_fix), \ 323 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_10_11, post_fix), \ 324 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_10_11, post_fix), \ 325 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_10_11, post_fix), \ 326 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_10_11, post_fix), \ 327 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_12_13, post_fix), \ 328 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_12_13, post_fix), \ 329 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_12_13, post_fix), \ 330 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_12_13, post_fix), \ 331 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_14_15, post_fix), \ 332 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_14_15, post_fix), \ 333 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_14_15, post_fix), \ 334 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_14_15, post_fix), \ 335 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_16_17, post_fix), \ 336 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_16_17, post_fix), \ 337 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_16_17, post_fix), \ 338 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_16_17, post_fix), \ 339 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_18_19, post_fix), \ 340 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_18_19, post_fix), \ 341 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_18_19, post_fix), \ 342 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_18_19, post_fix), \ 343 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_20_21, post_fix), \ 344 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_20_21, post_fix), \ 345 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_20_21, post_fix), \ 346 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_20_21, post_fix), \ 347 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_22_23, post_fix), \ 348 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_22_23, post_fix), \ 349 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_22_23, post_fix), \ 350 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_22_23, post_fix), \ 351 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_24_25, post_fix), \ 352 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_24_25, post_fix), \ 353 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_24_25, post_fix), \ 354 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_24_25, post_fix), \ 355 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_26_27, post_fix), \ 356 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_26_27, post_fix), \ 357 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_26_27, post_fix), \ 358 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_26_27, post_fix), \ 359 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_28_29, post_fix), \ 360 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_28_29, post_fix), \ 361 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_28_29, post_fix), \ 362 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_28_29, post_fix), \ 363 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_30_31, post_fix), \ 364 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_30_31, post_fix), \ 365 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_30_31, post_fix), \ 366 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_30_31, post_fix), \ 367 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_32_33, post_fix), \ 368 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_32_33, post_fix), \ 369 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET, VPMPCC_OGAM_RAMA_REGION_32_33, post_fix), \ 370 SFRB(VPMPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, VPMPCC_OGAM_RAMA_REGION_32_33, post_fix), \ 371 SFRB(VPMPCC_GAMUT_REMAP_COEF_FORMAT, VPMPCC_GAMUT_REMAP_COEF_FORMAT, post_fix), \ 372 SFRB(VPMPCC_GAMUT_REMAP_MODE, VPMPCC_GAMUT_REMAP_MODE, post_fix), \ 373 SFRB(VPMPCC_GAMUT_REMAP_MODE_CURRENT, VPMPCC_GAMUT_REMAP_MODE, post_fix), \ 374 SFRB(VPMPCC_GAMUT_REMAP_C11_A, VPMPC_GAMUT_REMAP_C11_C12_A, post_fix), \ 375 SFRB(VPMPCC_GAMUT_REMAP_C12_A, VPMPC_GAMUT_REMAP_C11_C12_A, post_fix), \ 376 SFRB(VPMPCC_GAMUT_REMAP_C13_A, VPMPC_GAMUT_REMAP_C13_C14_A, post_fix), \ 377 SFRB(VPMPCC_GAMUT_REMAP_C14_A, VPMPC_GAMUT_REMAP_C13_C14_A, post_fix), \ 378 SFRB(VPMPCC_GAMUT_REMAP_C21_A, VPMPC_GAMUT_REMAP_C21_C22_A, post_fix), \ 379 SFRB(VPMPCC_GAMUT_REMAP_C22_A, VPMPC_GAMUT_REMAP_C21_C22_A, post_fix), \ 380 SFRB(VPMPCC_GAMUT_REMAP_C23_A, VPMPC_GAMUT_REMAP_C23_C24_A, post_fix), \ 381 SFRB(VPMPCC_GAMUT_REMAP_C24_A, VPMPC_GAMUT_REMAP_C23_C24_A, post_fix), \ 382 SFRB(VPMPCC_GAMUT_REMAP_C31_A, VPMPC_GAMUT_REMAP_C31_C32_A, post_fix), \ 383 SFRB(VPMPCC_GAMUT_REMAP_C32_A, VPMPC_GAMUT_REMAP_C31_C32_A, post_fix), \ 384 SFRB(VPMPCC_GAMUT_REMAP_C33_A, VPMPC_GAMUT_REMAP_C33_C34_A, post_fix), \ 385 SFRB(VPMPCC_GAMUT_REMAP_C34_A, VPMPC_GAMUT_REMAP_C33_C34_A, post_fix), \ 386 SFRB(VPMPCC_MCM_1DLUT_MODE, VPMPCC_MCM_1DLUT_CONTROL, post_fix), \ 387 SFRB(VPMPCC_MCM_1DLUT_PWL_DISABLE, VPMPCC_MCM_1DLUT_CONTROL, post_fix), \ 388 SFRB(VPMPCC_MCM_1DLUT_MODE_CURRENT, VPMPCC_MCM_1DLUT_CONTROL, post_fix), \ 389 SFRB(VPMPCC_MCM_1DLUT_SELECT_CURRENT, VPMPCC_MCM_1DLUT_CONTROL, post_fix), \ 390 SFRB(VPMPCC_MCM_1DLUT_LUT_INDEX, VPMPCC_MCM_1DLUT_LUT_INDEX, post_fix), \ 391 SFRB(VPMPCC_MCM_1DLUT_LUT_DATA, VPMPCC_MCM_1DLUT_LUT_DATA, post_fix), \ 392 SFRB(VPMPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK, VPMPCC_MCM_1DLUT_LUT_CONTROL, post_fix), \ 393 SFRB(VPMPCC_MCM_1DLUT_LUT_READ_COLOR_SEL, VPMPCC_MCM_1DLUT_LUT_CONTROL, post_fix), \ 394 SFRB(VPMPCC_MCM_1DLUT_LUT_READ_DBG, VPMPCC_MCM_1DLUT_LUT_CONTROL, post_fix), \ 395 SFRB(VPMPCC_MCM_1DLUT_LUT_HOST_SEL, VPMPCC_MCM_1DLUT_LUT_CONTROL, post_fix), \ 396 SFRB(VPMPCC_MCM_1DLUT_LUT_CONFIG_MODE, VPMPCC_MCM_1DLUT_LUT_CONTROL, post_fix), \ 397 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B, VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B, \ 398 post_fix), \ 399 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B, VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B, \ 400 post_fix), \ 401 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G, VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G, \ 402 post_fix), \ 403 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G, VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G, \ 404 post_fix), \ 405 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R, VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R, \ 406 post_fix), \ 407 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R, VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R, \ 408 post_fix), \ 409 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B, \ 410 VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B, post_fix), \ 411 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G, \ 412 VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G, post_fix), \ 413 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R, \ 414 VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R, post_fix), \ 415 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B, \ 416 VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B, post_fix), \ 417 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G, \ 418 VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G, post_fix), \ 419 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R, \ 420 VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R, post_fix), \ 421 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B, VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B, \ 422 post_fix), \ 423 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B, VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B, post_fix), \ 424 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B, VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B, \ 425 post_fix), \ 426 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G, VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G, \ 427 post_fix), \ 428 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G, VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G, post_fix), \ 429 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G, VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G, \ 430 post_fix), \ 431 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R, VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R, \ 432 post_fix), \ 433 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R, VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R, post_fix), \ 434 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R, VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R, \ 435 post_fix), \ 436 SFRB(VPMPCC_MCM_1DLUT_RAMA_OFFSET_B, VPMPCC_MCM_1DLUT_RAMA_OFFSET_B, post_fix), \ 437 SFRB(VPMPCC_MCM_1DLUT_RAMA_OFFSET_G, VPMPCC_MCM_1DLUT_RAMA_OFFSET_G, post_fix), \ 438 SFRB(VPMPCC_MCM_1DLUT_RAMA_OFFSET_R, VPMPCC_MCM_1DLUT_RAMA_OFFSET_R, post_fix), \ 439 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_0_1, \ 440 post_fix), \ 441 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_0_1, \ 442 post_fix), \ 443 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_0_1, \ 444 post_fix), \ 445 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_0_1, \ 446 post_fix), \ 447 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_2_3, \ 448 post_fix), \ 449 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_2_3, \ 450 post_fix), \ 451 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_2_3, \ 452 post_fix), \ 453 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_2_3, \ 454 post_fix), \ 455 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_4_5, \ 456 post_fix), \ 457 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_4_5, \ 458 post_fix), \ 459 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_4_5, \ 460 post_fix), \ 461 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_4_5, \ 462 post_fix), \ 463 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_6_7, \ 464 post_fix), \ 465 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_6_7, \ 466 post_fix), \ 467 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_6_7, \ 468 post_fix), \ 469 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_6_7, \ 470 post_fix), \ 471 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_8_9, \ 472 post_fix), \ 473 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_8_9, \ 474 post_fix), \ 475 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_8_9, \ 476 post_fix), \ 477 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_8_9, \ 478 post_fix), \ 479 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_10_11, \ 480 post_fix), \ 481 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_10_11, \ 482 post_fix), \ 483 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_10_11, \ 484 post_fix), \ 485 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_10_11, \ 486 post_fix), \ 487 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_12_13, \ 488 post_fix), \ 489 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_12_13, \ 490 post_fix), \ 491 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_12_13, \ 492 post_fix), \ 493 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_12_13, \ 494 post_fix), \ 495 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_14_15, \ 496 post_fix), \ 497 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_14_15, \ 498 post_fix), \ 499 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_14_15, \ 500 post_fix), \ 501 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_14_15, \ 502 post_fix), \ 503 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_16_17, \ 504 post_fix), \ 505 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_16_17, \ 506 post_fix), \ 507 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_16_17, \ 508 post_fix), \ 509 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_16_17, \ 510 post_fix), \ 511 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_18_19, \ 512 post_fix), \ 513 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_18_19, \ 514 post_fix), \ 515 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_18_19, \ 516 post_fix), \ 517 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_18_19, \ 518 post_fix), \ 519 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_20_21, \ 520 post_fix), \ 521 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_20_21, \ 522 post_fix), \ 523 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_20_21, \ 524 post_fix), \ 525 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_20_21, \ 526 post_fix), \ 527 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_22_23, \ 528 post_fix), \ 529 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_22_23, \ 530 post_fix), \ 531 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_22_23, \ 532 post_fix), \ 533 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_22_23, \ 534 post_fix), \ 535 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_24_25, \ 536 post_fix), \ 537 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_24_25, \ 538 post_fix), \ 539 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_24_25, \ 540 post_fix), \ 541 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_24_25, \ 542 post_fix), \ 543 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_26_27, \ 544 post_fix), \ 545 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_26_27, \ 546 post_fix), \ 547 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_26_27, \ 548 post_fix), \ 549 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_26_27, \ 550 post_fix), \ 551 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_28_29, \ 552 post_fix), \ 553 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_28_29, \ 554 post_fix), \ 555 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_28_29, \ 556 post_fix), \ 557 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_28_29, \ 558 post_fix), \ 559 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_30_31, \ 560 post_fix), \ 561 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_30_31, \ 562 post_fix), \ 563 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_30_31, \ 564 post_fix), \ 565 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_30_31, \ 566 post_fix), \ 567 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_32_33, \ 568 post_fix), \ 569 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_32_33, \ 570 post_fix), \ 571 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET, VPMPCC_MCM_1DLUT_RAMA_REGION_32_33, \ 572 post_fix), \ 573 SFRB(VPMPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS, VPMPCC_MCM_1DLUT_RAMA_REGION_32_33, \ 574 post_fix), \ 575 SFRB(VPMPCC_MCM_1DLUT_MEM_PWR_FORCE, VPMPCC_MCM_MEM_PWR_CTRL, post_fix), \ 576 SFRB(VPMPCC_MCM_1DLUT_MEM_PWR_DIS, VPMPCC_MCM_MEM_PWR_CTRL, post_fix), \ 577 SFRB(VPMPCC_MCM_1DLUT_MEM_LOW_PWR_MODE, VPMPCC_MCM_MEM_PWR_CTRL, post_fix), \ 578 SFRB(VPMPCC_MCM_1DLUT_MEM_PWR_STATE, VPMPCC_MCM_MEM_PWR_CTRL, post_fix) 579 580 #define MPC_FIELD_LIST_VPE10(post_fix) \ 581 MPC_FIELD_LIST_VPE10_COMMON(post_fix), \ 582 SFRB(VPMPCC_BG_BPC, VPMPCC_CONTROL, post_fix), \ 583 SFRB(VPMPCC_GLOBAL_ALPHA, VPMPCC_CONTROL, post_fix), \ 584 SFRB(VPMPCC_GLOBAL_GAIN, VPMPCC_CONTROL, post_fix), \ 585 SFRB(VPMPCC_MCM_SHAPER_LUT_MODE, VPMPCC_MCM_SHAPER_CONTROL, post_fix), \ 586 SFRB(VPMPCC_MCM_SHAPER_MODE_CURRENT, VPMPCC_MCM_SHAPER_CONTROL, post_fix), \ 587 SFRB(VPMPCC_MCM_SHAPER_SELECT_CURRENT, VPMPCC_MCM_SHAPER_CONTROL, post_fix), \ 588 SFRB(VPMPCC_MCM_SHAPER_OFFSET_R, VPMPCC_MCM_SHAPER_OFFSET_R, post_fix), \ 589 SFRB(VPMPCC_MCM_SHAPER_OFFSET_G, VPMPCC_MCM_SHAPER_OFFSET_G, post_fix), \ 590 SFRB(VPMPCC_MCM_SHAPER_OFFSET_B, VPMPCC_MCM_SHAPER_OFFSET_B, post_fix), \ 591 SFRB(VPMPCC_MCM_SHAPER_SCALE_R, VPMPCC_MCM_SHAPER_SCALE_R, post_fix), \ 592 SFRB(VPMPCC_MCM_SHAPER_SCALE_G, VPMPCC_MCM_SHAPER_SCALE_G_B, post_fix), \ 593 SFRB(VPMPCC_MCM_SHAPER_SCALE_B, VPMPCC_MCM_SHAPER_SCALE_G_B, post_fix), \ 594 SFRB(VPMPCC_MCM_SHAPER_LUT_INDEX, VPMPCC_MCM_SHAPER_LUT_INDEX, post_fix), \ 595 SFRB(VPMPCC_MCM_SHAPER_LUT_DATA, VPMPCC_MCM_SHAPER_LUT_DATA, post_fix), \ 596 SFRB(VPMPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, VPMPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, post_fix), \ 597 SFRB(VPMPCC_MCM_SHAPER_LUT_WRITE_SEL, VPMPCC_MCM_SHAPER_LUT_WRITE_EN_MASK, post_fix), \ 598 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B, VPMPCC_MCM_SHAPER_RAMA_START_CNTL_B, \ 599 post_fix), \ 600 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B, \ 601 VPMPCC_MCM_SHAPER_RAMA_START_CNTL_B, post_fix), \ 602 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G, VPMPCC_MCM_SHAPER_RAMA_START_CNTL_G, \ 603 post_fix), \ 604 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G, \ 605 VPMPCC_MCM_SHAPER_RAMA_START_CNTL_G, post_fix), \ 606 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R, VPMPCC_MCM_SHAPER_RAMA_START_CNTL_R, \ 607 post_fix), \ 608 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R, \ 609 VPMPCC_MCM_SHAPER_RAMA_START_CNTL_R, post_fix), \ 610 SFRB( \ 611 VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B, VPMPCC_MCM_SHAPER_RAMA_END_CNTL_B, post_fix), \ 612 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B, VPMPCC_MCM_SHAPER_RAMA_END_CNTL_B, \ 613 post_fix), \ 614 SFRB( \ 615 VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G, VPMPCC_MCM_SHAPER_RAMA_END_CNTL_G, post_fix), \ 616 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G, VPMPCC_MCM_SHAPER_RAMA_END_CNTL_G, \ 617 post_fix), \ 618 SFRB( \ 619 VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R, VPMPCC_MCM_SHAPER_RAMA_END_CNTL_R, post_fix), \ 620 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R, VPMPCC_MCM_SHAPER_RAMA_END_CNTL_R, \ 621 post_fix), \ 622 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_0_1, \ 623 post_fix), \ 624 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS, VPMPCC_MCM_SHAPER_RAMA_REGION_0_1, \ 625 post_fix), \ 626 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_0_1, \ 627 post_fix), \ 628 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS, VPMPCC_MCM_SHAPER_RAMA_REGION_0_1, \ 629 post_fix), \ 630 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_2_3, \ 631 post_fix), \ 632 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS, VPMPCC_MCM_SHAPER_RAMA_REGION_2_3, \ 633 post_fix), \ 634 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_2_3, \ 635 post_fix), \ 636 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS, VPMPCC_MCM_SHAPER_RAMA_REGION_2_3, \ 637 post_fix), \ 638 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_4_5, \ 639 post_fix), \ 640 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS, VPMPCC_MCM_SHAPER_RAMA_REGION_4_5, \ 641 post_fix), \ 642 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_4_5, \ 643 post_fix), \ 644 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS, VPMPCC_MCM_SHAPER_RAMA_REGION_4_5, \ 645 post_fix), \ 646 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_6_7, \ 647 post_fix), \ 648 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS, VPMPCC_MCM_SHAPER_RAMA_REGION_6_7, \ 649 post_fix), \ 650 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_6_7, \ 651 post_fix), \ 652 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS, VPMPCC_MCM_SHAPER_RAMA_REGION_6_7, \ 653 post_fix), \ 654 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_8_9, \ 655 post_fix), \ 656 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS, VPMPCC_MCM_SHAPER_RAMA_REGION_8_9, \ 657 post_fix), \ 658 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_8_9, \ 659 post_fix), \ 660 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS, VPMPCC_MCM_SHAPER_RAMA_REGION_8_9, \ 661 post_fix), \ 662 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_10_11, \ 663 post_fix), \ 664 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS, \ 665 VPMPCC_MCM_SHAPER_RAMA_REGION_10_11, post_fix), \ 666 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_10_11, \ 667 post_fix), \ 668 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS, \ 669 VPMPCC_MCM_SHAPER_RAMA_REGION_10_11, post_fix), \ 670 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_12_13, \ 671 post_fix), \ 672 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS, \ 673 VPMPCC_MCM_SHAPER_RAMA_REGION_12_13, post_fix), \ 674 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_12_13, \ 675 post_fix), \ 676 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS, \ 677 VPMPCC_MCM_SHAPER_RAMA_REGION_12_13, post_fix), \ 678 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_14_15, \ 679 post_fix), \ 680 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS, \ 681 VPMPCC_MCM_SHAPER_RAMA_REGION_14_15, post_fix), \ 682 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_14_15, \ 683 post_fix), \ 684 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS, \ 685 VPMPCC_MCM_SHAPER_RAMA_REGION_14_15, post_fix), \ 686 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_16_17, \ 687 post_fix), \ 688 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS, \ 689 VPMPCC_MCM_SHAPER_RAMA_REGION_16_17, post_fix), \ 690 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_16_17, \ 691 post_fix), \ 692 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS, \ 693 VPMPCC_MCM_SHAPER_RAMA_REGION_16_17, post_fix), \ 694 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_18_19, \ 695 post_fix), \ 696 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS, \ 697 VPMPCC_MCM_SHAPER_RAMA_REGION_18_19, post_fix), \ 698 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_18_19, \ 699 post_fix), \ 700 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS, \ 701 VPMPCC_MCM_SHAPER_RAMA_REGION_18_19, post_fix), \ 702 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_20_21, \ 703 post_fix), \ 704 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS, \ 705 VPMPCC_MCM_SHAPER_RAMA_REGION_20_21, post_fix), \ 706 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_20_21, \ 707 post_fix), \ 708 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS, \ 709 VPMPCC_MCM_SHAPER_RAMA_REGION_20_21, post_fix), \ 710 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_22_23, \ 711 post_fix), \ 712 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS, \ 713 VPMPCC_MCM_SHAPER_RAMA_REGION_22_23, post_fix), \ 714 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_22_23, \ 715 post_fix), \ 716 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS, \ 717 VPMPCC_MCM_SHAPER_RAMA_REGION_22_23, post_fix), \ 718 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_24_25, \ 719 post_fix), \ 720 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS, \ 721 VPMPCC_MCM_SHAPER_RAMA_REGION_24_25, post_fix), \ 722 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_24_25, \ 723 post_fix), \ 724 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS, \ 725 VPMPCC_MCM_SHAPER_RAMA_REGION_24_25, post_fix), \ 726 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_26_27, \ 727 post_fix), \ 728 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS, \ 729 VPMPCC_MCM_SHAPER_RAMA_REGION_26_27, post_fix), \ 730 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_26_27, \ 731 post_fix), \ 732 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS, \ 733 VPMPCC_MCM_SHAPER_RAMA_REGION_26_27, post_fix), \ 734 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_28_29, \ 735 post_fix), \ 736 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS, \ 737 VPMPCC_MCM_SHAPER_RAMA_REGION_28_29, post_fix), \ 738 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_28_29, \ 739 post_fix), \ 740 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS, \ 741 VPMPCC_MCM_SHAPER_RAMA_REGION_28_29, post_fix), \ 742 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_30_31, \ 743 post_fix), \ 744 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS, \ 745 VPMPCC_MCM_SHAPER_RAMA_REGION_30_31, post_fix), \ 746 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_30_31, \ 747 post_fix), \ 748 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS, \ 749 VPMPCC_MCM_SHAPER_RAMA_REGION_30_31, post_fix), \ 750 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_32_33, \ 751 post_fix), \ 752 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS, \ 753 VPMPCC_MCM_SHAPER_RAMA_REGION_32_33, post_fix), \ 754 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET, VPMPCC_MCM_SHAPER_RAMA_REGION_32_33, \ 755 post_fix), \ 756 SFRB(VPMPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS, \ 757 VPMPCC_MCM_SHAPER_RAMA_REGION_32_33, post_fix), \ 758 SFRB(VPMPCC_MCM_3DLUT_MODE, VPMPCC_MCM_3DLUT_MODE, post_fix), \ 759 SFRB(VPMPCC_MCM_3DLUT_SIZE, VPMPCC_MCM_3DLUT_MODE, post_fix), \ 760 SFRB(VPMPCC_MCM_3DLUT_MODE_CURRENT, VPMPCC_MCM_3DLUT_MODE, post_fix), \ 761 SFRB(VPMPCC_MCM_3DLUT_SELECT_CURRENT, VPMPCC_MCM_3DLUT_MODE, post_fix), \ 762 SFRB(VPMPCC_MCM_3DLUT_INDEX, VPMPCC_MCM_3DLUT_INDEX, post_fix), \ 763 SFRB(VPMPCC_MCM_3DLUT_DATA0, VPMPCC_MCM_3DLUT_DATA, post_fix), \ 764 SFRB(VPMPCC_MCM_3DLUT_DATA1, VPMPCC_MCM_3DLUT_DATA, post_fix), \ 765 SFRB(VPMPCC_MCM_3DLUT_DATA_30BIT, VPMPCC_MCM_3DLUT_DATA_30BIT, post_fix), \ 766 SFRB(VPMPCC_MCM_3DLUT_WRITE_EN_MASK, VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL, post_fix), \ 767 SFRB(VPMPCC_MCM_3DLUT_RAM_SEL, VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL, post_fix), \ 768 SFRB(VPMPCC_MCM_3DLUT_30BIT_EN, VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL, post_fix), \ 769 SFRB(VPMPCC_MCM_3DLUT_READ_SEL, VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL, post_fix), \ 770 SFRB(VPMPCC_MCM_3DLUT_OUT_NORM_FACTOR, VPMPCC_MCM_3DLUT_OUT_NORM_FACTOR, post_fix), \ 771 SFRB(VPMPCC_MCM_3DLUT_OUT_OFFSET_R, VPMPCC_MCM_3DLUT_OUT_OFFSET_R, post_fix), \ 772 SFRB(VPMPCC_MCM_3DLUT_OUT_SCALE_R, VPMPCC_MCM_3DLUT_OUT_OFFSET_R, post_fix), \ 773 SFRB(VPMPCC_MCM_3DLUT_OUT_OFFSET_G, VPMPCC_MCM_3DLUT_OUT_OFFSET_G, post_fix), \ 774 SFRB(VPMPCC_MCM_3DLUT_OUT_SCALE_G, VPMPCC_MCM_3DLUT_OUT_OFFSET_G, post_fix), \ 775 SFRB(VPMPCC_MCM_3DLUT_OUT_OFFSET_B, VPMPCC_MCM_3DLUT_OUT_OFFSET_B, post_fix), \ 776 SFRB(VPMPCC_MCM_3DLUT_OUT_SCALE_B, VPMPCC_MCM_3DLUT_OUT_OFFSET_B, post_fix), \ 777 SFRB(VPMPCC_MCM_SHAPER_MEM_PWR_FORCE, VPMPCC_MCM_MEM_PWR_CTRL, post_fix), \ 778 SFRB(VPMPCC_MCM_SHAPER_MEM_PWR_DIS, VPMPCC_MCM_MEM_PWR_CTRL, post_fix), \ 779 SFRB(VPMPCC_MCM_SHAPER_MEM_LOW_PWR_MODE, VPMPCC_MCM_MEM_PWR_CTRL, post_fix), \ 780 SFRB(VPMPCC_MCM_3DLUT_MEM_PWR_FORCE, VPMPCC_MCM_MEM_PWR_CTRL, post_fix), \ 781 SFRB(VPMPCC_MCM_3DLUT_MEM_PWR_DIS, VPMPCC_MCM_MEM_PWR_CTRL, post_fix), \ 782 SFRB(VPMPCC_MCM_3DLUT_MEM_LOW_PWR_MODE, VPMPCC_MCM_MEM_PWR_CTRL, post_fix), \ 783 SFRB(VPMPCC_MCM_SHAPER_MEM_PWR_STATE, VPMPCC_MCM_MEM_PWR_CTRL, post_fix), \ 784 SFRB(VPMPCC_MCM_3DLUT_MEM_PWR_STATE, VPMPCC_MCM_MEM_PWR_CTRL, post_fix) 785 786 #define MPC_REG_VARIABLE_LIST_VPE10_COMMON \ 787 reg_id_val VPMPC_CLOCK_CONTROL; \ 788 reg_id_val VPMPC_SOFT_RESET; \ 789 reg_id_val VPMPC_CRC_CTRL; \ 790 reg_id_val VPMPC_CRC_SEL_CONTROL; \ 791 reg_id_val VPMPC_CRC_RESULT_AR; \ 792 reg_id_val VPMPC_CRC_RESULT_GB; \ 793 reg_id_val VPMPC_CRC_RESULT_C; \ 794 reg_id_val VPMPC_BYPASS_BG_AR; \ 795 reg_id_val VPMPC_BYPASS_BG_GB; \ 796 reg_id_val VPMPC_HOST_READ_CONTROL; \ 797 reg_id_val VPMPC_PENDING_STATUS_MISC; \ 798 reg_id_val VPMPC_OUT_MUX; \ 799 reg_id_val VPMPC_OUT_FLOAT_CONTROL; \ 800 reg_id_val VPMPC_OUT_DENORM_CONTROL; \ 801 reg_id_val VPMPC_OUT_DENORM_CLAMP_G_Y; \ 802 reg_id_val VPMPC_OUT_DENORM_CLAMP_B_CB; \ 803 reg_id_val VPMPC_OUT_CSC_COEF_FORMAT; \ 804 reg_id_val VPMPC_OUT_CSC_MODE; \ 805 reg_id_val VPMPC_OUT_CSC_C11_C12_A; \ 806 reg_id_val VPMPC_OUT_CSC_C13_C14_A; \ 807 reg_id_val VPMPC_OUT_CSC_C21_C22_A; \ 808 reg_id_val VPMPC_OUT_CSC_C23_C24_A; \ 809 reg_id_val VPMPC_OUT_CSC_C31_C32_A; \ 810 reg_id_val VPMPC_OUT_CSC_C33_C34_A; \ 811 reg_id_val VPMPCC_TOP_SEL; \ 812 reg_id_val VPMPCC_BOT_SEL; \ 813 reg_id_val VPMPCC_VPOPP_ID; \ 814 reg_id_val VPMPCC_CONTROL; \ 815 reg_id_val VPMPCC_TOP_GAIN; \ 816 reg_id_val VPMPCC_BOT_GAIN_INSIDE; \ 817 reg_id_val VPMPCC_BOT_GAIN_OUTSIDE; \ 818 reg_id_val VPMPCC_MOVABLE_CM_LOCATION_CONTROL; \ 819 reg_id_val VPMPCC_BG_R_CR; \ 820 reg_id_val VPMPCC_BG_G_Y; \ 821 reg_id_val VPMPCC_BG_B_CB; \ 822 reg_id_val VPMPCC_MEM_PWR_CTRL; \ 823 reg_id_val VPMPCC_STATUS; \ 824 reg_id_val VPMPCC_OGAM_CONTROL; \ 825 reg_id_val VPMPCC_OGAM_LUT_INDEX; \ 826 reg_id_val VPMPCC_OGAM_LUT_DATA; \ 827 reg_id_val VPMPCC_OGAM_LUT_CONTROL; \ 828 reg_id_val VPMPCC_OGAM_RAMA_START_CNTL_B; \ 829 reg_id_val VPMPCC_OGAM_RAMA_START_CNTL_G; \ 830 reg_id_val VPMPCC_OGAM_RAMA_START_CNTL_R; \ 831 reg_id_val VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B; \ 832 reg_id_val VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G; \ 833 reg_id_val VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R; \ 834 reg_id_val VPMPCC_OGAM_RAMA_START_BASE_CNTL_B; \ 835 reg_id_val VPMPCC_OGAM_RAMA_START_BASE_CNTL_G; \ 836 reg_id_val VPMPCC_OGAM_RAMA_START_BASE_CNTL_R; \ 837 reg_id_val VPMPCC_OGAM_RAMA_END_CNTL1_B; \ 838 reg_id_val VPMPCC_OGAM_RAMA_END_CNTL2_B; \ 839 reg_id_val VPMPCC_OGAM_RAMA_END_CNTL1_G; \ 840 reg_id_val VPMPCC_OGAM_RAMA_END_CNTL2_G; \ 841 reg_id_val VPMPCC_OGAM_RAMA_END_CNTL1_R; \ 842 reg_id_val VPMPCC_OGAM_RAMA_END_CNTL2_R; \ 843 reg_id_val VPMPCC_OGAM_RAMA_OFFSET_B; \ 844 reg_id_val VPMPCC_OGAM_RAMA_OFFSET_G; \ 845 reg_id_val VPMPCC_OGAM_RAMA_OFFSET_R; \ 846 reg_id_val VPMPCC_OGAM_RAMA_REGION_0_1; \ 847 reg_id_val VPMPCC_OGAM_RAMA_REGION_2_3; \ 848 reg_id_val VPMPCC_OGAM_RAMA_REGION_4_5; \ 849 reg_id_val VPMPCC_OGAM_RAMA_REGION_6_7; \ 850 reg_id_val VPMPCC_OGAM_RAMA_REGION_8_9; \ 851 reg_id_val VPMPCC_OGAM_RAMA_REGION_10_11; \ 852 reg_id_val VPMPCC_OGAM_RAMA_REGION_12_13; \ 853 reg_id_val VPMPCC_OGAM_RAMA_REGION_14_15; \ 854 reg_id_val VPMPCC_OGAM_RAMA_REGION_16_17; \ 855 reg_id_val VPMPCC_OGAM_RAMA_REGION_18_19; \ 856 reg_id_val VPMPCC_OGAM_RAMA_REGION_20_21; \ 857 reg_id_val VPMPCC_OGAM_RAMA_REGION_22_23; \ 858 reg_id_val VPMPCC_OGAM_RAMA_REGION_24_25; \ 859 reg_id_val VPMPCC_OGAM_RAMA_REGION_26_27; \ 860 reg_id_val VPMPCC_OGAM_RAMA_REGION_28_29; \ 861 reg_id_val VPMPCC_OGAM_RAMA_REGION_30_31; \ 862 reg_id_val VPMPCC_OGAM_RAMA_REGION_32_33; \ 863 reg_id_val VPMPCC_GAMUT_REMAP_COEF_FORMAT; \ 864 reg_id_val VPMPCC_GAMUT_REMAP_MODE; \ 865 reg_id_val VPMPC_GAMUT_REMAP_C11_C12_A; \ 866 reg_id_val VPMPC_GAMUT_REMAP_C13_C14_A; \ 867 reg_id_val VPMPC_GAMUT_REMAP_C21_C22_A; \ 868 reg_id_val VPMPC_GAMUT_REMAP_C23_C24_A; \ 869 reg_id_val VPMPC_GAMUT_REMAP_C31_C32_A; \ 870 reg_id_val VPMPC_GAMUT_REMAP_C33_C34_A; \ 871 reg_id_val VPMPCC_MCM_1DLUT_CONTROL; \ 872 reg_id_val VPMPCC_MCM_1DLUT_LUT_INDEX; \ 873 reg_id_val VPMPCC_MCM_1DLUT_LUT_DATA; \ 874 reg_id_val VPMPCC_MCM_1DLUT_LUT_CONTROL; \ 875 reg_id_val VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B; \ 876 reg_id_val VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G; \ 877 reg_id_val VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R; \ 878 reg_id_val VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B; \ 879 reg_id_val VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G; \ 880 reg_id_val VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R; \ 881 reg_id_val VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B; \ 882 reg_id_val VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G; \ 883 reg_id_val VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R; \ 884 reg_id_val VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B; \ 885 reg_id_val VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B; \ 886 reg_id_val VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G; \ 887 reg_id_val VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G; \ 888 reg_id_val VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R; \ 889 reg_id_val VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R; \ 890 reg_id_val VPMPCC_MCM_1DLUT_RAMA_OFFSET_B; \ 891 reg_id_val VPMPCC_MCM_1DLUT_RAMA_OFFSET_G; \ 892 reg_id_val VPMPCC_MCM_1DLUT_RAMA_OFFSET_R; \ 893 reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_0_1; \ 894 reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_2_3; \ 895 reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_4_5; \ 896 reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_6_7; \ 897 reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_8_9; \ 898 reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_10_11; \ 899 reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_12_13; \ 900 reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_14_15; \ 901 reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_16_17; \ 902 reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_18_19; \ 903 reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_20_21; \ 904 reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_22_23; \ 905 reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_24_25; \ 906 reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_26_27; \ 907 reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_28_29; \ 908 reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_30_31; \ 909 reg_id_val VPMPCC_MCM_1DLUT_RAMA_REGION_32_33; \ 910 911 #define MPC_REG_VARIABLE_LIST_VPE10 \ 912 MPC_REG_VARIABLE_LIST_VPE10_COMMON \ 913 reg_id_val VPMPCC_MCM_SHAPER_CONTROL; \ 914 reg_id_val VPMPCC_MCM_SHAPER_OFFSET_R; \ 915 reg_id_val VPMPCC_MCM_SHAPER_OFFSET_G; \ 916 reg_id_val VPMPCC_MCM_SHAPER_OFFSET_B; \ 917 reg_id_val VPMPCC_MCM_SHAPER_SCALE_R; \ 918 reg_id_val VPMPCC_MCM_SHAPER_SCALE_G_B; \ 919 reg_id_val VPMPCC_MCM_SHAPER_LUT_INDEX; \ 920 reg_id_val VPMPCC_MCM_SHAPER_LUT_DATA; \ 921 reg_id_val VPMPCC_MCM_SHAPER_LUT_WRITE_EN_MASK; \ 922 reg_id_val VPMPCC_MCM_SHAPER_RAMA_START_CNTL_B; \ 923 reg_id_val VPMPCC_MCM_SHAPER_RAMA_START_CNTL_G; \ 924 reg_id_val VPMPCC_MCM_SHAPER_RAMA_START_CNTL_R; \ 925 reg_id_val VPMPCC_MCM_SHAPER_RAMA_END_CNTL_B; \ 926 reg_id_val VPMPCC_MCM_SHAPER_RAMA_END_CNTL_G; \ 927 reg_id_val VPMPCC_MCM_SHAPER_RAMA_END_CNTL_R; \ 928 reg_id_val VPMPCC_MCM_SHAPER_RAMA_REGION_0_1; \ 929 reg_id_val VPMPCC_MCM_SHAPER_RAMA_REGION_2_3; \ 930 reg_id_val VPMPCC_MCM_SHAPER_RAMA_REGION_4_5; \ 931 reg_id_val VPMPCC_MCM_SHAPER_RAMA_REGION_6_7; \ 932 reg_id_val VPMPCC_MCM_SHAPER_RAMA_REGION_8_9; \ 933 reg_id_val VPMPCC_MCM_SHAPER_RAMA_REGION_10_11; \ 934 reg_id_val VPMPCC_MCM_SHAPER_RAMA_REGION_12_13; \ 935 reg_id_val VPMPCC_MCM_SHAPER_RAMA_REGION_14_15; \ 936 reg_id_val VPMPCC_MCM_SHAPER_RAMA_REGION_16_17; \ 937 reg_id_val VPMPCC_MCM_SHAPER_RAMA_REGION_18_19; \ 938 reg_id_val VPMPCC_MCM_SHAPER_RAMA_REGION_20_21; \ 939 reg_id_val VPMPCC_MCM_SHAPER_RAMA_REGION_22_23; \ 940 reg_id_val VPMPCC_MCM_SHAPER_RAMA_REGION_24_25; \ 941 reg_id_val VPMPCC_MCM_SHAPER_RAMA_REGION_26_27; \ 942 reg_id_val VPMPCC_MCM_SHAPER_RAMA_REGION_28_29; \ 943 reg_id_val VPMPCC_MCM_SHAPER_RAMA_REGION_30_31; \ 944 reg_id_val VPMPCC_MCM_SHAPER_RAMA_REGION_32_33; \ 945 reg_id_val VPMPCC_MCM_3DLUT_MODE; \ 946 reg_id_val VPMPCC_MCM_3DLUT_INDEX; \ 947 reg_id_val VPMPCC_MCM_3DLUT_DATA; \ 948 reg_id_val VPMPCC_MCM_3DLUT_DATA_30BIT; \ 949 reg_id_val VPMPCC_MCM_3DLUT_READ_WRITE_CONTROL; \ 950 reg_id_val VPMPCC_MCM_3DLUT_OUT_NORM_FACTOR; \ 951 reg_id_val VPMPCC_MCM_3DLUT_OUT_OFFSET_R; \ 952 reg_id_val VPMPCC_MCM_3DLUT_OUT_OFFSET_G; \ 953 reg_id_val VPMPCC_MCM_3DLUT_OUT_OFFSET_B; \ 954 reg_id_val VPMPCC_MCM_MEM_PWR_CTRL; 955 956 957 #define MPC_FIELD_VARIABLE_LIST_VPE10_COMMON(type) \ 958 type VPECLK_R_GATE_DISABLE; \ 959 type VPMPC_TEST_CLK_SEL; \ 960 type VPMPCC0_SOFT_RESET; \ 961 type VPMPC_SFR0_SOFT_RESET; \ 962 type VPMPC_SFT0_SOFT_RESET; \ 963 type VPMPC_SOFT_RESET; \ 964 type VPMPC_CRC_EN; \ 965 type VPMPC_CRC_CONT_EN; \ 966 type VPMPC_CRC_SRC_SEL; \ 967 type VPMPC_CRC_ONE_SHOT_PENDING; \ 968 type VPMPC_CRC_UPDATE_ENABLED; \ 969 type VPMPC_CRC_UPDATE_LOCK; \ 970 type VPMPC_CRC_VPDPP_SEL; \ 971 type VPMPC_CRC_VPOPP_SEL; \ 972 type VPMPC_CRC_MASK; \ 973 type VPMPC_CRC_RESULT_A; \ 974 type VPMPC_CRC_RESULT_R; \ 975 type VPMPC_CRC_RESULT_G; \ 976 type VPMPC_CRC_RESULT_B; \ 977 type VPMPC_CRC_RESULT_C; \ 978 type VPMPC_BYPASS_BG_ALPHA; \ 979 type VPMPC_BYPASS_BG_R_CR; \ 980 type VPMPC_BYPASS_BG_G_Y; \ 981 type VPMPC_BYPASS_BG_B_CB; \ 982 type HOST_READ_RATE_CONTROL; \ 983 type VPMPCC0_CONFIG_UPDATE_PENDING; \ 984 type VPMPC_OUT_MUX; \ 985 type VPMPC_OUT_FLOAT_EN; \ 986 type VPMPC_OUT_DENORM_CLAMP_MIN_R_CR; \ 987 type VPMPC_OUT_DENORM_CLAMP_MAX_R_CR; \ 988 type VPMPC_OUT_DENORM_MODE; \ 989 type VPMPC_OUT_DENORM_CLAMP_MIN_G_Y; \ 990 type VPMPC_OUT_DENORM_CLAMP_MAX_G_Y; \ 991 type VPMPC_OUT_DENORM_CLAMP_MIN_B_CB; \ 992 type VPMPC_OUT_DENORM_CLAMP_MAX_B_CB; \ 993 type VPMPC_OCSC0_COEF_FORMAT; \ 994 type VPMPC_OCSC_MODE; \ 995 type VPMPC_OCSC_MODE_CURRENT; \ 996 type VPMPC_OCSC_C11_A; \ 997 type VPMPC_OCSC_C12_A; \ 998 type VPMPC_OCSC_C13_A; \ 999 type VPMPC_OCSC_C14_A; \ 1000 type VPMPC_OCSC_C21_A; \ 1001 type VPMPC_OCSC_C22_A; \ 1002 type VPMPC_OCSC_C23_A; \ 1003 type VPMPC_OCSC_C24_A; \ 1004 type VPMPC_OCSC_C31_A; \ 1005 type VPMPC_OCSC_C32_A; \ 1006 type VPMPC_OCSC_C33_A; \ 1007 type VPMPC_OCSC_C34_A; \ 1008 type VPMPCC_TOP_SEL; \ 1009 type VPMPCC_BOT_SEL; \ 1010 type VPMPCC_VPOPP_ID; \ 1011 type VPMPCC_MODE; \ 1012 type VPMPCC_ALPHA_BLND_MODE; \ 1013 type VPMPCC_ALPHA_MULTIPLIED_MODE; \ 1014 type VPMPCC_BLND_ACTIVE_OVERLAP_ONLY; \ 1015 type VPMPCC_BG_BPC; \ 1016 type VPMPCC_BOT_GAIN_MODE; \ 1017 type VPMPCC_GLOBAL_ALPHA; \ 1018 type VPMPCC_GLOBAL_GAIN; \ 1019 type VPMPCC_TOP_GAIN; \ 1020 type VPMPCC_BOT_GAIN_INSIDE; \ 1021 type VPMPCC_BOT_GAIN_OUTSIDE; \ 1022 type VPMPCC_MOVABLE_CM_LOCATION_CNTL; \ 1023 type VPMPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT; \ 1024 type VPMPCC_BG_R_CR; \ 1025 type VPMPCC_BG_G_Y; \ 1026 type VPMPCC_BG_B_CB; \ 1027 type VPMPCC_OGAM_MEM_PWR_FORCE; \ 1028 type VPMPCC_OGAM_MEM_PWR_DIS; \ 1029 type VPMPCC_OGAM_MEM_LOW_PWR_MODE; \ 1030 type VPMPCC_OGAM_MEM_PWR_STATE; \ 1031 type VPMPCC_IDLE; \ 1032 type VPMPCC_BUSY; \ 1033 type VPMPCC_DISABLED; \ 1034 type VPMPCC_OGAM_MODE; \ 1035 type VPMPCC_OGAM_PWL_DISABLE; \ 1036 type VPMPCC_OGAM_MODE_CURRENT; \ 1037 type VPMPCC_OGAM_SELECT_CURRENT; \ 1038 type VPMPCC_OGAM_LUT_INDEX; \ 1039 type VPMPCC_OGAM_LUT_DATA; \ 1040 type VPMPCC_OGAM_LUT_WRITE_COLOR_MASK; \ 1041 type VPMPCC_OGAM_LUT_READ_COLOR_SEL; \ 1042 type VPMPCC_OGAM_LUT_READ_DBG; \ 1043 type VPMPCC_OGAM_LUT_HOST_SEL; \ 1044 type VPMPCC_OGAM_LUT_CONFIG_MODE; \ 1045 type VPMPCC_OGAM_RAMA_EXP_REGION_START_B; \ 1046 type VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B; \ 1047 type VPMPCC_OGAM_RAMA_EXP_REGION_START_G; \ 1048 type VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G; \ 1049 type VPMPCC_OGAM_RAMA_EXP_REGION_START_R; \ 1050 type VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R; \ 1051 type VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B; \ 1052 type VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G; \ 1053 type VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R; \ 1054 type VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_B; \ 1055 type VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_G; \ 1056 type VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_R; \ 1057 type VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_B; \ 1058 type VPMPCC_OGAM_RAMA_EXP_REGION_END_B; \ 1059 type VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B; \ 1060 type VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_G; \ 1061 type VPMPCC_OGAM_RAMA_EXP_REGION_END_G; \ 1062 type VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G; \ 1063 type VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_R; \ 1064 type VPMPCC_OGAM_RAMA_EXP_REGION_END_R; \ 1065 type VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R; \ 1066 type VPMPCC_OGAM_RAMA_OFFSET_B; \ 1067 type VPMPCC_OGAM_RAMA_OFFSET_G; \ 1068 type VPMPCC_OGAM_RAMA_OFFSET_R; \ 1069 type VPMPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; \ 1070 type VPMPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; \ 1071 type VPMPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; \ 1072 type VPMPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; \ 1073 type VPMPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET; \ 1074 type VPMPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS; \ 1075 type VPMPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET; \ 1076 type VPMPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS; \ 1077 type VPMPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET; \ 1078 type VPMPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS; \ 1079 type VPMPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET; \ 1080 type VPMPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS; \ 1081 type VPMPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET; \ 1082 type VPMPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS; \ 1083 type VPMPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET; \ 1084 type VPMPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS; \ 1085 type VPMPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET; \ 1086 type VPMPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS; \ 1087 type VPMPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET; \ 1088 type VPMPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS; \ 1089 type VPMPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET; \ 1090 type VPMPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS; \ 1091 type VPMPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET; \ 1092 type VPMPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS; \ 1093 type VPMPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET; \ 1094 type VPMPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS; \ 1095 type VPMPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET; \ 1096 type VPMPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS; \ 1097 type VPMPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET; \ 1098 type VPMPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS; \ 1099 type VPMPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET; \ 1100 type VPMPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS; \ 1101 type VPMPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET; \ 1102 type VPMPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS; \ 1103 type VPMPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET; \ 1104 type VPMPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS; \ 1105 type VPMPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET; \ 1106 type VPMPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS; \ 1107 type VPMPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET; \ 1108 type VPMPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS; \ 1109 type VPMPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET; \ 1110 type VPMPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS; \ 1111 type VPMPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET; \ 1112 type VPMPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS; \ 1113 type VPMPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET; \ 1114 type VPMPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS; \ 1115 type VPMPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET; \ 1116 type VPMPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS; \ 1117 type VPMPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET; \ 1118 type VPMPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS; \ 1119 type VPMPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET; \ 1120 type VPMPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS; \ 1121 type VPMPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET; \ 1122 type VPMPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS; \ 1123 type VPMPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET; \ 1124 type VPMPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS; \ 1125 type VPMPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET; \ 1126 type VPMPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS; \ 1127 type VPMPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET; \ 1128 type VPMPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS; \ 1129 type VPMPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET; \ 1130 type VPMPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS; \ 1131 type VPMPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET; \ 1132 type VPMPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS; \ 1133 type VPMPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET; \ 1134 type VPMPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS; \ 1135 type VPMPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET; \ 1136 type VPMPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS; \ 1137 type VPMPCC_GAMUT_REMAP_COEF_FORMAT; \ 1138 type VPMPCC_GAMUT_REMAP_MODE; \ 1139 type VPMPCC_GAMUT_REMAP_MODE_CURRENT; \ 1140 type VPMPCC_GAMUT_REMAP_C11_A; \ 1141 type VPMPCC_GAMUT_REMAP_C12_A; \ 1142 type VPMPCC_GAMUT_REMAP_C13_A; \ 1143 type VPMPCC_GAMUT_REMAP_C14_A; \ 1144 type VPMPCC_GAMUT_REMAP_C21_A; \ 1145 type VPMPCC_GAMUT_REMAP_C22_A; \ 1146 type VPMPCC_GAMUT_REMAP_C23_A; \ 1147 type VPMPCC_GAMUT_REMAP_C24_A; \ 1148 type VPMPCC_GAMUT_REMAP_C31_A; \ 1149 type VPMPCC_GAMUT_REMAP_C32_A; \ 1150 type VPMPCC_GAMUT_REMAP_C33_A; \ 1151 type VPMPCC_GAMUT_REMAP_C34_A; \ 1152 type VPMPCC_MCM_1DLUT_MODE; \ 1153 type VPMPCC_MCM_1DLUT_PWL_DISABLE; \ 1154 type VPMPCC_MCM_1DLUT_MODE_CURRENT; \ 1155 type VPMPCC_MCM_1DLUT_SELECT_CURRENT; \ 1156 type VPMPCC_MCM_1DLUT_LUT_INDEX; \ 1157 type VPMPCC_MCM_1DLUT_LUT_DATA; \ 1158 type VPMPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK; \ 1159 type VPMPCC_MCM_1DLUT_LUT_READ_COLOR_SEL; \ 1160 type VPMPCC_MCM_1DLUT_LUT_READ_DBG; \ 1161 type VPMPCC_MCM_1DLUT_LUT_HOST_SEL; \ 1162 type VPMPCC_MCM_1DLUT_LUT_CONFIG_MODE; \ 1163 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B; \ 1164 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B; \ 1165 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G; \ 1166 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G; \ 1167 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R; \ 1168 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R; \ 1169 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B; \ 1170 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G; \ 1171 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R; \ 1172 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B; \ 1173 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G; \ 1174 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R; \ 1175 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B; \ 1176 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B; \ 1177 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B; \ 1178 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G; \ 1179 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G; \ 1180 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G; \ 1181 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R; \ 1182 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R; \ 1183 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R; \ 1184 type VPMPCC_MCM_1DLUT_RAMA_OFFSET_B; \ 1185 type VPMPCC_MCM_1DLUT_RAMA_OFFSET_G; \ 1186 type VPMPCC_MCM_1DLUT_RAMA_OFFSET_R; \ 1187 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET; \ 1188 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS; \ 1189 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET; \ 1190 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS; \ 1191 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET; \ 1192 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS; \ 1193 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET; \ 1194 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS; \ 1195 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET; \ 1196 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS; \ 1197 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET; \ 1198 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS; \ 1199 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET; \ 1200 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS; \ 1201 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET; \ 1202 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS; \ 1203 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET; \ 1204 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS; \ 1205 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET; \ 1206 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS; \ 1207 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET; \ 1208 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS; \ 1209 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET; \ 1210 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS; \ 1211 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET; \ 1212 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS; \ 1213 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET; \ 1214 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS; \ 1215 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET; \ 1216 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS; \ 1217 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET; \ 1218 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS; \ 1219 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET; \ 1220 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS; \ 1221 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET; \ 1222 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS; \ 1223 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET; \ 1224 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS; \ 1225 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET; \ 1226 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS; \ 1227 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET; \ 1228 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS; \ 1229 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET; \ 1230 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS; \ 1231 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET; \ 1232 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS; \ 1233 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET; \ 1234 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS; \ 1235 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET; \ 1236 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS; \ 1237 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET; \ 1238 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS; \ 1239 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET; \ 1240 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS; \ 1241 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET; \ 1242 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS; \ 1243 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET; \ 1244 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS; \ 1245 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET; \ 1246 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS; \ 1247 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET; \ 1248 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS; \ 1249 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET; \ 1250 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS; \ 1251 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET; \ 1252 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS; \ 1253 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET; \ 1254 type VPMPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS; \ 1255 type VPMPCC_MCM_1DLUT_MEM_PWR_FORCE; \ 1256 type VPMPCC_MCM_1DLUT_MEM_PWR_DIS; \ 1257 type VPMPCC_MCM_1DLUT_MEM_LOW_PWR_MODE; \ 1258 type VPMPCC_MCM_1DLUT_MEM_PWR_STATE; 1259 1260 #define MPC_FIELD_VARIABLE_LIST_VPE10(type) \ 1261 MPC_FIELD_VARIABLE_LIST_VPE10_COMMON(type) \ 1262 type VPMPCC_MCM_SHAPER_LUT_MODE; \ 1263 type VPMPCC_MCM_SHAPER_MODE_CURRENT; \ 1264 type VPMPCC_MCM_SHAPER_SELECT_CURRENT; \ 1265 type VPMPCC_MCM_SHAPER_OFFSET_R; \ 1266 type VPMPCC_MCM_SHAPER_OFFSET_G; \ 1267 type VPMPCC_MCM_SHAPER_OFFSET_B; \ 1268 type VPMPCC_MCM_SHAPER_SCALE_R; \ 1269 type VPMPCC_MCM_SHAPER_SCALE_G; \ 1270 type VPMPCC_MCM_SHAPER_SCALE_B; \ 1271 type VPMPCC_MCM_SHAPER_LUT_INDEX; \ 1272 type VPMPCC_MCM_SHAPER_LUT_DATA; \ 1273 type VPMPCC_MCM_SHAPER_LUT_WRITE_EN_MASK; \ 1274 type VPMPCC_MCM_SHAPER_LUT_WRITE_SEL; \ 1275 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_B; \ 1276 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B; \ 1277 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_G; \ 1278 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G; \ 1279 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_R; \ 1280 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R; \ 1281 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_B; \ 1282 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_B; \ 1283 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_G; \ 1284 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_G; \ 1285 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_R; \ 1286 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION_END_BASE_R; \ 1287 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET; \ 1288 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS; \ 1289 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET; \ 1290 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS; \ 1291 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET; \ 1292 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS; \ 1293 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET; \ 1294 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS; \ 1295 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET; \ 1296 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS; \ 1297 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET; \ 1298 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS; \ 1299 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET; \ 1300 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS; \ 1301 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET; \ 1302 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS; \ 1303 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET; \ 1304 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS; \ 1305 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET; \ 1306 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS; \ 1307 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET; \ 1308 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS; \ 1309 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET; \ 1310 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS; \ 1311 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET; \ 1312 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS; \ 1313 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET; \ 1314 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS; \ 1315 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET; \ 1316 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS; \ 1317 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET; \ 1318 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS; \ 1319 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET; \ 1320 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS; \ 1321 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET; \ 1322 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS; \ 1323 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET; \ 1324 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS; \ 1325 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET; \ 1326 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS; \ 1327 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET; \ 1328 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS; \ 1329 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET; \ 1330 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS; \ 1331 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET; \ 1332 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS; \ 1333 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET; \ 1334 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS; \ 1335 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET; \ 1336 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS; \ 1337 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET; \ 1338 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS; \ 1339 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET; \ 1340 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS; \ 1341 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET; \ 1342 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS; \ 1343 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET; \ 1344 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS; \ 1345 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET; \ 1346 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS; \ 1347 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET; \ 1348 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS; \ 1349 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET; \ 1350 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS; \ 1351 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET; \ 1352 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS; \ 1353 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET; \ 1354 type VPMPCC_MCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS; \ 1355 type VPMPCC_MCM_3DLUT_MODE; \ 1356 type VPMPCC_MCM_3DLUT_SIZE; \ 1357 type VPMPCC_MCM_3DLUT_MODE_CURRENT; \ 1358 type VPMPCC_MCM_3DLUT_SELECT_CURRENT; \ 1359 type VPMPCC_MCM_3DLUT_INDEX; \ 1360 type VPMPCC_MCM_3DLUT_DATA0; \ 1361 type VPMPCC_MCM_3DLUT_DATA1; \ 1362 type VPMPCC_MCM_3DLUT_DATA_30BIT; \ 1363 type VPMPCC_MCM_3DLUT_WRITE_EN_MASK; \ 1364 type VPMPCC_MCM_3DLUT_RAM_SEL; \ 1365 type VPMPCC_MCM_3DLUT_30BIT_EN; \ 1366 type VPMPCC_MCM_3DLUT_READ_SEL; \ 1367 type VPMPCC_MCM_3DLUT_OUT_NORM_FACTOR; \ 1368 type VPMPCC_MCM_3DLUT_OUT_OFFSET_R; \ 1369 type VPMPCC_MCM_3DLUT_OUT_SCALE_R; \ 1370 type VPMPCC_MCM_3DLUT_OUT_OFFSET_G; \ 1371 type VPMPCC_MCM_3DLUT_OUT_SCALE_G; \ 1372 type VPMPCC_MCM_3DLUT_OUT_OFFSET_B; \ 1373 type VPMPCC_MCM_3DLUT_OUT_SCALE_B; \ 1374 type VPMPCC_MCM_SHAPER_MEM_PWR_STATE; \ 1375 type VPMPCC_MCM_3DLUT_MEM_PWR_STATE; \ 1376 type VPMPCC_MCM_SHAPER_MEM_PWR_FORCE; \ 1377 type VPMPCC_MCM_SHAPER_MEM_PWR_DIS; \ 1378 type VPMPCC_MCM_SHAPER_MEM_LOW_PWR_MODE; \ 1379 type VPMPCC_MCM_3DLUT_MEM_PWR_FORCE; \ 1380 type VPMPCC_MCM_3DLUT_MEM_PWR_DIS; \ 1381 type VPMPCC_MCM_3DLUT_MEM_LOW_PWR_MODE; 1382 1383 1384 struct vpe10_mpc_registers { 1385 MPC_REG_VARIABLE_LIST_VPE10 1386 }; 1387 1388 struct vpe10_mpc_shift { 1389 MPC_FIELD_VARIABLE_LIST_VPE10(uint8_t) 1390 }; 1391 1392 struct vpe10_mpc_mask { 1393 MPC_FIELD_VARIABLE_LIST_VPE10(uint32_t) 1394 }; 1395 1396 struct vpe10_mpc { 1397 struct mpc base; 1398 struct vpe10_mpc_registers *regs; 1399 const struct vpe10_mpc_shift *shift; 1400 const struct vpe10_mpc_mask *mask; 1401 }; 1402 1403 void vpe10_construct_mpc(struct vpe_priv *vpe_priv, struct mpc *mpc); 1404 1405 void vpe10_mpc_program_mpcc_mux(struct mpc *mpc, enum mpc_mpccid mpcc_idx, 1406 enum mpc_mux_topsel topsel, enum mpc_mux_botsel botsel, enum mpc_mux_outmux outmux, 1407 enum mpc_mux_oppid oppid); 1408 1409 void vpe10_mpc_program_mpcc_blending( 1410 struct mpc *mpc, enum mpc_mpccid mpcc_idx, struct mpcc_blnd_cfg *blnd_cfg); 1411 1412 void vpe10_mpc_program_mpc_bypass_bg_color(struct mpc *mpc, struct mpcc_blnd_cfg *blnd_cfg); 1413 1414 void vpe10_mpc_power_on_ogam_lut(struct mpc *mpc, bool power_on); 1415 1416 void vpe10_mpc_set_output_csc( 1417 struct mpc *mpc, const uint16_t *regval, enum mpc_output_csc_mode ocsc_mode); 1418 1419 void vpe10_mpc_set_ocsc_default(struct mpc *mpc, enum vpe_surface_pixel_format pixel_format, 1420 enum color_space color_space, enum mpc_output_csc_mode ocsc_mode); 1421 1422 void vpe10_program_output_csc(struct mpc *mpc, enum vpe_surface_pixel_format pixel_format, 1423 enum color_space colorspace, uint16_t *matrix); 1424 1425 void vpe10_mpc_set_output_gamma(struct mpc *mpc, const struct pwl_params *params); 1426 1427 void vpe10_mpc_set_gamut_remap(struct mpc *mpc, struct colorspace_transform *gamut_remap); 1428 1429 void vpe10_mpc_power_on_1dlut_shaper_3dlut(struct mpc *mpc, bool power_on); 1430 1431 bool vpe10_mpc_program_shaper(struct mpc *mpc, const struct pwl_params *params); 1432 1433 // using direct config to program the 3dlut specified in params 1434 void vpe10_mpc_program_3dlut(struct mpc *mpc, const struct tetrahedral_params *params); 1435 1436 // using indirect config to configure the 3DLut 1437 // note that we still need direct config to switch the mask between lut0 - lut3 1438 bool vpe10_mpc_program_3dlut_indirect(struct mpc *mpc, 1439 struct vpe_buf *lut0_3_buf, // 3d lut buf which contains the data for lut0-lut3 1440 bool use_tetrahedral_9, bool use_12bits); 1441 1442 // Blend-gamma control. 1443 void vpe10_mpc_program_1dlut(struct mpc *mpc, const struct pwl_params *params, enum cm_type gamma_type); 1444 1445 void vpe10_mpc_program_cm_location(struct mpc *mpc, uint8_t location); 1446 1447 void vpe10_mpc_set_denorm(struct mpc *mpc, int opp_id, enum color_depth output_depth, 1448 struct mpc_denorm_clamp *denorm_clamp); 1449 1450 void vpe10_mpc_set_out_float_en(struct mpc *mpc, bool float_enable); 1451 1452 void vpe10_mpc_program_mpc_out(struct mpc *mpc, enum vpe_surface_pixel_format format); 1453 1454 void vpe10_mpc_set_output_transfer_func(struct mpc *mpc, struct output_ctx *output_ctx); 1455 1456 void vpe10_mpc_set_mpc_shaper_3dlut( 1457 struct mpc *mpc, const struct transfer_func *func_shaper, const struct vpe_3dlut *lut3d_func); 1458 1459 void vpe10_mpc_set_blend_lut(struct mpc *mpc, const struct transfer_func *blend_tf); 1460 1461 bool vpe10_mpc_program_movable_cm(struct mpc *mpc, const struct transfer_func *func_shaper, 1462 const struct vpe_3dlut *lut3d_func, const struct transfer_func *blend_tf, bool afterblend); 1463 1464 void vpe10_mpc_program_crc(struct mpc *mpc, bool enable); 1465 #ifdef __cplusplus 1466 } 1467 #endif 1468