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Searched refs:ACPI_BASE_ADDRESS (Results 1 – 25 of 92) sorted by relevance

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/aosp_15_r20/external/coreboot/src/soc/intel/common/block/pmc/
H A Dpmclib.c128 uint32_t smi_sts = inl(ACPI_BASE_ADDRESS + SMI_STS); in pmc_reset_smi_status()
129 outl(smi_sts, ACPI_BASE_ADDRESS + SMI_STS); in pmc_reset_smi_status()
166 return inw(ACPI_BASE_ADDRESS + PM1_EN); in pmc_read_pm1_enable()
178 return inl(ACPI_BASE_ADDRESS + SMI_EN); in pmc_get_smi_en()
183 uint32_t smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN); in pmc_enable_smi()
185 outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN); in pmc_enable_smi()
190 uint32_t smi_en = inl(ACPI_BASE_ADDRESS + SMI_EN); in pmc_disable_smi()
192 outl(smi_en, ACPI_BASE_ADDRESS + SMI_EN); in pmc_disable_smi()
198 outw(events, ACPI_BASE_ADDRESS + PM1_EN); in pmc_enable_pm1()
203 return inl(ACPI_BASE_ADDRESS + PM1_CNT); in pmc_read_pm1_control()
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/aosp_15_r20/external/coreboot/src/soc/intel/broadwell/pch/
H A Dpower_state.c51 outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); in prev_sleep_state()
87 ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); in fill_power_state()
88 ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN); in fill_power_state()
89 ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); in fill_power_state()
90 ps->tco1_sts = inw(ACPI_BASE_ADDRESS + TCO1_STS); in fill_power_state()
91 ps->tco2_sts = inw(ACPI_BASE_ADDRESS + TCO2_STS); in fill_power_state()
92 ps->gpe0_sts[0] = inl(ACPI_BASE_ADDRESS + GPE0_STS(0)); in fill_power_state()
93 ps->gpe0_sts[1] = inl(ACPI_BASE_ADDRESS + GPE0_STS(1)); in fill_power_state()
94 ps->gpe0_sts[2] = inl(ACPI_BASE_ADDRESS + GPE0_STS(2)); in fill_power_state()
95 ps->gpe0_sts[3] = inl(ACPI_BASE_ADDRESS + GPE0_STS(3)); in fill_power_state()
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H A Dbootblock.c54 pci_write_config32(PCH_DEV_LPC, PMBASE, ACPI_BASE_ADDRESS | 1); in pch_enable_bars()
98 u16 reg16 = inb(ACPI_BASE_ADDRESS + TCO1_CNT); in pch_early_lpc()
100 outb(reg16, ACPI_BASE_ADDRESS + TCO1_CNT); in pch_early_lpc()
H A Dpmutil.c430 pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); in poweroff()
432 outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT); in poweroff()
438 return (uint16_t)ACPI_BASE_ADDRESS; in get_pmbase()
H A Dlpc.c181 reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT); in pch_misc_init()
184 outl(reg32, ACPI_BASE_ADDRESS + PM1_CNT); in pch_misc_init()
573 pch_lpc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, PMBASE); in pch_lpc_add_io_resources()
/aosp_15_r20/external/coreboot/src/soc/intel/baytrail/romstage/
H A Dromstage.c41 ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); in fill_power_state()
42 ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN); in fill_power_state()
43 ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); in fill_power_state()
44 ps->gpe0_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS); in fill_power_state()
45 ps->gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN); in fill_power_state()
46 ps->tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS); in fill_power_state()
78 outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); in chipset_prev_sleep_state()
/aosp_15_r20/external/coreboot/src/soc/intel/braswell/romstage/
H A Dromstage.c33 power_state.pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); in fill_power_state()
34 power_state.pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN); in fill_power_state()
35 power_state.pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); in fill_power_state()
36 power_state.gpe0_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS); in fill_power_state()
37 power_state.gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN); in fill_power_state()
38 power_state.tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS); in fill_power_state()
77 outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); in chipset_prev_sleep_state()
/aosp_15_r20/external/coreboot/src/soc/intel/apollolake/include/soc/
H A Diomap.h13 #define ACPI_BASE_ADDRESS 0x400 macro
17 #define TCO_BASE_ADDRESS (ACPI_BASE_ADDRESS + 0x60)
23 #define ACPI_PMIO_CST_REG (ACPI_BASE_ADDRESS + 0x14)
/aosp_15_r20/external/coreboot/src/soc/intel/braswell/
H A Dpmutil.c355 if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS)) in platform_is_resuming()
358 return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3; in platform_is_resuming()
366 pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); in poweroff()
368 outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT); in poweroff()
H A Dlpc_init.c100 pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); in lpc_init()
101 pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); in lpc_init()
/aosp_15_r20/external/coreboot/src/soc/intel/baytrail/
H A Dpmutil.c356 if (!(inw(ACPI_BASE_ADDRESS + PM1_STS) & WAK_STS)) in platform_is_resuming()
359 return acpi_sleep_from_pm1(inl(ACPI_BASE_ADDRESS + PM1_CNT)) == ACPI_S3; in platform_is_resuming()
367 pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); in poweroff()
369 outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT); in poweroff()
H A Dehci.c123 REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~0, UPRWC_WR_EN), in ehci_init()
126 REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~UPRWC_WR_EN, 0), in ehci_init()
H A Dxhci.c202 REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~0, UPRWC_WR_EN), in xhci_init()
206 REG_IO_RMW16(ACPI_BASE_ADDRESS + UPRWC, ~UPRWC_WR_EN, 0), in xhci_init()
/aosp_15_r20/external/coreboot/src/soc/intel/baytrail/bootblock/
H A Dbootblock.c35 reg = ACPI_BASE_ADDRESS | 2; in program_base_addresses()
45 reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); in tco_disable()
47 outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); in tco_disable()
/aosp_15_r20/external/coreboot/src/soc/intel/braswell/bootblock/
H A Dbootblock.c46 reg = ACPI_BASE_ADDRESS | 2; in program_base_addresses()
56 reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); in tco_disable()
58 outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); in tco_disable()
/aosp_15_r20/external/coreboot/src/soc/intel/skylake/
H A Dpmc.c24 cfg->abase_addr = ACPI_BASE_ADDRESS; in pmc_soc_get_resources()
87 reg32 = inl(ACPI_BASE_ADDRESS + PM1_CNT); in pmc_soc_init()
90 outl(reg32, ACPI_BASE_ADDRESS + PM1_CNT); in pmc_soc_init()
/aosp_15_r20/external/coreboot/src/soc/intel/xeon_sp/
H A Dpmc.c21 cfg->abase_addr = ACPI_BASE_ADDRESS; in pmc_soc_get_resources()
29 REG_IO_RMW32(ACPI_BASE_ADDRESS + PM1_CNT, ~SLP_TYP, SCI_EN),
/aosp_15_r20/external/coreboot/src/soc/intel/xeon_sp/lbg/
H A Dsoc_pch.c30 pci_write_config32(PCH_DEV_PMC, ABASE, ACPI_BASE_ADDRESS); in soc_config_acpibase()
41 reg32 = (0x3f << 18) | ACPI_BASE_ADDRESS | 1; in soc_config_acpibase()
/aosp_15_r20/external/coreboot/src/soc/intel/xeon_sp/gnr/
H A Dsoc_acpi.c28 const uint16_t pmbase = ACPI_BASE_ADDRESS; in soc_read_sci_irq_select()
34 const uint16_t pmbase = ACPI_BASE_ADDRESS; in soc_fill_fadt()
/aosp_15_r20/external/coreboot/src/soc/intel/skylake/bootblock/
H A Dpch.c49 pci_write_config32(PCH_DEV_PMC, ABASE, ACPI_BASE_ADDRESS); in soc_config_acpibase()
58 reg32 = ((0x3f << 18) | ACPI_BASE_ADDRESS | 1); in soc_config_acpibase()
/aosp_15_r20/external/coreboot/src/soc/intel/apollolake/bootblock/
H A Dbootblock.c51 pci_write_config16(dev, PCI_BASE_ADDRESS_4, ACPI_BASE_ADDRESS); in bootblock_c_entry()
70 pci_write_config16(pmc, PCI_BASE_ADDRESS_4, ACPI_BASE_ADDRESS); in enable_pmcbar()
/aosp_15_r20/external/coreboot/src/mainboard/acer/aspire_vn7_572g/
H A Dmainboard.c130 uint32_t gpe_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(GPE_STD)); in ec_init()
131 outl(gpe_sts, ACPI_BASE_ADDRESS + GPE0_STS(GPE_STD)); in ec_init()
/aosp_15_r20/external/coreboot/src/soc/intel/apollolake/
H A Dpmutil.c81 uint16_t pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); in soc_get_smi_status()
223 return (uint16_t)ACPI_BASE_ADDRESS; in get_pmbase()
/aosp_15_r20/external/coreboot/src/soc/intel/denverton_ns/
H A Dacpi.c45 ACPI_BASE_ADDRESS + 0x14),
52 ACPI_BASE_ADDRESS + 0x15),
/aosp_15_r20/external/coreboot/src/soc/intel/braswell/acpi/
H A Dlpc.asl105 IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS,

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