1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 3 /* $NoKeywords:$ */ 4 /** 5 * @file 6 * 7 * Agesa structures and definitions 8 * 9 * Contains AMD AGESA core interface 10 * 11 * @xrefitem bom "File Content Label" "Release Content" 12 * @e project: AGESA 13 * @e sub-project: Include 14 * @e \$Revision$ @e \$Date$ 15 */ 16 /***************************************************************************** 17 * 18 * Copyright (c) 2008 - 2017, Advanced Micro Devices, Inc. 19 * All rights reserved. 20 * 21 * Redistribution and use in source and binary forms, with or without 22 * modification, are permitted provided that the following conditions are met: 23 * * Redistributions of source code must retain the above copyright 24 * notice, this list of conditions and the following disclaimer. 25 * * Redistributions in binary form must reproduce the above copyright 26 * notice, this list of conditions and the following disclaimer in the 27 * documentation and/or other materials provided with the distribution. 28 * * Neither the name of Advanced Micro Devices, Inc. nor the names of 29 * its contributors may be used to endorse or promote products derived 30 * from this software without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 33 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 34 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 35 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY 36 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 37 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 38 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 39 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 41 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 42 * 43 ***************************************************************************/ 44 45 #include "check_for_wrapper.h" 46 47 #ifndef _AGESA_H_ 48 #define _AGESA_H_ 49 50 #include "Porting.h" 51 #include "AMD.h" 52 53 // 54 // 55 // AGESA Types and Definitions 56 // 57 // 58 59 // AGESA BASIC CALLOUTS 60 #define AGESA_MEM_RELEASE 0x00028000ul 61 62 // AGESA ADVANCED CALLOUTS, Processor 63 #define AGESA_CHECK_UMA 0x00028100ul 64 #define AGESA_DO_RESET 0x00028101ul 65 #define AGESA_ALLOCATE_BUFFER 0x00028102ul 66 #define AGESA_DEALLOCATE_BUFFER 0x00028103ul 67 #define AGESA_LOCATE_BUFFER 0x00028104ul 68 #define AGESA_RUNFUNC_ONAP 0x00028105ul 69 #define AGESA_RUNFUNC_ON_ALL_APS 0x00028106ul 70 #define AGESA_IDLE_AN_AP 0x00028107ul 71 #define AGESA_WAIT_FOR_ALL_APS 0x00028108ul 72 #define AGESA_HALT_THIS_AP 0x00028109ul 73 #define AGESA_GET_TEMP_HEAP_BASE 0x0002810Aul 74 #define AGESA_HEAP_REBASE 0x0002810Bul 75 76 // AGESA ADVANCED CALLOUTS, Memory 77 #define AGESA_READ_SPD 0x00028140ul 78 #define AGESA_HOOKBEFORE_DRAM_INIT 0x00028141ul 79 #define AGESA_HOOKBEFORE_DQS_TRAINING 0x00028142ul 80 #define AGESA_READ_SPD_RECOVERY 0x00028143ul 81 #define AGESA_HOOKBEFORE_EXIT_SELF_REF 0x00028144ul 82 #define AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY 0x00028145ul 83 #define AGESA_EXTERNAL_2D_TRAIN_VREF_CHANGE 0x00028146ul 84 #define AGESA_EXTERNAL_VOLTAGE_ADJUST 0x00028147ul 85 86 // AGESA IDS CALLOUTS 87 #define AGESA_GET_IDS_INIT_DATA 0x00028200ul 88 89 // AGESA GNB CALLOUTS 90 #define AGESA_GNB_PCIE_SLOT_RESET 0x00028301ul 91 #define AGESA_GNB_GFX_GET_VBIOS_IMAGE 0x00028302ul 92 #define AGESA_GNB_PCIE_CLK_REQ 0x00028303ul 93 94 // AGESA FCH CALLOUTS 95 #define AGESA_FCH_OEM_CALLOUT 0x00028401ul 96 97 //----------------------------------------------------------------------------- 98 // FCH DEFINITIONS AND MACROS 99 // 100 //----------------------------------------------------------------------------- 101 102 /// Configuration values for SdConfig 103 typedef enum { 104 SdDisable = 0, ///< Disabled 105 SdVer2, ///< Version 2.0 106 SdVer3, ///< Version 3.0 107 SdV3SDR50, ///< V3 SdSDR50 108 SdV3SDR104, ///< V3 SdSDR104 109 SdV3DDR50, ///< V3 SdDDR50 110 SdDump ///< SD DUMP, don't touch SD 111 } SD_MODE; 112 113 /// Configuration values for SdClockControl 114 typedef enum { 115 Sd50MhzTraceCableLengthWithinSixInches = 4, ///< 50Mhz, default 116 Sd40MhzTraceCableLengthSix2ElevenInches = 6, ///< 40Mhz 117 Sd25MhzTraceCableLengthEleven2TwentyfourInches = 7, ///< 25Mhz 118 } SD_CLOCK_CONTROL; 119 120 /// Configuration values for AzaliaController 121 typedef enum { 122 AzAuto = 0, ///< Auto - Detect Azalia controller automatically 123 AzDisable, ///< Diable - Disable Azalia controller 124 AzEnable ///< Enable - Enable Azalia controller 125 } HDA_CONFIG; 126 127 /// Configuration values for IrConfig 128 typedef enum { 129 IrDisable = 0, ///< Disable 130 IrRxTx0 = 1, ///< Rx and Tx0 131 IrRxTx1 = 2, ///< Rx and Tx1 132 IrRxTx0Tx1 = 3 ///< Rx and both Tx0,Tx1 133 } IR_CONFIG; 134 135 /// Configuration values for SataClass 136 typedef enum { 137 SataNativeIde = 0, ///< Native IDE mode 138 SataRaid, ///< RAID mode 139 SataAhci, ///< AHCI mode 140 SataLegacyIde, ///< Legacy IDE mode 141 SataIde2Ahci, ///< IDE->AHCI mode 142 SataAhci7804, ///< AHCI mode as 7804 ID (AMD driver) 143 SataIde2Ahci7804 ///< IDE->AHCI mode as 7804 ID (AMD driver) 144 } SATA_CLASS; 145 146 /// Configuration values for BLDCFG_FCH_GPP_LINK_CONFIG 147 typedef enum { 148 PortA4 = 0, ///< 4:0:0:0 149 PortA2B2 = 2, ///< 2:2:0:0 150 PortA2B1C1 = 3, ///< 2:1:1:0 151 PortA1B1C1D1 = 4 ///< 1:1:1:1 152 } GPP_LINKMODE; 153 154 /// Configuration values for FchPowerFail 155 typedef enum { 156 AlwaysOff = 0, ///< Always power off after power resumes 157 AlwaysOn = 1, ///< Always power on after power resumes 158 UsePrevious = 3, ///< Resume to same setting when power fails 159 } POWER_FAIL; 160 161 162 /// Configuration values for SATA Link Speed 163 typedef enum { 164 Gen1 = 1, ///< SATA port GEN1 speed 165 Gen2 = 2, ///< SATA port GEN2 speed 166 Gen3 = 3, ///< SATA port GEN3 speed 167 } SATA_SPEED; 168 169 170 /// Configuration values for GPIO function 171 typedef enum { 172 Function0 = 0, ///< GPIO Function 1 173 Function1 = 1, ///< GPIO Function 1 174 Function2 = 2, ///< GPIO Function 2 175 Function3 = 3, ///< GPIO Function 3 176 } GPIO_FUN; 177 178 /// Configuration values for memory phy voltage (VDDR) 179 #define VOLT0_95 0 ///< VDDR 0.95V 180 #define VOLT1_05 1 ///< VDDR 1.05V 181 #define MAX_VDDR 2 ///< Maxmum value for this enum definition 182 183 /// Configuration values for GPIO_CFG 184 typedef enum { 185 OwnedByEc = 1 << 0, ///< This bit can only be written by EC 186 OwnedByHost = 1 << 1, ///< This bit can only be written by host (BIOS) 187 Sticky = 1 << 2, ///< If set, [6:3] are sticky 188 PullUpB = 1 << 3, ///< 0: Pullup enable; 1: Pullup disabled 189 PullDown = 1 << 4, ///< 0: Pulldown disabled; 1: Pulldown enable 190 GpioOutEnB = 1 << 5, ///< 0: Output enable; 1: Output disable 191 GpioOut = 1 << 6, ///< Output state when GpioOutEnB is 0 192 GpioIn = 1 << 7, ///< This bit is read only - current pin state 193 } CFG_BYTE; 194 195 /// Configuration values for GPIO_CFG2 196 typedef enum { 197 DrvStrengthSel_4mA = 0 << 1, ///< 18:17 DrvStrengthSel. 198 DrvStrengthSel_8mA = 1 << 1, ///< 18:17 DrvStrengthSel. 199 DrvStrengthSel_12mA = 2 << 1, ///< 18:17 DrvStrengthSel. 200 DrvStrengthSel_16mA = 3 << 1, ///< 18:17 DrvStrengthSel. 201 PullUpSel_8K = 1 << 3, ///< 19 PullUpSel. Read-write. 0=4 K pull-up is selected. 1=8 K pull-up is selected. 202 PullUpEnable = 1 << 4, ///< 20 PullUpEnable. Read-write. 0=Pull-up is disabled on the pin. 1=Pull-up is enabled on the pin. 203 PullDownEnable = 1 << 5, ///< 21 PullDownEnable. Read-write. 0=Pull-down is disabled on the pin. 1=Pull-down is enabled on thepin. 204 OutputValue = 1 << 6, ///< 22 OutputValue. Read-write. 0=low. 1=high. 205 OutputEnable = 1 << 7, ///< 23 OutputEnable. Read-write. 0=Output is disabled on the pin. 1=Output is enabled on the pin. 206 } CFG2_BYTE; 207 208 /// FCH GPIO CONTROL 209 typedef struct { 210 IN UINT8 GpioPin; ///< Gpio Pin, valid range: 0-67, 128-150, 160-228 211 IN GPIO_FUN PinFunction; ///< Multi-function selection 212 IN CFG_BYTE CfgByte; ///< GPIO Register value 213 } GPIO_CONTROL; 214 215 /// 216 /// FCH SCI MAP CONTROL 217 /// 218 typedef struct { 219 IN UINT8 InputPin; ///< Input Pin, valid range 0-63 220 IN UINT8 GpeMap; ///< Gpe Map, valid range 0-31 221 } SCI_MAP_CONTROL; 222 223 /// 224 /// FCH SATA PHY CONTROL 225 /// 226 typedef struct { 227 IN BOOLEAN CommonPhy; ///< Common PHY or not 228 ///< @li <b>FALSE</b> - Only applied to specified port 229 ///< @li <b>TRUE</b> - Apply to all SATA ports 230 IN SATA_SPEED Gen; ///< SATA speed 231 IN UINT8 Port; ///< Port number, valid range: 0-7 232 IN UINT32 PhyData; ///< SATA PHY data, valid range: 0-0xFFFFFFFF 233 } SATA_PHY_CONTROL; 234 235 /// 236 /// FCH Component Data Structure in InitReset stage 237 /// 238 typedef struct { 239 IN BOOLEAN UmiGen2; ///< Enable Gen2 data rate of UMI 240 ///< @li <b>FALSE</b> - Disable Gen2 241 ///< @li <b>TRUE</b> - Enable Gen2 242 243 IN BOOLEAN SataEnable; ///< SATA controller function 244 ///< @li <b>FALSE</b> - SATA controller is disabled 245 ///< @li <b>TRUE</b> - SATA controller is enabled 246 247 IN BOOLEAN IdeEnable; ///< SATA IDE controller mode enabled/disabled 248 ///< @li <b>FALSE</b> - IDE controller is disabled 249 ///< @li <b>TRUE</b> - IDE controller is enabled 250 251 IN BOOLEAN GppEnable; ///< Master switch of GPP function 252 ///< @li <b>FALSE</b> - GPP disabled 253 ///< @li <b>TRUE</b> - GPP enabled 254 255 IN BOOLEAN Xhci0Enable; ///< XHCI0 controller function 256 ///< @li <b>FALSE</b> - XHCI0 controller disabled 257 ///< @li <b>TRUE</b> - XHCI0 controller enabled 258 259 IN BOOLEAN Xhci1Enable; ///< XHCI1 controller function 260 ///< @li <b>FALSE</b> - XHCI1 controller disabled 261 ///< @li <b>TRUE</b> - XHCI1 controller enabled 262 } FCH_RESET_INTERFACE; 263 264 265 /// 266 /// FCH Component Data Structure from InitEnv stage 267 /// 268 typedef struct { 269 IN SD_MODE SdConfig; ///< Secure Digital (SD) controller mode 270 IN HDA_CONFIG AzaliaController; ///< Azalia HD Audio Controller 271 272 IN IR_CONFIG IrConfig; ///< Infrared (IR) Configuration 273 IN BOOLEAN UmiGen2; ///< Enable Gen2 data rate of UMI 274 ///< @li <b>FALSE</b> - Disable Gen2 275 ///< @li <b>TRUE</b> - Enable Gen2 276 277 IN SATA_CLASS SataClass; ///< SATA controller mode 278 IN BOOLEAN SataEnable; ///< SATA controller function 279 ///< @li <b>FALSE</b> - SATA controller is disabled 280 ///< @li <b>TRUE</b> - SATA controller is enabled 281 282 IN BOOLEAN IdeEnable; ///< SATA IDE controller mode enabled/disabled 283 ///< @li <b>FALSE</b> - IDE controller is disabled 284 ///< @li <b>TRUE</b> - IDE controller is enabled 285 286 IN BOOLEAN SataIdeMode; ///< Native mode of SATA IDE controller 287 ///< @li <b>FALSE</b> - Legacy IDE mode 288 ///< @li <b>TRUE</b> - Native IDE mode 289 290 IN BOOLEAN Ohci1Enable; ///< OHCI controller #1 Function 291 ///< @li <b>FALSE</b> - OHCI1 is disabled 292 ///< @li <b>TRUE</b> - OHCI1 is enabled 293 294 IN BOOLEAN Ohci2Enable; ///< OHCI controller #2 Function 295 ///< @li <b>FALSE</b> - OHCI2 is disabled 296 ///< @li <b>TRUE</b> - OHCI2 is enabled 297 298 IN BOOLEAN Ohci3Enable; ///< OHCI controller #3 Function 299 ///< @li <b>FALSE</b> - OHCI3 is disabled 300 ///< @li <b>TRUE</b> - OHCI3 is enabled 301 302 IN BOOLEAN Ohci4Enable; ///< OHCI controller #4 Function 303 ///< @li <b>FALSE</b> - OHCI4 is disabled 304 ///< @li <b>TRUE</b> - OHCI4 is enabled 305 306 IN BOOLEAN GppEnable; ///< Master switch of GPP function 307 ///< @li <b>FALSE</b> - GPP disabled 308 ///< @li <b>TRUE</b> - GPP enabled 309 310 IN POWER_FAIL FchPowerFail; ///< FCH power failure option 311 } FCH_INTERFACE; 312 313 314 /*---------------------------------------------------------------------------- 315 * CPU Feature related info 316 *---------------------------------------------------------------------------- 317 */ 318 /// Build Configuration values for BLDCFG_PLATFORM_CONNECTED_STANDBY_MODE 319 typedef enum { 320 ConnectedStandbyAuto = 0, ///< Auto 321 ConnectedStandbyDisabled = 1, ///< Disabled 322 MaxConnectedStandbyMode = 2 ///< Not a valid value, used for verifying input 323 } PLATFORM_CONNECTED_STANDBY_MODES; 324 325 /// Build Configuration values for BLDCFG_PLATFORM_CSTATE_MODE 326 typedef enum { 327 CStateModeDisabled = 0, ///< Disabled 328 CStateModeC6 = 1, ///< C6 State 329 MaxCStateMode = 2 ///< Not a valid value, used for verifying input 330 } PLATFORM_CSTATE_MODES; 331 332 /// Build Configuration values for BLDCFG_PLATFORM_CPB_MODE 333 typedef enum { 334 CpbModeAuto = 0, ///< Auto 335 CpbModeDisabled = 1, ///< Disabled 336 MaxCpbMode = 2 ///< Not a valid value, used for verifying input 337 } PLATFORM_CPB_MODES; 338 339 340 /// Build Configuration values for BLDCFG_ACPI_PSTATES_PSD_POLICY 341 #define PsdPolicyProcessorDefault 0 ///< PSD is dependent or independent per processor default 342 #define PsdPolicyDependent 1 ///< PSD is forced dependent 343 #define PsdPolicyIndependent 2 ///< PSD is forced independent 344 #define PsdPolicyMax 3 ///< Not a valid value, used for verifying input 345 346 /*---------------------------------------------------------------------------- 347 * GNB PCIe configuration info 348 *---------------------------------------------------------------------------- 349 */ 350 351 // Event definitions 352 353 #define GNB_EVENT_INVALID_CONFIGURATION 0x20010000ul // User configuration invalid 354 #define GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION 0x20010001ul // Requested lane allocation for PCIe port can not be supported 355 #define GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION 0x20010002ul // Requested incorrect PCIe port device address 356 #define GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION 0x20010003ul // Incorrect parameter in DDI link configuration 357 #define GNB_EVENT_INVALID_LINK_WIDTH_CONFIGURATION 0x20010004ul // Invalid with for PCIe port or DDI link 358 #define GNB_EVENT_INVALID_LANES_CONFIGURATION 0x20010005ul // Lane double subscribe lanes 359 #define GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION 0x20010006ul // Requested lane allocation for DDI link(s) can not be supported 360 #define GNB_EVENT_LINK_TRAINING_FAIL 0x20020000ul // PCIe Link training fail 361 #define GNB_EVENT_BROKEN_LANE_RECOVERY 0x20030000ul // Broken lane workaround applied to recover link training 362 #define GNB_EVENT_GEN2_SUPPORT_RECOVERY 0x20040000ul // Scale back to GEN1 to recover link training 363 364 365 #define DESCRIPTOR_TERMINATE_LIST 0x80000000ull 366 #define DESCRIPTOR_IGNORE 0x40000000ull 367 368 /// PCIe link initialization 369 typedef enum { 370 EndpointDetect = 0, ///< Detect endpoint presence 371 EndpointNotPresent ///< Endpoint not present (or connected). Used in case there is alternative way to determine 372 ///< if device present on board or in slot. For example GPIO can be used to determine device presence. 373 } PCIE_ENDPOINT_STATUS; 374 375 376 /// PCIe port misc extended controls 377 typedef struct { 378 IN UINT8 LinkComplianceMode :1; ///< Force port into compliance mode (device will not be trained, port output compliance pattern) 379 IN UINT8 LinkSafeMode :2; /**< Safe mode PCIe capability. (Parameter may limit PCIe speed requested through PCIe_PORT_DATA::LinkSpeedCapability) 380 * @li @b 0 - port can advertize muximum supported capability 381 * @li @b 1 - port limit advertized capability and speed to PCIe Gen1 382 */ 383 IN UINT8 SbLink :1; /**< PCIe link type 384 * @li @b 0 - General purpose port 385 * @li @b 1 - Port connected to SB 386 */ 387 IN UINT8 ClkPmSupport :1; /**< Clock Power Management Support 388 * @li @b 0 - Clock Power Management not configured 389 * @li @b 1 - Clock Power Management configured according to PCIe device capability 390 */ 391 } PCIe_PORT_MISC_CONTROL; 392 393 /// The IO APIC Interrupt Mapping Info 394 typedef struct { 395 IN UINT8 GroupMap; /**< Group mapping for slot or endpoint device (connected to PCIE port) interrupts . 396 * @li <b>0</b> - IGNORE THIS STRUCTURE AND USE RECOMMENDED SETTINGS 397 * @li <b>1</b> - mapped to Grp 0 (Interrupts 0..3 of IO APIC redirection table) 398 * @li <b>2</b> - mapped to Grp 1 (Interrupts 4..7 of IO APIC redirection table) 399 * @li ... 400 * @li <b>8</b> - mapped to Grp 7 (Interrupts 28..31 of IO APIC redirection table) 401 */ 402 IN UINT8 Swizzle; /**< Swizzle interrupt in the Group. 403 * @li <b>0</b> - ABCD 404 * @li <b>1</b> - BCDA 405 * @li <b>2</b> - CDAB 406 * @li <b>3</b> - DABC 407 */ 408 IN UINT8 BridgeInt; /**< IOAPIC redirection table entry for PCIE bridge interrupt 409 * @li <b>0</b> - Entry 0 of IO APIC redirection table 410 * @li <b>1</b> - Entry 1 of IO APIC redirection table 411 * @li ... 412 * @li <b>31</b> - Entry 31 of IO APIC redirection table 413 */ 414 } APIC_DEVICE_INFO; 415 416 /// Initial Offset Calibration Control 417 typedef enum { 418 ADAPT_IOC_DISABLED = 0, ///< Initial Offset Calibration Disabled 419 ADAPT_IOC_ENABLED ///< Initial Offset Calibration Enabled 420 } ADAPT_IOC_CONTROL; 421 422 /// DFE Control values 423 typedef enum { 424 ADAPT_DFE_CONTROL_DISABLED = 0, ///< DFE Disabled 425 ADAPD_DFE_CONTROL_1TAP_DFE = 4, ///< 1-tap DFE 426 ADAPD_DFE_CONTROL_1TAP_DFE_FBF, ///< 1-tap DFE with Future Bit Filtering 427 ADAPD_DFE_CONTROL_2TAP_DFE, ///< 2-tap DFE 428 ADAPD_DFE_CONTROL_2TAP_DFE_FBF ///< 2-tap DFE with Future Bit Filtering 429 } ADAPT_DFE_CONTROL; 430 431 /// LEQ Control values 432 typedef enum { 433 ADAPT_LEQ_CONTROL_DISABLED = 0, ///< LEQ Disabled 434 ADAPT_LEQ_CONTROL_DC_GAIN = 2, ///< DC Gain Adaptation 435 ADAPT_LEQ_CONTROL_DC_GAIN_POLE ///< DC Gain and Pole Adaptation 436 } ADAPT_LEQ_CONTROL; 437 438 /// Dynamic Offset Calibration Control 439 typedef enum { 440 ADAPT_DOC_DISABLED = 0, ///< Dynamic Offset Calibration Disabled 441 ADAPT_DOC_ENABLED ///< Dynamic Offset Calibration Enabled 442 } ADAPT_DOC_CONTROL; 443 444 /// FOM Calculation Control 445 typedef enum { 446 ADAPT_FOMC_DISABLED = 0, ///< FOM Calculation Disabled 447 ADAPT_FOMC_ENABLED ///< FOM Calculation Enabled 448 } ADAPT_FOMC_CONTROL; 449 450 /// PI Offset Calibration Control 451 typedef enum { 452 ADAPT_PIOC_DISABLED = 0, ///< PI Offset Calibration Disabled 453 ADAPT_PIOC_ENABLED ///< PI Offset Calibration Enabled 454 } ADAPT_PIOC_CONTROL; 455 456 /// GEN3 RxAdaptMode Configuration Structure 457 typedef struct { 458 IN BOOLEAN InitOffsetCancellation; ///< Initial Offset Cancellation Enable 459 IN UINT8 DFEControl; ///< DFE Control 460 IN UINT8 LEQControl; ///< LEQ Control 461 IN BOOLEAN DynamicOffsetCalibration; ///< Dynamic Offset Calibration Enable 462 IN BOOLEAN FOMCalculation; ///< FOM Calculation Enable 463 IN BOOLEAN PIOffsetCalibration; ///< PI Offset Calibratino Enable 464 } RX_ADAPT_MODE; 465 466 /// PCIe port configuration data 467 typedef struct { 468 IN UINT8 PortPresent; ///< Enable PCIe port for initialization. 469 IN UINT8 ChannelType; /**< Channel type. 470 * @li @b 0 - "lowLoss", 471 * @li @b 1 - "highLoss", 472 * @li @b 2 - "mob0db", 473 * @li @b 3 - "mob3db", 474 * @li @b 4 - "extnd6db" 475 * @li @b 5 - "extnd8db" 476 */ 477 IN UINT8 DeviceNumber; /**< PCI Device number for port. 478 * @li @b 0 - Native port device number 479 * @li @b N - Port device number (See available configurations in BKDG 480 */ 481 IN UINT8 FunctionNumber; ///< Reserved for future use 482 IN UINT8 LinkSpeedCapability; /**< PCIe link speed/ 483 * @li @b 0 - Maximum supported by silicon 484 * @li @b 1 - Gen1 485 * @li @b 2 - Gen2 486 * @li @b 3 - Gen3 487 */ 488 IN UINT8 LinkAspm; /**< ASPM control. (see AgesaPcieLinkAspm for additional option to control ASPM) 489 * @li @b 0 - Disabled 490 * @li @b 1 - L0s only 491 * @li @b 2 - L1 only 492 * @li @b 3 - L0s and L1 493 */ 494 IN UINT8 LinkHotplug; /**< Hotplug control. 495 * @li @b 0 - Disabled 496 * @li @b 1 - Basic 497 * @li @b 2 - Server 498 * @li @b 3 - Enhanced 499 */ 500 IN UINT8 ResetId; /**< Arbitrary number greater than 0 assigned by platform firmware for GPIO 501 * identification which control reset for given port. 502 * Each port with unique GPIO should have unique ResetId assigned. 503 * All ports use same GPIO to control reset should have same ResetId assigned. 504 * see AgesaPcieSlotResetContol. 505 */ 506 IN PCIe_PORT_MISC_CONTROL MiscControls; ///< Misc extended controls 507 IN APIC_DEVICE_INFO ApicDeviceInfo; ///< IOAPIC device programming info 508 IN PCIE_ENDPOINT_STATUS EndpointStatus; ///< PCIe endpoint (device connected to PCIe port) status 509 IN RX_ADAPT_MODE RxAdaptMode; ///< Gen3 RxAdaptMode configuration 510 } PCIe_PORT_DATA; 511 512 /// DDI channel lane mapping 513 typedef struct { ///< Structure that discribe lane mapping 514 IN UINT8 Lane0 :2; /**< Lane 0 mapping 515 * @li @b 0 - Map to lane 0 516 * @li @b 1 - Map to lane 1 517 * @li @b 2 - Map to lane 2 518 * @li @b 2 - Map to lane 3 519 */ 520 IN UINT8 Lane1 :2; ///< Lane 1 mapping (see "Lane 0 mapping") 521 IN UINT8 Lane2 :2; ///< Lane 2 mapping (see "Lane 0 mapping") 522 IN UINT8 Lane3 :2; ///< Lane 3 mapping (see "Lane 0 mapping") 523 } CHANNEL_MAPPING; ///< Lane mapping 524 525 /// Common Channel Mapping 526 typedef union { 527 IN UINT8 ChannelMappingValue; ///< Raw lane mapping 528 IN CHANNEL_MAPPING ChannelMapping; ///< Channel mapping 529 } CONN_CHANNEL_MAPPING; 530 531 /// DDI Configuration data 532 typedef struct { 533 IN UINT8 ConnectorType; /**< Display Connector Type 534 * @li @b 0 - DP 535 * @li @b 1 - eDP 536 * @li @b 2 - Single Link DVI-D 537 * @li @b 3 - Dual Link DVI-D (see @ref DualLinkDviDescription "Example Dual Link DVI connector description") 538 * @li @b 4 - HDMI 539 * @li @b 5 - DP-to-VGA 540 * @li @b 6 - DP-to-LVDS 541 * @li @b 7 - Hudson-2 NutMeg DP-to-VGA 542 * @li @b 8 - Single Link DVI-I 543 * @li @b 9 - Native CRT (Family 0x14) 544 * @li @b 10 - Native LVDS (Family 0x14) 545 * @li @b 11 - Auto detect LCD panel connector type. VBIOS is able to auto detect the LVDS connector type: native LVDS, eDP or DP-to-LVDS 546 * The auto detection method only support panel with EDID. 547 */ 548 IN UINT8 AuxIndex; /**< Indicates which AUX or DDC Line is used 549 * @li @b 0 - AUX1 550 * @li @b 1 - AUX2 551 * @li @b 2 - AUX3 552 * @li @b 3 - AUX4 553 * @li @b 4 - AUX5 554 * @li @b 5 - AUX6 555 */ 556 IN UINT8 HdpIndex; /**< Indicates which HDP pin is used 557 * @li @b 0 - HDP1 558 * @li @b 1 - HDP2 559 * @li @b 2 - HDP3 560 * @li @b 3 - HDP4 561 * @li @b 4 - HDP5 562 * @li @b 5 - HDP6 563 */ 564 IN CONN_CHANNEL_MAPPING Mapping[2]; /**< Set specific mapping of lanes to connector pins 565 * @li Mapping[0] define mapping for group of 4 lanes starting at PCIe_ENGINE_DATA.StartLane 566 * @li Mapping[1] define mapping for group of 4 lanes ending at PCIe_ENGINE_DATA.EndLane (only applicable for Dual DDI link) 567 * if Mapping[x] set to 0 than default mapping assumed 568 */ 569 IN UINT8 LanePnInversionMask; /**< Specifies whether to invert the state of P and N for each lane. Each bit represents a PCIe lane on the DDI port. 570 * @li 0 - Do not invert (default) 571 * @li 1 - Invert P and N on this lane 572 */ 573 IN UINT8 Flags; /**< Capabilities flags 574 * @li Flags bit[0] DDI_DATA_FLAGS_DP1_1_ONLY Selects downgrade PHY link to DP1.1 575 * @li Flags bit[7:1] Reserved 576 */ 577 } PCIe_DDI_DATA; 578 579 /// Engine Configuration 580 typedef struct { 581 IN UINT8 EngineType; /**< Engine type 582 * @li @b 0 - Ignore engine configuration 583 * @li @b 1 - PCIe port 584 * @li @b 2 - DDI 585 */ 586 IN UINT16 StartLane; /**< Start Lane ID (in reversed configuration StartLane > EndLane) 587 * Refer to lane descriptions and supported configurations in BKDG 588 */ 589 IN UINT16 EndLane; /**< End lane ID (in reversed configuration StartLane > EndLane) 590 * Refer to lane descriptions and supported configurations in BKDG 591 */ 592 593 } PCIe_ENGINE_DATA; 594 595 /// PCIe port descriptor 596 typedef struct { 597 IN UINT32 Flags; /**< Descriptor flags 598 * @li @b Bit31 - last descriptor in complex 599 */ 600 IN PCIe_ENGINE_DATA EngineData; ///< Engine data 601 IN PCIe_PORT_DATA Port; ///< PCIe port specific configuration info 602 } PCIe_PORT_DESCRIPTOR; 603 604 /// DDI descriptor 605 typedef struct { 606 IN UINT32 Flags; /**< Descriptor flags 607 * @li @b Bit31 - last descriptor in complex 608 */ 609 IN PCIe_ENGINE_DATA EngineData; ///< Engine data 610 IN PCIe_DDI_DATA Ddi; ///< DDI port specific configuration info 611 } PCIe_DDI_DESCRIPTOR; 612 613 /// PCIe Complex descriptor 614 typedef struct { 615 IN UINT32 Flags; /**< Descriptor flags 616 * @li @b Bit31 - last descriptor in topology 617 */ 618 IN UINT32 SocketId; ///< Socket Id 619 IN const PCIe_PORT_DESCRIPTOR *PciePortList; ///< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST). 620 IN const PCIe_DDI_DESCRIPTOR *DdiLinkList; ///< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST). 621 IN VOID *Reserved; ///< Reserved for future use 622 } PCIe_COMPLEX_DESCRIPTOR; 623 624 /// Action to control PCIe slot reset 625 typedef enum { 626 AssertSlotReset, ///< Assert slot reset 627 DeassertSlotReset ///< Deassert slot reset 628 } PCIE_RESET_CONTROL; 629 630 ///Slot Reset Info 631 typedef struct { 632 IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header 633 IN UINT8 ResetId; ///< Slot reset ID as specified in PCIe_PORT_DESCRIPTOR 634 IN UINT8 ResetControl; ///< Reset control as in PCIE_RESET_CONTROL 635 } PCIe_SLOT_RESET_INFO; 636 637 #define GFX_VBIOS_IMAGE_FLAG_SPECIAL_POST 0x1 638 639 ///VBIOS image info 640 typedef struct { 641 IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header 642 OUT VOID *ImagePtr; ///< Pointer to VBIOS image 643 IN PCI_ADDR GfxPciAddress; ///< PCI address of integrated graphics controller 644 IN UINT32 Flags; ///< BIT[0] - special repost requred 645 } GFX_VBIOS_IMAGE_INFO; 646 647 /// Engine descriptor type 648 typedef enum { 649 PcieUnusedEngine = 0, ///< Unused descriptor 650 PciePortEngine = 1, ///< PCIe port 651 PcieDdiEngine = 2, ///< DDI 652 MaxPcieEngine ///< Max engine type for boundary check. 653 } PCIE_ENGINE_TYPE; 654 655 /// PCIe link capability/speed 656 typedef enum { 657 PcieGenMaxSupported, ///< Maximum supported 658 PcieGen1 = 1, ///< Gen1 659 PcieGen2, ///< Gen2 660 PcieGen3, ///< Gen3 661 MaxPcieGen ///< Max Gen for boundary check 662 } PCIE_LINK_SPEED_CAP; 663 664 /// PCIe PSPP Power policy 665 typedef enum { 666 PsppDisabled, ///< PSPP disabled 667 PsppPerformance = 1, ///< Performance 668 PsppBalanceHigh, ///< Balance-High 669 PsppBalanceLow, ///< Balance-Low 670 PsppPowerSaving, ///< Power Saving 671 MaxPspp ///< Max Pspp for boundary check 672 } PCIE_PSPP_POLICY; 673 674 /// DDI display connector type 675 typedef enum { 676 ConnectorTypeDP, ///< DP 677 ConnectorTypeEDP, ///< eDP 678 ConnectorTypeSingleLinkDVI, ///< Single Link DVI-D 679 ConnectorTypeDualLinkDVI, ///< Dual Link DVI-D 680 ConnectorTypeHDMI, ///< HDMI 681 ConnectorTypeDpToVga, ///< DP-to-VGA 682 ConnectorTypeDpToLvds, ///< DP-to-LVDS 683 ConnectorTypeNutmegDpToVga, ///< Hudson-2 NutMeg DP-to-VGA 684 ConnectorTypeSingleLinkDviI, ///< Single Link DVI-I 685 ConnectorTypeCrt, ///< CRT (VGA) 686 ConnectorTypeLvds, ///< LVDS 687 ConnectorTypeEDPToLvds, ///< 3rd party common eDP-to-LVDS translator chip without AMD SW init 688 ConnectorTypeEDPToLvdsSwInit, ///< 3rd party eDP-to-LVDS translator which requires AMD SW init 689 ConnectorTypeAutoDetect, ///< VBIOS auto detect connector type (native LVDS, eDP or DP-to-LVDS) 690 MaxConnectorType ///< Not valid value, used to verify input 691 } PCIE_CONNECTOR_TYPE; 692 693 /// PCIe link channel type 694 typedef enum { 695 ChannelTypeLowLoss, ///< Low Loss 696 ChannelTypeHighLoss, ///< High Loss 697 ChannelTypeMob0db, ///< Mobile 0dB 698 ChannelTypeMob3db, ///< Mobile 3dB 699 ChannelTypeExt6db, ///< Extended 6dB 700 ChannelTypeExt8db, ///< Extended 8dB 701 MaxChannelType ///< Not valid value, used to verify input 702 } PCIE_CHANNEL_TYPE; 703 704 /// PCIe link ASPM 705 typedef enum { 706 AspmDisabled, ///< Disabled 707 AspmL0s, ///< PCIe L0s link state 708 AspmL1, ///< PCIe L1 link state 709 AspmL0sL1, ///< PCIe L0s & L1 link state 710 MaxAspm ///< Not valid value, used to verify input 711 } PCIE_ASPM_TYPE; 712 713 /// PCIe link hotplug support 714 typedef enum { 715 HotplugDisabled, ///< Hotplug disable 716 HotplugBasic, ///< Basic Hotplug 717 HotplugServer, ///< Server Hotplug 718 HotplugEnhanced, ///< Enhanced 719 HotplugInboard, ///< Inboard 720 MaxHotplug ///< Not valid value, used to verify input 721 } PCIE_HOTPLUG_TYPE; 722 723 /// PCIe link initialization 724 typedef enum { 725 PortDisabled, ///< Disable 726 PortEnabled ///< Enable 727 } PCIE_PORT_ENABLE; 728 729 /// PCIe ACS capability - Access Control Services 730 typedef enum { 731 PcieAcsDisabled, ///< Disabled 732 PcieAcsEnabled, ///< Enabled 733 } PCIE_ACS_CAP; 734 735 /// PCIe ClkPmSupport initialization 736 typedef enum { 737 ClkPmSupportDisabled, ///< Disable 738 ClkPmSupportEnabled ///< Enable 739 } CLKPM_SUPPORT_ENABLE; 740 741 /// DDI Aux channel 742 typedef enum { 743 Aux1, ///< Aux1 744 Aux2, ///< Aux2 745 Aux3, ///< Aux3 746 Aux4, ///< Aux4 747 Aux5, ///< Aux5 748 Aux6, ///< Aux6 749 MaxAux ///< Not valid value, used to verify input 750 } PCIE_AUX_TYPE; 751 752 /// DDI Hdp Index 753 typedef enum { 754 Hdp1, ///< Hdp1 755 Hdp2, ///< Hdp2 756 Hdp3, ///< Hdp3 757 Hdp4, ///< Hdp4 758 Hdp5, ///< Hdp5 759 Hdp6, ///< Hdp6 760 MaxHdp ///< Not valid value, used to verify input 761 } PCIE_HDP_TYPE; 762 763 /// PCIe_DDI_DATA.Flags definitions 764 #define DDI_DATA_FLAGS_DP1_1_ONLY 0x01 ///< BIT[0] Selects downgrade PHY link to DP1.1 765 #define EXT_DISPLAY_PATH_CAPS_DP_FIXED_VS_EN 0x02 ///< BIT[1] VBIOS will always output fixed voltage swing during DP link training 766 #define EXT_DISPLAY_PATH_CAPS_HDMI20_PI3EQX1204 0x04 ///< BIT[2] HDMI 2.0 connector 767 #define EXT_DISPLAY_PATH_CAPS_HDMI20_TISN65DP159RSBT 0x08 ///< BIT[3] HDMI 2.0 connector 768 #define EXT_DISPLAY_PATH_CAPS_HDMI20_PARADE_PS175 0x0C ///< BIT[3:2] DP -> HDMI recoverter chip 769 770 /// DP receiver definitions with fixed voltage swing 771 typedef enum { 772 DP_VS_0_4V_0DB, ///< 0x00 773 DP_VS_0_6V_0DB, ///< 0x01 774 DP_VS_0_8V_0DB, ///< 0x02 775 DP_VS_1_2V_0DB, ///< 0x03 776 DP_VS_0_4V_3_5DB = 0x8, ///< 0x08 777 DP_VS_0_6V_3_5DB, ///< 0x09 778 DP_VS_0_8V_3_5DB, ///< 0x0a 779 DP_VS_0_4V_6DB = 0x10, ///< 0x10 780 DP_VS_0_6V_6DB, ///< 0x11 781 DP_VS_0_4V_9_5DB = 0x18 ///< 0x18 782 } DP_FIXED_VOLT_SWING_TYPE; 783 784 // definition for eDP 1.4 VSMode 785 #define EDP_VS_LEGACY_MODE 0 ///< Legacy Mode 786 #define EDP_VS_LOW_VDIFF_MODE 1 ///< Low Vdiff Training Mode 787 #define EDP_VS_HIGH_VDIFF_MODE 2 ///< High Vdiff Training Mode 788 #define EDP_VS_STRETCH_MODE 3 ///< Stretched DP training mode 789 #define EDP_VS_SINGLE_VDIFF_MODE 4 ///< Single Vdiff Training Mode 790 #define EDP_VS_VARIABLE_PREM_MODE 5 ///< Single Vdiff Training with Variable Transition Vdiff 791 792 /// HDMI re-driver register/value 793 typedef struct _HDMI_RE_DRIVER_I2C_REG_INFO { 794 IN UINT8 RegIndex; ///< HDMI re-driver Register Index 795 IN UINT8 RegVal; ///< HDMI re-driver Register Value 796 } HDMI_RE_DRIVER_I2C_REG_INFO; 797 798 /// AZ I2SBUS select 799 typedef enum { 800 GnbAcpI2sBus, ///< I2sBus 801 GnbAcpAzalia, ///< Azalia 802 MaxAcp ///< Not valid value, used to verify input 803 } GNB_ACP_TYPE; 804 805 /// AZ I2SBUS pin configuration 806 typedef enum { 807 GnbAcp4Tx4RxBluetooth, ///< 4Tx4Rx and Bluetooth 808 GnbAcp2Tx4RxBluetooth, ///< 2Tx4Rx and Bluetooth 809 GnbAcp6Tx4RxBluetooth, ///< 6Tx4Rx and Bluetooth 810 GnbAcpPinNotConfigured ///< Not valid value, used to verify input 811 } GNB_ACP_AZ_I2SBUS_PIN; 812 813 /// Alternative DRAM MAC 814 typedef enum { 815 MAC_UNTESTEDMAC, ///< Assign 0 to Untested MAC 816 MAC_700k, ///< Assign 1 to 700k 817 MAC_600k, ///< Assign 2 to 600k 818 MAC_500k, ///< Assign 3 to 500k 819 MAC_400k, ///< Assign 4 to 400k 820 MAC_300k, ///< Assign 5 to 300k 821 MAC_200k, ///< Assign 6 to 200k 822 MAC_UNRESTRICTEDMAC = 8, ///< Assign 8 to Unrestricted MAC 823 } DRAM_MAXIMUM_ACTIVATE_COUNT; 824 825 // Macro for statically initializing various structures 826 #define PCIE_ENGINE_DATA_INITIALIZER(mType, mStartLane, mEndLane) {mType, mStartLane, mEndLane} 827 #define PCIE_PORT_DATA_INITIALIZER(mPortPresent, mChannelType, mDevAddress, mHotplug, mMaxLinkSpeed, mMaxLinkCap, mAspm, mResetId) \ 828 {mPortPresent, mChannelType, mDevAddress, 0, mMaxLinkSpeed, mAspm, mHotplug, mResetId, {0, mMaxLinkCap, 0, 0}, {0, 0, 0}, EndpointDetect, \ 829 {ADAPT_IOC_ENABLED, ADAPT_DFE_CONTROL_DISABLED, ADAPT_LEQ_CONTROL_DC_GAIN_POLE, ADAPT_DOC_DISABLED, ADAPT_FOMC_ENABLED, ADAPT_PIOC_DISABLED}} 830 #define PCIE_PORT_DATA_INITIALIZER_V2(mPortPresent, mChannelType, mDevAddress, mDevFunction, mHotplug, mMaxLinkSpeed, mMaxLinkCap, mAspm, mResetId, mClkPmSupport) \ 831 {mPortPresent, mChannelType, mDevAddress, mDevFunction, mMaxLinkSpeed, mAspm, mHotplug, mResetId, {0, mMaxLinkCap, 0, mClkPmSupport}, {0, 0, 0}, EndpointDetect, \ 832 {ADAPT_IOC_ENABLED, ADAPT_DFE_CONTROL_DISABLED, ADAPT_LEQ_CONTROL_DC_GAIN_POLE, ADAPT_DOC_DISABLED, ADAPT_FOMC_ENABLED, ADAPT_PIOC_DISABLED}} 833 #define PCIE_PORT_DATA_INITIALIZER_GEN3(mPortPresent, mChannelType, mDevAddress, mDevFunction, mHotplug, mMaxLinkSpeed, mMaxLinkCap, mAspm, mResetId, mClkPmSupport, \ 834 mInitOffsetCancellation, mDFEControl, mLEQControl, mDynamicOffsetCalibration, mFOMCalculation, mPIOffsetCalibration) \ 835 {mPortPresent, mChannelType, mDevAddress, mDevFunction, mMaxLinkSpeed, mAspm, mHotplug, mResetId, {0, mMaxLinkCap, 0, mClkPmSupport}, {0, 0, 0}, EndpointDetect, \ 836 {mInitOffsetCancellation, mDFEControl, mLEQControl, mDynamicOffsetCalibration, mFOMCalculation, mPIOffsetCalibration}} 837 #define PCIE_DDI_DATA_INITIALIZER(mConnectorType, mAuxIndex, mHpdIndex ) \ 838 {mConnectorType, mAuxIndex, mHpdIndex, {{0}, {0}}, 0, 0} 839 #define PCIE_DDI_DATA_INITIALIZER_V1(mConnectorType, mAuxIndex, mHpdIndex, mMapping0, mMapping1, mPNInversion) \ 840 {mConnectorType, mAuxIndex, mHpdIndex, {mMapping0, mMapping1}, mPNInversion, 0} 841 #define PCIE_DDI_DATA_INITIALIZER_V2(mConnectorType, mAuxIndex, mHpdIndex, mMapping0, mMapping1, mPNInversion, mFlags) \ 842 {mConnectorType, mAuxIndex, mHpdIndex, {mMapping0, mMapping1}, mPNInversion, mFlags} 843 844 ///IOMMU requestor ID 845 typedef struct { 846 IN UINT16 Bus :8; ///< Bus 847 IN UINT16 Device :5; ///< Device 848 IN UINT16 Function :3; ///< Function 849 } IOMMU_REQUESTOR_ID; 850 851 /// IVMD exclusion range descriptor 852 typedef struct { 853 IN UINT32 Flags; /**< Descriptor flags 854 * @li @b Flags[31] - Terminate descriptor array. 855 * @li @b Flags[30] - Ignore descriptor. 856 */ 857 IN IOMMU_REQUESTOR_ID RequestorIdStart; ///< Requestor ID start 858 IN IOMMU_REQUESTOR_ID RequestorIdEnd; ///< Requestor ID end (use same as start for single ID) 859 IN UINT64 RangeBaseAddress; ///< Phisical base address of exclusion range 860 IN UINT64 RangeLength; ///< Length of exclusion range in bytes 861 } IOMMU_EXCLUSION_RANGE_DESCRIPTOR; 862 863 /*---------------------------------------------------------------------------- 864 * GNB configuration info 865 *---------------------------------------------------------------------------- 866 */ 867 868 /// LVDS Misc Control Field 869 typedef struct { 870 IN UINT8 FpdiMode:1; ///< This item configures LVDS 888bit panel mode 871 ///< @li FALSE = LVDS 888 panel in LDI mode 872 ///< @li TRUE = LVDS 888 panel in FPDI mode 873 ///< @BldCfgItem{BLDCFG_LVDS_MISC_888_FPDI_MODE} 874 IN UINT8 DlChSwap:1; ///< This item configures LVDS panel lower and upper link mapping 875 ///< @li FALSE = Lower link and upper link not swap 876 ///< @li TRUE = Lower link and upper link are swapped 877 ///< @BldCfgItem{BLDCFG_LVDS_MISC_DL_CH_SWAP} 878 IN UINT8 BitDepth:1; ///< Customer may use 888 bit LVDS panel, but the LVDS panel EDID does not support v1.4 so that VBIOS can not decide the panel bit per color 879 ///< @li FALSE = LCD 666 18bit panel 880 ///< @li TRUE = LCD 888 24bit panel 881 ///< @BldCfgItem{BLDCFG_LVDS_BIT_DEPTH} 882 IN UINT8 ParamOverwriteEn:1; ///< LVDS parameter overwrite enable 883 ///< @li FALSE = LVDS parameter overwrite disable 884 ///< @li TRUE = LVDS parameter overwrite enable 885 ///< @BldCfgItem{BLDCFG_LVDS_PARAM_OVERWRITE_EN} 886 IN UINT8 BLONActiveLow:1; ///< This item configures polarity of signal sent to digital BLON output pin 887 ///< @li FALSE = Not inverted(active high) 888 ///< @li TRUE = Inverted (active low) 889 ///< @BldCfgItem{BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW} 890 IN UINT8 LvdsVoltOverwriteEn:1; ///< This item configures polarity of DP-to-LVDS output voltage overwrite 891 ///< @li FALSE = DP-to-LVDS output voltage overwrite disable, use VBIOS default setting. 892 ///< @li TRUE = Use ucLVDSVolAdjust value to program register LVDS_CTRL_4 893 ///< @BldCfgItem{BLDCFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE} 894 IN UINT8 Reserved:2; ///< Reserved 895 } LVDS_MISC_CONTROL_FIELD; 896 897 /// LVDS Misc Control 898 typedef union _LVDS_MISC_CONTROL { 899 IN LVDS_MISC_CONTROL_FIELD Field; ///< LVDS_MISC_CONTROL_FIELD 900 IN UINT8 Value; ///< LVDS Misc Control Value 901 } LVDS_MISC_CONTROL; 902 903 /// Display Misc Control Field 904 typedef struct { 905 IN UINT8 Reserved1:3; ///< Reserved 906 IN UINT8 VbiosFastBootEn:1; ///< This item configures VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open. 907 ///< @li FALSE = VBIOS fast boot is disable. 908 ///< @li TRUE = VBIOS fast boot is enable. 909 ///< @BldCfgItem{BLDCFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE} 910 IN UINT8 Reserved2:4; ///< Reserved 911 } DISPLAY_MISC_CONTROL_FIELD; 912 913 /// LVDS Misc Control 914 typedef union _DISPLAY_MISC_CONTROL { 915 IN DISPLAY_MISC_CONTROL_FIELD Field; ///< DISPLAY_MISC_CONTROL_FIELD 916 IN UINT8 Value; ///< Display Misc Control Value 917 } DISPLAY_MISC_CONTROL; 918 919 /// HD Audio Codec table list 920 typedef struct _CODEC_VERB_TABLE_LIST { 921 IN UINT32 CodecId; ///< CodecID - Codec ID 922 IN CONST VOID * CodecTablePtr; ///< CodecTablePtr - Codec table pointer 923 } CODEC_VERB_TABLE_LIST; 924 925 /// POST Configuration settings for GNB. 926 typedef struct { 927 IN UINT8 IgpuEnableDisablePolicy; ///< This item defines the iGPU Enable/Disable policy 928 ///< @li 0 = Auto - use existing default - 929 ///< @li 1 = Disable iGPU if any PCIe/PCI graphics card present 930 ///< @BldCfgItem{BLDCFG_IGPU_ENABLE_DISABLE_POLICY} 931 } GNB_POST_CONFIGURATION; 932 933 /// iGPU Enable/Disable Policy values 934 #define IGPU_DISABLE_AUTO 0 ///< Auto setting - disable iGPU if ANY PCI graphics or non-AMD PCIe graphics 935 #define IGPU_DISABLE_ANY_PCIE 1 ///< Disable iGPU if any PCI or PCIE graphics card is present 936 937 /// ENV Configuration settings for GNB. 938 typedef struct { 939 IN UINT8 Gnb3dStereoPinIndex; ///< 3D Stereo Pin ID. 940 ///< @li 0 = Stereo 3D is disabled (default). 941 ///< @li 1 = Use processor pin HPD1. 942 ///< @li 2 = Use processor pin HPD2 943 ///< @li 3 = Use processor pin HPD3 944 ///< @li 4 = Use processor pin HPD4 945 ///< @li 5 = Use processor pin HPD5 946 ///< @li 6 = Use processor pin HPD6 947 ///< @BldCfgItem{BLDCFG_STEREO_3D_PINOUT} 948 IN BOOLEAN IommuSupport; ///< IOMMU support. 949 ///< @li FALSE = Disabled. Disable and hide IOMMU device. 950 ///< @li TRUE = Initialize IOMMU subsystem. Generate ACPI IVRS table. 951 ///< BldCfgItem{BLDCFG_IOMMU_SUPPORT} 952 IN UINT16 LvdsSpreadSpectrum; ///< Spread spectrum value in 0.01 % 953 ///< BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM} 954 IN UINT16 LvdsSpreadSpectrumRate; ///< Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz 955 ///< BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE} 956 IN UINT8 LvdsPowerOnSeqDigonToDe; ///< This item configures panel initialization timing. 957 ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE} 958 IN UINT8 LvdsPowerOnSeqDeToVaryBl; ///< This item configures panel initialization timing. 959 ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL} 960 IN UINT8 LvdsPowerOnSeqDeToDigon; ///< This item configures panel initialization timing. 961 ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON} 962 IN UINT8 LvdsPowerOnSeqVaryBlToDe; ///< This item configures panel initialization timing. 963 ///< @BldCfgItem{BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE} 964 IN UINT8 LvdsPowerOnSeqOnToOffDelay; ///< This item configures panel initialization timing. 965 ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY} 966 IN UINT8 LvdsPowerOnSeqVaryBlToBlon; ///< This item configures panel initialization timing. 967 ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON} 968 IN UINT8 LvdsPowerOnSeqBlonToVaryBl; ///< This item configures panel initialization timing. 969 ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL} 970 IN UINT16 LvdsMaxPixelClockFreq; ///< This item configures the maximum pixel clock frequency supported. 971 ///< @BldCfgItem{BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ} 972 IN UINT32 LcdBitDepthControlValue; ///< This item configures the LCD bit depth control settings. 973 ///< @BldCfgItem{BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE} 974 IN UINT8 Lvds24bbpPanelMode; ///< This item configures the LVDS 24 BBP mode. 975 ///< @BldCfgItem{BLDCFG_LVDS_24BBP_PANEL_MODE} 976 IN LVDS_MISC_CONTROL LvdsMiscControl;///< This item configures LVDS swap/Hsync/Vsync/BLON 977 IN UINT16 PcieRefClkSpreadSpectrum; ///< Spread spectrum value in 0.01 % 978 ///< @BldCfgItem{BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM} 979 IN BOOLEAN GnbRemoteDisplaySupport; ///< This item enables Wireless Display Support 980 ///< @li TRUE = Enable Wireless Display Support 981 ///< @li FALSE = Disable Wireless Display Support 982 ///< @BldCfgItem{BLDCFG_REMOTE_DISPLAY_SUPPORT} 983 IN UINT8 LvdsMiscVoltAdjustment; ///< Register LVDS_CTRL_4 to adjust LVDS output voltage 984 ///< @BldCfgItem{BLDCFG_LVDS_MISC_VOL_ADJUSTMENT} 985 IN DISPLAY_MISC_CONTROL DisplayMiscControl;///< This item configures display misc control 986 IN DP_FIXED_VOLT_SWING_TYPE DpFixedVoltSwingType;///< To indicate fixed voltage swing value 987 ///< @BldCfgItem{BLDCFG_DP_FIXED_VOLT_SWING} 988 IN UINT32 GpuFrequencyLimit; ///< GNB GPU Max Frequency(NULL if platform configured) 989 ///< @BldCfgItem{BLDCFG_GPU_FREQUENCY_LIMIT} 990 IN UINT8 EDPv1_4VSMode; ///< @BldCfgItem{BLDCFG_EDP_V1_4_VS_MODE} 991 IN UINT8 ExtHDMIReDrvSlvAddr; ///< @BldCfgItem{BLDCFG_EXT_HDMI_RE_DRIVE_SLAVE_ADDR} 992 IN UINT8 ExtHDMIReDrvRegNum; ///< @BldCfgItem{BLDCFG_EXT_HDMI_RE_DRIVE_REG_NUM} 993 IN UINT64 ExtHDMIRegSetting; ///< @BldCfgItem{BLDCFG_EXT_HDMI_RE_DRIVE_REG_INFO} 994 IN UINT8 DP0ExtHDMIReDrvSlvAddr; ///< @BldCfgItem{BLDCFG_DP0_EXT_HDMI_RE_DRIVE_SLAVE_ADDR} 995 IN UINT8 DP0ExtHDMIReDrvRegNum; ///< @BldCfgItem{BLDCFG_DP0_EXT_HDMI_RE_DRIVE_REG_NUM} 996 IN UINT64 DP0ExtHDMIRegSetting; ///< @BldCfgItem{BLDCFG_DP0_EXT_HDMI_RE_DRIVE_REG_INFO} 997 IN UINT8 DP1ExtHDMIReDrvSlvAddr; ///< @BldCfgItem{BLDCFG_DP1_EXT_HDMI_RE_DRIVE_SLAVE_ADDR} 998 IN UINT8 DP1ExtHDMIReDrvRegNum; ///< @BldCfgItem{BLDCFG_DP1_EXT_HDMI_RE_DRIVE_REG_NUM} 999 IN UINT64 DP1ExtHDMIRegSetting; ///< @BldCfgItem{BLDCFG_DP1_EXT_HDMI_RE_DRIVE_REG_INFO} 1000 IN UINT8 DP2ExtHDMIReDrvSlvAddr; ///< @BldCfgItem{BLDCFG_DP2_EXT_HDMI_RE_DRIVE_SLAVE_ADDR} 1001 IN UINT8 DP2ExtHDMIReDrvRegNum; ///< @BldCfgItem{BLDCFG_DP2_EXT_HDMI_RE_DRIVE_REG_NUM} 1002 IN UINT64 DP2ExtHDMIRegSetting; ///< @BldCfgItem{BLDCFG_DP2_EXT_HDMI_RE_DRIVE_REG_INFO} 1003 IN UINT8 DP0ExtHDMI6GRegNum; ///< @BldCfgItem{BLDCFG_DP0_EXT_HDMI_6G_REG_NUM} 1004 IN UINT64 DP0ExtHDMI6GhzRegSetting; ///< @BldCfgItem{BLDCFG_DP0_EXT_HDMI_6Ghz_REG_INFO} 1005 IN UINT8 DP1ExtHDMI6GRegNum; ///< @BldCfgItem{BLDCFG_DP1_EXT_HDMI_6G_REG_NUM} 1006 IN UINT64 DP1ExtHDMI6GhzRegSetting; ///< @BldCfgItem{BLDCFG_DP1_EXT_HDMI_6Ghz_REG_INFO} 1007 IN UINT8 DP2ExtHDMI6GRegNum; ///< @BldCfgItem{BLDCFG_DP2_EXT_HDMI_6G_REG_NUM} 1008 IN UINT64 DP2ExtHDMI6GhzRegSetting; ///< @BldCfgItem{BLDCFG_DP2_EXT_HDMI_6Ghz_REG_INFO} 1009 1010 } GNB_ENV_CONFIGURATION; 1011 1012 /// Configuration settings for GNB. 1013 typedef struct { 1014 IN UINT8 iGpuVgaMode; ///< VGA resources decoding configuration for iGPU 1015 ///< @li 0 = iGPU decode all VGA resources (must be primary VGA adapter) 1016 ///< @li 1 = iGPU will not decode any VGA resources (must be secondary graphics adapter) 1017 IN UINT8 PcieAcsCapability; ///< Pcie ACS Capability support 1018 ///< @li 0 = Disabled 1019 ///< @li 1 = Enabled 1020 IN UINT64 GnbIoapicAddress; ///< GNB IOAPIC Base Address(NULL if platform configured) 1021 ///< @BldCfgItem{BLDCFG_GNB_IOAPIC_ADDRESS} 1022 IN UINT8 MaxNumAudioEndpoints; ///< Max number of audio endpoints 1023 ///< @BldCfgItem{BLDCFG_MAX_NUM_AUDIO_ENDPOINTS} 1024 } GNB_MID_CONFIGURATION; 1025 1026 /// GNB configuration info 1027 typedef struct { 1028 IN const PCIe_COMPLEX_DESCRIPTOR *PcieComplexList; /**< Pointer to array of structures describe PCIe topology on each processor package or NULL. 1029 * Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST 1030 * Example of topology definition for single socket system: 1031 * @code 1032 * PCIe_PORT_DESCRIPTOR PortList [] = { 1033 * // Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...) 1034 * { 1035 * 0, //Descriptor flags 1036 * PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15), 1037 * PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) 1038 * }, 1039 * // Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...) 1040 * { 1041 * 0, //Descriptor flags 1042 * PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 19), 1043 * PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) 1044 * }, 1045 * // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) 1046 * { 1047 * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array 1048 * PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), 1049 * PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) 1050 * } 1051 * }; 1052 * PCIe_PORT_DESCRIPTOR DdiList [] = { 1053 * // Initialize Ddi descriptor (DDI interface Lanes 24:27, Display Port Connector, ...) 1054 * { 1055 * 0, //Descriptor flags 1056 * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), 1057 * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1, 0) 1058 * }, 1059 * // Initialize Ddi descriptor (DDI interface Lanes 28:31, HDMI, ...) 1060 * { 1061 * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array 1062 * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), 1063 * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2, 0) 1064 * } 1065 * }; 1066 * PCIe_COMPLEX_DESCRIPTOR PlatformTopology = { 1067 * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate complexes list 1068 * 0, //Socket ID 1069 * &PortList[0], 1070 * &DdiList[0], 1071 * } 1072 * @endcode 1073 */ 1074 IN UINT8 PsppPolicy; /**< PSPP (PCIe Speed Power Policy) 1075 * @li @b 0 - Disabled 1076 * @li @b 1 - Performance 1077 * @li @b 2 - Balance-High 1078 * @li @b 3 - Balance-Low 1079 * @li @b 4 - Power Saving 1080 */ 1081 1082 } GNB_CONFIGURATION; 1083 1084 /// Late Configuration settings for GNB. 1085 typedef struct { 1086 IN BOOLEAN Reserved; ///< Reserved -- Docked TDP headroom 1087 IN UINT8 GnbIoapicId; ///< GNB IOAPIC ID, platform BIOS needs to pass correct id number, default is 0xFF. 1088 ///< If BLDCFG_GNB_IOAPIC_ADDRESS == NULL or BLDCFG_IOMMU_SUPPORT == NULL or GnbIoapicId == default(0xFF), AGESA will skip it anyway. 1089 ///< @li 0~n = IOAPIC ID number for IVRS which should be matched with MADT 1090 IN UINT8 FchIoapicId; ///< Fch IOAPIC ID, platform BIOS needs to pass correct id number, default is 0xFF. 1091 ///< If BLDCFG_IOMMU_SUPPORT == NULL or or FchIoapicId == default(0xFF), AGESA will skip it anyway. 1092 ///< @li 0~n = IOAPIC ID number for IVRS which should be matched with MADT 1093 1094 } GNB_LATE_CONFIGURATION; 1095 1096 // 1097 // MEMORY-SPECIFIC DATA STRUCTURES 1098 // 1099 // 1100 // 1101 // 1102 // AGESA MAXIMIUM VALUES 1103 // 1104 // These Max values are used to define array sizes and associated loop 1105 // counts in the code. They reflect the maximum values that AGESA 1106 // currently supports and does not necessarily reflect the hardware 1107 // capabilities of configuration. 1108 // 1109 1110 #define MAX_SOCKETS_SUPPORTED 1 ///< Max number of sockets in system 1111 #define MAX_CHANNELS_PER_SOCKET 4 ///< Max Channels per sockets 1112 #define MAX_DIMMS_PER_CHANNEL 4 ///< Max DIMMs on a memory channel (independent of platform) 1113 #define NUMBER_OF_DELAY_TABLES 9 ///< Number of tables defined in CH_DEF_STRUCT. 1114 ///< Eg: UINT16 *RcvEnDlys; 1115 ///< UINT8 *WrDqsDlys; 1116 ///< UINT8 *RdDqsDlys; 1117 ///< UINT8 *WrDatDlys; 1118 ///< UINT8 *RdDqsMinDlys; 1119 ///< UINT8 *RdDqsMaxDlys; 1120 ///< UINT8 *WrDatMinDlys; 1121 ///< UINT8 *WrDatMaxDlys; 1122 #define NUMBER_OF_FAILURE_MASK_TABLES 1 ///< Number of failure mask tables 1123 1124 #define MAX_PLATFORM_TYPES 16 ///< Platform types per system 1125 1126 #define MCT_TRNG_KEEPOUT_START 0x00004000ul ///< base [39:8] 1127 #define MCT_TRNG_KEEPOUT_END 0x00007FFFul ///< base [39:8] 1128 #define DATAEYE_VREF_RANGE 31 ///< Number of VREF steps in Data Eye Bitmap 1129 1130 #define UMA_ATTRIBUTE_INTERLEAVE 0x80000000ul ///< Uma Region is interleaved 1131 #define UMA_ATTRIBUTE_ON_DCT0 0x40000000ul ///< UMA resides on memory that belongs to DCT0 1132 #define UMA_ATTRIBUTE_ON_DCT1 0x20000000ul ///< UMA resides on memory that belongs to DCT1 1133 #define UMA_ATTRIBUTE_ON_DCT2 0x10000000ul ///< UMA resides on memory that belongs to DCT2 1134 #define UMA_ATTRIBUTE_ON_DCT3 0x08000000ul ///< UMA resides on memory that belongs to DCT3 1135 1136 typedef UINT8 PSO_TABLE; ///< Platform Configuration Table 1137 1138 // AGESA DEFINITIONS 1139 // 1140 // Many of these are derived from the platform and hardware specific definitions 1141 1142 /// EccSymbolSize override value 1143 #define ECCSYMBOLSIZE_USE_BKDG 0 ///< Use BKDG Recommended Value 1144 #define ECCSYMBOLSIZE_FORCE_X4 4 ///< Force to x4 1145 #define ECCSYMBOLSIZE_FORCE_X8 8 ///< Force to x8 1146 /// CPU Package Type 1147 #define PT_L1 0 ///< L1 Package type 1148 #define PT_M2 1 ///< AM Package type 1149 #define PT_S1 2 ///< S1 Package type 1150 1151 /// Build Configuration values for BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT & BLDCFG_MEMORY_CLOCK_SELECT 1152 #define DDR400_FREQUENCY 200 ///< DDR 400 1153 #define DDR533_FREQUENCY 266 ///< DDR 533 1154 #define DDR667_FREQUENCY 333 ///< DDR 667 1155 #define DDR800_FREQUENCY 400 ///< DDR 800 1156 #define DDR1066_FREQUENCY 533 ///< DDR 1066 1157 #define DDR1333_FREQUENCY 667 ///< DDR 1333 1158 #define DDR1600_FREQUENCY 800 ///< DDR 1600 1159 #define DDR1866_FREQUENCY 933 ///< DDR 1866 1160 #define DDR2100_FREQUENCY 1050 ///< DDR 2100 1161 #define DDR2133_FREQUENCY 1066 ///< DDR 2133 1162 #define DDR2400_FREQUENCY 1200 ///< DDR 2400 1163 #define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency 1164 1165 /// Build Configuration values for BLDCFG_TIMING_MODE_SELECT 1166 #define TIMING_MODE_AUTO 0 ///< Use best rate possible 1167 #define TIMING_MODE_LIMITED 1 ///< Set user top limit 1168 #define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed 1169 1170 /// Build Configuration values for BLDCFG_MEMORY_QUADRANK_TYPE 1171 #define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM 1172 #define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM 1173 1174 /// Build Configuration values for BLDCFG_POWER_DOWN_MODE 1175 #define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode 1176 #define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode 1177 #define POWER_DOWN_MODE_AUTO 2 ///< AGESA to select power down mode 1178 1179 /// Build Configuration limit for BLDCFG_GNB_GPU_MAX_FREQUENCY 1180 #define UNSUPPORTED_GPU_FREQUENCY 901 ///< Highest limit of GPU frequency 1181 1182 /// Structures use to pass system Logical CPU-ID 1183 typedef struct { 1184 IN OUT UINT16 Family; ///< Indicates logical ID Family 1185 IN OUT UINT16 Revision; ///< Indicates logical ID Family 1186 } CPU_LOGICAL_ID; 1187 1188 /// Structures use to report AMP status 1189 typedef struct { 1190 OUT BOOLEAN AmpVoltageValid; ///< Indicates if Amp voltage is valid 1191 OUT BOOLEAN AmpSupportDetectedButNotEnabled; ///< Indicates if Amp support is detected but not enabled 1192 OUT BOOLEAN AmpSelectedButNotEnabled; ///< Indicates if Amp is selected but not enabled 1193 } AMP_STATUS; 1194 1195 /// Normalized Critical Composite Data Eye 1196 /// Bit 15 represents trained eye Center 1197 /// Bit 0 represents eye center -15 delay steps 1198 /// Bit 31 represents eye center +16 delay steps 1199 /// Offset 0 represents +15 Vref Steps 1200 /// Offset 31 represents -15 Vref Steps 1201 typedef UINT32 COMPOSITE_DATAEYE[DATAEYE_VREF_RANGE]; 1202 1203 /// Build Configuration values for BLDCFG_AMD_PLATFORM_TYPE 1204 typedef enum { 1205 AMD_PLATFORM_SERVER = 0x8000, ///< Server 1206 AMD_PLATFORM_DESKTOP = 0x10000, ///< Desktop 1207 AMD_PLATFORM_MOBILE = 0x20000, ///< Mobile 1208 } AMD_PLATFORM_TYPE; 1209 1210 /// Dram technology type 1211 typedef enum { 1212 DDR2_TECHNOLOGY, ///< DDR2 technology 1213 DDR3_TECHNOLOGY, ///< DDR3 technology 1214 GDDR5_TECHNOLOGY, ///< GDDR5 technology 1215 DDR4_TECHNOLOGY, ///< DDR4 technology 1216 UNSUPPORTED_TECHNOLOGY, ///< Unsupported technology 1217 } TECHNOLOGY_TYPE; 1218 1219 /// Low voltage support 1220 typedef enum { 1221 VOLT_INITIAL, ///< Initial value for VDDIO 1222 VOLT1_5, ///< 1.5 Volt 1223 VOLT1_35, ///< 1.35 Volt 1224 VOLT1_25, ///< 1.25 Volt 1225 VOLT_DDR4_RANGE_START, ///< Start of DDR4 Voltage Range 1226 VOLT1_2 = VOLT_DDR4_RANGE_START, ///< 1.2 Volt 1227 VOLT_TBD1, ///< TBD1 Voltage 1228 VOLT_TBD2, ///< TBD2 Voltage 1229 VOLT_UNSUPPORTED = 0xFF ///< No common voltage found 1230 } DIMM_VOLTAGE; 1231 1232 /// AMP voltage support 1233 typedef enum { 1234 AMP_VOLT_RSVD, ///< Reserved 1235 AMP_VOLT1_5, ///< 1.5 Volt 1236 AMP_VOLT1_55, ///< 1.55 Volt 1237 AMP_VOLT1_6, ///< 1.6 Volt 1238 AMP_VOLT1_65, ///< 1.65 Volt 1239 AMP_VOLT1_7, ///< 1.7 Volt 1240 AMP_VOLT1_75, ///< 1.75 Volt 1241 AMP_VOLT1_8, ///< 1.8 Volt 1242 AMP_VOLT1_85, ///< 1.85 Volt 1243 AMP_VOLT1_9, ///< 1.9 Volt 1244 AMP_VOLT1_45 = 0x10, ///< 1.45 Volt 1245 AMP_VOLT1_4 = 0x20, ///< 1.4 Volt 1246 AMP_VOLT1_35 = 0x30, ///< 1.35 Volt 1247 AMP_VOLT1_3 = 0x40, ///< 1.3 Volt 1248 AMP_VOLT1_25 = 0x50, ///< 1.25 Volt 1249 AMP_VOLT1_2 = 0x60 ///< 1.2 Volt 1250 } AMP_DIMM_VOLTAGE; 1251 1252 /// Build Configuration values for BLDCFG_RESOLUTION 1253 typedef enum { 1254 DISPLAY_1920x1080_And_Below = 0, ///< 1920x1080 and below 1255 DISPLAY_2560x1600 = 1, ///< 2560x1600 1256 DISPLAY_3840x2160 = 2 ///< 3840x2160 1257 } DISPLAY_RESOLUTION; 1258 1259 /// Build Configuration values for BLDCFG_ACP_SIZE 1260 typedef enum { 1261 NO_ACP_SIZE = 0x00, ///< NO ACP 1262 ACP_SIZE_2MB = 0x20, ///< UMA 4MB aligned 1263 ACP_SIZE_4MB = 0x40, ///< UMA 128MB aligned 1264 } ACP_SIZE; 1265 1266 /// UMA Version 1267 typedef enum { 1268 UMA_LEGACY = 0, ///< UMA Legacy Version 1269 UMA_NON_LEGACY = 1, ///< UMA Non Legacy Version 1270 UMA_HSFB = 2 ///< UMA HSFB Version 1271 } UMA_VERSION; 1272 1273 /// UMA Mode 1274 typedef enum { 1275 UMA_NONE = 0, ///< UMA None 1276 UMA_SPECIFIED = 1, ///< UMA Specified 1277 UMA_AUTO = 2 ///< UMA Auto 1278 } UMA_MODE; 1279 1280 /// Force Training Mode 1281 typedef enum { 1282 FORCE_TRAIN_1D = 0, ///< 1D Training only 1283 FORCE_TRAIN_2D = 1, ///< 2D Training only 1284 FORCE_TRAIN_AUTO = 2 ///< Auto - 1D or 2D depending on configuration 1285 } FORCE_TRAIN_MODE; 1286 1287 /// PMU Training Mode 1288 typedef enum { 1289 PMU_TRAIN_1D = 0, ///< PMU 1D Training only 1290 PMU_TRAIN_1D_2D_READ = 1, ///< PMU 1D and 2D Training read only 1291 PMU_TRAIN_1D_2D = 2, ///< PMU 1D and 2D Training 1292 PMU_TRAIN_AUTO = 3 ///< Auto - PMU Training depend on configuration 1293 } PMU_TRAIN_MODE; 1294 1295 /// BankSwapOnly Mode 1296 typedef enum { 1297 BANK_SWAP_ONLY_DISABLED = 0, ///< Disable Bank Swap Only 1298 BANK_SWAP_ONLY_ENABLED = 1, ///< Enable Bank Swap Only 1299 BANK_SWAP_ONLY_AUTO = 2 ///< Auto - BankSwapOnly depending on family specific configuration 1300 } BANK_SWAP_ONLY_MODE; 1301 1302 1303 /// The possible DRAM prefetch mode settings. 1304 typedef enum { 1305 DRAM_PREFETCHER_AUTO, ///< Use the recommended setting for the processor. In most cases, the recommended setting is enabled. 1306 DISABLE_DRAM_PREFETCH_FOR_IO, ///< Disable DRAM prefetching for I/O requests only. 1307 DISABLE_DRAM_PREFETCH_FOR_CPU, ///< Disable DRAM prefetching for requests from processor cores only. 1308 DISABLE_DRAM_PREFETCHER, ///< Disable DRAM prefetching. 1309 MAX_DRAM_FREFETCH_MODE ///< Not a DRAM prefetch mode, use for limit checking. 1310 } DRAM_PREFETCH_MODE; 1311 1312 /// Build Configuration values for BLDCFG_UMA_ALIGNMENT 1313 typedef enum { 1314 NO_UMA_ALIGNED = 0x00FFFFFF, ///< NO UMA aligned 1315 UMA_4MB_ALIGNED = 0x00FFFFC0, ///< UMA 4MB aligned 1316 UMA_128MB_ALIGNED = 0x00FFF800, ///< UMA 128MB aligned 1317 UMA_256MB_ALIGNED = 0x00FFF000, ///< UMA 256MB aligned 1318 UMA_512MB_ALIGNED = 0x00FFE000, ///< UMA 512MB aligned 1319 } UMA_ALIGNMENT; 1320 1321 /// 1322 /// Global MCT Configuration Status Word (GStatus) 1323 /// 1324 typedef enum { 1325 GsbMTRRshort, ///< Ran out of MTRRs while mapping memory 1326 GsbAllECCDimms, ///< All banks of all Nodes are ECC capable 1327 GsbDramECCDis, ///< Dram ECC requested but not enabled. 1328 GsbSoftHole, ///< A Node Base gap was created 1329 GsbHWHole, ///< A HW dram remap was created 1330 GsbNodeIntlv, ///< Node Memory interleaving was enabled 1331 GsbSpIntRemapHole, ///< Special condition for Node Interleave and HW remapping 1332 GsbEnDIMMSpareNW, ///< Indicates that DIMM Spare can be used without a warm reset 1333 1334 GsbEOL ///< End of list 1335 } GLOBAL_STATUS_FIELD; 1336 1337 /// 1338 /// Local Error Status (DIE_STRUCT.ErrStatus[31:0]) 1339 /// 1340 typedef enum { 1341 EsbNoDimms, ///< No DIMMs 1342 EsbSpdChkSum, ///< SPD Checksum fail 1343 EsbDimmMismatchM, ///< dimm module type(buffer) mismatch 1344 EsbDimmMismatchT, ///< dimm CL/T mismatch 1345 EsbDimmMismatchO, ///< dimm organization mismatch (128-bit) 1346 EsbNoTrcTrfc, ///< SPD missing Trc or Trfc info 1347 EsbNoCycTime, ///< SPD missing byte 23 or 25 1348 EsbBkIntDis, ///< Bank interleave requested but not enabled 1349 EsbDramECCDis, ///< Dram ECC requested but not enabled 1350 EsbSpareDis, ///< Online spare requested but not enabled 1351 EsbMinimumMode, ///< Running in Minimum Mode 1352 EsbNoRcvrEn, ///< No DQS Receiver Enable pass window found 1353 EsbSmallRcvr, ///< DQS Rcvr En pass window too small (far right of dynamic range) 1354 EsbNoDqsPos, ///< No DQS-DQ passing positions 1355 EsbSmallDqs, ///< DQS-DQ passing window too small 1356 EsbDCBKScrubDis, ///< DCache scrub requested but not enabled 1357 1358 EsbEMPNotSupported, ///< Processor is not capable for EMP. 1359 EsbEMPConflict, ///< EMP requested but cannot be enabled since 1360 ///< channel interleaving, bank interleaving, or bank swizzle is enabled. 1361 EsbEMPDis, ///< EMP requested but cannot be enabled since 1362 ///< memory size of each DCT is not a power of two. 1363 1364 EsbEOL ///< End of list 1365 } ERROR_STATUS_FIELD; 1366 1367 /// 1368 /// Local Configuration Status (DIE_STRUCT.Status[31:0]) 1369 /// 1370 typedef enum { 1371 SbRegistered, ///< All DIMMs are Registered 1372 SbEccDimms, ///< All banks ECC capable 1373 SbParDimms, ///< All banks Addr/CMD Parity capable 1374 SbDiagClks, ///< Jedec ALL slots clock enable diag mode 1375 Sb128bitmode, ///< DCT in 128-bit mode operation 1376 Sb64MuxedMode, ///< DCT in 64-bit mux'ed mode. 1377 Sb2TMode, ///< 2T CMD timing mode is enabled. 1378 SbSWNodeHole, ///< Remapping of Node Base on this Node to create a gap. 1379 SbHWHole, ///< Memory Hole created on this Node using HW remapping. 1380 SbOver400Mhz, ///< DCT freq greater than or equal to 400MHz flag 1381 SbDQSPosPass2, ///< Used for TrainDQSPos DIMM0/1, when freq greater than or equal to 400MHz 1382 SbDQSRcvLimit, ///< Used for DQSRcvEnTrain to know we have reached the upper bound. 1383 SbExtConfig, ///< Indicate the default setting for extended PCI configuration support 1384 SbLrdimms, ///< All DIMMs are LRDIMMs 1385 1386 SbEOL ///< End of list 1387 } LOCAL_STATUS_FIELD; 1388 1389 1390 ///< CPU MSR Register definitions ------------------------------------------ 1391 #define SYS_CFG 0xC0010010ul 1392 #define TOP_MEM 0xC001001Aul 1393 #define TOP_MEM2 0xC001001Dul 1394 #define HWCR 0xC0010015ul 1395 #define NB_CFG 0xC001001Ful 1396 1397 #define FS_BASE 0xC0000100ul 1398 #define IORR0_BASE 0xC0010016ul 1399 #define IORR0_MASK 0xC0010017ul 1400 #define BU_CFG 0xC0011023ul 1401 #define BU_CFG2 0xC001102Aul 1402 #define COFVID_STAT 0xC0010071ul 1403 #define TSC 0x10 1404 1405 //----------------------------------------------------------------------------- 1406 /// 1407 /// SPD Data for each DIMM. 1408 /// 1409 typedef struct _SPD_DEF_STRUCT { 1410 IN BOOLEAN DimmPresent; ///< Indicates that the DIMM is present and Data is valid 1411 IN UINT8 PageAddress; ///< Indicates the 256 Byte EE Page the data belongs to 1412 ///< 0 = Lower Page 1413 ///< 1 = Upper Page (DDR4 Only) 1414 IN UINT8 Data[512]; ///< Buffer for 256 Bytes of SPD data from DIMM 1415 } SPD_DEF_STRUCT; 1416 1417 //----------------------------------------------------------------------------- 1418 /// 1419 /// VDDP_VDDR Voltage Info for Low Power DIMM 1420 /// 1421 typedef struct _VDDP_VDDR_VOLTAGE { 1422 IN BOOLEAN IsValid; ///< Indicates if daata is valid 1423 IN UINT8 Voltage; ///< VDDP VDDR Voltage Value 1424 } VDDP_VDDR_VOLTAGE; 1425 1426 /// 1427 /// Channel Definition Structure. 1428 /// This data structure defines entries that are specific to the channel initialization 1429 /// 1430 typedef struct _CH_DEF_STRUCT { 1431 OUT UINT8 ChannelID; ///< Physical channel ID of a socket(0 = CH A, 1 = CH B, 2 = CH C, 3 = CH D) 1432 OUT TECHNOLOGY_TYPE TechType; ///< Technology type of this channel 1433 OUT UINT8 ChDimmPresent; ///< For each bit n 0..7, 1 = DIMM n is present. 1434 ///< DIMM# Select Signal 1435 ///< 0 MA0_CS_L[0, 1] 1436 ///< 1 MB0_CS_L[0, 1] 1437 ///< 2 MA1_CS_L[0, 1] 1438 ///< 3 MB1_CS_L[0, 1] 1439 ///< 4 MA2_CS_L[0, 1] 1440 ///< 5 MB2_CS_L[0, 1] 1441 ///< 6 MA3_CS_L[0, 1] 1442 ///< 7 MB3_CS_L[0, 1] 1443 1444 OUT struct _DCT_STRUCT *DCTPtr; ///< Pointer to the DCT data of this channel. 1445 OUT struct _DIE_STRUCT *MCTPtr; ///< Pointer to the node data of this channel. 1446 OUT SPD_DEF_STRUCT *SpdPtr; ///< Pointer to the SPD data for this channel. (Setup by NB Constructor) 1447 OUT SPD_DEF_STRUCT *DimmSpdPtr[MAX_DIMMS_PER_CHANNEL]; ///< Array of pointers to 1448 ///< SPD Data for each Dimm. (Setup by Tech Block Constructor) 1449 OUT UINT8 ChDimmValid; ///< For each bit n 0..3, 1 = DIMM n is valid and is/will be configured where 4..7 are reserved. 1450 ///< 1451 OUT UINT8 RegDimmPresent; ///< For each bit n 0..3, 1 = DIMM n is a registered DIMM where 4..7 are reserved. 1452 OUT UINT8 LrDimmPresent; ///< For each bit n 0..3, 1 = DIMM n is Load Reduced DIMM where 4..7 are reserved. 1453 OUT UINT8 SODimmPresent; ///< For each bit n 0..3, 1 = DIMM n is a SO-DIMM, where 4..7 are reserved. 1454 OUT UINT8 Loads; ///< Number of devices loading bus 1455 OUT UINT8 Dimms; ///< Number of DIMMs loading Channel 1456 OUT UINT8 Ranks; ///< Number of ranks loading Channel DATA 1457 OUT BOOLEAN SlowMode; ///< 1T or 2T CMD mode (slow access mode) 1458 OUT BOOLEAN SlowModePs1; ///< 1T or 2T CMD mode (slow access mode) for Mem Pstate 1 1459 ///< FALSE = 1T 1460 ///< TRUE = 2T 1461 ///< The following pointers will be pointed to dynamically allocated buffers. 1462 ///< Each buffer is two dimensional (RowCount x ColumnCount) and is lay-outed as in below. 1463 ///< Example: If DIMM and Byte based training, then 1464 ///< XX is a value in Hex 1465 ///< BYTE 0, BYTE 1, BYTE 2, BYTE 3, BYTE 4, BYTE 5, BYTE 6, BYTE 7, ECC BYTE 1466 ///< Row1 - Logical DIMM0 XX XX XX XX XX XX XX XX XX 1467 ///< Row2 - Logical DIMM1 XX XX XX XX XX XX XX XX XX 1468 OUT UINT16 *RcvEnDlys; ///< DQS Receiver Enable Delays 1469 OUT UINT8 *WrDqsDlys; ///< Write DQS delays (only valid for DDR3) 1470 OUT UINT8 *RdDqsDlys; ///< Read Dqs delays 1471 OUT UINT8 *WrDatDlys; ///< Write Data delays 1472 OUT UINT8 *RdDqs2dDlys; ///< 2d Read DQS data 1473 OUT UINT8 *RdDqsMinDlys; ///< Minimum Window for Read DQS 1474 OUT UINT8 *RdDqsMaxDlys; ///< Maximum Window for Read DQS 1475 OUT UINT8 *WrDatMinDlys; ///< Minimum Window for Write data 1476 OUT UINT8 *WrDatMaxDlys; ///< Maximum Window for Write data 1477 OUT UINT16 *RcvEnDlysMemPs1; ///< DQS Receiver Enable Delays for Mem Pstate 1 1478 OUT UINT8 *WrDqsDlysMemPs1; ///< Write DQS delays (only valid for DDR3) for Mem Pstate 1 1479 OUT UINT8 *RdDqsDlysMemPs1; ///< Read Dqs delays for Memory Pstate 1 1480 OUT UINT8 *WrDatDlysMemPs1; ///< Write Data delays for Memory Pstate 1 1481 OUT UINT8 *RdDqs2dDlysMemPs1; ///< 2d Read DQS data for Memory Pstate 1 1482 OUT UINT8 *RdDqsMinDlysMemPs1; ///< Minimum Window for Read DQS for Memory Pstate 1 1483 OUT UINT8 *RdDqsMaxDlysMemPs1; ///< Maximum Window for Read DQS for Memory Pstate 1 1484 OUT UINT8 *WrDatMinDlysMemPs1; ///< Minimum Window for Write data for Memory Pstate 1 1485 OUT UINT8 *WrDatMaxDlysMemPs1; ///< Maximum Window for Write data for Memory Pstate 1 1486 OUT UINT8 RowCount; ///< Number of rows of the allocated buffer. 1487 OUT UINT8 ColumnCount; ///< Number of columns of the allocated buffer. 1488 OUT UINT8 *FailingBitMask; ///< Table of masks to Track Failing bits 1489 OUT UINT8 *FailingBitMaskMemPs1; ///< Table of masks to Track Failing bits for Memory Pstate 1 1490 OUT VOID *RdDataEyes; ///< Pointer to Read Data Eye Bitmaps 1491 OUT VOID *WrDataEyes; ///< Pointer to Write Data Eye Bitmaps 1492 OUT UINT32 DctOdcCtl; ///< Output Driver Strength (see BKDG FN2:Offset 9Ch, index 00h) 1493 OUT UINT32 DctAddrTmg; ///< Address Bus Timing (see BKDG FN2:Offset 9Ch, index 04h) 1494 OUT UINT32 DctAddrTmgPs1; ///< Address Bus Timing (see BKDG FN2:Offset 9Ch, index 04h) for Mem Pstate 1 1495 OUT UINT32 PhyRODTCSLow; ///< Phy Read ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 180h) 1496 OUT UINT32 PhyRODTCSHigh; ///< Phy Read ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 181h) 1497 OUT UINT32 PhyWODTCSLow; ///< Phy Write ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 182h) 1498 OUT UINT32 PhyWODTCSHigh; ///< Phy Write ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 183) 1499 OUT UINT8 PhyWLODT[4]; ///< Write Levelization ODT Pattern for Dimm 0-3 or CS 0-7(see BKDG FN2:Offset 9Ch, index 0x8[11:8]) 1500 OUT UINT16 DctEccDqsLike; ///< DCT DQS ECC UINT8 like... 1501 OUT UINT8 DctEccDqsScale; ///< DCT DQS ECC UINT8 scale 1502 OUT UINT16 PtrPatternBufA; ///< Ptr on stack to aligned DQS testing pattern 1503 OUT UINT16 PtrPatternBufB; ///< Ptr on stack to aligned DQS testing pattern 1504 OUT UINT8 ByteLane; ///< Current UINT8 Lane (0..7) 1505 OUT UINT8 Direction; ///< Current DQS-DQ training write direction (0=read, 1=write) 1506 OUT UINT8 Pattern; ///< Current pattern 1507 OUT UINT8 DqsDelay; ///< Current DQS delay value 1508 OUT UINT16 HostBiosSrvc1; ///< UINT16 sized general purpose field for use by host BIOS. Scratch space. 1509 OUT UINT32 HostBiosSrvc2; ///< UINT32 sized general purpose field for use by host BIOS. Scratch space. 1510 OUT UINT16 DctMaxRdLat[4]; ///< Max Read Latency (ns) for the DCT 1511 ///< DctMaxRdLat [i] is for NBPstate i 1512 OUT UINT8 DIMMValidCh; ///< DIMM# in CH 1513 OUT UINT8 MaxCh; ///< Max number of CH in system 1514 OUT UINT8 Dct; ///< Dct pointer 1515 OUT UINT8 WrDatGrossH; ///< Write Data Gross delay high value 1516 OUT UINT8 DqsRcvEnGrossL; ///< DQS Receive Enable Gross Delay low 1517 1518 OUT UINT8 TrwtWB; ///< Non-SPD timing value for TrwtWB 1519 OUT UINT8 CurrRcvrDctADelay; ///< for keep current RcvrEnDly 1520 OUT UINT16 T1000; ///< get the T1000 figure (cycle time (ns) * 1K) 1521 OUT UINT8 DqsRcvEnPass; ///< for TrainRcvrEn UINT8 lane pass flag 1522 OUT UINT8 DqsRcvEnSaved; ///< for TrainRcvrEn UINT8 lane saved flag 1523 OUT UINT8 SeedPass1Remainder; ///< for Phy assisted DQS receiver enable training 1524 1525 OUT UINT8 ClToNbFlag; ///< is used to restore ClLinesToNbDis bit after memory 1526 OUT UINT32 NodeSysBase; ///< for channel interleave usage 1527 OUT UINT8 RefRawCard[MAX_DIMMS_PER_CHANNEL]; ///< Array of rawcards detected 1528 OUT UINT8 CtrlWrd02[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 2 values per DIMM 1529 OUT UINT8 CtrlWrd03[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 3 values per DIMM 1530 OUT UINT8 CtrlWrd04[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 4 values per DIMM 1531 OUT UINT8 CtrlWrd05[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 5 values per DIMM 1532 OUT UINT8 CtrlWrd08[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 8 values per DIMM 1533 1534 OUT UINT16 CsPresentDCT; ///< For each bit n 0..7, 1 = Chip-select n is present 1535 OUT UINT8 DimmMirrorPresent; ///< For each bit n 0..3, 1 = DIMM n is OnDimmMirror capable where 4..7 are reserved. 1536 OUT UINT8 DimmSpdCse; ///< For each bit n 0..3, 1 = DIMM n SPD checksum error where 4..7 are reserved. 1537 OUT UINT8 DimmExclude; ///< For each bit n 0..3, 1 = DIMM n gets excluded where 4..7 are reserved. 1538 OUT UINT8 DimmYr06; ///< Bitmap indicating which Dimms have a manufacturer's year code <= 2006 1539 OUT UINT8 DimmWk2406; ///< Bitmap indicating which Dimms have a manufacturer's week code <= 24 of 2006 (June) 1540 OUT UINT8 DimmPlPresent; ///< Bitmap indicating that Planar (1) or Stacked (0) Dimms are present. 1541 OUT UINT8 DimmQrPresent; ///< QuadRank DIMM present? 1542 OUT UINT8 DimmDrPresent; ///< Bitmap indicating that Dual Rank Dimms are present 1543 OUT UINT8 DimmSRPresent; ///< Bitmap indicating that Single Rank Dimms are present 1544 OUT UINT8 Dimmx4Present; ///< For each bit n 0..3, 1 = DIMM n contains x4 data devices. where 4..7 are reserved. 1545 OUT UINT8 Dimmx8Present; ///< For each bit n 0..3, 1 = DIMM n contains x8 data devices. where 4..7 are reserved. 1546 OUT UINT8 Dimmx16Present; ///< For each bit n 0..3, 1 = DIMM n contains x16 data devices. where 4..7 are reserved. 1547 OUT UINT8 LrdimmPhysicalRanks[MAX_DIMMS_PER_CHANNEL];///< Number of Physical Ranks for LRDIMMs 1548 OUT UINT8 LrDimmLogicalRanks[MAX_DIMMS_PER_CHANNEL];///< Number of LRDIMM Logical ranks in this configuration 1549 OUT UINT8 LrDimmRankMult[MAX_DIMMS_PER_CHANNEL];///< Rank Multipication factor per dimm. 1550 OUT UINT8 DimmNibbleAccess; ///< For each bit n 0..3, 1 = DIMM n will use nibble signaling. Where 4..7 are reserved. 1551 OUT UINT8 *MemClkDisMap; ///< This pointer will be set to point to an array that describes 1552 ///< the routing of M[B,A]_CLK pins to the DIMMs' ranks. AGESA will 1553 ///< base on this array to disable unused MemClk to save power. 1554 ///< 1555 ///< The array must have 8 entries. Each entry, which associates with 1556 ///< one MemClkDis bit, is a bitmap of 8 CS that that MemClk is routed to. 1557 ///< Example: 1558 ///< BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package 1559 ///< is like below: 1560 ///< Bit AM3/S1g3 pin name 1561 ///< 0 M[B,A]_CLK_H/L[0] 1562 ///< 1 M[B,A]_CLK_H/L[1] 1563 ///< 2 M[B,A]_CLK_H/L[2] 1564 ///< 3 M[B,A]_CLK_H/L[3] 1565 ///< 4 M[B,A]_CLK_H/L[4] 1566 ///< 5 M[B,A]_CLK_H/L[5] 1567 ///< 6 M[B,A]_CLK_H/L[6] 1568 ///< 7 M[B,A]_CLK_H/L[7] 1569 ///< And platform has the following routing: 1570 ///< CS0 M[B,A]_CLK_H/L[4] 1571 ///< CS1 M[B,A]_CLK_H/L[2] 1572 ///< CS2 M[B,A]_CLK_H/L[3] 1573 ///< CS3 M[B,A]_CLK_H/L[5] 1574 ///< Then MemClkDisMap should be pointed to the following array: 1575 ///< CLK_2 CLK_3 CLK_4 CLK_5 1576 ///< 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00 1577 ///< Each entry of the array is the bitmask of 8 chip selects. 1578 1579 OUT UINT8 *CKETriMap; ///< This pointer will be set to point to an array that describes 1580 ///< the routing of CKE pins to the DIMMs' ranks. 1581 ///< The array must have 2 entries. Each entry, which associates with 1582 ///< one CKE pin, is a bitmap of 8 CS that that CKE is routed to. 1583 ///< AGESA will base on this array to disable unused CKE pins to save power. 1584 1585 OUT UINT8 *ODTTriMap; ///< This pointer will be set to point to an array that describes 1586 ///< the routing of ODT pins to the DIMMs' ranks. 1587 ///< The array must have 4 entries. Each entry, which associates with 1588 ///< one ODT pin, is a bitmap of 8 CS that that ODT is routed to. 1589 ///< AGESA will base on this array to disable unused ODT pins to save power. 1590 1591 OUT UINT8 *ChipSelTriMap; ///< This pointer will be set to point to an array that describes 1592 ///< the routing of chip select pins to the DIMMs' ranks. 1593 ///< The array must have 8 entries. Each entry is a bitmap of 8 CS. 1594 ///< AGESA will base on this array to disable unused Chip select pins to save power. 1595 1596 OUT UINT8 DimmSRTPresent; ///< For each bit n 0..3, 1 = DIMM n supports Extended Temperature Range where 4..7 are reserved 1597 OUT UINT8 DimmASRPresent; ///< For each bit n 0..3, 1 = DIMM n supports Auto Self Refresh where 4..7 are reserved 1598 OUT UINT8 DimmThermSensorPresent; ///< For each bit n 0..3, 1 = DIMM n has an On Dimm Thermal Sensor where 4..7 are reserved 1599 OUT UINT8 MaxVref; ///< Maximum Vref Value for channel 1600 OUT UINT8 Reserved[100]; ///< Reserved 1601 } CH_DEF_STRUCT; 1602 1603 /// 1604 /// DCT Channel Timing Parameters. 1605 /// This data structure sets timings that are specific to the channel. 1606 /// 1607 typedef struct _CH_TIMING_STRUCT { 1608 OUT UINT16 DctDimmValid; ///< For each bit n 0..3, 1=DIMM n is valid and is/will be configured where 4..7 are reserved. 1609 OUT UINT16 DimmMirrorPresent; ///< For each bit n 0..3, 1=DIMM n is OnDimmMirror capable where 4..7 are reserved. 1610 OUT UINT16 DimmSpdCse; ///< For each bit n 0..3, 1=DIMM n SPD checksum error where 4..7 are reserved. 1611 OUT UINT16 DimmExclude; ///< For each bit n 0..3, 1 = DIMM n gets excluded where 4..7 are reserved. 1612 OUT UINT16 CsPresent; ///< For each bit n 0..7, 1=Chip-select n is present 1613 OUT UINT16 CsEnabled; ///< For each bit n 0..7, 1=Chip-select n is enabled 1614 OUT UINT16 CsTestFail; ///< For each bit n 0..7, 1=Chip-select n is present but disabled 1615 OUT UINT16 CsTrainFail; ///< Bitmap showing which chipselects failed training 1616 OUT UINT16 DIMM1KPage; ///< For each bit n 0..3, 1=DIMM n contains 1K page devices. where 4..7 are reserved 1617 OUT UINT16 DimmQrPresent; ///< QuadRank DIMM present? 1618 OUT UINT16 DimmDrPresent; ///< Bitmap indicating that Dual Rank Dimms are present , where 4..7 are reserved 1619 OUT UINT8 DimmSRPresent; ///< Bitmap indicating that Single Rank Dimms are present, where 4..7 are reserved 1620 OUT UINT16 Dimmx4Present; ///< For each bit n 0..3, 1=DIMM n contains x4 data devices. where 4..7 are reserved 1621 OUT UINT16 Dimmx8Present; ///< For each bit n 0..3, 1=DIMM n contains x8 data devices. where 4..7 are reserved 1622 OUT UINT16 Dimmx16Present; ///< For each bit n 0..3, 1=DIMM n contains x16 data devices. where 4..7 are reserved 1623 1624 OUT UINT16 DIMMTrcd; ///< Minimax Trcd*40 (ns) of DIMMs 1625 OUT UINT16 DIMMTrp; ///< Minimax Trp*40 (ns) of DIMMs 1626 OUT UINT16 DIMMTrtp; ///< Minimax Trtp*40 (ns) of DIMMs 1627 OUT UINT16 DIMMTras; ///< Minimax Tras*40 (ns) of DIMMs 1628 OUT UINT16 DIMMTrc; ///< Minimax Trc*40 (ns) of DIMMs 1629 OUT UINT16 DIMMTwr; ///< Minimax Twr*40 (ns) of DIMMs 1630 OUT UINT16 DIMMTrrd; ///< Minimax Trrd*40 (ns) of DIMMs 1631 OUT UINT16 DIMMTwtr; ///< Minimax Twtr*40 (ns) of DIMMs 1632 OUT UINT16 DIMMTfaw; ///< Minimax Tfaw*40 (ns) of DIMMs 1633 OUT UINT16 DIMMTrrdL; ///< Minimax TrrdL*40 (ns) of DIMMs 1634 OUT UINT16 DIMMTwtrL; ///< Minimax TtwrL*40 (ns) of DIMMs 1635 OUT UINT16 DIMMTccdL; ///< Minimax TccdL*40 (ns) of DIMMs 1636 OUT UINT16 TargetSpeed; ///< Target DRAM bus speed in MHz 1637 OUT UINT16 Speed; ///< DRAM bus speed in MHz 1638 ///< 400 (MHz) 1639 ///< 533 (MHz) 1640 ///< 667 (MHz) 1641 ///< 800 (MHz) 1642 ///< and so on... 1643 OUT UINT8 Trcpage; ///< DCT Trcpage (10 ns) 1644 OUT UINT8 CasL; ///< CAS latency DCT setting (busclocks) 1645 OUT UINT8 Trcd; ///< DCT Trcd (busclocks) 1646 OUT UINT8 Trp; ///< DCT Trp (busclocks) 1647 OUT UINT8 Trtp; ///< DCT Trtp (busclocks) 1648 OUT UINT8 Tras; ///< DCT Tras (busclocks) 1649 OUT UINT8 Trc; ///< DCT Trc (busclocks) 1650 OUT UINT8 Twr; ///< DCT Twr (busclocks) 1651 OUT UINT8 Trrd; ///< DCT Trrd (busclocks) 1652 OUT UINT8 Twtr; ///< DCT Twtr (busclocks) 1653 OUT UINT8 Tfaw; ///< DCT Tfaw (busclocks) 1654 OUT UINT8 TrrdL; ///< DCT TrrdL (busclocks) 1655 OUT UINT8 TwtrL; ///< DCT TwtrL (busclocks) 1656 OUT UINT8 TccdL; ///< DCT TccdL (busclocks) 1657 OUT UINT16 Trfc0; ///< DCT Logical DIMM0 Trfc (in ns) 1658 OUT UINT16 Trfc1; ///< DCT Logical DIMM1 Trfc (in ns) 1659 OUT UINT16 Trfc2; ///< DCT Logical DIMM2 Trfc (in ns) 1660 OUT UINT16 Trfc3; ///< DCT Logical DIMM3 Trfc (in ns) 1661 OUT UINT16 Trfc4; ///< DCT Trfc4min All DIMMS (in ns) - DDR4 Only 1662 OUT UINT32 DctMemSize; ///< Base[47:16], total DRAM size controlled by this DCT. 1663 ///< 1664 OUT BOOLEAN SlowMode; ///< 1T or 2T CMD mode (slow access mode) 1665 ///< FALSE = 1T 1666 ///< TRUE = 2T 1667 OUT UINT8 TrwtTO; ///< DCT TrwtTO (busclocks) 1668 OUT UINT8 Twrrd; ///< DCT Twrrd (busclocks) 1669 OUT UINT8 Twrwr; ///< DCT Twrwr (busclocks) 1670 OUT UINT8 Trdrd; ///< DCT Trdrd (busclocks) 1671 OUT UINT8 TrwtWB; ///< DCT TrwtWB (busclocks) 1672 OUT UINT8 TrdrdSD; ///< DCT TrdrdSD (busclocks) 1673 OUT UINT8 TwrwrSD; ///< DCT TwrwrSD (busclocks) 1674 OUT UINT8 TwrrdSD; ///< DCT TwrrdSD (busclocks) 1675 OUT UINT16 MaxRdLat0; ///< Max Read Latency 0 1676 OUT UINT16 MaxRdLat1; ///< Max Read Latency 1 1677 OUT UINT16 MaxRdLat2; ///< Max Read Latency 2 1678 OUT UINT16 MaxRdLat3; ///< Max Read Latency 3 1679 OUT UINT8 WrDatGrossH; ///< Temporary variables must be removed 1680 OUT UINT8 DqsRcvEnGrossL; ///< Temporary variables must be removed 1681 OUT UINT8 RdOdtOnDuration; ///< RdOdtOnDuration 1682 OUT UINT8 WrOdtOnDuration; ///< WrOdtOnDuration 1683 } CH_TIMING_STRUCT; 1684 1685 /// 1686 /// Data for each DCT. 1687 /// This data structure defines data used to configure each DRAM controller. 1688 /// 1689 typedef struct _DCT_STRUCT { 1690 OUT UINT8 Dct; ///< Current Dct 1691 OUT CH_TIMING_STRUCT Timings; ///< Channel Timing structure 1692 OUT CH_TIMING_STRUCT *TimingsMemPs1; ///< Pointed to channel timing structure for memory Pstate 1 1693 OUT CH_DEF_STRUCT *ChData; ///< Pointed to a dynamically allocated array of Channel structures 1694 OUT UINT8 ChannelCount; ///< Number of channel per this DCT 1695 OUT BOOLEAN BkIntDis; ///< Bank interleave requested but not enabled on current DCT 1696 OUT UINT8 BankAddrMap; ///< Bank Address Mapping 1697 OUT UINT8 EnabledChipSels; ///< Number of enabled chip selects on current DCT 1698 } DCT_STRUCT; 1699 1700 1701 /// 1702 /// Data Structure defining each Die. 1703 /// This data structure contains information that is used to configure each Die. 1704 /// 1705 typedef struct _DIE_STRUCT { 1706 1707 /// Advanced: 1708 1709 OUT UINT8 NodeId; ///< Node ID of current controller 1710 OUT UINT8 SocketId; ///< Socket ID of this Die 1711 OUT UINT8 DieId; ///< ID of this die relative to the socket 1712 OUT PCI_ADDR PciAddr; ///< Pci bus and device number of this controller. 1713 OUT AGESA_STATUS ErrCode; ///< Current error condition of Node 1714 ///< 0x0 = AGESA_SUCCESS 1715 ///< 0x1 = AGESA_UNSUPPORTED 1716 ///< 0x2 = AGESA_BOUNDS_CHK 1717 ///< 0x3 = AGESA_ALERT 1718 ///< 0x4 = AGESA_WARNING 1719 ///< 0x5 = AGESA_ERROR 1720 ///< 0x6 = AGESA_CRITICAL 1721 ///< 0x7 = AGESA_FATAL 1722 ///< 1723 OUT BOOLEAN ErrStatus[EsbEOL]; ///< Error Status bit Field 1724 ///< 1725 OUT BOOLEAN Status[SbEOL]; ///< Status bit Field 1726 ///< 1727 OUT UINT32 NodeMemSize; ///< Base[47:16], total DRAM size controlled by both DCT0 and DCT1 of this Node. 1728 ///< 1729 OUT UINT32 NodeSysBase; ///< Base[47:16] (system address) DRAM base address of this Node. 1730 ///< 1731 OUT UINT32 NodeHoleBase; ///< If not zero, Base[47:16] (system address) of dram hole for HW remapping. Dram hole exists on this Node 1732 ///< 1733 OUT UINT32 NodeSysLimit; ///< Base[47:16] (system address) DRAM limit address of this Node. 1734 ///< 1735 OUT UINT32 DimmPresent; ///< For each bit n 0..7, 1 = DIMM n is present. 1736 ///< DIMM# Select Signal 1737 ///< 0 MA0_CS_L[0, 1] 1738 ///< 1 MB0_CS_L[0, 1] 1739 ///< 2 MA1_CS_L[0, 1] 1740 ///< 3 MB1_CS_L[0, 1] 1741 ///< 4 MA2_CS_L[0, 1] 1742 ///< 5 MB2_CS_L[0, 1] 1743 ///< 6 MA3_CS_L[0, 1] 1744 ///< 7 MB3_CS_L[0, 1] 1745 ///< 1746 OUT UINT32 DimmValid; ///< For each bit n 0..7, 1 = DIMM n is valid and is / will be configured 1747 OUT UINT32 RegDimmPresent; ///< For each bit n 0..7, 1 = DIMM n is registered DIMM 1748 OUT UINT32 LrDimmPresent; ///< For each bit n 0..7, 1 = DIMM n is Load Reduced DIMM 1749 OUT UINT32 DimmEccPresent; ///< For each bit n 0..7, 1 = DIMM n is ECC capable. 1750 OUT UINT32 DimmParPresent; ///< For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable. 1751 ///< 1752 OUT UINT16 DimmTrainFail; ///< Bitmap showing which dimms failed training 1753 OUT UINT16 ChannelTrainFail; ///< Bitmap showing the channel information about failed Chip Selects 1754 ///< 0 in any bit field indicates Channel 0 1755 ///< 1 in any bit field indicates Channel 1 1756 OUT UINT8 Dct; ///< Need to be removed 1757 ///< DCT pointer 1758 OUT BOOLEAN GangedMode; ///< Ganged mode 1759 ///< 0 = disabled 1760 ///< 1 = enabled 1761 OUT CPU_LOGICAL_ID LogicalCpuid; ///< The logical CPUID of the node 1762 ///< 1763 OUT UINT16 HostBiosSrvc1; ///< UINT16 sized general purpose field for use by host BIOS. Scratch space. 1764 ///< 1765 OUT UINT32 HostBiosSrvc2; ///< UINT32 sized general purpose field for use by host BIOS. Scratch space. 1766 ///< 1767 OUT UINT8 MLoad; ///< Need to be removed 1768 ///< Number of devices loading MAA bus 1769 ///< 1770 OUT UINT8 MaxAsyncLat; ///< Legacy wrapper 1771 ///< 1772 OUT UINT8 ChbD3Rcvrdly; ///< Legacy wrapper 1773 ///< 1774 OUT UINT16 ChaMaxRdLat; ///< Max Read Latency (ns) for DCT 0 1775 ///< 1776 OUT UINT8 ChbD3BcRcvrdly; ///< CHB DIMM 3 Check UINT8 Receiver Enable Delay 1777 1778 OUT DCT_STRUCT *DctData; ///< Pointed to a dynamically allocated array of DCT_STRUCTs 1779 OUT UINT8 DctCount; ///< Number of DCTs per this Die 1780 OUT UINT8 Reserved[16]; ///< Reserved 1781 } DIE_STRUCT; 1782 1783 /********************************************************************** 1784 * S3 data block structure 1785 **********************************************************************/ 1786 /// AmdInitResume, AmdS3LateRestore, and AmdInitRtb param structure 1787 typedef struct { 1788 OUT UINT32 Signature; ///< "ASTR" for AMD Suspend-To-RAM 1789 OUT UINT16 Version; ///< S3 Params version number 1790 IN OUT UINT32 Flags; ///< Indicates operation 1791 IN OUT VOID *NvStorage; ///< Pointer to memory critical save state data 1792 IN OUT UINT32 NvStorageSize; ///< Size in bytes of the NvStorage region 1793 IN OUT VOID *VolatileStorage; ///< Pointer to remaining AMD save state data 1794 IN OUT UINT32 VolatileStorageSize; ///< Size in bytes of the VolatileStorage region 1795 } S3_DATA_BLOCK; 1796 1797 /// Header at the beginning of a context save buffer. 1798 typedef struct { 1799 _2BYTE_ALIGN UINT16 Version; ///< Version of header 1800 _4BYTE_ALIGN UINT32 Revision; ///< Revision of the S3 data blob 1801 _2BYTE_ALIGN UINT16 NumDevices; ///< Number of devices in the list 1802 _2BYTE_ALIGN UINT16 RelativeOrMaskOffset; ///< Size of device list + header 1803 _4BYTE_ALIGN UINT32 BlobSize; ///<Size of the whole S3 data blob (including the header) 1804 _4BYTE_ALIGN UINT32 NextBlockOffset; ///< Size of the whole device save context 1805 } DEVICE_BLOCK_HEADER; 1806 1807 ///=============================================================================== 1808 /// CPU_VREF_OVERRIDE 1809 /// 1810 typedef struct _CPU_VREF_OVERRIDE{ 1811 IN UINT8 VrefOp; ///< Operater to adjust VrefHspeed 1812 IN UINT8 VrefOffset; ///< Offset to adjust VrefHspeed 1813 } CPU_VREF_OVERRIDE; 1814 1815 ///=============================================================================== 1816 /// MEM_PARAMETER_STRUCT 1817 /// This data structure is used to pass wrapper parameters to the memory configuration code 1818 /// 1819 typedef struct _MEM_PARAMETER_STRUCT { 1820 1821 // Basic (Return parameters) 1822 // (This section contains the outbound parameters from the memory init code) 1823 1824 OUT BOOLEAN GStatus[GsbEOL]; ///< Global Status bitfield. 1825 ///< 1826 OUT UINT32 HoleBase; ///< If not zero Base[47:16] (system address) of sub 4GB dram hole for HW remapping. 1827 ///< 1828 OUT UINT32 Sub4GCacheTop; ///< If not zero, the 32-bit top of cacheable memory. 1829 ///< 1830 OUT UINT32 Sub1THoleBase; ///< If not zero Base[47:16] (system address) of sub 1TB dram hole. 1831 ///< 1832 OUT UINT32 SysLimit; ///< Limit[47:16] (system address). 1833 ///< 1834 OUT DIMM_VOLTAGE DDRVoltage; ///< Find support voltage and send back to platform BIOS for DDR3 or DDR4. 1835 ///< 1836 OUT VDDP_VDDR_VOLTAGE VddpVddrVoltage; ///< For a given configuration, request is made to change the VDDP/VDDR 1837 ///< voltage in platform BIOS via AgesaHookBeforeDramInit callout and 1838 ///< MEM_PARAMETER_STRUCT.VddpVddrVoltage.Voltage parameter if 1839 ///< MEM_PARAMETER_STRUCT.VddpVddrVoltage.IsValid is TRUE. The 1840 ///< MEM_PARAMETER_STRUCT.VddpVddrVoltage.Voltage is defined in 1841 ///< MEMORY_PHY_VOLTAGE 1842 OUT UINT8 ExternalVrefValue; ///< Target reference voltage for external Vref for 2D training 1843 ///< 1844 OUT struct _MEM_DATA_STRUCT *MemData; ///< Access to global memory init data. 1845 1846 // Advanced (Optional parameters) 1847 // Optional (all defaults values will be initialized by the 1848 // 'AmdMemInitDataStructDef' based on AMD defaults. It is up 1849 // to the IBV/OEM to change the defaults after initialization 1850 // but prior to the main entry to the memory code): 1851 1852 // Memory Map/Mgt. 1853 1854 IN UINT16 BottomIo; ///< Bottom of 32-bit IO space (8-bits). 1855 ///< NV_BOTTOM_IO[7:0]=Addr[31:24] 1856 ///< 1857 IN BOOLEAN MemHoleRemapping; ///< Memory Hole Remapping (1-bit). 1858 ///< FALSE = disable 1859 ///< TRUE = enable 1860 ///< 1861 IN BOOLEAN LimitMemoryToBelow1Tb; ///< Limit memory address space to below 1 TB 1862 ///< FALSE = disable 1863 ///< TRUE = enable 1864 ///< 1865 ///< @BldCfgItem{BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB} 1866 1867 // Dram Timing 1868 1869 IN UINT32 UserTimingMode; ///< User Memclock Mode. 1870 ///< @BldCfgItem{BLDCFG_TIMING_MODE_SELECT} 1871 1872 IN UINT32 MemClockValue; ///< Memory Clock Value. 1873 ///< @BldCfgItem{BLDCFG_MEMORY_CLOCK_SELECT} 1874 1875 // Dram Configuration 1876 1877 IN BOOLEAN EnableBankSwapOnly; ///< Bank Swap Only 1878 ///< - FALSE =disable (default) 1879 ///< - TRUE = enable 1880 ///< 1881 ///< @BldCfgItem{BLDCFG_MEMORY_ENABLE_BANK_SWAP_ONLY} 1882 1883 IN BOOLEAN EnableBankIntlv; ///< Dram Bank (chip-select) Interleaving (1-bit). 1884 ///< - FALSE =disable (default) 1885 ///< - TRUE = enable 1886 ///< 1887 ///< @BldCfgItem{BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING} 1888 1889 IN BOOLEAN EnableNodeIntlv; ///< Node Memory Interleaving (1-bit). 1890 ///< - FALSE = disable (default) 1891 ///< - TRUE = enable 1892 ///< 1893 ///< @BldCfgItem{BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING} 1894 1895 IN BOOLEAN EnableChannelIntlv; ///< Channel Interleaving (1-bit). 1896 ///< - FALSE = disable (default) 1897 ///< - TRUE = enable 1898 ///< 1899 ///< @BldCfgItem{BLDCFG_MEMORY_CHANNEL_INTERLEAVING} 1900 // DllPDBypassMode 1901 1902 IN BOOLEAN EnableDllPDBypassMode; ///< Enable low-power DDR phy operation. This feature is used for low-power 1903 ///< solder-down DRAM motherboard designs with route matched CK/DQS/DQ signals. 1904 ///< It limits maximim achieveable DDR rates on the platform and should not be 1905 ///< enabled for systems requiring high DDR rate operation and/or DIMM-based systems. 1906 ///< - FALSE = disable 1907 ///< - TRUE = enable (default) 1908 ///< 1909 ///< @BldCfgItem{BLDCFG_DDR_PHY_DLL_BYPASS_MODE} 1910 // ECC 1911 1912 IN BOOLEAN EnableEccFeature; ///< enable ECC error to go into MCE. 1913 ///< - FALSE = disable (default) 1914 ///< - TRUE = enable 1915 ///< 1916 ///< @BldCfgItem{BLDCFG_ENABLE_ECC_FEATURE} 1917 // Dram Power 1918 1919 IN BOOLEAN EnablePowerDown; ///< CKE based power down mode (1-bit). 1920 ///< - FALSE =disable (default) 1921 ///< - TRUE =enable 1922 ///< 1923 ///< @BldCfgItem{BLDCFG_MEMORY_POWER_DOWN} 1924 1925 // Dram Mac Default 1926 1927 IN UINT8 DramMacDefault; ///< Default Maximum Activate Count 1928 ///< 1929 ///< @BldCfgItem{BLDCFG_MEMORY_ALTERNATIVE_MAX_ACTIVATE_COUNT} 1930 1931 // Dram Extended Temperature Range 1932 1933 IN BOOLEAN EnableExtendedTemperatureRange; ///< enable extended temperature support. 1934 ///< - FALSE =disable (default) 1935 ///< - TRUE =enable 1936 ///< 1937 ///< @BldCfgItem{BLDCFG_MEMORY_EXTENDED_TEMPERATURE_RANGE} 1938 1939 // Temperature Controlled Refresh 1940 1941 IN BOOLEAN DramTempControlledRefreshEn; ///< Enable Temperature Controlled Refresh 1942 ///< - FALSE = Disable 1943 ///< - TRUE = Enable (Default) 1944 ///< @BldCfgItem{BLDCFG_DRAM_TEMP_CONTROLLED_REFRESH_EN} 1945 ///< If EnableExtendedTemperatureRange is enabled with this feature 1946 ///< then CfgDramDoubleRefreshrate must also be enabled. 1947 1948 // Online Spare 1949 1950 IN BOOLEAN EnableOnLineSpareCtl; ///< Chip Select Spare Control bit 0. 1951 ///< - FALSE = disable Spare (default) 1952 ///< - TRUE = enable Spare 1953 ///< 1954 ///< @BldCfgItem{BLDCFG_ONLINE_SPARE} 1955 1956 IN UINT8 *TableBasedAlterations; ///< Desired modifications to register settings. 1957 1958 IN PSO_TABLE *PlatformMemoryConfiguration; 1959 ///< A table that contains platform specific settings. 1960 ///< For example, MemClk routing, the number of DIMM slots per channel, .... 1961 ///< AGESA initializes this pointer with DefaultPlatformMemoryConfiguration that 1962 ///< contains default conservative settings. Platform BIOS can either tweak 1963 ///< DefaultPlatformMemoryConfiguration or reassign this pointer to its own table. 1964 ///< 1965 IN BOOLEAN EnableParity; ///< Parity control. 1966 ///< - TRUE = enable 1967 ///< - FALSE = disable (default) 1968 ///< 1969 ///< @BldCfgItem{BLDCFG_MEMORY_PARITY_ENABLE} 1970 1971 IN BOOLEAN EnableBankSwizzle; ///< BankSwizzle control. 1972 ///< - FALSE = disable 1973 ///< - TRUE = enable (default) 1974 ///< 1975 ///< @BldCfgItem{BLDCFG_BANK_SWIZZLE} 1976 ///< 1977 1978 IN BOOLEAN EnableMemClr; ///< Memory Clear functionality control. 1979 ///< - FALSE = disable 1980 ///< - TRUE = enable (default) 1981 ///< 1982 // Uma Configuration 1983 1984 IN UMA_VERSION UmaVersion; ///< Uma Version 1985 ///< 0 = Legacy Version 1986 ///< 1 = Non-Legacy Version 1987 IN UMA_MODE UmaMode; ///< Uma Mode 1988 ///< 0 = None 1989 ///< 1 = Specified 1990 ///< 2 = Auto 1991 IN OUT UINT32 UmaSize; ///< The size of shared graphics dram (16-bits) 1992 ///< NV_UMA_Size[31:0]=Addr[47:16] 1993 ///< 1994 OUT UINT32 UmaBase; ///< The allocated Uma base address (32-bits) 1995 ///< NV_UMA_Base[31:0]=Addr[47:16] 1996 ///< 1997 1998 /// Memory Restore Feature 1999 2000 IN BOOLEAN MemRestoreCtl; ///< Memory context restore control 2001 ///< FALSE = perform memory init as normal (AMD default) 2002 ///< TRUE = restore memory context and skip training. This requires 2003 ///< MemContext is valid before AmdInitPost 2004 ///< 2005 IN BOOLEAN SaveMemContextCtl; ///< Control switch to save memory context at the end of MemAuto 2006 ///< TRUE = AGESA will setup MemContext block before exit AmdInitPost 2007 ///< FALSE = AGESA will not setup MemContext block. Platform is 2008 ///< expected to call S3Save later in POST if it wants to 2009 ///< use memory context restore feature. 2010 ///< 2011 IN OUT S3_DATA_BLOCK MemContext; ///< Memory context block describes the data that platform needs to 2012 ///< save and restore for memory context restore feature to work. 2013 ///< It uses the subset of S3Save block to save/restore. Hence platform 2014 ///< may save only S3 block and uses it for both S3 resume and 2015 ///< memory context restore. 2016 ///< - If MemRestoreCtl is TRUE, platform needs to pass in MemContext 2017 ///< before AmdInitPost. 2018 ///< - If SaveMemContextCtl is TRUE, platform needs to save MemContext 2019 ///< right after AmdInitPost. 2020 ///< 2021 IN BOOLEAN IsCapsuleMode; ///< Capsule reboot control 2022 ///< FALSE = This is not a capsule reboot. 2023 ///< TRUE = This is a capsule reboot. 2024 ///< 2025 IN BOOLEAN ExternalVrefCtl; ///< Control the use of external Vref 2026 ///< TRUE = AGESA will use the function defined in "AGESA_EXTERNAL_VREF_CHANGE" in function list 2027 ///< to change the vref 2028 ///< FALSE = AGESA will will use the internal vref control. 2029 ///< @BldCfgItem{BLDCFG_ENABLE_EXTERNAL_VREF_FEATURE} 2030 ///< 2031 IN FORCE_TRAIN_MODE ForceTrainMode; ///< Training Mode 2032 ///< 0 = Force 1D Training for all configurations 2033 ///< 1 = Force 2D Training for all configurations 2034 ///< 2 = Auto - AGESA will control 1D or 2D 2035 IN TECHNOLOGY_TYPE DimmTypeUsedInMixedConfig; ///< Select the preferred technology type that AGESA will enable 2036 ///< when it is mixed with other technology types. 2037 ///< DDR3_TECHNOLOGY = Use DDR3 DIMMs 2038 ///< GDDR5_TECHNOLOGY = Use GDDR5 DIMMs 2039 ///< UNSUPPORTED_TECHNOLOGY = Exit with fatal error when DDR3 and GDDR5 DIMMs 2040 ///< are installed on the same system 2041 ///< @BldCfgItem{BLDCFG_DIMM_TYPE_USED_IN_MIXED_CONFIG} 2042 IN BOOLEAN AmpEnable; ///< AMP functionality control 2043 ///< TRUE = Enable, platform BIOS requests to enable memory overclocking function, and AGESA 2044 ///< detects if memory is capable of it 2045 ///< FALSE = Disable, there is no request to enable memory overclocking function 2046 ///< 2047 IN BOOLEAN AmpWarningMsgEnable; ///< AMP warning messages control 2048 ///< TRUE = Enable to log the warning messages of AMP 2049 ///< FALSE = Disable 2050 ///< 2051 OUT AMP_STATUS AmpStatus; ///< AMP status allows platform BIOS to check which voltage or warning message it should 2052 ///< use/apply. 2053 ///< 2054 ///< AmpVoltageValid : 2055 ///< TRUE - AGESA does enable AMP function, so use AmpVoltage for voltage adjustment 2056 ///< FALSE - AGESA does not enable AMP function, so use DDRVoltage for voltage adjustment 2057 ///< 2058 ///< AmpSupportDetectedButNotEnabled : 2059 ///< TRUE - Display warning message of "AMP support detected but not enabled" 2060 ///< FALSE - No corresponding message should be displayed 2061 ///< 2062 ///< AmpSelectedButNotEnabled : 2063 ///< TRUE - Display warning message of "AMP selected but not enabled" 2064 ///< FALSE - No corresponding message should be displayed 2065 ///< 2066 ///< Note that both of warning message status reports are controlled by AmpWarningMsgEnable 2067 ///< 2068 OUT AMP_DIMM_VOLTAGE AmpVoltage; ///< AMP voltage which will be sent back to platform BIOS, and 2069 ///< the value in AmpVoltage is valid only if AmpStatus is TRUE returned 2070 IN BOOLEAN DataEyeEn; ///< Get 2D training data eye 2071 ///< TRUE = Enable to get the 2D data eye 2072 ///< FALSE = The 2D data eye is not enabled 2073 ///< @BldCfgItem{BLDCFG_ENABLE_DATA_EYE} 2074 IN BOOLEAN DramDoubleRefreshRate; ///< Specify the average time between refresh requests to all DRAM devices. 2075 ///< TRUE = 2x refresh rate. 2076 ///< FALSE = 1x refresh rate. 2077 ///< @BldCfgItem{BLDCFG_DRAM_DOUBLE_REFRESH_RATE} 2078 IN PMU_TRAIN_MODE PmuTrainMode; ///< PMU Training Mode 2079 ///< @BldCfgItem{BLDCFG_PMU_TRAINING_MODE} 2080 ///< 0 = PMU 1D Training only for all configurations 2081 ///< 1 = PMU 1D and 2D Training read only for all configurations 2082 ///< 2 = PMU 1D and 2D Training for all configurations 2083 ///< 3 = AGESA control type of training depend on configurations 2084 IN BOOLEAN CfgEccRedirection; ///< ECC Redirection. 2085 ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_REDIRECTION} 2086 IN UINT16 CfgScrubDramRate; ///< Scrub Dram Rate. 2087 ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_DRAM_RATE} 2088 IN UINT16 CfgScrubL2Rate; ///< Scrub L2Rate. 2089 ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_L2_RATE} 2090 IN UINT16 CfgScrubL3Rate; ///< Scrub L3Rate. 2091 ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_L3_RATE} 2092 IN UINT16 CfgScrubIcRate; ///< Scrub Ic Rate. 2093 ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_IC_RATE} 2094 IN UINT16 CfgScrubDcRate; ///< Scrub Dc Rate. 2095 ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_DC_RATE} 2096 IN BOOLEAN CfgEccSyncFlood; ///< ECC Sync Flood. 2097 ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_SYNC_FLOOD} 2098 IN UINT16 CfgEccSymbolSize; ///< ECC Symbol Size. 2099 ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_SYMBOL_SIZE} 2100 IN BOOLEAN CfgDqsTrainingControl; ///< Dqs Training Control. 2101 ///< Build-time customizable only - @BldCfgItem{BLDCFG_DQS_TRAINING_CONTROL} 2102 IN BOOLEAN CfgUmaAbove4G; ///< Uma Above 4G Support 2103 IN UMA_ALIGNMENT CfgUmaAlignment; ///< Uma alignment 2104 IN BOOLEAN CfgMemoryAllClocksOn; ///< Memory All Clocks On. 2105 ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_ALL_CLOCKS_ON} 2106 IN UINT32 CfgMemoryBusFrequencyLimit; ///< Memory Bus Frequency Limit. 2107 ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT} 2108 IN UINT32 CfgPowerDownMode; ///< Power Down Mode. 2109 IN BOOLEAN CfgIgnoreSpdChecksum; ///< Ignore Spd Checksum. 2110 ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGNORE_SPD_CHECKSUM} 2111 IN BOOLEAN CfgMemoryModeUnganged; ///< Memory Mode Unganged. 2112 ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_MODE_UNGANGED} 2113 IN BOOLEAN CfgMemoryQuadRankCapable; ///< Memory Quad Rank Capable. 2114 IN BOOLEAN CfgMemoryRDimmCapable; ///< Memory RDIMM Capable. 2115 IN BOOLEAN CfgMemoryLRDimmCapable; ///< Memory LRDIMM Capable. 2116 IN BOOLEAN CfgMemoryUDimmCapable; ///< Memory UDIMM Capable. 2117 IN BOOLEAN CfgMemorySODimmCapable; ///< Memory SODimm Capable. 2118 ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_SODIMM_CAPABLE} 2119 ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_QUAD_RANK_CAPABLE} 2120 IN TECHNOLOGY_TYPE CfgDimmTypeUsedInMixedConfig; // Dimm Type Used In Mized Config 2121 IN BOOLEAN CfgDramDoubleRefreshRateEn; ///< Double DRAM refresh rate 2122 IN BOOLEAN DimmTypeDddr4Capable; ///< Indicates that the system is DDR4 Capable 2123 ///< TRUE = Enable, platfrom BIOS requests support for DDR4 2124 ///< FALSE = Disable, platform BIOS requests no DDR4 support 2125 ///< @BldCfgItem{BLDCFG_DIMM_TYPE_DDR4_CAPABLE} 2126 IN BOOLEAN DimmTypeDddr3Capable; ///< Indicates that the system is DDR3 Capable 2127 ///< TRUE = Enable, platfrom BIOS requests support for DDR3 2128 ///< FALSE = Disable, platform BIOS requests no DDR3 support 2129 ///< @BldCfgItem{BLDCFG_DIMM_TYPE_DDR3_CAPABLE} 2130 IN UINT16 CustomVddioSupport; ///< CustomVddioSupport 2131 ///< @BldCfgItem{BLDCFG_CUSTOM_VDDIO_VOLTAGE} 2132 IN CPU_VREF_OVERRIDE CpuVrefOverride[2][4]; ///< Structure to adjust VrefHspeed 2133 ///< PerDct, Per MemPstate 2134 } MEM_PARAMETER_STRUCT; 2135 2136 2137 /// 2138 /// Function definition. 2139 /// This data structure passes function pointers to the memory configuration code. 2140 /// The wrapper can use this structure with customized versions. 2141 /// 2142 typedef struct _MEM_FUNCTION_STRUCT { 2143 2144 // PUBLIC required Internal functions 2145 2146 IN OUT BOOLEAN (*amdMemGetPsCfgU) ( VOID *pMemData); ///< Proc for Unbuffered DIMMs, platform specific 2147 IN OUT BOOLEAN (*amdMemGetPsCfgR) (VOID *pMemData); ///< Proc for Registered DIMMs, platform specific 2148 2149 // PUBLIC optional functions 2150 2151 IN OUT VOID (*amdMemEccInit) (VOID *pMemData); ///< NB proc for ECC feature 2152 IN OUT VOID (*amdMemChipSelectInterleaveInit) (VOID *pMemData); ///< NB proc for CS interleave feature 2153 IN OUT VOID (*amdMemDctInterleavingInit) (VOID *pMemData); ///< NB proc for Channel interleave feature 2154 IN OUT VOID (*amdMemMctInterleavingInit) (VOID *pMemData); ///< NB proc for Node interleave feature 2155 IN OUT VOID (*amdMemParallelTraining) (VOID *pMemData); ///< NB proc for parallel training feature 2156 IN OUT VOID (*amdMemEarlySampleSupport) (VOID *pMemData); ///< NB code for early sample support feature 2157 IN OUT VOID (*amdMemMultiPartInitSupport) (VOID *pMemData); ///< NB code for 'multi-part' 2158 IN OUT VOID (*amdMemOnlineSpareSupport) (VOID *pMemData); ///< NB code for On-Line Spare feature 2159 IN OUT VOID (*amdMemUDimmInit) (VOID *pMemData); ///< NB code for UDIMMs 2160 IN OUT VOID (*amdMemRDimmInit) (VOID *pMemData); ///< NB code for RDIMMs 2161 IN OUT VOID (*amdMemLrDimmInit) (VOID *pMemData); ///< NB code for LRDIMMs 2162 IN OUT UINT32 Reserved[100]; ///< Reserved for later function definition 2163 } MEM_FUNCTION_STRUCT; 2164 2165 /// 2166 /// Socket Structure 2167 /// 2168 /// 2169 typedef struct _MEM_SOCKET_STRUCT { 2170 OUT VOID *ChannelPtr[MAX_CHANNELS_PER_SOCKET]; ///< Pointers to each channels training data 2171 2172 OUT VOID *TimingsPtr[MAX_CHANNELS_PER_SOCKET]; ///< Pointers to each channels timing data 2173 } MEM_SOCKET_STRUCT; 2174 2175 /// 2176 /// Contains all data relevant to Memory Initialization. 2177 /// 2178 typedef struct _MEM_DATA_STRUCT { 2179 IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header 2180 2181 IN MEM_PARAMETER_STRUCT *ParameterListPtr; ///< List of input Parameters 2182 2183 OUT MEM_FUNCTION_STRUCT FunctionList; ///< List of function Pointers 2184 2185 IN OUT AGESA_STATUS (*GetPlatformCfg[MAX_PLATFORM_TYPES]) (struct _MEM_DATA_STRUCT *MemData, UINT8 SocketID, CH_DEF_STRUCT *CurrentChannel); ///< look-up platform info 2186 2187 IN OUT BOOLEAN (*ErrorHandling)(struct _DIE_STRUCT *MCTPtr, UINT8 DCT, UINT16 ChipSelMask, AMD_CONFIG_PARAMS *StdHeader); ///< Error Handling 2188 2189 2190 OUT MEM_SOCKET_STRUCT SocketList[MAX_SOCKETS_SUPPORTED]; ///< Socket list for memory code. 2191 ///< SocketList is a shortcut for IBVs to retrieve training 2192 ///< and timing data for each channel indexed by socket/channel, 2193 ///< eliminating their need to parse die/dct/channel etc. 2194 ///< It contains pointers to the populated data structures for 2195 ///< each channel and skips the channel structures that are 2196 ///< unpopulated. In the case of channels sharing the same DCT, 2197 ///< the pTimings pointers will point to the same DCT Timing data. 2198 2199 OUT DIE_STRUCT *DiesPerSystem; ///< Pointed to an array of DIE_STRUCTs 2200 OUT UINT8 DieCount; ///< Number of MCTs in the system. 2201 2202 IN SPD_DEF_STRUCT *SpdDataStructure; ///< Pointer to SPD Data structure 2203 2204 IN OUT struct _PLATFORM_CONFIGURATION *PlatFormConfig; ///< Platform profile/build option config structure 2205 2206 IN OUT BOOLEAN IsFlowControlSupported; ///< Indicates if flow control is supported 2207 2208 OUT UINT32 TscRate; ///< The rate at which the TSC increments in megahertz. 2209 IN BOOLEAN PhyReceiverLowPower; ///< Force PHY receiver in low power. 2210 ///< TRUE = PHY receiver low power 2211 ///< FALSE = PHY receiver high power 2212 } MEM_DATA_STRUCT; 2213 2214 /// 2215 /// Uma Structure 2216 /// 2217 /// 2218 typedef struct _UMA_INFO { 2219 OUT UINT64 UmaBase; ///< UmaBase[63:0] = Addr[63:0] 2220 OUT UINT32 UmaSize; ///< UmaSize[31:0] = Addr[31:0] 2221 OUT UINT32 UmaAttributes; ///< Indicate the attribute of Uma 2222 OUT UINT8 UmaMode; ///< Indicate the mode of Uma 2223 OUT UINT16 MemClock; ///< Indicate memory running speed in MHz 2224 OUT UINT8 MemType; ///< Indicate the DRAM technology type that is being used 2225 OUT UINT8 Reserved[2]; ///< Reserved for future usage 2226 } UMA_INFO; 2227 2228 2229 /// Bitfield for ID 2230 typedef struct { 2231 OUT UINT16 SocketId:8; ///< Socket ID 2232 OUT UINT16 ModuleId:8; ///< Module ID 2233 } ID_FIELD; 2234 /// 2235 /// Union for ID of socket and module that will be passed out in call out 2236 /// 2237 typedef union { 2238 OUT ID_FIELD IdField; ///< Bitfield for ID 2239 OUT UINT16 IdInformation; ///< ID information for call out 2240 } ID_INFO; 2241 2242 // AGESA MEMORY ERRORS 2243 2244 // AGESA_SUCCESS memory events 2245 #define MEM_EVENT_CAPSULE_IN_EFFECT 0x04013600ul ///< Capsule is in effect 2246 #define MEM_EVENT_CONTEXT_RESTORE_IN_EFFECT 0x04023600ul ///< Context restore is in effect 2247 2248 // AGESA_ALERT Memory Errors 2249 #define MEM_ALERT_USER_TMG_MODE_OVERRULED 0x04010000ul ///< TIMING_MODE_SPECIFIC is requested but 2250 ///< cannot be applied to current configurations. 2251 #define MEM_ALERT_ORG_MISMATCH_DIMM 0x04010100ul ///< DIMM organization miss-match 2252 #define MEM_ALERT_BK_INT_DIS 0x04010200ul ///< Bank interleaving disable for internal issue 2253 #define MEM_ALERT_DRAM_DOUBLE_REFRESH_RATE_ENABLED 0x04010300ul ///< CfgDramDoubleRefreshRate has been enabled due 2254 /// to Extended Temperature Range feature 2255 2256 // AGESA_ERROR Memory Errors 2257 #define MEM_ERROR_NO_DQS_POS_RD_WINDOW 0x04010300ul ///< No DQS Position window for RD DQS 2258 #define MEM_ERROR_SMALL_DQS_POS_RD_WINDOW 0x04020300ul ///< Small DQS Position window for RD DQS 2259 #define MEM_ERROR_NO_DQS_POS_WR_WINDOW 0x04030300ul ///< No DQS Position window for WR DQS 2260 #define MEM_ERROR_SMALL_DQS_POS_WR_WINDOW 0x04040300ul ///< Small DQS Position window for WR DQS 2261 #define MEM_ERROR_DIMM_SPARING_NOT_ENABLED 0x04010500ul ///< DIMM sparing has not been enabled for an internal issues 2262 #define MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE 0x04050300ul ///< Receive Enable value is too large 2263 #define MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW 0x04060300ul ///< There is no DQS receiver enable window 2264 #define MEM_ERROR_DRAM_ENABLED_TIME_OUT 0x04010600ul ///< Time out when polling DramEnabled bit 2265 #define MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT 0x04010700ul ///< Time out when polling DctAccessDone bit 2266 #define MEM_ERROR_SEND_CTRL_WORD_TIME_OUT 0x04010800ul ///< Time out when polling SendCtrlWord bit 2267 #define MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT 0x04010900ul ///< Time out when polling PrefDramTrainMode bit 2268 #define MEM_ERROR_ENTER_SELF_REF_TIME_OUT 0x04010A00ul ///< Time out when polling EnterSelfRef bit 2269 #define MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT 0x04010B00ul ///< Time out when polling FreqChgInProg bit 2270 #define MEM_ERROR_EXIT_SELF_REF_TIME_OUT 0x04020A00ul ///< Time out when polling ExitSelfRef bit 2271 #define MEM_ERROR_SEND_MRS_CMD_TIME_OUT 0x04010C00ul ///< Time out when polling SendMrsCmd bit 2272 #define MEM_ERROR_SEND_ZQ_CMD_TIME_OUT 0x04010D00ul ///< Time out when polling SendZQCmd bit 2273 #define MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT 0x04010E00ul ///< Time out when polling DctExtraAccessDone bit 2274 #define MEM_ERROR_MEM_CLR_BUSY_TIME_OUT 0x04010F00ul ///< Time out when polling MemClrBusy bit 2275 #define MEM_ERROR_MEM_CLEARED_TIME_OUT 0x04020F00ul ///< Time out when polling MemCleared bit 2276 #define MEM_ERROR_FLUSH_WR_TIME_OUT 0x04011000ul ///< Time out when polling FlushWr bit 2277 #define MEM_ERROR_NBPSTATE_TRANSITION_TIME_OUT 0x04012600ul ///< Time out when polling CurNBPstate bit 2278 #define MEM_ERROR_MAX_LAT_NO_WINDOW 0x04070300ul ///< Fail to find pass during Max Rd Latency training 2279 #define MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL 0x04080300ul ///< Fail to launch training code on an AP 2280 #define MEM_ERROR_PARALLEL_TRAINING_TIME_OUT 0x04090300ul ///< Fail to finish parallel training 2281 #define MEM_ERROR_NO_ADDRESS_MAPPING 0x04011100ul ///< No address mapping found for a dimm 2282 #define MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT 0x040A0300ul ///< There is no DQS receiver enable window and the value is equal to the largest value 2283 #define MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE 0x040B0300ul ///< Receive Enable value is too large and is 1 less than limit 2284 #define MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR 0x04011200ul ///< SPD Checksum error for NV_SPDCHK_RESTRT 2285 #define MEM_ERROR_NO_CHIPSELECT 0x04011300ul ///< No chipselects found 2286 #define MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM 0x04011500ul ///< Unbuffered dimm is not supported at 333MHz 2287 #define MEM_ERROR_WL_PRE_OUT_OF_RANGE 0x040C0300ul ///< Returned PRE value during write levelizzation was out of range 2288 #define MEM_ERROR_NO_2D_RDDQS_WINDOW 0x040D0300ul ///< No 2D RdDqs Window 2289 #define MEM_ERROR_NO_2D_RDDQS_HEIGHT 0x040E0300ul ///< No 2D RdDqs Height 2290 #define MEM_ERROR_2D_DQS_ERROR 0x040F0300ul ///< 2d RdDqs Error 2291 #define MEM_ERROR_INVALID_2D_RDDQS_VALUE 0x04022400ul ///< 2d RdDqs invalid value found 2292 #define MEM_ERROR_2D_DQS_VREF_MARGIN_ERROR 0x04023400ul ///< 2d RdDqs Vef Margin error found 2293 #define MEM_ERROR_LR_IBT_NOT_FOUND 0x04013500ul ///< No LR dimm IBT value is found 2294 #define MEM_ERROR_MR0_NOT_FOUND 0x04023500ul ///< No MR0 value is found 2295 #define MEM_ERROR_ODT_PATTERN_NOT_FOUND 0x04033500ul ///< No odt pattern value is found 2296 #define MEM_ERROR_RC2_IBT_NOT_FOUND 0x04043500ul ///< No RC2 IBT value is found 2297 #define MEM_ERROR_RC10_OP_SPEED_NOT_FOUND 0x04053500ul ///< No RC10 op speed is found 2298 #define MEM_ERROR_RTT_NOT_FOUND 0x04063500ul ///< No RTT value is found 2299 #define MEM_ERROR_P2D_NOT_FOUND 0x04073500ul ///< No 2D training config value is found 2300 #define MEM_ERROR_SAO_NOT_FOUND 0x04083500ul ///< No slow access mode, Address timing and Output driver compensation value is found 2301 #define MEM_ERROR_CLK_DIS_MAP_NOT_FOUND 0x04093500ul ///< No CLK disable map is found 2302 #define MEM_ERROR_CKE_TRI_MAP_NOT_FOUND 0x040A3500ul ///< No CKE tristate map is found 2303 #define MEM_ERROR_ODT_TRI_MAP_NOT_FOUND 0x040B3500ul ///< No ODT tristate map is found 2304 #define MEM_ERROR_CS_TRI_MAP_NOT_FOUND 0x040C3500ul ///< No CS tristate map is found 2305 #define MEM_ERROR_TRAINING_SEED_NOT_FOUND 0x040D3500ul ///< No training seed is found 2306 #define MEM_ERROR_CAD_BUS_TMG_NOT_FOUND 0x040E3500ul ///< No CAD Bus Timing Entries found 2307 #define MEM_ERROR_DATA_BUS_CFG_NOT_FOUND 0x040F3500ul ///< No Data Bus Config Entries found 2308 #define MEM_ERROR_NO_2D_WRDAT_WINDOW 0x040D0400ul ///< No 2D WrDat Window 2309 #define MEM_ERROR_NO_2D_WRDAT_HEIGHT 0x040E0400ul ///< No 2D WrDat Height 2310 #define MEM_ERROR_2D_WRDAT_ERROR 0x040F0400ul ///< 2d WrDat Error 2311 #define MEM_ERROR_INVALID_2D_WRDAT_VALUE 0x04100400ul ///< 2d WrDat invalid value found 2312 #define MEM_ERROR_2D_WRDAT_VREF_MARGIN_ERROR 0x04110400ul ///< 2d WrDat Vef Margin error found 2313 #define MEM_ERROR_PMU_TRAINING 0x04120400ul ///< Fail PMU training. 2314 2315 // AGESA_WARNING Memory Errors 2316 #define MEM_WARNING_UNSUPPORTED_QRDIMM 0x04011600ul ///< QR DIMMs detected but not supported 2317 #define MEM_WARNING_UNSUPPORTED_UDIMM 0x04021600ul ///< U DIMMs detected but not supported 2318 #define MEM_WARNING_UNSUPPORTED_SODIMM 0x04031600ul ///< SO-DIMMs detected but not supported 2319 #define MEM_WARNING_UNSUPPORTED_X4DIMM 0x04041600ul ///< x4 DIMMs detected but not supported 2320 #define MEM_WARNING_UNSUPPORTED_RDIMM 0x04051600ul ///< R DIMMs detected but not supported 2321 #define MEM_WARNING_UNSUPPORTED_LRDIMM 0x04061600ul ///< LR DIMMs detected but not supported 2322 #define MEM_WARNING_EMP_NOT_SUPPORTED 0x04011700ul ///< Processor is not capable for EMP 2323 #define MEM_WARNING_EMP_CONFLICT 0x04021700ul ///< EMP cannot be enabled if channel interleaving, 2324 #define MEM_WARNING_EMP_NOT_ENABLED 0x04031700ul ///< Memory size is not power of two. 2325 #define MEM_WARNING_ECC_DIS 0x04041700ul ///< ECC has been disabled as a result of an internal issue 2326 #define MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED 0x04011800ul ///< Performance has been enabled, but battery life is preferred. 2327 ///< bank interleaving, or bank swizzle is enabled. 2328 #define MEM_WARNING_NO_SPDTRC_FOUND 0x04011900ul ///< No Trc timing value found in SPD of a dimm. 2329 #define MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED 0x04012000ul ///< Node Interleaveing Requested, but could not be enabled 2330 #define MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED 0x04012100ul ///< Channel Interleaveing Requested, but could not be enabled 2331 #define MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED 0x04012200ul ///< Bank Interleaveing Requested, but could not be enabled 2332 #define MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED 0x04012300ul ///< Voltage 1.35 determined, but could not be supported 2333 #define MEM_WARNING_INITIAL_DDR3VOLT_NONZERO 0x04012400ul ///< DDR3 voltage initial value is not 0 2334 #define MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO 0x04012500ul ///< Cannot find a commonly supported VDDIO 2335 #define MEM_WARNING_AMP_SUPPORT_DETECTED_BUT_NOT_ENABLED 0x04012900ul ///< AMP support detected but not enabled 2336 #define MEM_WARNING_AMP_SELECTED_BUT_NOT_ENABLED 0x04022900ul ///< AMP selected but not enabled 2337 2338 // AGESA_FATAL Memory Errors 2339 #define MEM_ERROR_MINIMUM_MODE 0x04011A00ul ///< Running in minimum mode 2340 #define MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM 0x04011B00ul ///< DIMM modules are miss-matched 2341 #define MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM 0x04011C00ul ///< No DIMMs have been found 2342 #define MEM_ERROR_MISMATCH_DIMM_CLOCKS 0x04011D00ul ///< DIMM clocks miss-matched 2343 #define MEM_ERROR_NO_CYC_TIME 0x04011E00ul ///< No cycle time found 2344 #define MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS 0x04011F00ul ///< Heap allocation error with dynamic storing of trained timings 2345 #define MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs 0x04021F00ul ///< Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT 2346 #define MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV 0x04031F00ul ///< Heap allocation error with REMOTE_TRAINING_ENV 2347 #define MEM_ERROR_HEAP_ALLOCATE_FOR_SPD 0x04041F00ul ///< Heap allocation error for SPD data 2348 #define MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA 0x04051F00ul ///< Heap allocation error for RECEIVED_DATA during parallel training 2349 #define MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS 0x04061F00ul ///< Heap allocation error for S3 "SPECIAL_CASE_REGISTER" 2350 #define MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA 0x04071F00ul ///< Heap allocation error for Training Data 2351 #define MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK 0x04081F00ul ///< Heap allocation error for DIMM Identify "MEM_NB_BLOCK" 2352 #define MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM 0x04022300ul ///< No Constructor for DIMM Identify 2353 #define MEM_ERROR_VDDIO_UNSUPPORTED 0x04022500ul ///< VDDIO of the dimms on the board is not supported 2354 #define MEM_ERROR_VDDPVDDR_UNSUPPORTED 0x04032500ul ///< VDDP/VDDR value indicated by the platform BIOS is not supported 2355 #define MEM_ERROR_HEAP_ALLOCATE_FOR_2D 0x040B1F00ul ///< Heap allocation error for 2D training data 2356 #define MEM_ERROR_HEAP_DEALLOCATE_FOR_2D 0x040C1F00ul ///< Heap de-allocation error for 2D training data 2357 #define MEM_ERROR_HEAP_ALLOCATE_FOR_DATAEYE 0x040F1F00ul ///< Heap allocation error for DATAEYE Storage 2358 #define MEM_ERROR_HEAP_DEALLOCATE_FOR_DATAEYE 0x040E1F00ul ///< Heap de-allocation error for DATAEYE Storage 2359 #define MEM_ERROR_HEAP_ALLOCATE_FOR_PMU_SRAM_MSG_BLOCK 0x04101F00ul ///< Heap allocation error for PMU SRAM Message Block Storage 2360 #define MEM_ERROR_HEAP_DEALLOCATE_FOR_PMU_SRAM_MSG_BLOCK 0x04111F00ul ///< Heap de-allocation error for PMU SRAM Message Block Storage 2361 #define MEM_ERROR_HEAP_LOCATE_FOR_PMU_SRAM_MSG_BLOCK 0x04121F00ul ///< Heap location error for PMU SRAM Message Block Storage 2362 2363 // AGESA_CRITICAL Memory Errors 2364 #define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3 0x04091F00ul ///< Heap allocation error for DMI table for DDR3 2365 #define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR4 0x040A1F00ul ///< Heap allocation error for DMI table for DDR4 2366 #define MEM_ERROR_UNSUPPORTED_DIMM_CONFIG 0x04011400ul ///< Dimm population is not supported 2367 #define MEM_ERROR_HEAP_ALLOCATE_FOR_CRAT_MEM_AFFINITY 0x040D1F00ul ///< Heap allocation error for CRAT memory affinity info 2368 2369 2370 2371 /*---------------------------------------------------------------------------- 2372 * 2373 * END OF MEMORY-SPECIFIC DATA STRUCTURES 2374 * 2375 *---------------------------------------------------------------------------- 2376 */ 2377 2378 2379 2380 2381 /*---------------------------------------------------------------------------- 2382 * 2383 * CPU RELATED DEFINITIONS 2384 * 2385 *---------------------------------------------------------------------------- 2386 */ 2387 2388 // CPU Event definitions. 2389 2390 // Defines used to filter CPU events based on functional blocks 2391 #define CPU_EVENT_PM_EVENT_MASK 0xFF00FF00ul 2392 #define CPU_EVENT_PM_EVENT_CLASS 0x08000400ul 2393 2394 //================================================================ 2395 // CPU General events 2396 // Heap allocation (AppFunction = 01h) 2397 #define CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT 0x08000100ul 2398 #define CPU_ERROR_HEAP_IS_ALREADY_INITIALIZED 0x08010100ul 2399 #define CPU_ERROR_HEAP_IS_FULL 0x08020100ul 2400 #define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED 0x08030100ul 2401 #define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT 0x08040100ul 2402 // BrandId (AppFunction = 02h) 2403 #define CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE 0x08000200ul 2404 // Micro code patch (AppFunction = 03h) 2405 #define CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED 0x08000300ul 2406 // Power management (AppFunction = 04h) 2407 #define CPU_EVENT_PM_PSTATE_OVERCURRENT 0x08000400ul 2408 #define CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT 0x08010400ul 2409 #define CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE 0x08020400ul 2410 #define CPU_ERROR_PM_NB_PSTATE_MISMATCH 0x08030400ul 2411 #define CPU_ERROR_PM_ALL_PSTATE_OVER_FREQUENCY_LIMIT 0x08040400ul 2412 #define CPU_EVENT_PM_PSTATE_FREQUENCY_LIMIT 0x08050400ul 2413 // Other CPU events (AppFunction = 05h) 2414 #define CPU_EVENT_BIST_ERROR 0x08000500ul 2415 #define CPU_EVENT_UNKNOWN_PROCESSOR_FAMILY 0x08010500ul 2416 #define CPU_EVENT_STACK_REENTRY 0x08020500ul 2417 #define CPU_EVENT_CORE_NOT_IDENTIFIED 0x08030500ul 2418 2419 //================================================================= 2420 // CPU Feature events 2421 // Execution cache (AppFunction = 21h) 2422 // AGESA_CACHE_SIZE_REDUCED 2101 2423 // AGESA_CACHE_REGIONS_ACROSS_1MB 2102 2424 // AGESA_CACHE_REGIONS_ACROSS_4GB 2103 2425 // AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY 2104 2426 // AGESA_CACHE_START_ADDRESS_LESS_D0000 2105 2427 // AGESA_THREE_CACHE_REGIONS_ABOVE_1MB 2106 2428 // AGESA_DEALLOCATE_CACHE_REGIONS 2107 2429 #define CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR 0x08002100ul 2430 // Core Leveling (AppFunction = 22h) 2431 #define CPU_WARNING_ADJUSTED_LEVELING_MODE 0x08002200ul 2432 // SCS initialization (AppFunction = 24h) 2433 // AGESA_SCS_HEAP_ENTRY_MISSING 2401 2434 // AGESA_SCS_BUFFER_EMPTY 2402 2435 // AGESA_SCS_WEIGHTS_MISMATCH 2403 2436 #define CPU_EVENT_SCS_INITIALIZATION_ERROR 0x08002400ul 2437 // BTC vid adjustment error 2438 #define CPU_EVENT_BTC_INITIALIZATION_ERROR 0x08002500ul 2439 2440 // CPU Build Configuration structures and definitions 2441 2442 /// Build Configuration structure for BLDCFG_AP_MTRR_SETTINGS 2443 typedef struct { 2444 IN UINT32 MsrAddr; ///< Fixed-Sized MTRR address 2445 IN UINT64 MsrData; ///< MTRR Settings 2446 } AP_MTRR_SETTINGS; 2447 2448 #define AMD_AP_MTRR_FIX64k_00000 0x00000250ul 2449 #define AMD_AP_MTRR_FIX16k_80000 0x00000258ul 2450 #define AMD_AP_MTRR_FIX16k_A0000 0x00000259ul 2451 #define AMD_AP_MTRR_FIX4k_C0000 0x00000268ul 2452 #define AMD_AP_MTRR_FIX4k_C8000 0x00000269ul 2453 #define AMD_AP_MTRR_FIX4k_D0000 0x0000026Aul 2454 #define AMD_AP_MTRR_FIX4k_D8000 0x0000026Bul 2455 #define AMD_AP_MTRR_FIX4k_E0000 0x0000026Cul 2456 #define AMD_AP_MTRR_FIX4k_E8000 0x0000026Dul 2457 #define AMD_AP_MTRR_FIX4k_F0000 0x0000026Eul 2458 #define AMD_AP_MTRR_FIX4k_F8000 0x0000026Ful 2459 #define CPU_LIST_TERMINAL 0xFFFFFFFFul 2460 2461 /// Data structure for the Mapping Item between Unified ID for IDS Setup Option 2462 /// and the option value. 2463 /// 2464 typedef struct { 2465 IN UINT16 IdsNvId; ///< Unified ID for IDS Setup Option. 2466 OUT UINT16 IdsNvValue; ///< The value of IDS Setup Option. 2467 } IDS_NV_ITEM; 2468 2469 /// Data Structure for IDS CallOut Function 2470 typedef struct { 2471 IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header 2472 IN IDS_NV_ITEM *IdsNvPtr; ///< Memory Pointer of IDS NV Table 2473 IN OUT UINTN Reserved; ///< reserved 2474 } IDS_CALLOUT_STRUCT; 2475 2476 /// Data Structure for Connected Standby Function 2477 typedef struct { 2478 IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header 2479 IN VOID *CsRestoreTable; ///< Pointer to the CsRestoreTable 2480 IN UINT32 CsRestoreTableSize; ///< Size in bytes of the CsRestoreTable 2481 } CS_CALLOUT_STRUCT; 2482 2483 /************************************************************************ 2484 * 2485 * AGESA interface Call-Out function parameter structures 2486 * 2487 ***********************************************************************/ 2488 2489 /// Parameters structure for interface call-out AgesaAllocateBuffer 2490 typedef struct { 2491 IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header 2492 IN OUT UINT32 BufferLength; ///< Size of buffer to allocate 2493 IN UINT32 BufferHandle; ///< Identifier or name for the buffer 2494 OUT VOID *BufferPointer; ///< location of the created buffer 2495 } AGESA_BUFFER_PARAMS; 2496 2497 /// Parameters structure for interface call-out AgesaHeapRebase 2498 typedef struct { 2499 IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header 2500 OUT UINTN HeapAddress; ///< The address which heap content will be temporarily stored in 2501 } AGESA_REBASE_PARAMS; 2502 2503 /// Parameters structure for interface call-out AgesaRunCodeOnAp 2504 typedef struct { 2505 IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header 2506 IN UINT32 FunctionNumber; ///< Index of the procedure to execute 2507 IN VOID *RelatedDataBlock; ///< Location of data structure the procedure will use 2508 IN UINT32 RelatedBlockLength; ///< Size of the related data block 2509 IN BOOLEAN AllAPs; ///< run on all Aps or on one only 2510 } AP_EXE_PARAMS; 2511 2512 /// Parameters structure for the interface call-out AgesaReadSpd & AgesaReadSpdRecovery 2513 typedef struct { 2514 IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header 2515 IN UINT8 SocketId; ///< Address of SPD - socket ID 2516 IN UINT8 MemChannelId; ///< Address of SPD - memory channel ID 2517 IN UINT8 DimmId; ///< Address of SPD - DIMM ID 2518 IN OUT UINT8 *Buffer; ///< Location where to place the SPD content 2519 IN OUT MEM_DATA_STRUCT *MemData; ///< Location of the MemData structure, for reference 2520 } AGESA_READ_SPD_PARAMS; 2521 2522 /// Parameters structure for the interface call-out AGESA_HALT_THIS_AP 2523 typedef struct { 2524 IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header 2525 IN BOOLEAN ExecWbinvd; ///< Indicates whether to execute 2526 /// WBINVD 2527 IN BOOLEAN PrimaryCore; ///< Indicates whether current core 2528 /// is the primary core of the 2529 /// compute unit 2530 IN BOOLEAN CacheEn; ///< Indicates whether cache should 2531 /// be enabled 2532 } AGESA_HALT_THIS_AP_PARAMS; 2533 2534 /// Parameters structure for interface call-out AgesaGetTempHeapBase 2535 typedef struct { 2536 IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration 2537 /// header 2538 OUT UINTN TempHeapAddress; ///< The address where heap 2539 /// contents will be stored 2540 /// temporarily 2541 } AGESA_TEMP_HEAP_BASE_PARAMS; 2542 2543 /// VoltageType values 2544 typedef enum { 2545 VTYPE_CPU_VREF, ///< Cpu side Vref 2546 VTYPE_DIMM_VREF, ///< Dimm Side Vref 2547 VTYPE_VDDIO ///< Vddio 2548 } VTYPE; 2549 2550 /// Parameters structure for the interface call-out AgesaExternalVoltageAdjust 2551 typedef struct _VOLTAGE_ADJUST { 2552 IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header 2553 IN OUT MEM_DATA_STRUCT *MemData; ///< Location of the MemData structure, for reference 2554 IN VTYPE VoltageType; ///< Which Voltage Type to adjust 2555 IN INT8 AdjustValue; ///< Positive/Negative Adjust Value 2556 } VOLTAGE_ADJUST; 2557 2558 /// Buffer Handles 2559 typedef enum { 2560 AMD_DMI_INFO_BUFFER_HANDLE = 0x000D000, ///< Assign 0x000D000 buffer handle to DMI function 2561 AMD_PSTATE_DATA_BUFFER_HANDLE, ///< Assign 0x000D001 buffer handle to Pstate data 2562 AMD_PSTATE_ACPI_BUFFER_HANDLE, ///< Assign 0x000D002 buffer handle to Pstate table 2563 AMD_BRAND_ID_BUFFER_HANDLE, ///< Assign 0x000D003 buffer handle to Brand ID 2564 AMD_WHEA_BUFFER_HANDLE, ///< Assign 0x000D004 buffer handle to WHEA function 2565 AMD_S3_INFO_BUFFER_HANDLE, ///< Assign 0x000D005 buffer handle to S3 function 2566 AMD_S3_NB_INFO_BUFFER_HANDLE, ///< Assign 0x000D006 buffer handle to S3 NB device info 2567 AMD_ACPI_ALIB_BUFFER_HANDLE, ///< Assign 0x000D007 buffer handle to ALIB SSDT table 2568 AMD_ACPI_IVRS_BUFFER_HANDLE, ///< Assign 0x000D008 buffer handle to IOMMU IVRS table 2569 AMD_CRAT_INFO_BUFFER_HANDLE, ///< Assign 0x000D009 buffer handle to CRAT function 2570 AMD_ACPI_CDIT_BUFFER_HANDLE, ///< Assign 0x000D00A buffer handle to CDIT function 2571 AMD_GNB_SMU_MEMORY_INFO_BUFFER_HANDLE ///< Assign 0x000D00B buffer handle to SMU memory parameters function 2572 } AMD_BUFFER_HANDLE; 2573 2574 2575 /************************************************************************ 2576 * 2577 * AGESA interface Call-Out function prototypes 2578 * 2579 ***********************************************************************/ 2580 2581 VOID 2582 AgesaDoReset ( 2583 IN UINTN ResetType, 2584 IN OUT AMD_CONFIG_PARAMS *StdHeader 2585 ); 2586 2587 AGESA_STATUS 2588 AgesaAllocateBuffer ( 2589 IN UINTN FcnData, 2590 IN OUT AGESA_BUFFER_PARAMS *AllocParams 2591 ); 2592 2593 AGESA_STATUS 2594 AgesaDeallocateBuffer ( 2595 IN UINTN FcnData, 2596 IN OUT AGESA_BUFFER_PARAMS *DeallocParams 2597 ); 2598 2599 AGESA_STATUS 2600 AgesaLocateBuffer ( 2601 IN UINTN FcnData, 2602 IN OUT AGESA_BUFFER_PARAMS *LocateParams 2603 ); 2604 2605 AGESA_STATUS 2606 AgesaHeapRebase ( 2607 IN UINTN FcnData, 2608 IN OUT AGESA_REBASE_PARAMS *RebaseParams 2609 ); 2610 2611 AGESA_STATUS 2612 AgesaReadSpd ( 2613 IN UINTN FcnData, 2614 IN OUT AGESA_READ_SPD_PARAMS *ReadSpd 2615 ); 2616 2617 AGESA_STATUS 2618 AgesaReadSpdRecovery ( 2619 IN UINTN FcnData, 2620 IN OUT AGESA_READ_SPD_PARAMS *ReadSpd 2621 ); 2622 2623 AGESA_STATUS 2624 AgesaHookBeforeDramInitRecovery ( 2625 IN UINTN FcnData, 2626 IN OUT MEM_DATA_STRUCT *MemData 2627 ); 2628 2629 AGESA_STATUS 2630 AgesaGetTempHeapBase ( 2631 IN UINTN FcnData, 2632 IN OUT AGESA_TEMP_HEAP_BASE_PARAMS *TempHeapBaseParams 2633 ); 2634 2635 AGESA_STATUS 2636 AgesaRunFcnOnAp ( 2637 IN UINTN ApicIdOfCore, 2638 IN AP_EXE_PARAMS *LaunchApParams 2639 ); 2640 2641 AGESA_STATUS 2642 AgesaRunFcnOnAllAps ( 2643 IN UINTN FcnData, 2644 IN AP_EXE_PARAMS *LaunchApParams 2645 ); 2646 2647 AGESA_STATUS 2648 AgesaWaitForAllApsFinished ( 2649 IN UINTN FcnData, 2650 IN AMD_CONFIG_PARAMS *StdHeader 2651 ); 2652 2653 AGESA_STATUS 2654 AgesaIdleAnAp ( 2655 IN UINTN ApicIdOfCore, 2656 IN AMD_CONFIG_PARAMS *StdHeader 2657 ); 2658 2659 AGESA_STATUS 2660 AgesaHaltThisAp ( 2661 IN UINTN FcnData, 2662 IN AGESA_HALT_THIS_AP_PARAMS *HaltApParams 2663 ); 2664 2665 AGESA_STATUS 2666 AgesaHookBeforeDramInit ( 2667 IN UINTN SocketIdModuleId, 2668 IN OUT MEM_DATA_STRUCT *MemData 2669 ); 2670 2671 AGESA_STATUS 2672 AgesaHookBeforeDQSTraining ( 2673 IN UINTN SocketIdModuleId, 2674 IN OUT MEM_DATA_STRUCT *MemData 2675 ); 2676 2677 AGESA_STATUS 2678 AgesaHookBeforeExitSelfRefresh ( 2679 IN UINTN FcnData, 2680 IN OUT MEM_DATA_STRUCT *MemData 2681 ); 2682 2683 AGESA_STATUS 2684 AgesaPcieSlotResetControl ( 2685 IN UINTN FcnData, 2686 IN PCIe_SLOT_RESET_INFO *ResetInfo 2687 ); 2688 2689 AGESA_STATUS 2690 AgesaGetVbiosImage ( 2691 IN UINTN FcnData, 2692 IN OUT GFX_VBIOS_IMAGE_INFO *VbiosImageInfo 2693 ); 2694 2695 AGESA_STATUS 2696 AgesaFchOemCallout ( 2697 IN VOID *FchData 2698 ); 2699 2700 AGESA_STATUS 2701 AgesaExternal2dTrainVrefChange ( 2702 IN UINTN SocketIdModuleId, 2703 IN OUT MEM_DATA_STRUCT *MemData 2704 ); 2705 2706 AGESA_STATUS 2707 AgesaGetIdsData ( 2708 IN UINTN Data, 2709 IN OUT IDS_CALLOUT_STRUCT *IdsCalloutData 2710 ); 2711 2712 AGESA_STATUS 2713 AgesaExternalVoltageAdjust ( 2714 IN UINTN SocketIdModuleId, 2715 IN OUT VOLTAGE_ADJUST *AdjustValue 2716 ); 2717 2718 AGESA_STATUS 2719 AgesaGnbOemCallout ( 2720 IN AMD_CONFIG_PARAMS *StdHeader, 2721 IN UINTN FcnData, 2722 IN OUT VOID *GnbCalloutData 2723 ); 2724 2725 /************************************************************************ 2726 * 2727 * AGESA interface structure definition and function prototypes 2728 * 2729 ***********************************************************************/ 2730 2731 /********************************************************************** 2732 * Platform Configuration: The parameters in boot branch function 2733 **********************************************************************/ 2734 2735 /// The possible platform control flow settings. 2736 typedef enum { 2737 Nfcm, ///< Normal Flow Control Mode. 2738 UmaDr, ///< UMA using Display Refresh flow control. 2739 UmaIfcm, ///< UMA using Isochronous Flow Control. 2740 Ifcm, ///< Isochronous Flow Control Mode (other than for UMA). 2741 Iommu, ///< An IOMMU is in use in the system. 2742 MaxControlFlow ///< Not a control flow mode, use for limit checking. 2743 } PLATFORM_CONTROL_FLOW; 2744 2745 /// The possible hardware prefetch mode settings. 2746 typedef enum { 2747 HARDWARE_PREFETCHER_AUTO, ///< Use the recommended setting for the processor. In most cases, the recommended setting is enabled. 2748 DISABLE_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES, ///< Use the recommended setting for the hardware prefetcher, but disable training on software prefetches. 2749 DISABLE_L1_PREFETCHER, ///< Use the recommended settings for the hardware prefetcher, but disable L1 prefetching and above. 2750 DISABLE_L2_STRIDE_PREFETCHER, ///< Use the recommended settings for the hardware prefetcher, but disable the L2 stride prefetcher and above 2751 DISABLE_HARDWARE_PREFETCH, ///< Disable hardware prefetching. 2752 MAX_HARDWARE_PREFETCH_MODE ///< Not a hardware prefetch mode, use for limit checking. 2753 } HARDWARE_PREFETCH_MODE; 2754 2755 /// The possible software prefetch mode settings. 2756 typedef enum { 2757 SOFTWARE_PREFETCHES_AUTO, ///< Use the recommended setting for the processor. In most cases, the recommended setting is enabled. 2758 DISABLE_SOFTWARE_PREFETCHES, ///< Disable software prefetches (convert software prefetch instructions to NOP). 2759 MAX_SOFTWARE_PREFETCH_MODE ///< Not a software prefetch mode, use for limit checking. 2760 } SOFTWARE_PREFETCH_MODE; 2761 2762 /// Advanced performance tunings, prefetchers. 2763 /// These settings provide for performance tuning to optimize for specific workloads. 2764 typedef struct { 2765 IN HARDWARE_PREFETCH_MODE HardwarePrefetchMode; ///< This value provides for advanced performance tuning by controlling the hardware prefetcher setting. 2766 IN SOFTWARE_PREFETCH_MODE SoftwarePrefetchMode; ///< This value provides for advanced performance tuning by controlling the software prefetch instructions. 2767 IN DRAM_PREFETCH_MODE DramPrefetchMode; ///< This value provides for advanced performance tuning by controlling the DRAM prefetcher setting. 2768 } ADVANCED_PERFORMANCE_PROFILE; 2769 2770 /// The possible memory power policy settings. 2771 typedef enum { 2772 Performance, ///< Optimize for performance. 2773 BatteryLife, ///< Optimize for battery life. 2774 Auto, ///< Auto 2775 MaxPowerPolicy ///< Not a power policy mode, use for limit checking. 2776 } MEMORY_POWER_POLICY; 2777 2778 /// Platform performance settings for optimized settings. 2779 /// Several configuration settings for the processor depend upon other parts and 2780 /// general designer choices for the system. The determination of these data points 2781 /// is not standard for all platforms, so the host environment needs to provide these 2782 /// to specify how the system is to be configured. 2783 typedef struct { 2784 IN PLATFORM_CONTROL_FLOW PlatformControlFlowMode; ///< The platform's control flow mode for optimum platform performance. 2785 ///< @BldCfgItem{BLDCFG_PLATFORM_CONTROL_FLOW_MODE} 2786 IN BOOLEAN Use32ByteRefresh; ///< Display Refresh traffic generates 32 byte requests. 2787 ///< @BldCfgItem{BLDCFG_USE_32_BYTE_REFRESH} 2788 IN BOOLEAN UseVariableMctIsocPriority; ///< The Memory controller will be set to Variable Isoc Priority. 2789 ///< @BldCfgItem{BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY} 2790 IN ADVANCED_PERFORMANCE_PROFILE AdvancedPerformanceProfile; ///< The advanced platform performance settings. 2791 IN MEMORY_POWER_POLICY MemoryPowerPolicy; ///< The memory's desired power policy 2792 ///< @BldCfgItem{BLDCFG_MEMORY_POWER_POLICY_MODE} 2793 IN BOOLEAN NbPstatesSupported; ///< The Nb-Pstates is supported or not 2794 ///< @BldCfgItem{BLDCFG_NB_PSTATES_SUPPORTED} 2795 } PERFORMANCE_PROFILE; 2796 2797 /// Platform settings that describe the voltage regulator modules of the system. 2798 /// Many power management settings are dependent upon the characteristics of the 2799 /// on-board voltage regulator module (VRM). The host environment needs to provide 2800 /// these to specify how the system is to be configured. 2801 typedef struct { 2802 IN UINT32 CurrentLimit; ///< Vrm Current Limit. 2803 ///< @BldCfgItem{BLDCFG_VRM_CURRENT_LIMIT} 2804 ///< @BldCfgItem{BLDCFG_VRM_NB_CURRENT_LIMIT} 2805 ///< @BldCfgItem{BLDCFG_VRM_GFX_CURRENT_LIMIT} 2806 IN UINT32 LowPowerThreshold; ///< Vrm Low Power Threshold. 2807 ///< @BldCfgItem{BLDCFG_VRM_LOW_POWER_THRESHOLD} 2808 ///< @BldCfgItem{BLDCFG_VRM_NB_LOW_POWER_THRESHOLD} 2809 ///< @BldCfgItem{BLDCFG_VRM_GFX_LOW_POWER_THRESHOLD} 2810 IN UINT32 SlewRate; ///< Vrm Slew Rate. 2811 ///< @BldCfgItem{BLDCFG_VRM_SLEW_RATE} 2812 ///< @BldCfgItem{BLDCFG_VRM_NB_SLEW_RATE} 2813 ///< @BldCfgItem{BLDCFG_VRM_GFX_SLEW_RATE} 2814 IN BOOLEAN HiSpeedEnable; ///< Select high speed VRM. 2815 ///< @BldCfgItem{BLDCFG_VRM_HIGH_SPEED_ENABLE} 2816 ///< @BldCfgItem{BLDCFG_VRM_NB_HIGH_SPEED_ENABLE} 2817 ///< @BldCfgItem{BLDCFG_VRM_GFX_HIGH_SPEED_ENABLE} 2818 IN UINT32 MaximumCurrentLimit; ///< Vrm Maximum Current Limit. 2819 ///< @BldCfgItem{BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT} 2820 ///< @BldCfgItem{BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT} 2821 ///< @BldCfgItem{BLDCFG_VRM_GFX_MAXIMUM_CURRENT_LIMIT} 2822 IN UINT32 SviOcpLevel; ///< SVI OCP Level. 2823 ///< @BldCfgItem{BLDCFG_VRM_SVI_OCP_LEVEL} 2824 ///< @BldCfgItem{BLDCFG_VRM_NB_SVI_OCP_LEVEL} 2825 ///< @BldCfgItem{BLDCFG_VRM_GFX_SVI_OCP_LEVEL} 2826 } PLATFORM_VRM_CONFIGURATION; 2827 2828 /// The VRM types to characterize. 2829 typedef enum { 2830 CoreVrm, ///< VDD plane. 2831 NbVrm, ///< VDDNB plane. 2832 GfxVrm, ///< GFX plane. 2833 MaxVrmType ///< Not a valid VRM type, use for limit checking. 2834 } PLATFORM_VRM_TYPE; 2835 2836 /// The StapmBoost settings. 2837 typedef enum { 2838 StapmBoostDisabled, ///< Disable Stapm Boost 2839 StapmBoostEnabled, ///< Enable Stapm Boost 2840 StapmBoostSystemConfig ///< Default setting uses IRM programming setting 2841 } STAPM_BOOST_TYPE; 2842 2843 2844 /// These to specify how the system is to be configured for STAPM 2845 typedef struct { 2846 IN UINT32 CfgStapmScalar; ///< Specify a % scalar to adjust this. Leave this unused for now until it is figured out. 2847 ///< @BldCfgItem{BLDCFG_STAPM_SCALAR} 2848 IN UINT32 CfgStapmBoost; ///< If STAPM boost is enabled. System will actively track skin temperature and will allow higher performance till Skin temperature is below the limit 2849 ///< @BldCfgItem{BLDCFG_STAPM_BOOST} 2850 IN UINT32 CfgStapmTimeConstant; ///< Maximum power that the APU is allowed to consume when STAPM is enabled and Skin temperature is below the limit. 2851 ///< Specified time in seconds. 2852 ///< @BldCfgItem{BLDCFG_STAPM_TIME_CONSTANT} 2853 } PLATFORM_STAPM_CONFIGURATION; 2854 2855 /// FCH Platform Configuration Policy 2856 typedef struct { 2857 IN UINT16 CfgSmbus0BaseAddress; ///< SMBUS0 Controller Base Address 2858 IN UINT16 CfgSmbus1BaseAddress; ///< SMBUS1 Controller Base Address 2859 IN UINT16 CfgSioPmeBaseAddress; ///< I/O base address for LPC I/O target range 2860 IN UINT16 CfgAcpiPm1EvtBlkAddr; ///< I/O base address of ACPI power management Event Block 2861 IN UINT16 CfgAcpiPm1CntBlkAddr; ///< I/O base address of ACPI power management Control Block 2862 IN UINT16 CfgAcpiPmTmrBlkAddr; ///< I/O base address of ACPI power management Timer Block 2863 IN UINT16 CfgCpuControlBlkAddr; ///< I/O base address of ACPI power management CPU Control Block 2864 IN UINT16 CfgAcpiGpe0BlkAddr; ///< I/O base address of ACPI power management General Purpose Event Block 2865 IN UINT16 CfgSmiCmdPortAddr; ///< I/O base address of ACPI SMI Command Block 2866 IN UINT16 CfgAcpiPmaCntBlkAddr; ///< I/O base address of ACPI power management additional control block 2867 IN UINT32 CfgGecShadowRomBase; ///< 32-bit base address to the GEC shadow ROM 2868 IN UINT32 CfgWatchDogTimerBase; ///< Watchdog Timer base address 2869 IN UINT32 CfgSpiRomBaseAddress; ///< Base address for the SPI ROM controller 2870 IN UINT32 CfgHpetBaseAddress; ///< HPET MMIO base address 2871 IN UINT32 CfgAzaliaSsid; ///< Subsystem ID of HD Audio controller 2872 IN UINT32 CfgSmbusSsid; ///< Subsystem ID of SMBUS controller 2873 IN UINT32 CfgIdeSsid; ///< Subsystem ID of IDE controller 2874 IN UINT32 CfgSataAhciSsid; ///< Subsystem ID of SATA controller in AHCI mode 2875 IN UINT32 CfgSataIdeSsid; ///< Subsystem ID of SATA controller in IDE mode 2876 IN UINT32 CfgSataRaid5Ssid; ///< Subsystem ID of SATA controller in RAID5 mode 2877 IN UINT32 CfgSataRaidSsid; ///< Subsystem ID of SATA controller in RAID mode 2878 IN UINT32 CfgEhciSsid; ///< Subsystem ID of EHCI 2879 IN UINT32 CfgOhciSsid; ///< Subsystem ID of OHCI 2880 IN UINT32 CfgLpcSsid; ///< Subsystem ID of LPC ISA Bridge 2881 IN UINT32 CfgSdSsid; ///< Subsystem ID of SecureDigital controller 2882 IN UINT32 CfgXhciSsid; ///< Subsystem ID of XHCI 2883 IN BOOLEAN CfgFchPort80BehindPcib; ///< Is port80 cycle going to the PCI bridge 2884 IN BOOLEAN CfgFchEnableAcpiSleepTrap; ///< ACPI sleep SMI enable/disable 2885 IN GPP_LINKMODE CfgFchGppLinkConfig; ///< GPP link configuration 2886 IN BOOLEAN CfgFchGppPort0Present; ///< Is FCH GPP port 0 present 2887 IN BOOLEAN CfgFchGppPort1Present; ///< Is FCH GPP port 1 present 2888 IN BOOLEAN CfgFchGppPort2Present; ///< Is FCH GPP port 2 present 2889 IN BOOLEAN CfgFchGppPort3Present; ///< Is FCH GPP port 3 present 2890 IN BOOLEAN CfgFchGppPort0HotPlug; ///< Is FCH GPP port 0 hotplug capable 2891 IN BOOLEAN CfgFchGppPort1HotPlug; ///< Is FCH GPP port 1 hotplug capable 2892 IN BOOLEAN CfgFchGppPort2HotPlug; ///< Is FCH GPP port 2 hotplug capable 2893 IN BOOLEAN CfgFchGppPort3HotPlug; ///< Is FCH GPP port 3 hotplug capable 2894 2895 IN UINT8 CfgFchEsataPortBitMap; ///< ESATA Port definition, eg: [0]=1, means port 0 is ESATA capable 2896 IN UINT8 CfgFchIrPinControl; ///< Register bitfield describing Infrared Pin Control: 2897 ///< [0] - IR Enable 0 2898 ///< [1] - IR Enable 1 2899 ///< [2] - IR Tx0 2900 ///< [3] - IR Tx1 2901 ///< [4] - IR Open Drain 2902 ///< [5] - IR Enable LED 2903 IN SD_CLOCK_CONTROL CfgFchSdClockControl; ///< FCH SD Clock Control 2904 IN SCI_MAP_CONTROL *CfgFchSciMapControl; ///< FCH SCI Mapping Control 2905 IN SATA_PHY_CONTROL *CfgFchSataPhyControl; ///< FCH SATA PHY Control 2906 IN GPIO_CONTROL *CfgFchGpioControl; ///< FCH GPIO Control 2907 IN BOOLEAN CfgFchRtcWorkAround; ///< FCH RTC Workaround 2908 IN BOOLEAN CfgFchUsbPortDisWorkAround; ///< FCH USB Workaround 2909 IN BOOLEAN CfgFchAllowSpiInterfaceUpdate; ///< FchAllowSpiInterfaceUpdate - Fch Allow Spi Interface Update 2910 } FCH_PLATFORM_POLICY; 2911 2912 2913 /// Build Option/Configuration Boolean Structure. 2914 typedef struct { 2915 IN AMD_CODE_HEADER VersionString; ///< AMD embedded code version string 2916 2917 //Build Option Area 2918 IN BOOLEAN OptionUDimms; ///< @ref BLDOPT_REMOVE_UDIMMS_SUPPORT "BLDOPT_REMOVE_UDIMMS_SUPPORT" 2919 IN BOOLEAN OptionRDimms; ///< @ref BLDOPT_REMOVE_RDIMMS_SUPPORT "BLDOPT_REMOVE_RDIMMS_SUPPORT" 2920 IN BOOLEAN OptionLrDimms; ///< @ref BLDOPT_REMOVE_LRDIMMS_SUPPORT "BLDOPT_REMOVE_LRDIMMS_SUPPORT" 2921 IN BOOLEAN OptionEcc; ///< @ref BLDOPT_REMOVE_ECC_SUPPORT "BLDOPT_REMOVE_ECC_SUPPORT" 2922 IN BOOLEAN OptionBankInterleave; ///< @ref BLDOPT_REMOVE_BANK_INTERLEAVE "BLDOPT_REMOVE_BANK_INTERLEAVE" 2923 IN BOOLEAN OptionDctInterleave; ///< @ref BLDOPT_REMOVE_DCT_INTERLEAVE "BLDOPT_REMOVE_DCT_INTERLEAVE" 2924 IN BOOLEAN OptionNodeInterleave; ///< @ref BLDOPT_REMOVE_NODE_INTERLEAVE "BLDOPT_REMOVE_NODE_INTERLEAVE" 2925 IN BOOLEAN OptionParallelTraining; ///< @ref BLDOPT_REMOVE_PARALLEL_TRAINING "BLDOPT_REMOVE_PARALLEL_TRAINING" 2926 IN BOOLEAN OptionOnlineSpare; ///< @ref BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT "BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT" 2927 IN BOOLEAN OptionMemRestore; ///< @ref BLDOPT_REMOVE_MEM_RESTORE_SUPPORT "BLDOPT_REMOVE_MEM_RESTORE_SUPPORT" 2928 IN BOOLEAN OptionAcpiPstates; ///< @ref BLDOPT_REMOVE_ACPI_PSTATES "BLDOPT_REMOVE_ACPI_PSTATES" 2929 IN BOOLEAN OptionCrat; ///< @ref BLDOPT_REMOVE_CRAT "BLDOPT_REMOVE_CRAT" 2930 IN BOOLEAN OptionCdit; ///< @ref BLDOPT_REMOVE_CDIT "BLDOPT_REMOVE_CDIT" 2931 IN BOOLEAN OptionWhea; ///< @ref BLDOPT_REMOVE_WHEA "BLDOPT_REMOVE_WHEA" 2932 IN BOOLEAN OptionDmi; ///< @ref BLDOPT_REMOVE_DMI "BLDOPT_REMOVE_DMI" 2933 IN BOOLEAN OptionEarlySamples; ///< @ref BLDOPT_REMOVE_EARLY_SAMPLES "BLDOPT_REMOVE_EARLY_SAMPLES" 2934 IN BOOLEAN OptionAddrToCsTranslator; ///< ADDR_TO_CS_TRANSLATOR 2935 2936 //Build Configuration Area 2937 IN UINT64 CfgPciMmioAddress; ///< Pci Mmio Base Address to use for PCI Config accesses. 2938 ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCI_MMIO_BASE} 2939 IN UINT32 CfgPciMmioSize; ///< Pci Mmio region Size. 2940 ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCI_MMIO_SIZE} 2941 IN PLATFORM_VRM_CONFIGURATION CfgPlatVrmCfg[MaxVrmType]; ///< Several configuration settings for the voltage regulator modules. 2942 IN UINT32 CfgCpuFrequencyLimit; ///< CPU frequency limit 2943 IN PLATFORM_CONNECTED_STANDBY_MODES CfgPlatformConnectedStandbyMode; ///< Enable or disable connected standby 2944 IN UINT32 CfgPlatNumIoApics; ///< The number of IO APICS for the platform. 2945 IN UINT32 CfgMemInitPstate; ///< Memory Init Pstate. 2946 IN PLATFORM_CSTATE_MODES CfgPlatformCStateMode; ///< Select the C-State Mode that will used. 2947 IN UINT32 CfgPlatformCStateOpData; ///< An IO port or additional C-State setup data, depends on C-State mode. 2948 IN UINT16 CfgPlatformCStateIoBaseAddress; ///< Specifies I/O ports that can be used to allow CPU to enter CStates 2949 IN PLATFORM_CPB_MODES CfgPlatformCpbMode; ///< Enable or disable core performance boost 2950 IN UINT32 CfgCoreLevelingMode; ///< Apply any downcoring or core count leveling as specified. 2951 IN PERFORMANCE_PROFILE CfgPerformanceProfile; ///< The platform's control flow mode and platform performance settings. 2952 2953 IN UINT32 CfgAmdPlatformType; ///< Designate the platform as a Server, Desktop, or Mobile. 2954 IN UINT32 CfgAmdPowerCeiling; ///< PowerCeiling, specifies a maximum power usage limit for the platform 2955 IN UINT16 CfgHtcTemperatureLimit; ///< Hardware Thermal Control temperature limit in tenths of degrees Celsius. 2956 IN UINT16 CfgLhtcTemperatureLimit; ///< Local Hardware Thermal Control temperature limit in tenths of degrees Celsius. 2957 2958 IN UINT32 CfgMemoryBusFrequencyLimit; ///< Memory Bus Frequency Limit. 2959 ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT} 2960 IN BOOLEAN CfgMemoryModeUnganged; ///< Memory Mode Unganged. 2961 ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_MODE_UNGANGED} 2962 IN BOOLEAN CfgMemoryQuadRankCapable; ///< Memory Quad Rank Capable. 2963 ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_QUAD_RANK_CAPABLE} 2964 IN UINT32 CfgMemoryQuadrankType; ///< Memory Quadrank Type. 2965 ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_QUADRANK_TYPE} 2966 IN BOOLEAN CfgMemoryRDimmCapable; ///< Memory RDIMM Capable. 2967 IN BOOLEAN CfgMemoryLRDimmCapable; ///< Memory LRDIMM Capable. 2968 IN BOOLEAN CfgMemoryUDimmCapable; ///< Memory UDIMM Capable. 2969 IN BOOLEAN CfgMemorySODimmCapable; ///< Memory SODimm Capable. 2970 ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_SODIMM_CAPABLE} 2971 IN BOOLEAN CfgLimitMemoryToBelow1Tb; ///< Limit memory address space to below 1TB 2972 IN BOOLEAN CfgMemoryEnableBankSwapOnly; ///< Memory Enable Bank Swap Only @BldCfgItem{BLDCFG_MEMORY_ENABLE_BANK_SWAP_ONLY} 2973 IN BOOLEAN CfgMemoryEnableBankInterleaving; ///< Memory Enable Bank Interleaving. 2974 IN BOOLEAN CfgMemoryEnableNodeInterleaving; ///< Memory Enable Node Interleaving. 2975 IN BOOLEAN CfgMemoryChannelInterleaving; ///< Memory Channel Interleaving. 2976 IN BOOLEAN CfgMemoryPowerDown; ///< Memory Power Down. 2977 IN UINT8 CfgMemoryMacDefault; ///< Memory DRAM MAC Default 2978 IN BOOLEAN CfgMemoryExtendedTemperatureRange; ///< Memory Extended Temperature Range 2979 IN BOOLEAN CfgDramTempControlledRefreshEn; ///< Temperature Controlled Refresh Rate - @BldCfgItem{BLDCFG_DRAM_TEMP_CONTROLLED_REFRESH_EN} 2980 IN UINT32 CfgPowerDownMode; ///< Power Down Mode. 2981 IN BOOLEAN CfgOnlineSpare; ///< Online Spare. 2982 IN BOOLEAN CfgMemoryParityEnable; ///< Memory Parity Enable. 2983 IN BOOLEAN CfgBankSwizzle; ///< Bank Swizzle. 2984 IN UINT32 CfgTimingModeSelect; ///< Timing Mode Select. 2985 IN UINT32 CfgMemoryClockSelect; ///< Memory Clock Select. 2986 IN BOOLEAN CfgDqsTrainingControl; ///< Dqs Training Control. 2987 ///< Build-time customizable only - @BldCfgItem{BLDCFG_DQS_TRAINING_CONTROL} 2988 IN BOOLEAN CfgIgnoreSpdChecksum; ///< Ignore Spd Checksum. 2989 ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGNORE_SPD_CHECKSUM} 2990 IN BOOLEAN CfgUseBurstMode; ///< Use Burst Mode. 2991 ///< Build-time customizable only - @BldCfgItem{BLDCFG_USE_BURST_MODE} 2992 IN BOOLEAN CfgMemoryAllClocksOn; ///< Memory All Clocks On. 2993 ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_ALL_CLOCKS_ON} 2994 IN BOOLEAN CfgDdrPhyDllBypassMode; ///< Enable DllPDBypassMode 2995 IN BOOLEAN CfgEnableEccFeature; ///< Enable ECC Feature. 2996 IN BOOLEAN CfgEccRedirection; ///< ECC Redirection. 2997 ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_REDIRECTION} 2998 IN UINT16 CfgScrubDramRate; ///< Scrub Dram Rate. 2999 ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_DRAM_RATE} 3000 IN UINT16 CfgScrubL2Rate; ///< Scrub L2Rate. 3001 ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_L2_RATE} 3002 IN UINT16 CfgScrubL3Rate; ///< Scrub L3Rate. 3003 ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_L3_RATE} 3004 IN UINT16 CfgScrubIcRate; ///< Scrub Ic Rate. 3005 ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_IC_RATE} 3006 IN UINT16 CfgScrubDcRate; ///< Scrub Dc Rate. 3007 ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_DC_RATE} 3008 IN BOOLEAN CfgEccSyncFlood; ///< ECC Sync Flood. 3009 ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_SYNC_FLOOD} 3010 IN UINT16 CfgEccSymbolSize; ///< ECC Symbol Size. 3011 ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_SYMBOL_SIZE} 3012 IN UINT64 CfgHeapDramAddress; ///< Heap contents will be temporarily stored in this address during the transition. 3013 ///< Build-time customizable only - @BldCfgItem{BLDCFG_HEAP_DRAM_ADDRESS} 3014 IN BOOLEAN CfgNodeMem1GBAlign; ///< Node Mem 1GB boundary Alignment 3015 IN BOOLEAN CfgS3LateRestore; ///< S3 Late Restore 3016 IN BOOLEAN CfgAcpiPstateIndependent; ///< PSD method dependent/Independent 3017 IN UINT32 CfgAcpiPstatesPsdPolicy; ///< PSD policy 3018 IN AP_MTRR_SETTINGS *CfgApMtrrSettingsList; ///< The AP's MTRR settings before final halt 3019 ///< Build-time customizable only - @BldCfgItem{BLDCFG_AP_MTRR_SETTINGS_LIST} 3020 IN UMA_VERSION CfgUmaVersion; ///< Uma Version 3021 IN UMA_MODE CfgUmaMode; ///< Uma Mode 3022 IN UINT32 CfgUmaSize; ///< Uma Size [31:0]=Addr[47:16] 3023 IN BOOLEAN CfgUmaAbove4G; ///< Uma Above 4G Support 3024 IN UMA_ALIGNMENT CfgUmaAlignment; ///< Uma alignment 3025 IN BOOLEAN CfgProcessorScopeInSb; ///< ACPI Processor Object in \\_SB scope 3026 IN CHAR8 CfgProcessorScopeName0; ///< OEM specific 1st character of processor scope name. 3027 IN CHAR8 CfgProcessorScopeName1; ///< OEM specific 2nd character of processor scope name. 3028 IN UINT8 CfgGnbHdAudio; ///< GNB HD Audio 3029 IN UINT8 CfgAbmSupport; ///< Abm Support 3030 IN UINT8 CfgDynamicRefreshRate; ///< DRR Dynamic Refresh Rate 3031 IN UINT16 CfgLcdBackLightControl; ///< LCD Backlight Control 3032 IN UINT8 CfgGnb3dStereoPinIndex; ///< 3D Stereo Pin ID. 3033 IN UINT32 CfgTempPcieMmioBaseAddress; ///< Temp pcie MMIO base Address 3034 ///< Build-time customizable only - @BldCfgItem{BLDCFG_TEMP_PCIE_MMIO_BASE_ADDRESS} 3035 IN UINT32 CfgGnbIGPUSSID; ///< Gnb internal GPU SSID 3036 ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGPU_SUBSYSTEM_ID} 3037 IN UINT32 CfgGnbHDAudioSSID; ///< Gnb HD Audio SSID 3038 ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID} 3039 IN UINT32 CfgGnbPcieSSID; ///< Gnb PCIe SSID 3040 ///< Build-time customizable only - @BldCfgItem{BLDCFG_APU_PCIE_PORTS_SUBSYSTEM_ID} 3041 IN UINT16 CfgLvdsSpreadSpectrum; ///< Lvds Spread Spectrum 3042 ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM} 3043 IN UINT16 CfgLvdsSpreadSpectrumRate; ///< Lvds Spread Spectrum Rate 3044 ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE} 3045 IN CONST FCH_PLATFORM_POLICY *FchBldCfg; ///< FCH platform build configuration policy 3046 3047 IN BOOLEAN CfgIommuSupport; ///< IOMMU support 3048 IN UINT8 CfgLvdsPowerOnSeqDigonToDe; ///< Panel initialization timing 3049 IN UINT8 CfgLvdsPowerOnSeqDeToVaryBl; ///< Panel initialization timing 3050 IN UINT8 CfgLvdsPowerOnSeqDeToDigon; ///< Panel initialization timing 3051 IN UINT8 CfgLvdsPowerOnSeqVaryBlToDe; ///< Panel initialization timing 3052 IN UINT8 CfgLvdsPowerOnSeqOnToOffDelay; ///< Panel initialization timing 3053 IN UINT8 CfgLvdsPowerOnSeqVaryBlToBlon; ///< Panel initialization timing 3054 IN UINT8 CfgLvdsPowerOnSeqBlonToVaryBl; ///< Panel initialization timing 3055 IN UINT16 CfgLvdsMaxPixelClockFreq; ///< The maximum pixel clock frequency supported 3056 IN UINT32 CfgLcdBitDepthControlValue; ///< The LCD bit depth control settings 3057 IN UINT8 CfgLvds24bbpPanelMode; ///< The LVDS 24 BBP mode 3058 IN LVDS_MISC_CONTROL CfgLvdsMiscControl; ///< THe LVDS Misc control 3059 IN UINT16 CfgPcieRefClkSpreadSpectrum; ///< PCIe Reference Clock Spread Spectrum 3060 ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM} 3061 IN BOOLEAN CfgExternalVrefCtlFeature; ///< External Vref control 3062 IN FORCE_TRAIN_MODE CfgForceTrainMode; ///< Force Train Mode 3063 IN BOOLEAN CfgGnbRemoteDisplaySupport; ///< Wireless Display Support 3064 IN IOMMU_EXCLUSION_RANGE_DESCRIPTOR *CfgIvrsExclusionRangeList; 3065 IN BOOLEAN CfgGnbSyncFloodPinAsNmi; ///< @ref BLDCFG_USE_SYNCFLOOD_AS_NMI "BLDCFG_USE_SYNCFLOOD_AS_NMI" 3066 IN UINT8 CfgIgpuEnableDisablePolicy; ///< This item defines the iGPU Enable/Disable policy 3067 ///< @li 0 = Auto - use current default 3068 ///< @li 2 = Disable iGPU if ANY PCI or PCIe Graphics card is present 3069 ///< @BldCfgItem{BLDCFG_IGPU_ENABLE_DISABLE_POLICY} 3070 IN UINT8 CfgGnbSwTjOffset; ///< Software-writeable TjOffset to account for changes in junction temperature 3071 ///< Build-time customizable only - @BldCfgItem{BLDCFG_GNB_THERMAL_SENSOR_CORRECTION} 3072 IN UINT8 CfgLvdsMiscVoltAdjustment; ///< Register LVDS_CTRL_4 to adjust LVDS output voltage 3073 ///< Build-time customizable only - @BldCfgItem{BLDCFG_LVDS_MISC_VOL_ADJUSTMENT} 3074 IN DISPLAY_MISC_CONTROL CfgDisplayMiscControl; ///< The Display Misc control 3075 IN DP_FIXED_VOLT_SWING_TYPE CfgDpFixedVoltSwingType;///< To indicate fixed voltage swing value 3076 ///< @BldCfgItem{BLDCFG_DP_FIXED_VOLT_SWING} 3077 IN TECHNOLOGY_TYPE CfgDimmTypeUsedInMixedConfig; ///< Select the preferred technology type that AGESA will enable 3078 ///< when it is mixed with other technology types. 3079 IN BOOLEAN CfgDimmTypeDdr4Capable; ///< Select DDR4 as technology type that AGESA will enable 3080 ///< @BldCfgItem{BLDCFG_DIMM_TYPE_DDR4_CAPABLE} 3081 IN BOOLEAN CfgDimmTypeDdr3Capable; ///< Select DDR3 as technology type that AGESA will enable 3082 ///< @BldCfgItem{BLDCFG_DIMM_TYPE_DDR3_CAPABLE} 3083 IN BOOLEAN CfgHybridBoostEnable; ///< HyBrid Boost support 3084 ///< @BldCfgItem{BLDCFG_HYBRID_BOOST_ENABLE} 3085 IN UINT64 CfgGnbIoapicAddress; ///< GNB IOAPIC Base Address(NULL if platform configured) 3086 ///< @BldCfgItem{BLDCFG_GNB_IOAPIC_ADDRESS} 3087 IN BOOLEAN CfgDataEyeEn; ///< Enable get 2D Data Eye 3088 IN UINT32 CfgBatteryBoostTune; ///< @BldCfgItem{BLDCFG_BATTERY_BOOST_TUNE} 3089 IN BOOLEAN CfgDramDoubleRefreshRateEn; ///< Double DRAM refresh rate 3090 IN DISPLAY_RESOLUTION CfgGnbResolution; ///< Display Resolution 3091 ///< @BldCfgItem{BLDCFG_RESOLUTION} 3092 IN ACP_SIZE CfgGnbAcpSize; ///< ACP size [31:0]=Addr[47:16] 3093 ///< @BldCfgItem{BLDCFG_ACP_SIZE} 3094 IN PMU_TRAIN_MODE CfgPmuTrainMode; ///< Force Train Mode 3095 ///< @BldCfgItem{BLDCFG_PMU_TRAINING_MODE} 3096 IN UINT8 CfgMemoryPhyVoltage; ///< Memory Phy voltage (VDDR) 3097 ///< @BldCfgItem{BLDCFG_MEMORY_PHY_VOLTAGE} 3098 IN UINT32 CfgGpuFrequencyLimit; ///< @BldCfgItem{BLDCFG_GPU_FREQUENCY_LIMIT} 3099 IN UINT8 CfgMaxNumAudioEndpoints; ///< @BldCfgItem{BLDCFG_MAX_NUM_AUDIO_ENDPOINTS} 3100 IN BOOLEAN CfgBapmEnable; ///< @BldCfgItem{BLDCFG_BAPM_ENABLE} 3101 IN UINT32 CfgGnbAzI2sBusSelect; ///< Acp AZ/I2sBus select 3102 ///< @BldCfgItem{BLDCFG_GNB_AZ_I2SBUS_SELECT} 3103 IN UINT32 CfgGnbAzI2sBusPinConfig; ///< Acp AZ/I2sBus pin configuration 3104 ///< @BldCfgItem{BLDCFG_GNB_AZ_I2SBUS_PIN_CONFIG} 3105 IN UINT32 CfgPkgPwrLimitAC; ///< Package Power Limit under AC 3106 ///< @BldCfgItem{BLDCFG_PPT_LIMIT_AC} 3107 IN UINT32 CfgPkgPwrLimitDC; ///< Package Power Limit under DC 3108 ///< @BldCfgItem{BLDCFG_PPT_LIMIT_DC} 3109 IN UINT32 CfgSystemConfiguration; ///< SMU System Configuration 3110 ///< @BldCfgItem{BLDCFG_SYSTEM_CONFIGURATION} 3111 IN PLATFORM_STAPM_CONFIGURATION CfgPlatStapmConfig; ///< Several configuration settings for the STAPM. 3112 IN UINT8 CfgEDPv1_4VSMode; ///< @BldCfgItem{BLDCFG_EDP_V1_4_VS_MODE} 3113 IN UINT8 CfgExtHDMIReDrvSlvAddr; ///< @BldCfgItem{BLDCFG_EXT_HDMI_RE_DRIVE_SLAVE_ADDR} 3114 IN UINT8 CfgExtHDMIReDrvRegNum; ///< @BldCfgItem{BLDCFG_EXT_HDMI_RE_DRIVE_REG_NUM} 3115 IN UINT64 CfgExtHDMIRegSetting; ///< @BldCfgItem{BLDCFG_EXT_HDMI_RE_DRIVE_REG_INFO} 3116 IN UINT8 CfgDP0ExtHDMIReDrvSlvAddr; ///< @BldCfgItem{BLDCFG_DP0_EXT_HDMI_RE_DRIVE_SLAVE_ADDR} 3117 IN UINT8 CfgDP0ExtHDMIReDrvRegNum; ///< @BldCfgItem{BLDCFG_DP0_EXT_HDMI_RE_DRIVE_REG_NUM} 3118 IN UINT64 CfgDP0ExtHDMIRegSetting; ///< @BldCfgItem{BLDCFG_DP0_EXT_HDMI_RE_DRIVE_REG_INFO} 3119 IN UINT8 CfgDP1ExtHDMIReDrvSlvAddr; ///< @BldCfgItem{BLDCFG_DP1_EXT_HDMI_RE_DRIVE_SLAVE_ADDR} 3120 IN UINT8 CfgDP1ExtHDMIReDrvRegNum; ///< @BldCfgItem{BLDCFG_DP1_EXT_HDMI_RE_DRIVE_REG_NUM} 3121 IN UINT64 CfgDP1ExtHDMIRegSetting; ///< @BldCfgItem{BLDCFG_DP1_EXT_HDMI_RE_DRIVE_REG_INFO} 3122 IN UINT8 CfgDP2ExtHDMIReDrvSlvAddr; ///< @BldCfgItem{BLDCFG_DP2_EXT_HDMI_RE_DRIVE_SLAVE_ADDR} 3123 IN UINT8 CfgDP2ExtHDMIReDrvRegNum; ///< @BldCfgItem{BLDCFG_DP2_EXT_HDMI_RE_DRIVE_REG_NUM} 3124 IN UINT64 CfgDP2ExtHDMIRegSetting; ///< @BldCfgItem{BLDCFG_DP2_EXT_HDMI_RE_DRIVE_REG_INFO} 3125 IN UINT8 CfgDP0ExtHDMI6GRegNum; ///< @BldCfgItem{BLDCFG_DP0_EXT_HDMI_6G_REG_NUM} 3126 IN UINT64 CfgDP0ExtHDMI6GhzRegSetting; ///< @BldCfgItem{BLDCFG_DP0_EXT_HDMI_6Ghz_REG_INFO} 3127 IN UINT8 CfgDP1ExtHDMI6GRegNum; ///< @BldCfgItem{BLDCFG_DP1_EXT_HDMI_6G_REG_NUM} 3128 IN UINT64 CfgDP1ExtHDMI6GhzRegSetting; ///< @BldCfgItem{BLDCFG_DP1_EXT_HDMI_6Ghz_REG_INFO} 3129 IN UINT8 CfgDP2ExtHDMI6GRegNum; ///< @BldCfgItem{BLDCFG_DP2_EXT_HDMI_6G_REG_NUM} 3130 IN UINT64 CfgDP2ExtHDMI6GhzRegSetting; ///< @BldCfgItem{BLDCFG_DP2_EXT_HDMI_6Ghz_REG_INFO} 3131 IN UINT32 CfgThermCtlLimit; ///< @BldCfgItem{BLDCFG_THERMCTL_LIMIT} 3132 IN UINT64 CfgCodecVerbTable; ///< @BldCfgItem{BLDCFG_CODEC_VERB_TABLE} 3133 IN UINT32 CfgGnbAzSsid; ///< @BldCfgItem{BLDCFG_GNB_AZ_SSID} 3134 IN UINT16 CfgCustomVddioVoltage; ///< Custom VDDIO voltage 3135 ///< @BldCfgItem{BLDCFG_CUSTOM_VDDIO_VOLTAGE} 3136 IN BOOLEAN CfgAcpPowerGating; ///< @BldCfgItem{BLDCFG_ACP_POWER_GATING} 3137 IN BOOLEAN CfgSmuOverclocking; ///< @BldCfgItem{BLDCFG_SMU_OVERCLOCKING} 3138 IN BOOLEAN CfgSmuCPUIdleActivityMonitorEnable; ///< @BldCfgItem{BLDCFG_CPU_IDLE_ACTIVITY_MONITOR} 3139 IN UINT16 CfgBootUpDisplayDevice; ///< @BldCfgItem{BLDCFG_CFG_BOOT_UP_DISPLAY_DEVICE} 3140 IN BOOLEAN Reserved; ///< reserved... 3141 } BUILD_OPT_CFG; 3142 3143 /// A structure containing platform specific operational characteristics. This 3144 /// structure is initially populated by the initializer with a copy of the same 3145 /// structure that was created at build time using the build configuration controls. 3146 typedef struct _PLATFORM_CONFIGURATION { 3147 IN PERFORMANCE_PROFILE PlatformProfile; ///< Several configuration settings for the processor. 3148 IN UINT8 CoreLevelingMode; ///< Indicates how to balance the number of cores per processor. 3149 ///< @BldCfgItem{BLDCFG_CORE_LEVELING_MODE} 3150 IN PLATFORM_CSTATE_MODES CStateMode; ///< Specifies the method of C-State enablement - Disabled, or C6. 3151 ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_MODE} 3152 IN UINT32 CStatePlatformData; ///< This element specifies some pertinent data needed for the operation of the Cstate feature 3153 ///< If CStateMode is CStateModeC6, this item is reserved 3154 ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_OPDATA} 3155 IN UINT16 CStateIoBaseAddress; ///< This item specifies a free block of 8 consecutive bytes of I/O ports that 3156 ///< can be used to allow the CPU to enter Cstates. 3157 ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS} 3158 IN PLATFORM_CPB_MODES CpbMode; ///< Specifies the method of core performance boost enablement - Disabled, or Auto. 3159 ///< @BldCfgItem{BLDCFG_PLATFORM_CPB_MODE} 3160 IN BOOLEAN UserOptionDmi; ///< When set to TRUE, the DMI data table is generated. 3161 IN BOOLEAN UserOptionPState; ///< When set to TRUE, the PState data tables are generated. 3162 IN BOOLEAN UserOptionCrat; ///< When set to TRUE, the CRAT data table is generated. 3163 IN BOOLEAN UserOptionCdit; ///< When set to TRUE, the CDIT data table is generated. 3164 IN BOOLEAN UserOptionWhea; ///< When set to TRUE, the WHEA data table is generated. 3165 IN UINT32 PowerCeiling; ///< P-State Ceiling Enabling Deck - Max power milli-watts. 3166 IN BOOLEAN ForcePstateIndependent; ///< Deprecated in favor of PstatesPsdPolicy. 3167 ///< P-State _PSD is forced independent. 3168 ///< @BldCfgItem{BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT} 3169 IN UINT32 PstatesPsdPolicy; ///< PSD policy 3170 ///< @BldCfgItem{BLDCFG_ACPI_PSTATES_PSD_POLICY} 3171 IN UINT32 CpuFrequencyLimit; ///< @BldCfgItem{BLDCFG_CPU_FREQUENCY_LIMIT} 3172 IN PLATFORM_CONNECTED_STANDBY_MODES CfgPlatformConnectedStandbyMode; ///< @BldCfgItem{BLDCFG_CPU_CONNECTED_STANDBY_MODE} 3173 IN UINT32 NumberOfIoApics; ///< Number of I/O APICs in the system 3174 ///< @BldCfgItem{BLDCFG_PLATFORM_NUM_IO_APICS} 3175 IN PLATFORM_VRM_CONFIGURATION VrmProperties[MaxVrmType]; ///< Several configuration settings for the voltage regulator modules. 3176 IN BOOLEAN ProcessorScopeInSb; ///< ACPI Processor Object in \\_SB scope 3177 ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_IN_SB} 3178 IN CHAR8 ProcessorScopeName0; ///< OEM specific 1st character of processor scope name. 3179 ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_NAME0} 3180 IN CHAR8 ProcessorScopeName1; ///< OEM specific 2nd character of processor scope name. 3181 ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_NAME1} 3182 IN UINT8 GnbHdAudio; ///< Control GFX HD Audio controller(Used for HDMI and DP display output), 3183 ///< essentially it enables function 1 of graphics device. 3184 ///< @li 0 = HD Audio disable 3185 ///< @li 1 = HD Audio enable 3186 ///< @BldCfgItem{BLDCFG_CFG_GNB_HD_AUDIO} 3187 IN UINT8 AbmSupport; ///< Automatic adjust LVDS/eDP Back light level support.It is 3188 ///< characteristic specific to display panel which used by platform design. 3189 ///< @li 0 = ABM support disabled 3190 ///< @li 1 = ABM support enabled 3191 ///< @BldCfgItem{BLDCFG_CFG_ABM_SUPPORT} 3192 IN UINT8 DynamicRefreshRate; ///< Adjust refresh rate on LVDS/eDP. 3193 ///< @BldCfgItem{BLDCFG_CFG_DYNAMIC_REFRESH_RATE} 3194 IN UINT16 LcdBackLightControl; ///< The PWM frequency to LCD backlight control. 3195 ///< If equal to 0 backlight not controlled by iGPU 3196 ///< @BldCfgItem{BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL} 3197 IN UINT16 HtcTemperatureLimit; ///< The Hardware Thermal Control temperature limit in tenths of degrees Celsius. 3198 ///< If equal to 0, use hardware defaults. 3199 ///< @BldCfgItem{BLDCFG_HTC_TEMPERATURE_LIMIT} 3200 IN UINT16 LhtcTemperatureLimit; ///< The Local Hardware Thermal Control temperature limit in tenths of degrees Celsius. 3201 ///< If equal to 0, use hardware defaults. 3202 ///< @BldCfgItem{BLDCFG_LHTC_TEMPERATURE_LIMIT} 3203 IN DISPLAY_RESOLUTION Resolution; ///< Display Resolution 3204 ///< @BldCfgItem{BLDCFG_RESOLUTION} 3205 IN ACP_SIZE AcpSize; ///< The size of ACP dram 3206 ///< ACP_Size[31:0]=Addr[47:16] 3207 ///< @BldCfgItem{BLDCFG_ACP_SIZE} 3208 IN UINT32 BatteryBoostTune; ///< @BldCfgItem{BLDCFG_BATTERY_BOOST_TUNE} 3209 IN UINT32 PkgPwrLimitAC; ///< Package Power Limit under AC 3210 ///< @BldCfgItem{BLDCFG_PPT_LIMIT_AC} 3211 IN UINT32 PkgPwrLimitDC; ///< Package Power Limit under DC 3212 ///< @BldCfgItem{BLDCFG_PPT_LIMIT_DC} 3213 IN UINT32 SystemConfiguration; ///< SMU System Configuration 3214 ///< @BldCfgItem{BLDCFG_SYSTEM_CONFIGURATION} 3215 IN PLATFORM_STAPM_CONFIGURATION PlatStapmConfig; ///< Several configuration settings for the STAPM. 3216 IN UINT32 ThermCtlLimit; ///< @BldCfgItem{BLDCFG_THERMCTL_LIMIT} 3217 IN UINT64 AzaliaCodecVerbTable; ///< @BldCfgItem{BLDCFG_CODEC_VERB_TABLE} 3218 IN UINT32 AzaliaSsid; ///< @BldCfgItem{BLDCFG_GNB_AZ_SSID} 3219 IN UINT32 GnbAzI2sBusSelect; ///< @BldCfgItem{BLDCFG_GNB_AZ_I2SBUS_SELECT} 3220 IN UINT32 GnbAzI2sBusPinConfig; ///< @BldCfgItem{BLDCFG_GNB_AZ_I2SBUS_PIN_CONFIG} 3221 IN BOOLEAN AcpPowerGating; ///< @BldCfgItem{BLDCFG_ACP_POWER_GATING} 3222 IN BOOLEAN SmuOverclocking; ///< @BldCfgItem{BLDCFG_SMU_OVERCLOCKING} 3223 IN BOOLEAN SmuCPUIdleActivityMonitorEnable; ///< @BldCfgItem{BLDCFG_CPU_IDLE_ACTIVITY_MONITOR} 3224 IN UINT16 BootUpDisplayDevice; ///< The boot up display device selected. 3225 ///< If equal to 0 default setting in VBIOS for boot up display devices 3226 ///< @BldCfgItem{BLDCFG_CFG_BOOT_UP_DISPLAY_DEVICE} 3227 } PLATFORM_CONFIGURATION; 3228 3229 3230 /********************************************************************** 3231 * Structures for: AmdInitLate 3232 **********************************************************************/ 3233 #define PROC_VERSION_LENGTH 48 3234 #define MAX_DIMMS_PER_SOCKET 16 3235 #define PROC_MANU_LENGTH 29 3236 3237 /* Interface Parameter Structures */ 3238 /// DMI Type4 - Processor ID 3239 typedef struct { 3240 OUT UINT32 ProcIdLsd; ///< Lower half of 64b ID 3241 OUT UINT32 ProcIdMsd; ///< Upper half of 64b ID 3242 } TYPE4_PROC_ID; 3243 3244 /// DMI Type 4 - Processor information 3245 typedef struct { 3246 OUT UINT8 T4ProcType; ///< CPU Type 3247 OUT UINT8 T4ProcFamily; ///< Family 1 3248 OUT TYPE4_PROC_ID T4ProcId; ///< Id 3249 OUT UINT8 T4Voltage; ///< Voltage 3250 OUT UINT16 T4ExternalClock; ///< External clock 3251 OUT UINT16 T4MaxSpeed; ///< Max speed 3252 OUT UINT16 T4CurrentSpeed; ///< Current speed 3253 OUT UINT8 T4Status; ///< Status 3254 OUT UINT8 T4ProcUpgrade; ///< Up grade 3255 OUT UINT8 T4CoreCount; ///< Core count 3256 OUT UINT8 T4CoreEnabled; ///< Core Enable 3257 OUT UINT8 T4ThreadCount; ///< Thread count 3258 OUT UINT16 T4ProcCharacteristics; ///< Characteristics 3259 OUT UINT16 T4ProcFamily2; ///< Family 2 3260 OUT CHAR8 T4ProcVersion[PROC_VERSION_LENGTH]; ///< Cpu version 3261 OUT CHAR8 T4ProcManufacturer[PROC_MANU_LENGTH]; ///< Manufacturer 3262 OUT UINT16 T4CoreCount2; ///< Core count 2 3263 OUT UINT16 T4CoreEnabled2; ///< Core Enable 2 3264 OUT UINT16 T4ThreadCount2; ///< Thread count 2 3265 3266 } TYPE4_DMI_INFO; 3267 3268 /// DMI Type 7 - Cache information 3269 typedef struct _TYPE7_DMI_INFO { 3270 OUT UINT16 T7CacheCfg; ///< Cache cfg 3271 OUT UINT16 T7MaxCacheSize; ///< Max size 3272 OUT UINT16 T7InstallSize; ///< Install size 3273 OUT UINT16 T7SupportedSramType; ///< Supported Sram Type 3274 OUT UINT16 T7CurrentSramType; ///< Current type 3275 OUT UINT8 T7CacheSpeed; ///< Speed 3276 OUT UINT8 T7ErrorCorrectionType; ///< ECC type 3277 OUT UINT8 T7SystemCacheType; ///< Cache type 3278 OUT UINT8 T7Associativity; ///< Associativity 3279 } TYPE7_DMI_INFO; 3280 3281 /// DMI Type 16 offset 04h - Location 3282 typedef enum { 3283 OtherLocation = 0x01, ///< Assign 01 to Other 3284 UnknownLocation, ///< Assign 02 to Unknown 3285 SystemboardOrMotherboard, ///< Assign 03 to systemboard or motherboard 3286 IsaAddonCard, ///< Assign 04 to ISA add-on card 3287 EisaAddonCard, ///< Assign 05 to EISA add-on card 3288 PciAddonCard, ///< Assign 06 to PCI add-on card 3289 McaAddonCard, ///< Assign 07 to MCA add-on card 3290 PcmciaAddonCard, ///< Assign 08 to PCMCIA add-on card 3291 ProprietaryAddonCard, ///< Assign 09 to proprietary add-on card 3292 NuBus, ///< Assign 0A to NuBus 3293 Pc98C20AddonCard, ///< Assign 0A0 to PC-98/C20 add-on card 3294 Pc98C24AddonCard, ///< Assign 0A1 to PC-98/C24 add-on card 3295 Pc98EAddoncard, ///< Assign 0A2 to PC-98/E add-on card 3296 Pc98LocalBusAddonCard ///< Assign 0A3 to PC-98/Local bus add-on card 3297 } DMI_T16_LOCATION; 3298 3299 /// DMI Type 16 offset 05h - Memory Error Correction 3300 typedef enum { 3301 OtherUse = 0x01, ///< Assign 01 to Other 3302 UnknownUse, ///< Assign 02 to Unknown 3303 SystemMemory, ///< Assign 03 to system memory 3304 VideoMemory, ///< Assign 04 to video memory 3305 FlashMemory, ///< Assign 05 to flash memory 3306 NonvolatileRam, ///< Assign 06 to non-volatile RAM 3307 CacheMemory ///< Assign 07 to cache memory 3308 } DMI_T16_USE; 3309 3310 /// DMI Type 16 offset 07h - Maximum Capacity 3311 typedef enum { 3312 Dmi16OtherErrCorrection = 0x01, ///< Assign 01 to Other 3313 Dmi16UnknownErrCorrection, ///< Assign 02 to Unknown 3314 Dmi16NoneErrCorrection, ///< Assign 03 to None 3315 Dmi16Parity, ///< Assign 04 to parity 3316 Dmi16SingleBitEcc, ///< Assign 05 to Single-bit ECC 3317 Dmi16MultiBitEcc, ///< Assign 06 to Multi-bit ECC 3318 Dmi16Crc ///< Assign 07 to CRC 3319 } DMI_T16_ERROR_CORRECTION; 3320 3321 /// DMI Type 16 - Physical Memory Array 3322 typedef struct { 3323 OUT DMI_T16_LOCATION Location; ///< The physical location of the Memory Array, 3324 ///< whether on the system board or an add-in board. 3325 OUT DMI_T16_USE Use; ///< Identifies the function for which the array 3326 ///< is used. 3327 OUT DMI_T16_ERROR_CORRECTION MemoryErrorCorrection; ///< The primary hardware error correction or 3328 ///< detection method supported by this memory array. 3329 OUT UINT16 NumberOfMemoryDevices; ///< The number of slots or sockets available 3330 ///< for memory devices in this array. 3331 } TYPE16_DMI_INFO; 3332 3333 /// DMI Type 17 offset 0Eh - Form Factor 3334 typedef enum { 3335 OtherFormFactor = 0x01, ///< Assign 01 to Other 3336 UnknowFormFactor, ///< Assign 02 to Unknown 3337 SimmFormFactor, ///< Assign 03 to SIMM 3338 SipFormFactor, ///< Assign 04 to SIP 3339 ChipFormFactor, ///< Assign 05 to Chip 3340 DipFormFactor, ///< Assign 06 to DIP 3341 ZipFormFactor, ///< Assign 07 to ZIP 3342 ProprietaryCardFormFactor, ///< Assign 08 to Proprietary Card 3343 DimmFormFactorFormFactor, ///< Assign 09 to DIMM 3344 TsopFormFactor, ///< Assign 10 to TSOP 3345 RowOfChipsFormFactor, ///< Assign 11 to Row of chips 3346 RimmFormFactor, ///< Assign 12 to RIMM 3347 SodimmFormFactor, ///< Assign 13 to SODIMM 3348 SrimmFormFactor, ///< Assign 14 to SRIMM 3349 FbDimmFormFactor ///< Assign 15 to FB-DIMM 3350 } DMI_T17_FORM_FACTOR; 3351 3352 /// DMI Type 17 offset 12h - Memory Type 3353 typedef enum { 3354 OtherMemType = 0x01, ///< Assign 01 to Other 3355 UnknownMemType, ///< Assign 02 to Unknown 3356 DramMemType, ///< Assign 03 to DRAM 3357 EdramMemType, ///< Assign 04 to EDRAM 3358 VramMemType, ///< Assign 05 to VRAM 3359 SramMemType, ///< Assign 06 to SRAM 3360 RamMemType, ///< Assign 07 to RAM 3361 RomMemType, ///< Assign 08 to ROM 3362 FlashMemType, ///< Assign 09 to Flash 3363 EepromMemType, ///< Assign 10 to EEPROM 3364 FepromMemType, ///< Assign 11 to FEPROM 3365 EpromMemType, ///< Assign 12 to EPROM 3366 CdramMemType, ///< Assign 13 to CDRAM 3367 ThreeDramMemType, ///< Assign 14 to 3DRAM 3368 SdramMemType, ///< Assign 15 to SDRAM 3369 SgramMemType, ///< Assign 16 to SGRAM 3370 RdramMemType, ///< Assign 17 to RDRAM 3371 DdrMemType, ///< Assign 18 to DDR 3372 Ddr2MemType, ///< Assign 19 to DDR2 3373 Ddr2FbdimmMemType, ///< Assign 20 to DDR2 FB-DIMM 3374 Ddr3MemType = 0x18, ///< Assign 24 to DDR3 3375 Fbd2MemType, ///< Assign 25 to FBD2 3376 Ddr4MemType, ///< Assign 26 to DDR4 3377 LpDdrMemType, ///< Assign 27 to LPDDR 3378 LpDdr2MemType, ///< Assign 28 to LPDDR2 3379 LpDdr3MemType, ///< Assign 29 to LPDDR3 3380 LpDdr4MemType, ///< Assign 30 to LPDDR4 3381 } DMI_T17_MEMORY_TYPE; 3382 3383 /// DMI Type 17 offset 13h - Type Detail 3384 typedef struct { 3385 OUT UINT16 Reserved1:1; ///< Reserved 3386 OUT UINT16 Other:1; ///< Other 3387 OUT UINT16 Unknown:1; ///< Unknown 3388 OUT UINT16 FastPaged:1; ///< Fast-Paged 3389 OUT UINT16 StaticColumn:1; ///< Static column 3390 OUT UINT16 PseudoStatic:1; ///< Pseudo-static 3391 OUT UINT16 Rambus:1; ///< RAMBUS 3392 OUT UINT16 Synchronous:1; ///< Synchronous 3393 OUT UINT16 Cmos:1; ///< CMOS 3394 OUT UINT16 Edo:1; ///< EDO 3395 OUT UINT16 WindowDram:1; ///< Window DRAM 3396 OUT UINT16 CacheDram:1; ///< Cache Dram 3397 OUT UINT16 NonVolatile:1; ///< Non-volatile 3398 OUT UINT16 Registered:1; ///< Registered (Buffered) 3399 OUT UINT16 Unbuffered:1; ///< Unbuffered (Unregistered) 3400 OUT UINT16 LRDIMM:1; ///< LRDIMM 3401 } DMI_T17_TYPE_DETAIL; 3402 3403 /// DMI Type 17 - Memory Device 3404 typedef struct { 3405 OUT UINT16 Handle; ///< The temporary handle, or instance number, associated with the structure 3406 OUT UINT16 TotalWidth; ///< Total Width, in bits, of this memory device, including any check or error-correction bits. 3407 OUT UINT16 DataWidth; ///< Data Width, in bits, of this memory device. 3408 OUT UINT16 MemorySize; ///< The size of the memory device. 3409 OUT DMI_T17_FORM_FACTOR FormFactor; ///< The implementation form factor for this memory device. 3410 OUT UINT8 DeviceSet; ///< Identifies when the Memory Device is one of a set of 3411 ///< Memory Devices that must be populated with all devices of 3412 ///< the same type and size, and the set to which this device belongs. 3413 OUT CHAR8 DeviceLocator[8]; ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located. 3414 OUT CHAR8 BankLocator[10]; ///< The string number of the string that identifies the physically labeled bank where the memory device is located. 3415 OUT DMI_T17_MEMORY_TYPE MemoryType; ///< The type of memory used in this device. 3416 OUT DMI_T17_TYPE_DETAIL TypeDetail; ///< Additional detail on the memory device type 3417 OUT UINT16 Speed; ///< Identifies the speed of the device, in megahertz (MHz). 3418 OUT UINT64 ManufacturerIdCode; ///< Manufacturer ID code. 3419 OUT CHAR8 SerialNumber[9]; ///< Serial Number. 3420 OUT CHAR8 PartNumber[21]; ///< Part Number. 3421 OUT UINT8 Attributes; ///< Bits 7-4: Reserved, Bits 3-0: rank. 3422 OUT UINT32 ExtSize; ///< Extended Size. 3423 OUT UINT16 ConfigSpeed; ///< Configured memory clock speed 3424 OUT UINT16 MinimumVoltage; ///< Minimum operating voltage for this device, in millivolts 3425 OUT UINT16 MaximumVoltage; ///< Maximum operating voltage for this device, in millivolts 3426 OUT UINT16 ConfiguredVoltage; ///< Configured voltage for this device, in millivolts 3427 } TYPE17_DMI_INFO; 3428 3429 /// Memory DMI Type 17 - for memory use 3430 typedef struct { 3431 OUT UINT8 Socket:3; ///< Socket ID 3432 OUT UINT8 Channel:2; ///< Channel ID 3433 OUT UINT8 Dimm:2; ///< DIMM ID 3434 OUT UINT8 DimmPresent:1; ///< Dimm Present 3435 OUT UINT16 Handle; ///< The temporary handle, or instance number, associated with the structure 3436 OUT UINT16 TotalWidth; ///< Total Width, in bits, of this memory device, including any check or error-correction bits. 3437 OUT UINT16 DataWidth; ///< Data Width, in bits, of this memory device. 3438 OUT UINT16 MemorySize; ///< The size of the memory device. 3439 OUT DMI_T17_FORM_FACTOR FormFactor; ///< The implementation form factor for this memory device. 3440 OUT UINT8 DeviceLocator; ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located. 3441 OUT UINT8 BankLocator; ///< The string number of the string that identifies the physically labeled bank where the memory device is located. 3442 OUT UINT16 Speed; ///< Identifies the speed of the device, in megahertz (MHz). 3443 OUT UINT64 ManufacturerIdCode; ///< Manufacturer ID code. 3444 OUT UINT8 SerialNumber[4]; ///< Serial Number. 3445 OUT UINT8 PartNumber[21]; ///< Part Number. 3446 OUT UINT8 Attributes; ///< Bits 7-4: Reserved, Bits 3-0: rank. 3447 OUT UINT32 ExtSize; ///< Extended Size. 3448 OUT UINT16 ConfigSpeed; ///< Configured memory clock speed 3449 OUT UINT16 MinimumVoltage; ///< Minimum operating voltage for this device, in millivolts 3450 OUT UINT16 MaximumVoltage; ///< Maximum operating voltage for this device, in millivolts 3451 OUT UINT16 ConfiguredVoltage; ///< Configured voltage for this device, in millivolts 3452 } MEM_DMI_PHYSICAL_DIMM_INFO; 3453 3454 /// Memory DMI Type 20 - for memory use 3455 typedef struct { 3456 OUT UINT8 Socket:3; ///< Socket ID 3457 OUT UINT8 Channel:2; ///< Channel ID 3458 OUT UINT8 Dimm:2; ///< DIMM ID 3459 OUT UINT8 DimmPresent:1; ///< Dimm Present 3460 OUT BOOLEAN Interleaved; ///< Interleaved; 3461 OUT UINT32 StartingAddr; ///< The physical address, in kilobytes, of a range 3462 ///< of memory mapped to the referenced Memory Device. 3463 OUT UINT32 EndingAddr; ///< The handle, or instance number, associated with 3464 ///< the Memory Device structure to which this address 3465 ///< range is mapped. 3466 OUT UINT16 MemoryDeviceHandle; ///< The handle, or instance number, associated with 3467 ///< the Memory Device structure to which this address 3468 ///< range is mapped. 3469 OUT UINT64 ExtStartingAddr; ///< The physical address, in bytes, of a range of 3470 ///< memory mapped to the referenced Memory Device. 3471 OUT UINT64 ExtEndingAddr; ///< The physical ending address, in bytes, of the last of 3472 ///< a range of addresses mapped to the referenced Memory Device. 3473 } MEM_DMI_LOGICAL_DIMM_INFO; 3474 3475 /// DMI Type 19 - Memory Array Mapped Address 3476 typedef struct { 3477 OUT UINT32 StartingAddr; ///< The physical address, in kilobytes, 3478 ///< of a range of memory mapped to the 3479 ///< specified physical memory array. 3480 OUT UINT32 EndingAddr; ///< The physical ending address of the 3481 ///< last kilobyte of a range of addresses 3482 ///< mapped to the specified physical memory array. 3483 OUT UINT16 MemoryArrayHandle; ///< The handle, or instance number, associated 3484 ///< with the physical memory array to which this 3485 ///< address range is mapped. 3486 OUT UINT8 PartitionWidth; ///< Identifies the number of memory devices that 3487 ///< form a single row of memory for the address 3488 ///< partition defined by this structure. 3489 OUT UINT64 ExtStartingAddr; ///< The physical address, in bytes, of a range of 3490 ///< memory mapped to the specified Physical Memory Array. 3491 OUT UINT64 ExtEndingAddr; ///< The physical address, in bytes, of a range of 3492 ///< memory mapped to the specified Physical Memory Array. 3493 } TYPE19_DMI_INFO; 3494 3495 ///DMI Type 20 - Memory Device Mapped Address 3496 typedef struct { 3497 OUT UINT32 StartingAddr; ///< The physical address, in kilobytes, of a range 3498 ///< of memory mapped to the referenced Memory Device. 3499 OUT UINT32 EndingAddr; ///< The handle, or instance number, associated with 3500 ///< the Memory Device structure to which this address 3501 ///< range is mapped. 3502 OUT UINT16 MemoryDeviceHandle; ///< The handle, or instance number, associated with 3503 ///< the Memory Device structure to which this address 3504 ///< range is mapped. 3505 OUT UINT16 MemoryArrayMappedAddressHandle; ///< The handle, or instance number, associated 3506 ///< with the Memory Array Mapped Address structure to 3507 ///< which this device address range is mapped. 3508 OUT UINT8 PartitionRowPosition; ///< Identifies the position of the referenced Memory 3509 ///< Device in a row of the address partition. 3510 OUT UINT8 InterleavePosition; ///< The position of the referenced Memory Device in 3511 ///< an interleave. 3512 OUT UINT8 InterleavedDataDepth; ///< The maximum number of consecutive rows from the 3513 ///< referenced Memory Device that are accessed in a 3514 ///< single interleaved transfer. 3515 OUT UINT64 ExtStartingAddr; ///< The physical address, in bytes, of a range of 3516 ///< memory mapped to the referenced Memory Device. 3517 OUT UINT64 ExtEndingAddr; ///< The physical ending address, in bytes, of the last of 3518 ///< a range of addresses mapped to the referenced Memory Device. 3519 } TYPE20_DMI_INFO; 3520 3521 /// Collection of pointers to the DMI records 3522 typedef struct { 3523 OUT TYPE4_DMI_INFO T4[MAX_SOCKETS_SUPPORTED]; ///< Type 4 struc 3524 OUT TYPE7_DMI_INFO T7L1[MAX_SOCKETS_SUPPORTED]; ///< Type 7 struc 1 3525 OUT TYPE7_DMI_INFO T7L2[MAX_SOCKETS_SUPPORTED]; ///< Type 7 struc 2 3526 OUT TYPE7_DMI_INFO T7L3[MAX_SOCKETS_SUPPORTED]; ///< Type 7 struc 3 3527 OUT TYPE16_DMI_INFO T16; ///< Type 16 struc 3528 OUT TYPE17_DMI_INFO T17[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 17 struc 3529 OUT TYPE19_DMI_INFO T19; ///< Type 19 struc 3530 OUT TYPE20_DMI_INFO T20[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 20 struc 3531 } DMI_INFO; 3532 3533 /********************************************************************** 3534 * Interface call: AllocateExecutionCache 3535 **********************************************************************/ 3536 #define MAX_CACHE_REGIONS 3 3537 3538 /// AllocateExecutionCache sub param structure for cached memory region 3539 typedef struct { 3540 IN OUT UINT32 ExeCacheStartAddr; ///< Start address 3541 IN OUT UINT32 ExeCacheSize; ///< Size 3542 } EXECUTION_CACHE_REGION; 3543 3544 /********************************************************************** 3545 * Interface call: AmdGetAvailableExeCacheSize 3546 **********************************************************************/ 3547 /// Get available Cache remain 3548 typedef struct { 3549 IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header 3550 OUT UINT32 AvailableExeCacheSize; ///< Remain size 3551 } AMD_GET_EXE_SIZE_PARAMS; 3552 3553 AGESA_STATUS 3554 AmdGetAvailableExeCacheSize ( 3555 IN OUT AMD_GET_EXE_SIZE_PARAMS *AmdGetExeSizeParams 3556 ); 3557 3558 /// Selection type for core leveling 3559 typedef enum { 3560 CORE_LEVEL_LOWEST, ///< Level to lowest common denominator 3561 CORE_LEVEL_TWO, ///< Level to 2 cores 3562 CORE_LEVEL_POWER_OF_TWO, ///< Level to 1,2,4 or 8 3563 CORE_LEVEL_NONE, ///< Do no leveling 3564 CORE_LEVEL_COMPUTE_UNIT, ///< Level cores to one core per compute unit 3565 CORE_LEVEL_COMPUTE_UNIT_TWO, ///< Level cores to two cores per compute unit 3566 CORE_LEVEL_COMPUTE_UNIT_THREE, ///< Level cores to three cores per compute unit 3567 CORE_LEVEL_ONE, ///< Level to 1 core 3568 CORE_LEVEL_THREE, ///< Level to 3 cores 3569 CORE_LEVEL_FOUR, ///< Level to 4 cores 3570 CORE_LEVEL_FIVE, ///< Level to 5 cores 3571 CORE_LEVEL_SIX, ///< Level to 6 cores 3572 CORE_LEVEL_SEVEN, ///< Level to 7 cores 3573 CORE_LEVEL_EIGHT, ///< Level to 8 cores 3574 CORE_LEVEL_NINE, ///< Level to 9 cores 3575 CORE_LEVEL_TEN, ///< Level to 10 cores 3576 CORE_LEVEL_ELEVEN, ///< Level to 11 cores 3577 CORE_LEVEL_TWELVE, ///< Level to 12 cores 3578 CORE_LEVEL_THIRTEEN, ///< Level to 13 cores 3579 CORE_LEVEL_FOURTEEN, ///< Level to 14 cores 3580 CORE_LEVEL_FIFTEEN, ///< Level to 15 cores 3581 CoreLevelModeMax ///< Used for bounds checking 3582 } CORE_LEVELING_TYPE; 3583 3584 #ifndef IDS_CALLOUT_INIT 3585 #define IDS_CALLOUT_INIT 0x01 ///< The function data of IDS callout function of initialization. 3586 3587 #define IDS_PERF_VERSION 0x00010001ul //version number 0.1.0.1 3588 /// Time points performance function used 3589 /// N O T E: NEVER change below defination, any new TP MUST be appended to the end of this enum 3590 typedef enum { 3591 TP_BEGINPROCAMDINITEARLY = 0x100, ///< BeginProcAmdInitEarly 3592 TP_ENDPROCAMDINITEARLY = 0x101, ///< EndProcAmdInitEarly 3593 TP_BEGINAMDTOPOINITIALIZE = 0x102, ///< BeginAmdTopoInitialize 3594 TP_ENDAMDTOPOINITIALIZE = 0x103, ///< EndAmdTopoInitialize 3595 TP_BEGINGNBINITATEARLIER = 0x104, ///< BeginGnbInitAtEarlier 3596 TP_ENDGNBINITATEARLIER = 0x105, ///< EndGnbInitAtEarlier 3597 TP_BEGINAMDCPUEARLY = 0x106, ///< BeginAmdCpuEarly 3598 TP_ENDAMDCPUEARLY = 0x107, ///< EndAmdCpuEarly 3599 TP_BEGINGNBINITATEARLY = 0x108, ///< BeginGnbInitAtEarly 3600 TP_ENDGNBINITATEARLY = 0x109, ///< EndGnbInitAtEarly 3601 TP_BEGINPROCAMDINITENV = 0x10A, ///< BeginProcAmdInitEnv 3602 TP_ENDPROCAMDINITENV = 0x10B, ///< EndProcAmdInitEnv 3603 TP_BEGININITENV = 0x10C, ///< BeginInitEnv 3604 TP_ENDINITENV = 0x10D, ///< EndInitEnv 3605 TP_BEGINGNBINITATENV = 0x10E, ///< BeginGnbInitAtEnv 3606 TP_ENDGNBINITATENV = 0x10F, ///< EndGnbInitAtEnv 3607 TP_BEGINPROCAMDINITLATE = 0x110, ///< BeginProcAmdInitLate 3608 TP_ENDPROCAMDINITLATE = 0x111, ///< EndProcAmdInitLate 3609 TP_BEGINCREATSYSTEMTABLE = 0x112, ///< BeginCreatSystemTable 3610 TP_ENDCREATSYSTEMTABLE = 0x113, ///< EndCreatSystemTable 3611 TP_BEGINDISPATCHCPUFEATURESLATE = 0x114, ///< BeginDispatchCpuFeaturesLate 3612 TP_ENDDISPATCHCPUFEATURESLATE = 0x115, ///< EndDispatchCpuFeaturesLate 3613 TP_BEGINAMDCPULATE = 0x116, ///< BeginAmdCpuLate 3614 TP_ENDAMDCPULATE = 0x117, ///< EndAmdCpuLate 3615 TP_BEGINGNBINITATLATE = 0x118, ///< BeginGnbInitAtLate 3616 TP_ENDGNBINITATLATE = 0x119, ///< EndGnbInitAtLate 3617 TP_BEGINPROCAMDINITMID = 0x11A, ///< BeginProcAmdInitMid 3618 TP_ENDPROCAMDINITMID = 0x11B, ///< EndProcAmdInitMid 3619 TP_BEGININITMID = 0x11E, ///< BeginInitMid 3620 TP_ENDINITMID = 0x11F, ///< EndInitMid 3621 TP_BEGINGNBINITATMID = 0x120, ///< BeginGnbInitAtMid 3622 TP_ENDGNBINITATMID = 0x121, ///< EndGnbInitAtMid 3623 TP_BEGINPROCAMDINITPOST = 0x122, ///< BeginProcAmdInitPost 3624 TP_ENDPROCAMDINITPOST = 0x123, ///< EndProcAmdInitPost 3625 TP_BEGINGNBINITATPOST = 0x124, ///< BeginGnbInitAtPost 3626 TP_ENDGNBINITATPOST = 0x125, ///< EndGnbInitAtPost 3627 TP_BEGINAMDMEMAUTO = 0x126, ///< BeginAmdMemAuto 3628 TP_ENDAMDMEMAUTO = 0x127, ///< EndAmdMemAuto 3629 TP_BEGINAMDCPUPOST = 0x128, ///< BeginAmdCpuPost 3630 TP_ENDAMDCPUPOST = 0x129, ///< EndAmdCpuPost 3631 TP_BEGINGNBINITATPOSTAFTERDRAM = 0x12A, ///< BeginGnbInitAtPostAfterDram 3632 TP_ENDGNBINITATPOSTAFTERDRAM = 0x12B, ///< EndGnbInitAtPostAfterDram 3633 TP_BEGINPROCAMDINITRESET = 0x12C, ///< BeginProcAmdInitReset 3634 TP_ENDPROCAMDINITRESET = 0x12D, ///< EndProcAmdInitReset 3635 TP_BEGININITRESET = 0x12E, ///< BeginInitReset 3636 TP_ENDINITRESET = 0x12F, ///< EndInitReset 3637 TP_BEGINHTINITRESET = 0x130, ///< BeginHtInitReset 3638 TP_ENDHTINITRESET = 0x131, ///< EndHtInitReset 3639 TP_BEGINPROCAMDINITRESUME = 0x132, ///< BeginProcAmdInitResume 3640 TP_ENDPROCAMDINITRESUME = 0x133, ///< EndProcAmdInitResume 3641 TP_BEGINAMDMEMS3RESUME = 0x134, ///< BeginAmdMemS3Resume 3642 TP_ENDAMDMEMS3RESUME = 0x135, ///< EndAmdMemS3Resume 3643 TP_BEGINDISPATCHCPUFEATURESS3RESUME = 0x136, ///< BeginDispatchCpuFeaturesS3Resume 3644 TP_ENDDISPATCHCPUFEATURESS3RESUME = 0x137, ///< EndDispatchCpuFeaturesS3Resume 3645 TP_BEGINSETCORESTSCFREQSEL = 0x138, ///< BeginSetCoresTscFreqSel 3646 TP_ENDSETCORESTSCFREQSEL = 0x139, ///< EndSetCoresTscFreqSel 3647 TP_BEGINMEMFMCTMEMCLR_INIT = 0x13A, ///< BeginMemFMctMemClr_Init 3648 TP_ENDNMEMFMCTMEMCLR_INIT = 0x13B, ///< EndnMemFMctMemClr_Init 3649 TP_BEGINMEMBEFOREMEMDATAINIT = 0x13C, ///< BeginMemBeforeMemDataInit 3650 TP_ENDMEMBEFOREMEMDATAINIT = 0x13D, ///< EndMemBeforeMemDataInit 3651 TP_BEGINPROCAMDMEMAUTO = 0x13E, ///< BeginProcAmdMemAuto 3652 TP_ENDPROCAMDMEMAUTO = 0x13F, ///< EndProcAmdMemAuto 3653 TP_BEGINMEMMFLOWC32 = 0x140, ///< BeginMemMFlowC32 3654 TP_ENDMEMMFLOWC32 = 0x141, ///< EndMemMFlowC32 3655 TP_BEGINMEMINITIALIZEMCT = 0x142, ///< BeginMemInitializeMCT 3656 TP_ENDMEMINITIALIZEMCT = 0x143, ///< EndMemInitializeMCT 3657 TP_BEGINMEMSYSTEMMEMORYMAPPING = 0x144, ///< BeginMemSystemMemoryMapping 3658 TP_ENDMEMSYSTEMMEMORYMAPPING = 0x145, ///< EndMemSystemMemoryMapping 3659 TP_BEGINMEMDRAMTRAINING = 0x146, ///< BeginMemDramTraining 3660 TP_ENDMEMDRAMTRAINING = 0x147, ///< EndMemDramTraining 3661 TP_BEGINMEMOTHERTIMING = 0x148, ///< BeginMemOtherTiming 3662 TP_ENDMEMOTHERTIMING = 0x149, ///< EndMemOtherTiming 3663 TP_BEGINMEMUMAMEMTYPING = 0x14A, ///< BeginMemUMAMemTyping 3664 TP_ENDMEMUMAMEMTYPING = 0x14B, ///< EndMemUMAMemTyping 3665 TP_BEGINMEMMEMCLR = 0x14C, ///< BeginMemMemClr 3666 TP_ENDMEMMEMCLR = 0x14D, ///< EndMemMemClr 3667 TP_BEGINMEMMFLOWTN = 0x14E, ///< BeginMemMFlowTN 3668 TP_ENDMEMMFLOWTN = 0x14F, ///< EndMemMFlowTN 3669 TP_BEGINAGESAHOOKBEFOREDRAMINIT = 0x150, ///< BeginAgesaHookBeforeDramInit 3670 TP_ENDAGESAHOOKBEFOREDRAMINIT = 0x151, ///< EndAgesaHookBeforeDramInit 3671 TP_BEGINPROCMEMDRAMTRAINING = 0x152, ///< BeginProcMemDramTraining 3672 TP_ENDPROCMEMDRAMTRAINING = 0x153, ///< EndProcMemDramTraining 3673 TP_BEGINGNBINITATRTB = 0x154, ///< BeginGnbInitAtRtb 3674 TP_ENDGNBINITATRTB = 0x155, ///< EndGnbInitAtRtb 3675 TP_BEGINGNBLOADSCSDATA = 0x156, ///< BeginGnbLoadScsData 3676 TP_ENDGNBLOADSCSDATA = 0x157, ///< EndGnbLoadScsData 3677 TP_BEGINGNBPCIETRAINING = 0x158, ///< BeginGnbPcieTraining 3678 TP_ENDGNBPCIETRAINING = 0x159, ///< EndGnbPcieTraining 3679 TP_BEGINDISPATCHCPUFEATURESINITRTB = 0x15A, ///< BeginDispatchCpuFeaturesInitRtb 3680 TP_ENDDISPATCHCPUFEATURESINITRTB = 0x15B, ///< EndDispatchCpuFeaturesInitRtb 3681 TP_BEGINAMDCPUMID = 0x15C, ///< BeginAmdCpuEarly 3682 TP_ENDAMDCPUMID = 0x15D, ///< EndAmdCpuEarly 3683 TP_BEGINAMDGNBMIDLATE = 0x15E, ///< BeginAmdGnbMidLate 3684 TP_ENDAMDAMDGNBMIDLATE = 0x15F, ///< EndAmdGnbMidLate 3685 IDS_TP_END ///< End of IDS TP list 3686 } IDS_PERF_DATA; 3687 3688 /// Data Structure of Parameters for TestPoint_TSC. 3689 typedef struct { 3690 UINT32 LineInFile; ///< Line of current time counter 3691 UINT64 Description; ///<Description ID 3692 UINT64 StartTsc; ///< The StartTimer of TestPoint_TSC 3693 } TestPoint_TSC; 3694 3695 #define RESERVED_TP_NUMER 0x20 3696 #define MAX_PERFORMANCE_UNIT_NUM (IDS_TP_END - TP_BEGINPROCAMDINITEARLY + 1 + RESERVED_TP_NUMER) 3697 /// Data Structure of Parameters for TP_Perf_STRUCT. 3698 typedef struct { 3699 UINT32 Signature; ///< "PERF" 3700 UINT32 Version; ///< version 3701 UINT32 Index; ///< The Index of TP_Perf_STRUCT 3702 UINT32 TscInMhz; ///< Tsc counter in 1 mhz 3703 TestPoint_TSC TP[MAX_PERFORMANCE_UNIT_NUM]; ///< The TP of TP_Perf_STRUCT 3704 } TP_Perf_STRUCT; 3705 #endif 3706 3707 /************************************************************************ 3708 * 3709 * AGESA Basic Level interface structure definition and function prototypes 3710 * 3711 ***********************************************************************/ 3712 3713 /********************************************************************** 3714 * Interface call: AmdCreateStruct 3715 **********************************************************************/ 3716 AGESA_STATUS 3717 AmdCreateStruct ( 3718 IN OUT AMD_INTERFACE_PARAMS *InterfaceParams 3719 ); 3720 3721 /********************************************************************** 3722 * Interface call: AmdReleaseStruct 3723 **********************************************************************/ 3724 AGESA_STATUS 3725 AmdReleaseStruct ( 3726 IN OUT AMD_INTERFACE_PARAMS *InterfaceParams 3727 ); 3728 3729 /********************************************************************** 3730 * Interface call: AmdInitReset 3731 **********************************************************************/ 3732 /// AmdInitReset param structure 3733 typedef struct { 3734 IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header 3735 IN EXECUTION_CACHE_REGION CacheRegion[3]; ///< The cached memory region 3736 IN FCH_RESET_INTERFACE FchInterface; ///< Interface for FCH configuration 3737 } AMD_RESET_PARAMS; 3738 3739 AGESA_STATUS 3740 AmdInitReset ( 3741 IN OUT AMD_RESET_PARAMS *ResetParams 3742 ); 3743 3744 3745 /********************************************************************** 3746 * Interface call: AmdInitEarly 3747 **********************************************************************/ 3748 /// InitEarly param structure 3749 /// 3750 /// Provide defaults or customizations to each service performed in AmdInitEarly. 3751 /// 3752 typedef struct { 3753 IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header 3754 IN EXECUTION_CACHE_REGION CacheRegion[3]; ///< Execution Map Interface 3755 IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. 3756 IN GNB_CONFIGURATION GnbConfig; ///< GNB configuration 3757 } AMD_EARLY_PARAMS; 3758 3759 AGESA_STATUS 3760 AmdInitEarly ( 3761 IN OUT AMD_EARLY_PARAMS *EarlyParams 3762 ); 3763 3764 3765 /********************************************************************** 3766 * Interface call: AmdInitPost 3767 **********************************************************************/ 3768 /// AmdInitPost param structure 3769 typedef struct { 3770 IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header 3771 IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. 3772 IN MEM_PARAMETER_STRUCT MemConfig; ///< Memory post param 3773 IN GNB_POST_CONFIGURATION GnbPostConfig; ///< GNB post param 3774 } AMD_POST_PARAMS; 3775 3776 AGESA_STATUS 3777 AmdInitPost ( 3778 IN OUT AMD_POST_PARAMS *PostParams ///< Amd Cpu init param 3779 ); 3780 3781 3782 /********************************************************************** 3783 * Interface call: AmdInitEnv 3784 **********************************************************************/ 3785 /// AmdInitEnv param structure 3786 typedef struct { 3787 IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header 3788 IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. 3789 IN GNB_ENV_CONFIGURATION GnbEnvConfiguration; ///< GNB configuration 3790 IN FCH_INTERFACE FchInterface; ///< FCH configuration 3791 } AMD_ENV_PARAMS; 3792 3793 AGESA_STATUS 3794 AmdInitEnv ( 3795 IN OUT AMD_ENV_PARAMS *EnvParams 3796 ); 3797 3798 3799 /********************************************************************** 3800 * Interface call: AmdInitMid 3801 **********************************************************************/ 3802 /// AmdInitMid param structure 3803 typedef struct { 3804 IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header 3805 IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. 3806 IN GNB_MID_CONFIGURATION GnbMidConfiguration; ///< GNB configuration 3807 IN FCH_INTERFACE FchInterface; ///< FCH configuration 3808 } AMD_MID_PARAMS; 3809 3810 AGESA_STATUS 3811 AmdInitMid ( 3812 IN OUT AMD_MID_PARAMS *MidParams 3813 ); 3814 3815 3816 /********************************************************************** 3817 * Interface call: AmdInitLate 3818 **********************************************************************/ 3819 /// AmdInitLate param structure 3820 typedef struct { 3821 IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header 3822 IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. 3823 IN IOMMU_EXCLUSION_RANGE_DESCRIPTOR *IvrsExclusionRangeList; ///< Pointer to array of exclusion ranges 3824 OUT DMI_INFO *DmiTable; ///< DMI Interface 3825 OUT VOID *AcpiPState; ///< Acpi Pstate SSDT Table 3826 OUT VOID *AcpiWheaMce; ///< WHEA MCE Table 3827 OUT VOID *AcpiWheaCmc; ///< WHEA CMC Table 3828 OUT VOID *AcpiAlib; ///< ACPI SSDT table with ALIB implementation 3829 OUT VOID *AcpiIvrs; ///< IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table 3830 OUT VOID *AcpiCrat; ///< Component Resource Affinity Table table 3831 OUT VOID *AcpiCdit; ///< Component Locality Distance Information table 3832 IN GNB_LATE_CONFIGURATION GnbLateConfiguration; ///< GNB configuration 3833 } AMD_LATE_PARAMS; 3834 3835 AGESA_STATUS 3836 AmdInitLate ( 3837 IN OUT AMD_LATE_PARAMS *LateParams 3838 ); 3839 3840 /********************************************************************** 3841 * Interface call: AmdInitRecovery 3842 **********************************************************************/ 3843 /// CPU Recovery Parameters 3844 typedef struct { 3845 IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header 3846 IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. 3847 } AMD_CPU_RECOVERY_PARAMS; 3848 3849 /// AmdInitRecovery param structure 3850 typedef struct { 3851 IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header 3852 IN MEM_PARAMETER_STRUCT MemConfig; ///< Memory post param 3853 IN EXECUTION_CACHE_REGION CacheRegion[3]; ///< The cached memory region. And the max cache region is 3 3854 IN AMD_CPU_RECOVERY_PARAMS CpuRecoveryParams; ///< Params for CPU related recovery init. 3855 } AMD_RECOVERY_PARAMS; 3856 3857 AGESA_STATUS 3858 AmdInitRecovery ( 3859 IN OUT AMD_RECOVERY_PARAMS *RecoveryParams 3860 ); 3861 3862 /********************************************************************** 3863 * Interface call: AmdInitResume 3864 **********************************************************************/ 3865 /// AmdInitResume param structure 3866 typedef struct { 3867 IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header 3868 IN PLATFORM_CONFIGURATION PlatformConfig; ///< Platform operational characteristics 3869 IN S3_DATA_BLOCK S3DataBlock; ///< Save state data 3870 } AMD_RESUME_PARAMS; 3871 3872 AGESA_STATUS 3873 AmdInitResume ( 3874 IN AMD_RESUME_PARAMS *ResumeParams 3875 ); 3876 3877 3878 /********************************************************************** 3879 * Interface call: AmdS3LateRestore 3880 **********************************************************************/ 3881 /// AmdS3LateRestore param structure 3882 typedef struct { 3883 IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header 3884 IN PLATFORM_CONFIGURATION PlatformConfig; ///< Platform operational characteristics. 3885 IN S3_DATA_BLOCK S3DataBlock; ///< Save state data 3886 } AMD_S3LATE_PARAMS; 3887 3888 AGESA_STATUS 3889 AmdS3LateRestore ( 3890 IN OUT AMD_S3LATE_PARAMS *S3LateParams 3891 ); 3892 3893 3894 /********************************************************************** 3895 * Interface call: AmdS3FinalRestore 3896 **********************************************************************/ 3897 /// AmdS3FinalRestore param structure 3898 typedef struct { 3899 IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header 3900 IN PLATFORM_CONFIGURATION PlatformConfig; ///< Platform operational characteristics. 3901 IN S3_DATA_BLOCK S3DataBlock; ///< Save state data 3902 } AMD_S3FINAL_PARAMS; 3903 3904 AGESA_STATUS 3905 AmdS3FinalRestore ( 3906 IN OUT AMD_S3FINAL_PARAMS *S3FinalParams 3907 ); 3908 3909 /********************************************************************** 3910 * Interface call: AmdInitRtb 3911 **********************************************************************/ 3912 /// AmdInitRtb param structure 3913 typedef struct { 3914 IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header 3915 IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics. 3916 OUT S3_DATA_BLOCK S3DataBlock; ///< Save state data 3917 IN FCH_INTERFACE FchInterface; ///< FCH configuration 3918 } AMD_RTB_PARAMS; 3919 3920 AGESA_STATUS 3921 AmdInitRtb ( 3922 IN OUT AMD_RTB_PARAMS *AmdInitRtbParams 3923 ); 3924 3925 3926 /********************************************************************** 3927 * Interface call: AmdLateRunApTask 3928 **********************************************************************/ 3929 /** 3930 * Entry point for AP tasking. 3931 */ 3932 AGESA_STATUS 3933 AmdLateRunApTask ( 3934 IN AP_EXE_PARAMS *AmdApExeParams 3935 ); 3936 3937 // 3938 // General Services API 3939 // 3940 3941 /********************************************************************** 3942 * Interface service call: AmdGetApicId 3943 **********************************************************************/ 3944 /// Request the APIC ID of a particular core. 3945 3946 typedef struct { 3947 IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header 3948 IN UINT8 Socket; ///< The Core's Socket. 3949 IN UINT8 Core; ///< The Core id. 3950 OUT BOOLEAN IsPresent; ///< The Core is present, and ApicAddress is valid. 3951 OUT UINT8 ApicAddress; ///< The Core's APIC ID. 3952 } AMD_APIC_PARAMS; 3953 3954 /** 3955 * Get a specified Core's APIC ID. 3956 */ 3957 AGESA_STATUS 3958 AmdGetApicId ( 3959 IN OUT AMD_APIC_PARAMS *AmdParamApic 3960 ); 3961 3962 /********************************************************************** 3963 * Interface service call: AmdGetPciAddress 3964 **********************************************************************/ 3965 /// Request the PCI Address of a Processor Module (that is, its Northbridge) 3966 3967 typedef struct { 3968 IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header 3969 IN UINT8 Socket; ///< The Processor's socket 3970 IN UINT8 Module; ///< The Module in that Processor 3971 OUT BOOLEAN IsPresent; ///< The Core is present, and PciAddress is valid. 3972 OUT PCI_ADDR PciAddress; ///< The Processor's PCI Config Space address (Function 0, Register 0) 3973 } AMD_GET_PCI_PARAMS; 3974 3975 /** 3976 * Get Processor Module's PCI Config Space address. 3977 */ 3978 AGESA_STATUS 3979 AmdGetPciAddress ( 3980 IN OUT AMD_GET_PCI_PARAMS *AmdParamGetPci 3981 ); 3982 3983 /********************************************************************** 3984 * Interface service call: AmdIdentifyCore 3985 **********************************************************************/ 3986 /// Request the identity (Socket, Module, Core) of the current Processor Core 3987 3988 typedef struct { 3989 IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header 3990 OUT UINT8 Socket; ///< The current Core's Socket 3991 OUT UINT8 Module; ///< The current Core's Processor Module 3992 OUT UINT8 Core; ///< The current Core's core id. 3993 } AMD_IDENTIFY_PARAMS; 3994 3995 /** 3996 * "Who am I" for the current running core. 3997 */ 3998 AGESA_STATUS 3999 AmdIdentifyCore ( 4000 IN OUT AMD_IDENTIFY_PARAMS *AmdParamIdentify 4001 ); 4002 4003 /********************************************************************** 4004 * Interface service call: AmdReadEventLog 4005 **********************************************************************/ 4006 /// An Event Log Entry. 4007 typedef struct { 4008 IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header 4009 OUT UINT32 EventClass; ///< The severity of this event, matches AGESA_STATUS. 4010 OUT UINT32 EventInfo; ///< The unique event identifier, zero means "no event". 4011 OUT UINT32 DataParam1; ///< Data specific to the Event. 4012 OUT UINT32 DataParam2; ///< Data specific to the Event. 4013 OUT UINT32 DataParam3; ///< Data specific to the Event. 4014 OUT UINT32 DataParam4; ///< Data specific to the Event. 4015 } EVENT_PARAMS; 4016 4017 /** 4018 * Read an Event from the Event Log. 4019 */ 4020 AGESA_STATUS 4021 AmdReadEventLog ( 4022 IN EVENT_PARAMS *Event 4023 ); 4024 4025 /********************************************************************** 4026 * Interface service call: AmdIdentifyDimm 4027 **********************************************************************/ 4028 /// Request the identity of dimm from system address 4029 4030 typedef struct { 4031 IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header 4032 IN UINT64 MemoryAddress; ///< System Address that needs to be translated to dimm identification. 4033 OUT UINT8 SocketId; ///< The socket on which the targeted address locates. 4034 OUT UINT8 MemChannelId; ///< The channel on which the targeted address locates. 4035 OUT UINT8 DimmId; ///< The dimm on which the targeted address locates. 4036 OUT UINT8 ChipSelect; ///< The chip select on which the targeted address locates. 4037 OUT UINT8 Bank; ///< The Bank for which the error address resides 4038 OUT UINT32 Row; ///< The Row for which the error address resides 4039 OUT UINT16 Column; ///< The Column for which the error address resides 4040 } AMD_IDENTIFY_DIMM; 4041 4042 /** 4043 * Get the dimm identification for the address. 4044 */ 4045 AGESA_STATUS 4046 AmdIdentifyDimm ( 4047 IN OUT AMD_IDENTIFY_DIMM *AmdDimmIdentify 4048 ); 4049 4050 AGESA_STATUS 4051 AmdIdsRunApTaskLate ( 4052 IN AP_EXE_PARAMS *AmdApExeParams 4053 ); 4054 4055 /// Request the 2D Data Eye Training Data 4056 #define RD_DATAEYE 0 4057 #define WR_DATAEYE 1 4058 4059 /********************************************************************** 4060 * Interface service call: AmdGet2DDataEye 4061 **********************************************************************/ 4062 /// Request the training data eye on Socket, Channel, Dimm. 4063 4064 typedef struct _AMD_GET_DATAEYE { 4065 IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header 4066 IN OUT AMD_POST_PARAMS *PostParamsPtr; ///< Pointer to AMD_POST_PARAMS 4067 IN UINT8 SocketId; ///< The socket number to get the 2D data eye 4068 IN UINT8 MemChannelId; ///< The channel number to get the 2D data eye 4069 IN UINT8 DimmId; ///< The dimm number to get the 2D data eye 4070 IN UINT8 DataEyeType; ///< Get the 2D data eye on read or write training 4071 OUT UINT8* DataEyeBuffer; ///< The buffer to stores the 2D data eye 4072 } AMD_GET_DATAEYE; 4073 4074 AGESA_STATUS 4075 AmdGet2DDataEye ( 4076 IN OUT AMD_GET_DATAEYE *AmdGetDataEye 4077 ); 4078 4079 #define AGESA_IDS_DFT_VAL 0xFFFF ///< Default value of every uninitlized NV item, the action for it will be ignored 4080 #define AGESA_IDS_NV_END 0xFFFF ///< Flag specify end of option structure 4081 /// WARNING: Don't change the comment below, it used as signature for script 4082 /// AGESA IDS NV ID Definitions 4083 typedef enum { 4084 AGESA_IDS_EXT_ID_START = 0x0000,///< 0x0000 specify the start of external NV id 4085 4086 AGESA_IDS_NV_UCODE, ///< 0x0001 Enable or disable microcode patching 4087 4088 AGESA_IDS_NV_TARGET_PSTATE, ///< 0x0002 Set the P-state required to be activated 4089 AGESA_IDS_NV_POSTPSTATE, ///< 0x0003 Set the P-state required to be activated through POST 4090 4091 AGESA_IDS_NV_BANK_INTERLEAVE, ///< 0x0004 Enable or disable Bank Interleave 4092 AGESA_IDS_NV_CHANNEL_INTERLEAVE, ///< 0x0005 Enable or disable Channel Interleave 4093 AGESA_IDS_NV_NODE_INTERLEAVE, ///< 0x0006 Enable or disable Node Interleave 4094 AGESA_IDS_NV_MEMHOLE, ///< 0x0007 Enables or disable memory hole 4095 4096 AGESA_IDS_NV_SCRUB_REDIRECTION, ///< 0x0008 Enable or disable a write to dram with corrected data 4097 AGESA_IDS_NV_DRAM_SCRUB, ///< 0x0009 Set the rate of background scrubbing for DRAM 4098 AGESA_IDS_NV_DCACHE_SCRUB, ///< 0x000A Set the rate of background scrubbing for the DCache. 4099 AGESA_IDS_NV_L2_SCRUB, ///< 0x000B Set the rate of background scrubbing for the L2 cache 4100 AGESA_IDS_NV_L3_SCRUB, ///< 0x000C Set the rate of background scrubbing for the L3 cache 4101 AGESA_IDS_NV_ICACHE_SCRUB, ///< 0x000D Set the rate of background scrubbing for the Icache 4102 AGESA_IDS_NV_SYNC_ON_ECC_ERROR, ///< 0x000E Enable or disable the sync flood on un-correctable ECC error 4103 AGESA_IDS_NV_ECC_SYMBOL_SIZE, ///< 0x000F Set ECC symbol size 4104 4105 AGESA_IDS_NV_ALL_MEMCLKS, ///< 0x0010 Enable or disable all memory clocks enable 4106 AGESA_IDS_NV_DCT_GANGING_MODE, ///< 0x0011 Set the Ganged mode 4107 AGESA_IDS_NV_DRAM_BURST_LENGTH32, ///< 0x0012 Set the DRAM Burst Length 32 4108 AGESA_IDS_NV_MEMORY_POWER_DOWN, ///< 0x0013 Enable or disable Memory power down mode 4109 AGESA_IDS_NV_MEMORY_POWER_DOWN_MODE, ///< 0x0014 Set the Memory power down mode 4110 AGESA_IDS_NV_DLL_SHUT_DOWN, ///< 0x0015 Enable or disable DLLShutdown 4111 AGESA_IDS_NV_ONLINE_SPARE, ///< 0x0016 Enable or disable the Dram controller to designate a DIMM bank as a spare for logical swap 4112 4113 AGESA_IDS_NV_HDTOUT, ///< 0x0017 Enable or disable HDTOUT feature 4114 4115 AGESA_IDS_NV_GNBHDAUDIOEN, ///< 0x0018 Enable or disable GNB HD Audio 4116 4117 AGESA_IDS_NV_CPB_EN, ///< 0x0019 Core Performance Boost 4118 4119 AGESA_IDS_NV_HTC_EN, ///< 0x001A HTC Enable 4120 AGESA_IDS_NV_HTC_OVERRIDE, ///< 0x001B HTC Override 4121 AGESA_IDS_NV_HTC_PSTATE_LIMIT, ///< 0x001C HTC P-state limit select 4122 AGESA_IDS_NV_HTC_TEMP_HYS, ///< 0x001D HTC Temperature Hysteresis 4123 AGESA_IDS_NV_HTC_ACT_TEMP, ///< 0x001E HTC Activation Temp 4124 4125 AGESA_IDS_NV_DRAMCON, ///< 0x001F Specify the mode for controller initialization 4126 AGESA_IDS_NV_ALL_CKE, ///< 0x0020 Enable or disable all CKE 4127 AGESA_IDS_NV_ALL_CS, ///< 0x0021 Enable or disable all CS 4128 AGESA_IDS_NV_MSR_DE_CFG_BIT16, ///< 0x0022 Workaround GCC/C000005 issue for XV Core on CZ A0 4129 AGESA_IDS_EXT_ID_END, ///< 0x0023 specify the end of external NV ID 4130 } IDS_EX_NV_ID; 4131 4132 4133 #define IDS_NUM_EXT_NV_ITEM (AGESA_IDS_EXT_ID_END - AGESA_IDS_EXT_ID_START + 1) 4134 4135 4136 #endif // _AGESA_H_ 4137