1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 3 #ifndef CPU_SAMSUNG_EXYNOS5420_CLK_H 4 #define CPU_SAMSUNG_EXYNOS5420_CLK_H 5 6 #include <soc/cpu.h> 7 #include <soc/dmc.h> 8 #include <soc/pinmux.h> 9 #include <stdint.h> 10 11 enum periph_id; 12 13 /* This master list of PLLs is ordered arbitrarily. */ 14 #define APLL 0 15 #define MPLL 1 16 #define EPLL 2 17 #define HPLL 3 18 #define VPLL 4 19 #define BPLL 5 20 #define RPLL 6 21 #define SPLL 7 22 #define CPLL 8 23 #define DPLL 9 24 #define IPLL 10 25 26 unsigned long get_pll_clk(int pllreg); 27 unsigned long get_arm_clk(void); 28 unsigned long get_pwm_clk(void); 29 unsigned long get_uart_clk(int dev_index); 30 void set_mmc_clk(int dev_index, unsigned int div); 31 32 /** 33 * get the clk frequency of the required peripheral 34 * 35 * @param peripheral Peripheral id 36 * 37 * @return frequency of the peripheral clk 38 */ 39 unsigned long clock_get_periph_rate(enum periph_id peripheral); 40 41 #define MCT_HZ 24000000 42 43 /* 44 * Set mshci controller instances clock divider 45 * 46 * @param enum periph_id instance of the mshci controller 47 * 48 * Return 0 if ok else -1 49 */ 50 int clock_set_mshci(enum periph_id peripheral); 51 52 /* 53 * Set dwmci controller instances clock divider 54 * 55 * @param enum periph_id instance of the dwmci controller 56 * 57 * Return 0 if ok else -1 58 */ 59 int clock_set_dwmci(enum periph_id peripheral); 60 61 /* 62 * Sets the epll clockrate 63 * 64 * @param rate Required clock rate to the prescaler in Hz 65 * 66 * Return 0 if ok else -1 67 */ 68 int clock_epll_set_rate(unsigned long rate); 69 70 /* 71 * selects the clk source for I2S MCLK 72 */ 73 void clock_select_i2s_clk_source(void); 74 75 /* 76 * Set prescaler division based on input and output frequency 77 * for i2s audio clock 78 * 79 * @param src_frq Source frequency in Hz 80 * @param dst_frq Required MCLK frequency in Hz 81 * 82 * Return 0 if ok else -1 83 */ 84 int clock_set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq); 85 86 struct exynos5420_clock { 87 uint32_t apll_lock; /* 0x10010000 */ 88 uint8_t res1[0xfc]; 89 uint32_t apll_con0; 90 uint32_t apll_con1; 91 uint8_t res2[0xf8]; 92 uint32_t clk_src_cpu; 93 uint8_t res3[0x1fc]; 94 uint32_t clk_mux_stat_cpu; 95 uint8_t res4[0xfc]; 96 uint32_t clk_div_cpu0; /* 0x10010500 */ 97 uint32_t clk_div_cpu1; 98 uint8_t res5[0xf8]; 99 uint32_t clk_div_stat_cpu0; 100 uint32_t clk_div_stat_cpu1; 101 uint8_t res6[0xf8]; 102 uint32_t clk_gate_bus_cpu; 103 uint8_t res7[0xfc]; 104 uint32_t clk_gate_sclk_cpu; 105 uint8_t res8[0x1fc]; 106 uint32_t clkout_cmu_cpu; /* 0x10010a00 */ 107 uint32_t clkout_cmu_cpu_div_stat; 108 uint8_t res9[0x5f8]; 109 uint32_t armclk_stopctrl; 110 uint8_t res10[0x4]; 111 uint32_t arm_ema_ctrl; 112 uint32_t arm_ema_status; 113 uint8_t res11[0x10]; 114 uint32_t pwr_ctrl; 115 uint32_t pwr_ctrl2; 116 uint8_t res12[0xd8]; 117 uint32_t apll_con0_l8; /* 0x1001100 */ 118 uint32_t apll_con0_l7; 119 uint32_t apll_con0_l6; 120 uint32_t apll_con0_l5; 121 uint32_t apll_con0_l4; 122 uint32_t apll_con0_l3; 123 uint32_t apll_con0_l2; 124 uint32_t apll_con0_l1; 125 uint32_t iem_control; 126 uint8_t res13[0xdc]; 127 uint32_t apll_con1_l8; /* 0x10011200 */ 128 uint32_t apll_con1_l7; 129 uint32_t apll_con1_l6; 130 uint32_t apll_con1_l5; 131 uint32_t apll_con1_l4; 132 uint32_t apll_con1_l3; 133 uint32_t apll_con1_l2; 134 uint32_t apll_con1_l1; 135 uint8_t res14[0xe0]; 136 uint32_t clkdiv_iem_l8; 137 uint32_t clkdiv_iem_l7; /* 0x10011304 */ 138 uint32_t clkdiv_iem_l6; 139 uint32_t clkdiv_iem_l5; 140 uint32_t clkdiv_iem_l4; 141 uint32_t clkdiv_iem_l3; 142 uint32_t clkdiv_iem_l2; 143 uint32_t clkdiv_iem_l1; 144 uint8_t res15[0xe0]; 145 uint32_t l2_status; 146 uint8_t res16[0x0c]; 147 uint32_t cpu_status; /* 0x10011410 */ 148 uint8_t res17[0x0c]; 149 uint32_t ptm_status; 150 uint8_t res18[0xbdc]; 151 uint32_t cmu_cpu_spare0; 152 uint32_t cmu_cpu_spare1; 153 uint32_t cmu_cpu_spare2; 154 uint32_t cmu_cpu_spare3; 155 uint32_t cmu_cpu_spare4; 156 uint8_t res19[0x1fdc]; 157 uint32_t cmu_cpu_version; 158 uint8_t res20[0x20c]; 159 uint32_t clk_src_cperi0; /* 0x10014200 */ 160 uint32_t clk_src_cperi1; 161 uint8_t res21[0xf8]; 162 uint32_t clk_src_mask_cperi; 163 uint8_t res22[0x100]; 164 uint32_t clk_mux_stat_cperi1; 165 uint8_t res23[0xfc]; 166 uint32_t clk_div_cperi1; 167 uint8_t res24[0xfc]; 168 uint32_t clk_div_stat_cperi1; 169 uint8_t res25[0xf8]; 170 uint32_t clk_gate_bus_cperi0; /* 0x10014700 */ 171 uint32_t clk_gate_bus_cperi1; 172 uint8_t res26[0xf8]; 173 uint32_t clk_gate_sclk_cperi; 174 uint8_t res27[0xfc]; 175 uint32_t clk_gate_ip_cperi; 176 uint8_t res28[0xfc]; 177 uint32_t clkout_cmu_cperi; 178 uint32_t clkout_cmu_cperi_div_stat; 179 uint8_t res29[0x5f8]; 180 uint32_t dcgidx_map0; /* 0x10015000 */ 181 uint32_t dcgidx_map1; 182 uint32_t dcgidx_map2; 183 uint8_t res30[0x14]; 184 uint32_t dcgperf_map0; 185 uint32_t dcgperf_map1; 186 uint8_t res31[0x18]; 187 uint32_t dvcidx_map; 188 uint8_t res32[0x1c]; 189 uint32_t freq_cpu; 190 uint32_t freq_dpm; 191 uint8_t res33[0x18]; 192 uint32_t dvsemclk_en; /* 0x10015080 */ 193 uint32_t maxperf; 194 uint8_t res34[0x2e78]; 195 uint32_t cmu_cperi_spare0; 196 uint32_t cmu_cperi_spare1; 197 uint32_t cmu_cperi_spare2; 198 uint32_t cmu_cperi_spare3; 199 uint32_t cmu_cperi_spare4; 200 uint32_t cmu_cperi_spare5; 201 uint32_t cmu_cperi_spare6; 202 uint32_t cmu_cperi_spare7; 203 uint32_t cmu_cperi_spare8; 204 uint8_t res35[0xcc]; 205 uint32_t cmu_cperi_version; /* 0x10017ff0 */ 206 uint8_t res36[0x50c]; 207 uint32_t clk_div_g2d; 208 uint8_t res37[0xfc]; 209 uint32_t clk_div_stat_g2d; 210 uint8_t res38[0xfc]; 211 uint32_t clk_gate_bus_g2d; 212 uint8_t res39[0xfc]; 213 uint32_t clk_gate_ip_g2d; 214 uint8_t res40[0x1fc]; 215 uint32_t clkout_cmu_g2d; 216 uint32_t clkout_cmu_g2d_div_stat;/* 0x10018a04 */ 217 uint8_t res41[0xf8]; 218 uint32_t cmu_g2d_spare0; 219 uint32_t cmu_g2d_spare1; 220 uint32_t cmu_g2d_spare2; 221 uint32_t cmu_g2d_spare3; 222 uint32_t cmu_g2d_spare4; 223 uint8_t res42[0x34dc]; 224 uint32_t cmu_g2d_version; 225 uint8_t res43[0x30c]; 226 uint32_t clk_div_cmu_isp0; 227 uint32_t clk_div_cmu_isp1; 228 uint32_t clk_div_isp2; /* 0x1001c308 */ 229 uint8_t res44[0xf4]; 230 uint32_t clk_div_stat_cmu_isp0; 231 uint32_t clk_div_stat_cmu_isp1; 232 uint32_t clk_div_stat_isp2; 233 uint8_t res45[0x2f4]; 234 uint32_t clk_gate_bus_isp0; 235 uint32_t clk_gate_bus_isp1; 236 uint32_t clk_gate_bus_isp2; 237 uint32_t clk_gate_bus_isp3; 238 uint8_t res46[0xf0]; 239 uint32_t clk_gate_ip_isp0; 240 uint32_t clk_gate_ip_isp1; 241 uint8_t res47[0xf8]; 242 uint32_t clk_gate_sclk_isp; 243 uint8_t res48[0x0c]; 244 uint32_t mcuisp_pwr_ctrl; /* 0x1001c910 */ 245 uint8_t res49[0x0ec]; 246 uint32_t clkout_cmu_isp; 247 uint32_t clkout_cmu_isp_div_stat; 248 uint8_t res50[0xf8]; 249 uint32_t cmu_isp_spare0; 250 uint32_t cmu_isp_spare1; 251 uint32_t cmu_isp_spare2; 252 uint32_t cmu_isp_spare3; 253 uint8_t res51[0x34e0]; 254 uint32_t cmu_isp_version; 255 uint8_t res52[0x2c]; 256 uint32_t cpll_lock; /* 10020020 */ 257 uint8_t res53[0xc]; 258 uint32_t dpll_lock; 259 uint8_t res54[0xc]; 260 uint32_t epll_lock; 261 uint8_t res55[0xc]; 262 uint32_t rpll_lock; 263 uint8_t res56[0xc]; 264 uint32_t ipll_lock; 265 uint8_t res57[0xc]; 266 uint32_t spll_lock; 267 uint8_t res58[0xc]; 268 uint32_t vpll_lock; 269 uint8_t res59[0xc]; 270 uint32_t mpll_lock; 271 uint8_t res60[0x8c]; 272 uint32_t cpll_con0; /* 10020120 */ 273 uint32_t cpll_con1; 274 uint32_t dpll_con0; 275 uint32_t dpll_con1; 276 uint32_t epll_con0; 277 uint32_t epll_con1; 278 uint32_t epll_con2; 279 uint8_t res601[0x4]; 280 uint32_t rpll_con0; 281 uint32_t rpll_con1; 282 uint32_t rpll_con2; 283 uint8_t res602[0x4]; 284 uint32_t ipll_con0; 285 uint32_t ipll_con1; 286 uint8_t res61[0x8]; 287 uint32_t spll_con0; 288 uint32_t spll_con1; 289 uint8_t res62[0x8]; 290 uint32_t vpll_con0; 291 uint32_t vpll_con1; 292 uint8_t res63[0x8]; 293 uint32_t mpll_con0; 294 uint32_t mpll_con1; 295 uint8_t res64[0x78]; 296 uint32_t clk_src_top0; /* 0x10020200 */ 297 uint32_t clk_src_top1; 298 uint32_t clk_src_top2; 299 uint32_t clk_src_top3; 300 uint32_t clk_src_top4; 301 uint32_t clk_src_top5; 302 uint32_t clk_src_top6; 303 uint32_t clk_src_top7; 304 uint8_t res65[0xc]; 305 uint32_t clk_src_disp10; /* 0x1002022c */ 306 uint8_t res66[0x10]; 307 uint32_t clk_src_mau; 308 uint32_t clk_src_fsys; 309 uint8_t res67[0x8]; 310 uint32_t clk_src_peric0; 311 uint32_t clk_src_peric1; 312 uint8_t res68[0x18]; 313 uint32_t clk_src_isp; 314 uint8_t res69[0x0c]; 315 uint32_t clk_src_top10; 316 uint32_t clk_src_top11; 317 uint32_t clk_src_top12; 318 uint8_t res70[0x74]; 319 uint32_t clk_src_mask_top0; 320 uint32_t clk_src_mask_top1; 321 uint32_t clk_src_mask_top2; 322 uint8_t res71[0x10]; 323 uint32_t clk_src_mask_top7; 324 uint8_t res72[0xc]; 325 uint32_t clk_src_mask_disp10; /* 0x1002032c */ 326 uint8_t res73[0x4]; 327 uint32_t clk_src_mask_mau; 328 uint8_t res74[0x8]; 329 uint32_t clk_src_mask_fsys; 330 uint8_t res75[0xc]; 331 uint32_t clk_src_mask_peric0; 332 uint32_t clk_src_mask_peric1; 333 uint8_t res76[0x18]; 334 uint32_t clk_src_mask_isp; 335 uint8_t res77[0x8c]; 336 uint32_t clk_mux_stat_top0; /* 0x10020400 */ 337 uint32_t clk_mux_stat_top1; 338 uint32_t clk_mux_stat_top2; 339 uint32_t clk_mux_stat_top3; 340 uint32_t clk_mux_stat_top4; 341 uint32_t clk_mux_stat_top5; 342 uint32_t clk_mux_stat_top6; 343 uint32_t clk_mux_stat_top7; 344 uint8_t res78[0x60]; 345 uint32_t clk_mux_stat_top10; 346 uint32_t clk_mux_stat_top11; 347 uint32_t clk_mux_stat_top12; 348 uint8_t res79[0x74]; 349 uint32_t clk_div_top0; /* 0x10020500 */ 350 uint32_t clk_div_top1; 351 uint32_t clk_div_top2; 352 uint8_t res80[0x20]; 353 uint32_t clk_div_disp10; 354 uint8_t res81[0x14]; 355 uint32_t clk_div_mau; 356 uint32_t clk_div_fsys0; 357 uint32_t clk_div_fsys1; 358 uint32_t clk_div_fsys2; 359 uint8_t res82[0x4]; 360 uint32_t clk_div_peric0; 361 uint32_t clk_div_peric1; 362 uint32_t clk_div_peric2; 363 uint32_t clk_div_peric3; 364 uint32_t clk_div_peric4; /* 0x10020568 */ 365 uint8_t res83[0x14]; 366 uint32_t clk_div_isp0; 367 uint32_t clk_div_isp1; 368 uint8_t res84[0x8]; 369 uint32_t clkdiv2_ratio; 370 uint8_t res850[0xc]; 371 uint32_t clkdiv4_ratio; 372 uint8_t res85[0x5c]; 373 uint32_t clk_div_stat_top0; 374 uint32_t clk_div_stat_top1; 375 uint32_t clk_div_stat_top2; 376 uint8_t res86[0x20]; 377 uint32_t clk_div_stat_disp10; 378 uint8_t res87[0x14]; 379 uint32_t clk_div_stat_mau; /* 0x10020644 */ 380 uint32_t clk_div_stat_fsys0; 381 uint32_t clk_div_stat_fsys1; 382 uint32_t clk_div_stat_fsys2; 383 uint8_t res88[0x4]; 384 uint32_t clk_div_stat_peric0; 385 uint32_t clk_div_stat_peric1; 386 uint32_t clk_div_stat_peric2; 387 uint32_t clk_div_stat_peric3; 388 uint32_t clk_div_stat_peric4; 389 uint8_t res89[0x14]; 390 uint32_t clk_div_stat_isp0; 391 uint32_t clk_div_stat_isp1; 392 uint8_t res90[0x8]; 393 uint32_t clkdiv2_stat0; 394 uint8_t res91[0xc]; 395 uint32_t clkdiv4_stat; 396 uint8_t res92[0x5c]; 397 uint32_t clk_gate_bus_top; /* 0x10020700 */ 398 uint8_t res93[0xc]; 399 uint32_t clk_gate_bus_gscl0; 400 uint8_t res94[0xc]; 401 uint32_t clk_gate_bus_gscl1; 402 uint8_t res95[0x4]; 403 uint32_t clk_gate_bus_disp1; 404 uint8_t res96[0x4]; 405 uint32_t clk_gate_bus_wcore; 406 uint32_t clk_gate_bus_mfc; 407 uint32_t clk_gate_bus_g3d; 408 uint32_t clk_gate_bus_gen; 409 uint32_t clk_gate_bus_fsys0; 410 uint32_t clk_gate_bus_fsys1; 411 uint32_t clk_gate_bus_fsys2; 412 uint32_t clk_gate_bus_mscl; 413 uint32_t clk_gate_bus_peric; 414 uint32_t clk_gate_bus_peric1; 415 uint8_t res97[0x8]; 416 uint32_t clk_gate_bus_peris0; 417 uint32_t clk_gate_bus_peris1; /* 0x10020764 */ 418 uint8_t res98[0x8]; 419 uint32_t clk_gate_bus_noc; 420 uint8_t res99[0xac]; 421 uint32_t clk_gate_top_sclk_gscl; 422 uint8_t res1000[0x4]; 423 uint32_t clk_gate_top_sclk_disp1; 424 uint8_t res100[0x10]; 425 uint32_t clk_gate_top_sclk_mau; 426 uint32_t clk_gate_top_sclk_fsys; 427 uint8_t res101[0xc]; 428 uint32_t clk_gate_top_sclk_peric; 429 uint8_t res102[0xc]; 430 uint32_t clk_gate_top_sclk_cperi; 431 uint8_t res103[0xc]; 432 uint32_t clk_gate_top_sclk_isp; 433 uint8_t res104[0x9c]; 434 uint32_t clk_gate_ip_gscl0; 435 uint8_t res105[0xc]; 436 uint32_t clk_gate_ip_gscl1; 437 uint8_t res106[0x4]; 438 uint32_t clk_gate_ip_disp1; 439 uint32_t clk_gate_ip_mfc; 440 uint32_t clk_gate_ip_g3d; 441 uint32_t clk_gate_ip_gen; /* 0x10020934 */ 442 uint8_t res107[0xc]; 443 uint32_t clk_gate_ip_fsys; 444 uint8_t res108[0x8]; 445 uint32_t clk_gate_ip_peric; 446 uint8_t res109[0xc]; 447 uint32_t clk_gate_ip_peris; 448 uint8_t res110[0xc]; 449 uint32_t clk_gate_ip_mscl; 450 uint8_t res111[0xc]; 451 uint32_t clk_gate_ip_block; 452 uint8_t res112[0xc]; 453 uint32_t bypass; 454 uint8_t res113[0x6c]; 455 uint32_t clkout_cmu_top; 456 uint32_t clkout_cmu_top_div_stat; 457 uint8_t res114[0xf8]; 458 uint32_t clkout_top_spare0; 459 uint32_t clkout_top_spare1; 460 uint32_t clkout_top_spare2; 461 uint32_t clkout_top_spare3; 462 uint8_t res115[0x34e0]; 463 uint32_t clkout_top_version; 464 uint8_t res116[0xc01c]; 465 uint32_t bpll_lock; /* 0x10030010 */ 466 uint8_t res117[0xfc]; 467 uint32_t bpll_con0; 468 uint32_t bpll_con1; 469 uint8_t res118[0xe8]; 470 uint32_t clk_src_cdrex; 471 uint8_t res119[0x1fc]; 472 uint32_t clk_mux_stat_cdrex; 473 uint8_t res120[0xfc]; 474 uint32_t clk_div_cdrex0; 475 uint32_t clk_div_cdrex1; 476 uint8_t res121[0xf8]; 477 uint32_t clk_div_stat_cdrex; 478 uint8_t res1211[0xfc]; 479 uint32_t clk_gate_bus_cdrex; 480 uint32_t clk_gate_bus_cdrex1; 481 uint8_t res122[0x1f8]; 482 uint32_t clk_gate_ip_cdrex; 483 uint8_t res123[0x10]; 484 uint32_t dmc_freq_ctrl; /* 0x10030914 */ 485 uint8_t res124[0x4]; 486 uint32_t pause; 487 uint32_t ddrphy_lock_ctrl; 488 uint8_t res125[0xdc]; 489 uint32_t clkout_cmu_cdrex; 490 uint32_t clkout_cmu_cdrex_div_stat; 491 uint8_t res126[0x8]; 492 uint32_t lpddr3phy_ctrl; 493 uint32_t lpddr3phy_con0; 494 uint32_t lpddr3phy_con1; 495 uint32_t lpddr3phy_con2; 496 uint32_t lpddr3phy_con3; 497 uint32_t lpddr3phy_con4; 498 uint32_t lpddr3phy_con5; /* 0x10030a28 */ 499 uint32_t pll_div2_sel; 500 uint8_t res127[0xd0]; 501 uint32_t cmu_cdrex_spare0; 502 uint32_t cmu_cdrex_spare1; 503 uint32_t cmu_cdrex_spare2; 504 uint32_t cmu_cdrex_spare3; 505 uint32_t cmu_cdrex_spare4; 506 uint8_t res128[0x34dc]; 507 uint32_t cmu_cdrex_version; /* 0x10033ff0 */ 508 uint8_t res129[0x400c]; 509 uint32_t kpll_lock; 510 uint8_t res130[0xfc]; 511 uint32_t kpll_con0; 512 uint32_t kpll_con1; 513 uint8_t res131[0xf8]; 514 uint32_t clk_src_kfc; 515 uint8_t res132[0x1fc]; 516 uint32_t clk_mux_stat_kfc; /* 0x10038400 */ 517 uint8_t res133[0xfc]; 518 uint32_t clk_div_kfc0; 519 uint8_t res134[0xfc]; 520 uint32_t clk_div_stat_kfc0; 521 uint8_t res135[0xfc]; 522 uint32_t clk_gate_bus_cpu_kfc; 523 uint8_t res136[0xfc]; 524 uint32_t clk_gate_sclk_cpu_kfc; 525 uint8_t res137[0x1fc]; 526 uint32_t clkout_cmu_kfc; 527 uint32_t clkout_cmu_kfc_div_stat;/* 0x10038a04 */ 528 uint8_t res138[0x5f8]; 529 uint32_t armclk_stopctrl_kfc; 530 uint8_t res139[0x4]; 531 uint32_t armclk_ema_ctrl_kfc; 532 uint32_t armclk_ema_status_kfc; 533 uint8_t res140[0x10]; 534 uint32_t pwr_ctrl_kfc; 535 uint32_t pwr_ctrl2_kfc; 536 uint8_t res141[0xd8]; 537 uint32_t kpll_con0_l8; 538 uint32_t kpll_con0_l7; 539 uint32_t kpll_con0_l6; 540 uint32_t kpll_con0_l5; 541 uint32_t kpll_con0_l4; 542 uint32_t kpll_con0_l3; 543 uint32_t kpll_con0_l2; 544 uint32_t kpll_con0_l1; 545 uint32_t iem_control_kfc; /* 0x10039120 */ 546 uint8_t res142[0xdc]; 547 uint32_t kpll_con1_l8; 548 uint32_t kpll_con1_l7; 549 uint32_t kpll_con1_l6; 550 uint32_t kpll_con1_l5; 551 uint32_t kpll_con1_l4; 552 uint32_t kpll_con1_l3; 553 uint32_t kpll_con1_l2; 554 uint32_t kpll_con1_l1; 555 uint8_t res143[0xe0]; 556 uint32_t clkdiv_iem_l8_kfc; /* 0x10039300 */ 557 uint32_t clkdiv_iem_l7_kfc; 558 uint32_t clkdiv_iem_l6_kfc; 559 uint32_t clkdiv_iem_l5_kfc; 560 uint32_t clkdiv_iem_l4_kfc; 561 uint32_t clkdiv_iem_l3_kfc; 562 uint32_t clkdiv_iem_l2_kfc; 563 uint32_t clkdiv_iem_l1_kfc; 564 uint8_t res144[0xe0]; 565 uint32_t l2_status_kfc; 566 uint8_t res145[0xc]; 567 uint32_t cpu_status_kfc; /* 0x10039410 */ 568 uint8_t res146[0xc]; 569 uint32_t ptm_status_kfc; 570 uint8_t res147[0xbdc]; 571 uint32_t cmu_kfc_spare0; 572 uint32_t cmu_kfc_spare1; 573 uint32_t cmu_kfc_spare2; 574 uint32_t cmu_kfc_spare3; 575 uint32_t cmu_kfc_spare4; 576 uint8_t res148[0x1fdc]; 577 uint32_t cmu_kfc_version; /* 0x1003bff0 */ 578 }; 579 check_member(exynos5420_clock, cmu_kfc_version, 0x2bff0); 580 581 static struct exynos5420_clock * const exynos_clock = 582 (void *)EXYNOS5_CLOCK_BASE; 583 584 struct exynos5_mct { 585 uint32_t mct_cfg; 586 uint8_t reserved0[0xfc]; 587 uint32_t g_cnt_l; 588 uint32_t g_cnt_u; 589 uint8_t reserved1[0x8]; 590 uint32_t g_cnt_wstat; 591 uint8_t reserved2[0xec]; 592 uint32_t g_comp0_l; 593 uint32_t g_comp0_u; 594 uint32_t g_comp0_addr_incr; 595 uint8_t reserved3[0x4]; 596 uint32_t g_comp1_l; 597 uint32_t g_comp1_u; 598 uint32_t g_comp1_addr_incr; 599 uint8_t reserved4[0x4]; 600 uint32_t g_comp2_l; 601 uint32_t g_comp2_u; 602 uint32_t g_comp2_addr_incr; 603 uint8_t reserved5[0x4]; 604 uint32_t g_comp3_l; 605 uint32_t g_comp3_u; 606 uint32_t g_comp3_addr_incr; 607 uint8_t reserved6[0x4]; 608 uint32_t g_tcon; 609 uint32_t g_int_cstat; 610 uint32_t g_int_enb; 611 uint32_t g_wstat; 612 uint8_t reserved7[0xb0]; 613 uint32_t l0_tcntb; 614 uint32_t l0_tcnto; 615 uint32_t l0_icntb; 616 uint32_t l0_icnto; 617 uint32_t l0_frcntb; 618 uint32_t l0_frcnto; 619 uint8_t reserved8[0x8]; 620 uint32_t l0_tcon; 621 uint8_t reserved9[0xc]; 622 uint32_t l0_int_cstat; 623 uint32_t l0_int_enb; 624 uint8_t reserved10[0x8]; 625 uint32_t l0_wstat; 626 uint8_t reserved11[0xbc]; 627 uint32_t l1_tcntb; 628 uint32_t l1_tcnto; 629 uint32_t l1_icntb; 630 uint32_t l1_icnto; 631 uint32_t l1_frcntb; 632 uint32_t l1_frcnto; 633 uint8_t reserved12[0x8]; 634 uint32_t l1_tcon; 635 uint8_t reserved13[0xc]; 636 uint32_t l1_int_cstat; 637 uint32_t l1_int_enb; 638 uint8_t reserved14[0x8]; 639 uint32_t l1_wstat; 640 }; 641 check_member(exynos5_mct, l1_wstat, 0x440); 642 643 static struct exynos5_mct * const exynos_mct = 644 (void *)EXYNOS5_MULTI_CORE_TIMER_BASE; 645 646 #define EXYNOS5_EPLLCON0_LOCKED_SHIFT 29 /* EPLL Locked bit position*/ 647 #define EPLL_SRC_CLOCK 24000000 /*24 MHz Crystal Input */ 648 #define TIMEOUT_EPLL_LOCK 1000 649 650 #define AUDIO_0_RATIO_MASK 0x0f 651 #define AUDIO_1_RATIO_MASK 0x0f 652 653 #define CLK_SRC_PERIC1 0x254 654 #define AUDIO1_SEL_MASK 0xf 655 #define CLK_SRC_AUDIOCDCLK1 0x0 656 #define CLK_SRC_XXTI 0x1 657 #define CLK_SRC_SCLK_EPLL 0x7 658 659 /* CON0 bit-fields */ 660 #define EPLL_CON0_MDIV_MASK 0x1ff 661 #define EPLL_CON0_PDIV_MASK 0x3f 662 #define EPLL_CON0_SDIV_MASK 0x7 663 #define EPLL_CON0_LOCKED_SHIFT 29 664 #define EPLL_CON0_MDIV_SHIFT 16 665 #define EPLL_CON0_PDIV_SHIFT 8 666 #define EPLL_CON0_SDIV_SHIFT 0 667 #define EPLL_CON0_LOCK_DET_EN_SHIFT 28 668 #define EPLL_CON0_LOCK_DET_EN_MASK 1 669 670 /* structure for epll configuration used in audio clock configuration */ 671 struct st_epll_con_val { 672 unsigned int freq_out; /* frequency out */ 673 unsigned int en_lock_det; /* enable lock detect */ 674 unsigned int m_div; /* m divider value */ 675 unsigned int p_div; /* p divider value */ 676 unsigned int s_div; /* s divider value */ 677 unsigned int k_dsm; /* k value of delta signal modulator */ 678 }; 679 680 /** 681 * Low-level function to set the clock pre-ratio for a peripheral 682 * 683 * @param periph_id Peripheral ID of peripheral to change 684 * @param divisor New divisor for this peripheral's clock 685 */ 686 void clock_ll_set_pre_ratio(enum periph_id periph_id, unsigned int divisor); 687 688 /** 689 * Low-level function to set the clock ratio for a peripheral 690 * 691 * @param periph_id Peripheral ID of peripheral to change 692 * @param divisor New divisor for this peripheral's clock 693 */ 694 void clock_ll_set_ratio(enum periph_id periph_id, unsigned int divisor); 695 696 /** 697 * Low-level function that selects the best clock scalars for a given rate and 698 * sets up the given peripheral's clock accordingly. 699 * 700 * @param periph_id Peripheral ID of peripheral to change 701 * @param rate Desired clock rate in Hz 702 * 703 * @return zero on success, negative on error 704 */ 705 int clock_set_rate(enum periph_id periph_id, unsigned int rate); 706 707 /* Clock gate unused IP */ 708 void clock_gate(void); 709 710 /* These are the ratio's for configuring ARM clock */ 711 struct arm_clk_ratios { 712 unsigned int arm_freq_mhz; /* Frequency of ARM core in MHz */ 713 714 unsigned int apll_mdiv; 715 unsigned int apll_pdiv; 716 unsigned int apll_sdiv; 717 718 unsigned int arm2_ratio; 719 unsigned int apll_ratio; 720 unsigned int pclk_dbg_ratio; 721 unsigned int atb_ratio; 722 unsigned int periph_ratio; 723 unsigned int acp_ratio; 724 unsigned int cpud_ratio; 725 unsigned int arm_ratio; 726 }; 727 728 /** 729 * Get the clock ratios for CPU configuration 730 * 731 * @return pointer to the clock ratios that we should use 732 */ 733 struct arm_clk_ratios *get_arm_clk_ratios(void); 734 735 /* 736 * Initialize clock for the device 737 */ 738 struct mem_timings; 739 void system_clock_init(void); 740 741 #endif 742