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Searched refs:CSSELR (Results 1 – 25 of 26) sorted by relevance

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/btstack/port/renesas-ek-ra6m4a-da14531/e2-project/ra/arm/CMSIS_5/CMSIS/Core/Include/
H A Dcachel1_armv7.h150 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_EnableDCache()
188 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_DisableDCache()
226 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_InvalidateDCache()
261 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_CleanDCache()
296 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_CleanInvalidateDCache()
H A Dcore_cm7.h485 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
H A Dcore_cm35p.h528 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
H A Dcore_armv8mml.h528 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
H A Dcore_cm33.h528 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
H A Dcore_cm55.h535 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
/btstack/port/stm32-l451-miromico-sx1280/Drivers/CMSIS/Include/
H A Dcore_cm7.h480 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
2288 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ in SCB_EnableDCache()
2326 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ in SCB_DisableDCache()
2364 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ in SCB_InvalidateDCache()
2399 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ in SCB_CleanDCache()
2434 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ in SCB_CleanInvalidateDCache()
H A Dcore_armv8mml.h521 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
H A Dcore_cm33.h521 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
/btstack/port/stm32-l073rz-nucleo-em9304/Drivers/CMSIS/Include/
H A Dcore_cm7.h525 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
2130 SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ in SCB_EnableDCache()
2168 SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ in SCB_DisableDCache()
2205 SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ in SCB_InvalidateDCache()
2240 SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ in SCB_CleanDCache()
2275 SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */ in SCB_CleanInvalidateDCache()
/btstack/port/stm32-f4discovery-usb/Drivers/CMSIS/Include/
H A Dcore_cm7.h480 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
2288 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ in SCB_EnableDCache()
2326 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ in SCB_DisableDCache()
2364 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ in SCB_InvalidateDCache()
2399 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ in SCB_CleanDCache()
2434 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ in SCB_CleanInvalidateDCache()
H A Dcore_armv8mml.h521 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
H A Dcore_cm33.h521 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
/btstack/port/stm32-f4discovery-usb/Drivers/CMSIS/Core/Include/
H A Dcore_cm7.h480 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
2288 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ in SCB_EnableDCache()
2326 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ in SCB_DisableDCache()
2364 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ in SCB_InvalidateDCache()
2399 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ in SCB_CleanDCache()
2434 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ in SCB_CleanInvalidateDCache()
H A Dcore_armv8mml.h521 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
H A Dcore_cm33.h521 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
/btstack/port/stm32-wb55xx-nucleo-freertos/Drivers/CMSIS/Include/
H A Dcore_cm7.h480 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
2288 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ in SCB_EnableDCache()
2326 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ in SCB_DisableDCache()
2364 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ in SCB_InvalidateDCache()
2399 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ in SCB_CleanDCache()
2434 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ in SCB_CleanInvalidateDCache()
/btstack/port/stm32-f4discovery-cc256x/Drivers/CMSIS/Include/
H A Dcore_cm7.h480 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
2288 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ in SCB_EnableDCache()
2326 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ in SCB_DisableDCache()
2364 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ in SCB_InvalidateDCache()
2399 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ in SCB_CleanDCache()
2434 SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/ /* Level 1 data cache */ in SCB_CleanInvalidateDCache()
H A Dcore_armv8mml.h521 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
H A Dcore_cm33.h521 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
/btstack/port/stm32-l476rg-nucleo-sx1280/Drivers/CMSIS/Include/
H A Dcore_cm7.h480 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
2334 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_EnableDCache()
2372 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_DisableDCache()
2410 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_InvalidateDCache()
2445 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_CleanDCache()
2480 SCB->CSSELR = 0U; /* select Level 1 data cache */ in SCB_CleanInvalidateDCache()
H A Dcore_armv8mml.h521 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
H A Dcore_cm33.h521 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member
/btstack/port/samv71-xplained-atwilc3000/ASF/thirdparty/CMSIS/Include/
H A Dcore_cm7.h435 …__IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register … member
/btstack/port/renesas-tb-s1ja-cc256x/template/btstack_example/synergy/ssp/inc/bsp/cmsis/Include/
H A Dcore_armv8mml.h477 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ member

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