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Searched refs:CoreDebug_DHCSR_S_RESTART_ST_Pos (Results 1 – 25 of 30) sorted by relevance

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/btstack/port/stm32-f4discovery-cc256x/Drivers/CMSIS/Include/
H A Dcore_armv8mbl.h1003 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< Core… macro
1004 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< Core…
H A Dcore_cm23.h1078 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< Core… macro
1079 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< Core…
H A Dcore_armv8mml.h1830 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< Core… macro
1831 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< Core…
H A Dcore_cm33.h1905 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< Core… macro
1906 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< Core…
/btstack/port/renesas-tb-s1ja-cc256x/template/btstack_example/synergy/ssp/inc/bsp/cmsis/Include/
H A Dcore_armv8mbl.h1050 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< Core… macro
1051 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< Core…
H A Dcore_cm23.h1050 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< Core… macro
1051 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< Core…
/btstack/port/stm32-l476rg-nucleo-sx1280/Drivers/CMSIS/Include/
H A Dcore_armv8mbl.h1003 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< Core… macro
1004 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< Core…
H A Dcore_cm23.h1078 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< Core… macro
1079 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< Core…
H A Dcore_armv8mml.h1735 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< Core… macro
1736 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< Core…
H A Dcore_cm33.h1810 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< Core… macro
1811 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< Core…
/btstack/port/stm32-f4discovery-usb/Drivers/CMSIS/Core/Include/
H A Dcore_armv8mbl.h1003 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< Core… macro
1004 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< Core…
H A Dcore_cm23.h1078 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< Core… macro
1079 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< Core…
H A Dcore_armv8mml.h1830 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< Core… macro
1831 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< Core…
H A Dcore_cm33.h1905 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< Core… macro
1906 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< Core…
/btstack/port/stm32-l451-miromico-sx1280/Drivers/CMSIS/Include/
H A Dcore_armv8mbl.h1003 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< Core… macro
1004 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< Core…
H A Dcore_cm23.h1078 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< Core… macro
1079 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< Core…
H A Dcore_armv8mml.h1830 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< Core… macro
1831 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< Core…
H A Dcore_cm33.h1905 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< Core… macro
1906 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< Core…
/btstack/port/stm32-f4discovery-usb/Drivers/CMSIS/Include/
H A Dcore_armv8mbl.h1003 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< Core… macro
1004 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< Core…
H A Dcore_cm23.h1078 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< Core… macro
1079 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< Core…
H A Dcore_armv8mml.h1830 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< Core… macro
1831 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< Core…
H A Dcore_cm33.h1905 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< Core… macro
1906 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< Core…
/btstack/port/renesas-ek-ra6m4a-da14531/e2-project/ra/arm/CMSIS_5/CMSIS/Core/Include/
H A Dcore_armv8mbl.h1006 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \dep… macro
1007 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \dep…
H A Dcore_cm23.h1081 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \dep… macro
1082 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \dep…
H A Dcore_cm35p.h1823 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \dep… macro
1824 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \dep…

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