1 
2 /****************************************************************************************************//**
3  * @file     s1ja.h
4  *
5  * @brief    CMSIS Cortex-M4 Peripheral Access Layer Header File for
6  *           R7FS3A7x from Renesas.
7  *
8  * @version  V1.2
9  * @date     5. December 2014
10  *
11  * @note     Generated with SVDConv V2.85b
12  *           from CMSIS SVD File 'R7FS1JAx.svd' Version 1.2, Hand edited 9/11/2017
13  *******************************************************************************************************/
14 
15 
16 
17 /** @addtogroup Renesas
18   * @{
19   */
20 
21 /** @addtogroup R7FS1JAx
22   * @{
23   */
24 
25 #ifndef R7FS1JAX_H
26 #define R7FS1JAX_H
27 
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31 
32 /* -------------------------  Interrupt Number Definition  ------------------------ */
33 
34 typedef enum {
35 /* -------------------  Cortex-M0 Processor Exceptions Numbers  ------------------- */
36   Reset_IRQn                    = -15,              /*!<   1  Reset Vector, invoked on Power up and warm reset                 */
37   NonMaskableInt_IRQn           = -14,              /*!<   2  Non maskable Interrupt, cannot be stopped or preempted           */
38   HardFault_IRQn                = -13,              /*!<   3  Hard Fault, all classes of Fault                                 */
39   MemoryManagement_IRQn         = -12,              /*!<   4  Memory Management, MPU mismatch, including Access Violation
40                                                          and No Match                                                          */
41   BusFault_IRQn                 = -11,              /*!<   5  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
42                                                          related Fault                                                         */
43   UsageFault_IRQn               = -10,              /*!<   6  Usage Fault, i.e. Undef Instruction, Illegal State Transition    */
44   SVCall_IRQn                   =  -5,              /*!<  11  System Service Call via SVC instruction                          */
45   DebugMonitor_IRQn             =  -4,              /*!<  12  Debug Monitor                                                    */
46   PendSV_IRQn                   =  -2,              /*!<  14  Pendable request for system service                              */
47   SysTick_IRQn                  =  -1,              /*!<  15  System Tick Timer                                                */
48 } IRQn_Type;
49 
50 /** @addtogroup Configuration_of_CMSIS
51   * @{
52   */
53 
54 
55 /* ================================================================================ */
56 /* ================      Processor and Core Peripheral Section     ================ */
57 /* ================================================================================ */
58 
59 /* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
60 #define __CM0_REV                 0x0001            /*!< Cortex-M0 Core Revision                                               */
61 #define __MPU_PRESENT                  1            /*!< MPU present or not                                                    */
62 #define __NVIC_PRIO_BITS               2            /*!< Number of Bits used for Priority Levels                               */
63 #define __Vendor_SysTickConfig         0            /*!< Set to 1 if different SysTick Config is used                          */
64 #define __FPU_PRESENT                  0            /*!< FPU present or not                                                    */
65 #define __VTOR_PRESENT                 1            /*!< Vector table VTOR register available or not                           */
66 /** @} */ /* End of group Configuration_of_CMSIS */
67 
68 #include "core_armv8mbl.h"                          /*!< Cortex-M23 (ARMv8MBL) processor and core peripherals                  */
69 #include "system_S1JA.h"                            /*!< S1JA System                                                           */
70 
71 
72 /* ================================================================================ */
73 /* ================       Device Specific Peripheral Section       ================ */
74 /* ================================================================================ */
75 
76 
77 /** @addtogroup Device_Peripheral_Registers
78   * @{
79   */
80 
81 #ifndef __IM                                    /*!< Fallback for older CMSIS versions                                         */
82   #define __IM   __I
83 #endif
84 #ifndef __OM                                    /*!< Fallback for older CMSIS versions                                         */
85   #define __OM   __O
86 #endif
87 #ifndef __IOM                                   /*!< Fallback for older CMSIS versions                                         */
88   #define __IOM  __IO
89 #endif
90 
91 /* -------  Start of section using anonymous unions and disabling warnings  ------- */
92 #if   defined (__CC_ARM)
93   #pragma push
94   #pragma anon_unions
95 #elif defined (__ICCARM__)
96   #pragma language=extended
97 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
98   #pragma clang diagnostic push
99   #pragma clang diagnostic ignored "-Wc11-extensions"
100   #pragma clang diagnostic ignored "-Wreserved-id-macro"
101 #elif defined (__GNUC__)
102   /* anonymous unions are enabled by default */
103 #elif defined (__TMS470__)
104   /* anonymous unions are enabled by default */
105 #elif defined (__TASKING__)
106   #pragma warning 586
107 #elif defined (__CSMC__)
108   /* anonymous unions are enabled by default */
109 #else
110   #warning Not supported compiler type
111 #endif
112 
113 
114 typedef struct {
115   union {
116     __IO uint32_t  MMPUACAn;                        /*!< Group A Region %s Access Control Register                             */
117 
118     struct {
119       __IO uint32_t  ENABLE     :  1;               /*!< Region enable                                                         */
120       __IO uint32_t  RP         :  1;               /*!< Read protection                                                       */
121       __IO uint32_t  WP         :  1;               /*!< Write protection                                                      */
122     } MMPUACAn_b;                                   /*!< BitSize                                                               */
123   };
124 
125   union {
126     __IO uint32_t  MMPUSAn;                         /*!< Group A Region %s Start Address Register                              */
127 
128     struct {
129       __IO uint32_t  MMPUSA     : 32;               /*!< Address where the region starts, for use in region determination.
130                                                          NOTE: The low-order 2 bits are fixed to 0.                            */
131     } MMPUSAn_b;                                    /*!< BitSize                                                               */
132   };
133 
134   union {
135     __IO uint32_t  MMPUEAn;                         /*!< Group A Region %s End Address Register                                */
136 
137     struct {
138       __IO uint32_t  MMPUEA     : 32;               /*!< Region end address register Address where the region end, for
139                                                          use in region determination. NOTE: The low-order 2 bits are
140                                                           fixed to 1.                                                          */
141     } MMPUEAn_b;                                    /*!< BitSize                                                               */
142   };
143   __I  uint32_t  RESERVED;
144 } R_MMPU_MMPUACAnRC0_Type;
145 
146 typedef struct {
147   union {
148     __IO uint32_t  MMPUACBn;                        /*!< Group B Region %s Access Control Register                             */
149 
150     struct {
151       __IO uint32_t  ENABLE     :  1;               /*!< Region enable                                                         */
152       __IO uint32_t  RP         :  1;               /*!< Read protection                                                       */
153       __IO uint32_t  WP         :  1;               /*!< Write protection                                                      */
154     } MMPUACBn_b;                                   /*!< BitSize                                                               */
155   };
156 
157   union {
158     __IO uint32_t  MMPUSBn;                         /*!< Group B Region %s Start Address Register                              */
159 
160     struct {
161       __IO uint32_t  MMPUSB     : 32;               /*!< Address where the region starts, for use in region determination.
162                                                          NOTE: The low-order 2 bits are fixed to 0.                            */
163     } MMPUSBn_b;                                    /*!< BitSize                                                               */
164   };
165 
166   union {
167     __IO uint32_t  MMPUEBn;                         /*!< Group B Region %s End Address Register                                */
168 
169     struct {
170       __IO uint32_t  MMPUEB     : 32;               /*!< Region end address register Address where the region end, for
171                                                          use in region determination. NOTE: The low-order 2 bits are
172                                                           fixed to 1.                                                          */
173     } MMPUEBn_b;                                    /*!< BitSize                                                               */
174   };
175   __I  uint32_t  RESERVED1;
176 } R_MMPU_MMPUACBnRC0_Type;
177 
178 typedef struct {
179   union {
180     __IO uint32_t  MMPUACCn;                        /*!< Group C Region %s Access Control Register                             */
181 
182     struct {
183       __IO uint32_t  ENABLE     :  1;               /*!< Region enable                                                         */
184       __IO uint32_t  RP         :  1;               /*!< Read protection                                                       */
185       __IO uint32_t  WP         :  1;               /*!< Write protection                                                      */
186     } MMPUACCn_b;                                   /*!< BitSize                                                               */
187   };
188 
189   union {
190     __IO uint32_t  MMPUSCn;                         /*!< Group C Region %s Start Address Register                              */
191 
192     struct {
193       __IO uint32_t  MMPUSC     : 32;               /*!< Address where the region starts, for use in region determination.
194                                                          NOTE: The low-order 2 bits are fixed to 0.                            */
195     } MMPUSCn_b;                                    /*!< BitSize                                                               */
196   };
197 
198   union {
199     __IO uint32_t  MMPUECn;                         /*!< Group C Region %s Start Address Register                              */
200 
201     struct {
202       __IO uint32_t  MMPUEC     : 32;               /*!< Region end address register Address where the region end, for
203                                                          use in region determination. NOTE: The low-order 2 bits are
204                                                           fixed to 1.                                                          */
205     } MMPUECn_b;                                    /*!< BitSize                                                               */
206   };
207   __I  uint32_t  RESERVED2;
208 } R_MMPU_MMPUACCnRC0_Type;
209 
210 typedef struct {
211   union {
212     __IO uint16_t  SMPUSRAMn;                       /*!< Access Control Register for SRAM%s                                    */
213 
214     struct {
215       __IO uint16_t  RP_CPU     :  1;               /*!< CPU Read protection                                                   */
216       __IO uint16_t  WP_CPU     :  1;               /*!< CPU Write protection                                                  */
217       __IO uint16_t  RP_GRPA    :  1;               /*!< Master Group A Read protection                                        */
218       __IO uint16_t  WP_GRPA    :  1;               /*!< Master Group A Write protection                                       */
219       __IO uint16_t  RP_GRPB    :  1;               /*!< Master Group B Read protection                                        */
220       __IO uint16_t  WP_GRPB    :  1;               /*!< Master Group B Write protection                                       */
221       __IO uint16_t  RP_GRPC    :  1;               /*!< Master Group C Read protection                                        */
222       __IO uint16_t  WP_GRPC    :  1;               /*!< Master Group C Write protection                                       */
223     } SMPUSRAMn_b;                                  /*!< BitSize                                                               */
224   };
225   __I  uint16_t  RESERVED3;
226 } R_SMPU_SMPUSRAMnRC0_Type;
227 
228 typedef struct {
229   __I  uint16_t  RESERVED4;
230 
231   union {
232     __IO uint16_t  CSnMOD;                          /*!< CS%s Mode Register                                                    */
233 
234     struct {
235       __IO uint16_t  WRMOD      :  1;               /*!< Write Access Mode Select                                              */
236            uint16_t             :  2;
237       __IO uint16_t  EWENB      :  1;               /*!< External Wait Enable                                                  */
238            uint16_t             :  4;
239       __IO uint16_t  PRENB      :  1;               /*!< Page Read Access Enable                                               */
240       __IO uint16_t  PWENB      :  1;               /*!< Page Write Access Enable                                              */
241            uint16_t             :  5;
242       __IO uint16_t  PRDMOD     :  1;               /*!< Page Read Access Mode Select                                          */
243     } CSnMOD_b;                                     /*!< BitSize                                                               */
244   };
245 
246   union {
247     __IO uint32_t  CSnWCR1;                         /*!< CS%s Wait Control Register 1                                          */
248 
249     struct {
250       __IO uint32_t  CSPWWAIT   :  3;               /*!< Page Write Cycle Wait Select NOTE: The CSPWWAIT value is valid
251                                                          only when the PWENB bit in CSnMOD is set to 1.                        */
252            uint32_t             :  5;
253       __IO uint32_t  CSPRWAIT   :  3;               /*!< Page Read Cycle Wait Select NOTE: The CSPRWAIT value is valid
254                                                          only when the PRENB bit in CSnMOD is set to 1.                        */
255            uint32_t             :  5;
256       __IO uint32_t  CSWWAIT    :  5;               /*!< Normal Write Cycle Wait Select                                        */
257            uint32_t             :  3;
258       __IO uint32_t  CSRWAIT    :  5;               /*!< Normal Read Cycle Wait Select                                         */
259     } CSnWCR1_b;                                    /*!< BitSize                                                               */
260   };
261 
262   union {
263     __IO uint32_t  CSnWCR2;                         /*!< CS%s Wait Control Register 2                                          */
264 
265     struct {
266            uint32_t             :  2;
267       __IO uint32_t  CSROFF     :  1;               /*!< Read-Access CS Extension Cycle Select                                 */
268            uint32_t             :  3;
269       __IO uint32_t  CSWOFF     :  1;               /*!< Write-Access CS Extension Cycle Select                                */
270            uint32_t             :  3;
271       __IO uint32_t  WDOFF      :  1;               /*!< Write Data Output Extension Cycle Select                              */
272            uint32_t             :  2;
273       __IO uint32_t  AWAIT      :  1;               /*!< Address Cycle Wait Select                                             */
274            uint32_t             :  4;
275       __IO uint32_t  RDON       :  1;               /*!< RD Assert Wait Select                                                 */
276            uint32_t             :  3;
277       __IO uint32_t  WRON       :  1;               /*!< WR Assert Wait Select                                                 */
278            uint32_t             :  3;
279       __IO uint32_t  WDON       :  1;               /*!< Write Data Output Wait Select                                         */
280            uint32_t             :  1;
281       __IO uint32_t  CSON       :  3;               /*!< CS Assert Wait Select                                                 */
282     } CSnWCR2_b;                                    /*!< BitSize                                                               */
283   };
284   __I  uint32_t  RESERVED5;
285 } CSRC0_Type;
286 
287 typedef struct {
288   __I  uint16_t  RESERVED6;
289 
290   union {
291     __IO uint16_t  CSnCR;                           /*!< CS%s Control Register                                                 */
292 
293     struct {
294       __IO uint16_t  EXENB      :  1;               /*!< Operation Enable                                                      */
295            uint16_t             :  3;
296       __IO uint16_t  BSIZE      :  2;               /*!< External Bus Width Select                                             */
297            uint16_t             :  2;
298       __IO uint16_t  EMODE      :  1;               /*!< Endian Mode                                                           */
299     } CSnCR_b;                                      /*!< BitSize                                                               */
300   };
301   __I  uint16_t  RESERVED7[3];
302 
303   union {
304     __IO uint16_t  CSnREC;                          /*!< CS%s Recovery Cycle Register                                          */
305 
306     struct {
307       __IO uint16_t  RRCV       :  4;               /*!< Read Recovery                                                         */
308            uint16_t             :  4;
309       __IO uint16_t  WRCV       :  4;               /*!< Write Recovery                                                        */
310     } CSnREC_b;                                     /*!< BitSize                                                               */
311   };
312   __I  uint32_t  RESERVED8;
313 } CSRC1_Type;
314 
315 typedef struct {
316   union {
317     __I  uint32_t  BUSnERRADD;                      /*!< Bus Error Address Register %s                                         */
318 
319     struct {
320       __I  uint32_t  BERAD      : 32;               /*!< Bus Error Address When a bus error occurs, It stores an error
321                                                          address..                                                             */
322     } BUSnERRADD_b;                                 /*!< BitSize                                                               */
323   };
324 
325   union {
326     __I  uint8_t   BUSnERRSTAT;                     /*!< Bus Error Status Register %s                                          */
327 
328     struct {
329       __I  uint8_t   ACCSTS     :  1;               /*!< Error access status The status at the time of the error               */
330            uint8_t              :  6;
331       __I  uint8_t   ERRSTAT    :  1;               /*!< Bus Error Status When bus error assert, error flag occurs.            */
332     } BUSnERRSTAT_b;                                /*!< BitSize                                                               */
333   };
334   __I  uint8_t   RESERVED9[11];
335 } BUSnERRRC0_Type;
336 
337 typedef struct {
338   union {
339     __IO uint16_t  DELSRn;                          /*!< DMAC Event Link Setting Register %s                                   */
340 
341     struct {
342       __IO uint16_t  DELS       :  9;               /*!< Event selection to DMAC Start request                                 */
343     } DELSRn_b;                                     /*!< BitSize                                                               */
344   };
345   __I  uint16_t  RESERVED10;
346 } R_ICU_DELSRn_Type;
347 
348 typedef struct {
349   union {
350     __IO uint8_t   LVDnCR1;                         /*!< Voltage Monitoring %s Circuit Control Register 1                      */
351 
352     struct {
353       __IO uint8_t   IDTSEL     :  2;               /*!< Voltage Monitoring Interrupt Generation Condition Select              */
354       __IO uint8_t   IRQSEL     :  1;               /*!< Voltage Monitoring Interrupt Type Select                              */
355     } LVDnCR1_b;                                    /*!< BitSize                                                               */
356   };
357 
358   union {
359     __IO uint8_t   LVDnSR;                          /*!< Voltage Monitoring %s Circuit Status Register                         */
360 
361     struct {
362       __IO uint8_t   DET        :  1;               /*!< Voltage Monitoring Voltage Change Detection Flag NOTE: Only
363                                                          0 can be written to this bit. After writing 0 to this bit, it
364                                                           takes 2 system clock cycles for the bit to be read as 0.             */
365       __I  uint8_t   MON        :  1;               /*!< Voltage Monitoring 1 Signal Monitor Flag                              */
366     } LVDnSR_b;                                     /*!< BitSize                                                               */
367   };
368 } R_SYSTEM_LVDnRC0_Type;
369 
370 typedef struct {
371   union {
372     __IO uint8_t   ELSEGRn;                         /*!< Event Link Software Event Generation Register %s                      */
373 
374     struct {
375       __O  uint8_t   SEG        :  1;               /*!< Software Event Generation                                             */
376            uint8_t              :  5;
377       __IO uint8_t   WE         :  1;               /*!< SEG Bit Write Enable                                                  */
378       __O  uint8_t   WI         :  1;               /*!< ELSEGR Register Write Disable                                         */
379     } ELSEGRn_b;                                    /*!< BitSize                                                               */
380   };
381   __I  uint8_t   RESERVED11;
382 } R_ELC_ELSEGRnRC0_Type;
383 
384 typedef struct {
385   union {
386     __IO uint16_t  ELSRn;                           /*!< Event Link Setting Register %s                                        */
387 
388     struct {
389       __IO uint16_t  ELS        :  9;               /*!< Event Link Select                                                     */
390     } ELSRn_b;                                      /*!< BitSize                                                               */
391   };
392   __I  uint16_t  RESERVED12;
393 } R_ELC_ELSRnRC0_Type;
394 
395 typedef struct {
396   union {
397     __IO uint8_t   RTCCRn;                          /*!< Time Capture Control Register %s                                      */
398 
399     struct {
400       __IO uint8_t   TCCT       :  2;               /*!< Time Capture Control                                                  */
401       __I  uint8_t   TCST       :  1;               /*!< Time Capture Status                                                   */
402            uint8_t              :  1;
403       __IO uint8_t   TCNF       :  2;               /*!< Time Capture Noise Filter Control                                     */
404            uint8_t              :  1;
405       __IO uint8_t   TCEN       :  1;               /*!< Time Capture Event Input Pin Enable                                   */
406     } RTCCRn_b;                                     /*!< BitSize                                                               */
407   };
408   __I  uint8_t   RESERVED13;
409 } R_RTC_RTCCRnRC0_Type;
410 
411 typedef struct {
412   union {
413     union {
414       __I  uint8_t   BCNT0CPn;                      /*!< BCNT0 Capture Register %s                                             */
415 
416       struct {
417         __I  uint8_t   BCNT0CP  :  8;               /*!< BCNT0CP is a read-only register that captures the BCNT0 value
418                                                          when a time capture event is detected.                                */
419       } BCNT0CPn_b;                                 /*!< BitSize                                                               */
420     };
421 
422     union {
423       __I  uint8_t   RSECCPn;                       /*!< Second Capture Register %s                                            */
424 
425       struct {
426         __I  uint8_t   SEC1     :  4;               /*!< 1-Second Capture Capture value for the ones place of seconds          */
427         __I  uint8_t   SEC10    :  3;               /*!< 10-Second Capture Capture value for the tens place of seconds         */
428       } RSECCPn_b;                                  /*!< BitSize                                                               */
429     };
430   };
431   __I  uint8_t   RESERVED14;
432 
433   union {
434     union {
435       __I  uint8_t   BCNT1CPn;                      /*!< BCNT1 Capture Register %s                                             */
436 
437       struct {
438         __I  uint8_t   BCNT1CP  :  8;               /*!< BCNT1CP is a read-only register that captures the BCNT1 value
439                                                          when a time capture event is detected.                                */
440       } BCNT1CPn_b;                                 /*!< BitSize                                                               */
441     };
442 
443     union {
444       __I  uint8_t   RMINCPn;                       /*!< Minute Capture Register %s                                            */
445 
446       struct {
447         __I  uint8_t   MIN1     :  4;               /*!< 1-Minute Capture Capture value for the ones place of minutes          */
448         __I  uint8_t   MIN10    :  3;               /*!< 10-Minute Capture Capture value for the tens place of minutes         */
449       } RMINCPn_b;                                  /*!< BitSize                                                               */
450     };
451   };
452   __I  uint8_t   RESERVED15;
453 
454   union {
455     union {
456       __I  uint8_t   BCNT2CPn;                      /*!< BCNT2 Capture Register %s                                             */
457 
458       struct {
459         __I  uint8_t   BCNT2CP  :  8;               /*!< BCNT2CP is a read-only register that captures the BCNT2 value
460                                                          when a time capture event is detected.                                */
461       } BCNT2CPn_b;                                 /*!< BitSize                                                               */
462     };
463 
464     union {
465       __I  uint8_t   RHRCPn;                        /*!< Hour Capture Register %s                                              */
466 
467       struct {
468         __I  uint8_t   HR1      :  4;               /*!< 1-Minute Capture Capture value for the ones place of minutes          */
469         __I  uint8_t   HR10     :  2;               /*!< 10-Minute Capture Capture value for the tens place of minutes         */
470         __I  uint8_t   PM       :  1;               /*!< PM                                                                    */
471       } RHRCPn_b;                                   /*!< BitSize                                                               */
472     };
473   };
474   __I  uint8_t   RESERVED16[3];
475 
476   union {
477     union {
478       __I  uint8_t   BCNT3CPn;                      /*!< BCNT3 Capture Register %s                                             */
479 
480       struct {
481         __I  uint8_t   BCNT3CP  :  8;               /*!< BCNT3CP is a read-only register that captures the BCNT3 value
482                                                          when a time capture event is detected.                                */
483       } BCNT3CPn_b;                                 /*!< BitSize                                                               */
484     };
485 
486     union {
487       __I  uint8_t   RDATECPn;                      /*!< Date Capture Register %s                                              */
488 
489       struct {
490         __I  uint8_t   DATE1    :  4;               /*!< 1-Day Capture Capture value for the ones place of minutes             */
491         __I  uint8_t   DATE10   :  2;               /*!< 10-Day Capture Capture value for the tens place of minutes            */
492       } RDATECPn_b;                                 /*!< BitSize                                                               */
493     };
494   };
495   __I  uint8_t   RESERVED17;
496 
497   union {
498     __I  uint8_t   RMONCPn;                         /*!< Month Capture Register %s                                             */
499 
500     struct {
501       __I  uint8_t   MON1       :  4;               /*!< 1-Month Capture Capture value for the ones place of months            */
502       __I  uint8_t   MON10      :  1;               /*!< 10-Month Capture Capture value for the tens place of months           */
503     } RMONCPn_b;                                    /*!< BitSize                                                               */
504   };
505   __I  uint8_t   RESERVED18[5];
506 } R_RTC_CnRC0_Type;
507 
508 typedef struct {
509   union {
510     __IO uint32_t  MBn_ID;                          /*!< Mailbox Register ID                                                   */
511 
512     struct {
513       __IO uint32_t  EID        : 18;               /*!< Extended ID                                                           */
514       __IO uint32_t  SID        : 11;               /*!< Standard ID                                                           */
515            uint32_t             :  1;
516       __IO uint32_t  RTR        :  1;               /*!< Remote Transmission Request                                           */
517       __IO uint32_t  IDE        :  1;               /*!< ID Extension                                                          */
518     } MBn_ID_b;                                     /*!< BitSize                                                               */
519   };
520   __I  uint8_t   RESERVED19;
521 
522   union {
523     __IO uint8_t   MBn_DL;                          /*!< Mailbox Register DL                                                   */
524 
525     struct {
526       __IO uint8_t   DLC        :  4;               /*!< Data Length Code                                                      */
527     } MBn_DL_b;                                     /*!< BitSize                                                               */
528   };
529   __IO uint8_t   MBn_D[8];                          /*!< Mailbox Register Data %s                                              */
530 
531   union {
532     __IO uint16_t  MBn_TS;                          /*!< Mailbox Register TS                                                   */
533 
534     struct {
535       __IO uint16_t  TSL        :  8;               /*!< Time Stamp Higher Byte Bits TSL[7:0] store the counter value
536                                                          of the time stamp when received messages are stored in the mailbox.   */
537       __IO uint16_t  TSH        :  8;               /*!< Time Stamp Lower Byte Bits TSH[7:0] store the counter value
538                                                          of the time stamp when received messages are stored in the mailbox.   */
539     } MBn_TS_b;                                     /*!< BitSize                                                               */
540   };
541 } R_CAN0_MBn_Type;
542 
543 typedef struct {
544   union {
545     __IO uint8_t   SARLn;                           /*!< Slave Address Register L%s                                            */
546 
547     struct {
548       __IO uint8_t   SVA        :  8;               /*!< A slave address is set.7-Bit Address = SVA[7:1] 10-Bit Address
549                                                          = { SVA9,SVA8,SVA[7:0] }                                              */
550     } SARLn_b;                                      /*!< BitSize                                                               */
551   };
552 
553   union {
554     __IO uint8_t   SARUn;                           /*!< Slave Address Register U%s                                            */
555 
556     struct {
557       __IO uint8_t   FS         :  1;               /*!< 7-Bit/10-Bit Address Format Selection                                 */
558       __IO uint8_t   SVA8       :  1;               /*!< 10-Bit Address(bit8)                                                  */
559       __IO uint8_t   SVA9       :  1;               /*!< 10-Bit Address(bit9)                                                  */
560     } SARUn_b;                                      /*!< BitSize                                                               */
561   };
562 } R_IIC0_SARLnRC0_Type;
563 
564 typedef struct {
565   union {
566     union {
567       __IO uint32_t  GTDLYRn;                       /*!< GTIOC%s Rising Output Delay Register                                  */
568 
569       struct {
570         __IO uint32_t  DLYA     :  5;               /*!< GTIOCnA Output Rising Edge Delay Setting                              */
571              uint32_t           : 11;
572         __IO uint32_t  DLYB     :  5;               /*!< GTIOCnB Output Rising Edge Delay Setting                              */
573       } GTDLYRn_b;                                  /*!< BitSize                                                               */
574     };
575 
576     struct {
577       union {
578         __IO uint16_t  GTDLYRnA;                    /*!< GTIOC%sA Rising Output Delay Register                                 */
579 
580         struct {
581           __IO uint16_t  DLY    :  5;               /*!< GTIOCnA Output Rising Edge Delay Setting                              */
582         } GTDLYRnA_b;                               /*!< BitSize                                                               */
583       };
584 
585       union {
586         __IO uint16_t  GTDLYRnB;                    /*!< GTIOC%sB Rising Output Delay Register                                 */
587 
588         struct {
589           __IO uint16_t  DLY    :  5;               /*!< GTIOCnB Output Rising Edge Delay Setting                              */
590         } GTDLYRnB_b;                               /*!< BitSize                                                               */
591       };
592     };
593   };
594 } R_GPT_ODC_GTDLYRnRC0_Type;
595 
596 typedef struct {
597   union {
598     union {
599       __IO uint32_t  GTDLYFn;                       /*!< GTIOC%s Falling Output Delay Register                                 */
600 
601       struct {
602         __IO uint32_t  DLYA     :  5;               /*!< GTIOCnA Output Falling Edge Delay Setting                             */
603              uint32_t           : 11;
604         __IO uint32_t  DLYB     :  5;               /*!< GTIOCnB Output Falling Edge Delay Setting                             */
605       } GTDLYFn_b;                                  /*!< BitSize                                                               */
606     };
607 
608     struct {
609       union {
610         __IO uint16_t  GTDLYFnA;                    /*!< GTIOC%sA Falling Output Delay Register                                */
611 
612         struct {
613           __IO uint16_t  DLY    :  5;               /*!< GTIOCnA Output Falling Edge Delay Setting                             */
614         } GTDLYFnA_b;                               /*!< BitSize                                                               */
615       };
616 
617       union {
618         __IO uint16_t  GTDLYFnB;                    /*!< GTIOC%sB Falling Output Delay Register                                */
619 
620         struct {
621           __IO uint16_t  DLY    :  5;               /*!< GTIOCnB Output Falling Edge Delay Setting                             */
622         } GTDLYFnB_b;                               /*!< BitSize                                                               */
623       };
624     };
625   };
626 } R_GPT_ODC_GTDLYFnRC0_Type;
627 
628 /* =========================================================================================================================== */
629 /* ================            R_ACMPHS0 - High-Speed Analog Comparator 0 (R_ACMPHS0)                         ================ */
630 /* Note: 9/12/17 - The following structure for R_ACMPHS0 was hand edited using the output from the R7FS1JA7.svd output file    */
631 /* =========================================================================================================================== */
632 /**
633   * @brief High-Speed Analog Comparator 0 (ACMPHS0)
634   */
635 
636 typedef struct {
637     union {
638       __IOM uint8_t CMPCTL;                       /*!< (@ 0x00000000) Comparator Control Register                                */
639 
640       struct {
641         __IOM uint8_t CINV        : 1;            /*!< [0..0] Comparator output polarity selection                               */
642         __IOM uint8_t COE         : 1;            /*!< [1..1] Comparator output enable                                           */
643         __IM  uint8_t             : 1;
644         __IOM uint8_t CEG         : 2;            /*!< [4..3] Selection of valid edge (Edge selector)                            */
645         __IOM uint8_t CDFS        : 2;            /*!< [6..5] Noise filter selection                                             */
646         __IOM uint8_t HCMPON      : 1;            /*!< [7..7] Comparator operation control                                       */
647       } CMPCTL_b;
648     } ;
649     __IM  uint8_t   RESERVED;
650     __IM  uint16_t  RESERVED1;
651 
652     union {
653       __IOM uint8_t CMPSEL0;                      /*!< (@ 0x00000004) Comparator Input Select Register                           */
654 
655       struct {
656         __IOM uint8_t CMPSEL      : 3;            /*!< [2..0] Comparator input selection                                         */
657       } CMPSEL0_b;
658     } ;
659     __IM  uint8_t   RESERVED2;
660     __IM  uint16_t  RESERVED3;
661 
662     union {
663       __IOM uint8_t CMPSEL1;                      /*!< (@ 0x00000008) Comparator Reference Voltage Select Register               */
664 
665       struct {
666         __IOM uint8_t CRVS        : 6;            /*!< [5..0] Reference voltage selection                                        */
667       } CMPSEL1_b;
668     } ;
669     __IM  uint8_t   RESERVED4;
670     __IM  uint16_t  RESERVED5;
671 
672     union {
673       __IM  uint8_t CMPMON;                       /*!< (@ 0x0000000C) Comparator Output Monitor Register                         */
674 
675       struct {
676         __IM  uint8_t CMPMON      : 1;            /*!< [0..0] Comparator output monitor                                          */
677       } CMPMON_b;
678     } ;
679     __IM  uint8_t   RESERVED6;
680     __IM  uint16_t  RESERVED7;
681 
682     union {
683       __IOM uint8_t CPIOC;                        /*!< (@ 0x00000010) Comparator Output Control Register                         */
684 
685       struct {
686         __IOM uint8_t CPOE        : 1;            /*!< [0..0] Comparator output selection                                        */
687         __IM  uint8_t             : 6;
688         __IOM uint8_t VREFEN      : 1;            /*!< [7..7] Internal Vref enable                                               */
689       } CPIOC_b;
690     } ;
691   __I  uint8_t   RESERVED24[239];
692 } R_ACMPHS0_Type;
693 
694 /* =========================================================================================================================== */
695 /* ================                                          R_ACMPLP                                         ================ */
696 /* Note: 9/12/17 - The following structure for R_ACMPLP was hand edited using the output from the R7FS1JA7.svd output file     */
697 /* =========================================================================================================================== */
698 
699 
700 /**
701   * @brief Low-Power Analog Comparator (R_ACMPLP)
702   */
703 
704 typedef struct {                                /*!< (@ 0x40085E00) ACMPLP Structure                                           */
705 
706   union {
707     __IOM uint8_t COMPMDR;                      /*!< (@ 0x00000000) ACMPLP Mode Setting Register                               */
708 
709     struct {
710       __IOM uint8_t C0ENB       : 1;            /*!< [0..0] ACMPLP0 Operation Enable                                           */
711       __IOM uint8_t C0WDE       : 1;            /*!< [1..1] ACMPLP0 Window Function Mode Enable                                */
712       __IOM uint8_t C0VRF       : 1;            /*!< [2..2] ACMPLP0 Reference Voltage SelectionNote1: It's effective
713                                                      only at the time of standard mode.IVREF0 and IVREF1 are
714                                                      chosen at window mode condition in spite of setting of
715                                                      this bit.                                                                 */
716       __IOM uint8_t C0MON       : 1;            /*!< [3..3] ACMPLP0 Monitor Flag                                               */
717       __IOM uint8_t C1ENB       : 1;            /*!< [4..4] ACMPLP1 Operation Enable                                           */
718       __IOM uint8_t C1WDE       : 1;            /*!< [5..5] ACMPLP1 Window Function Mode Enable                                */
719       __IOM uint8_t C1VRF       : 1;            /*!< [6..6] ACMPLP1 Reference Voltage SelectionNote1: It's effective
720                                                      only at the time of standard mode.IVREF0 and IVREF1 are
721                                                      chosen at window mode condition in spite of setting of
722                                                      this bit.                                                                 */
723       __IOM uint8_t C1MON       : 1;            /*!< [7..7] ACMPLP1 Monitor Flag                                               */
724     } COMPMDR_b;
725   } ;
726 
727   union {
728     __IOM uint8_t COMPFIR;                      /*!< (@ 0x00000001) ACMPLP Filter Control Register                             */
729 
730     struct {
731       __IOM uint8_t C0FCK       : 2;            /*!< [1..0] ACMPLP0 Edge Detection Selection                                   */
732       __IOM uint8_t C0EPO       : 1;            /*!< [2..2] ACMPLP0 Edge Polarity Switching                                    */
733       __IOM uint8_t C0EDG       : 1;            /*!< [3..3] ACMPLP0 Filter Select                                              */
734       __IOM uint8_t C1FCK       : 2;            /*!< [5..4] ACMPLP1 Edge Detection Selection                                   */
735       __IOM uint8_t C1EPO       : 1;            /*!< [6..6] ACMPLP1 Edge Polarity Switching                                    */
736       __IOM uint8_t C1EDG       : 1;            /*!< [7..7] ACMPLP1 Filter Select                                              */
737     } COMPFIR_b;
738   } ;
739 
740   union {
741     __IOM uint8_t COMPOCR;                      /*!< (@ 0x00000002) ACMPLP Output Control Register                             */
742 
743     struct {
744       __IM  uint8_t             : 1;
745       __IOM uint8_t C0OE        : 1;            /*!< [1..1] ACMPLP0 VCOUT Pin Output Enable                                    */
746       __IOM uint8_t C0OP        : 1;            /*!< [2..2] ACMPLP0 VCOUT Output Polarity Selection                            */
747       __IM  uint8_t             : 2;
748       __IOM uint8_t C1OE        : 1;            /*!< [5..5] ACMPLP1 VCOUT Pin Output Enable                                    */
749       __IOM uint8_t C1OP        : 1;            /*!< [6..6] ACMPLP1 VCOUT Output Polarity Selection                            */
750       __IOM uint8_t SPDMD       : 1;            /*!< [7..7] ACMPLP0/ACMPLP1 Speed Selection                                    */
751     } COMPOCR_b;
752   } ;
753   __IM  uint8_t   RESERVED;
754 
755   union {
756     __IOM uint8_t COMPSEL0;                     /*!< (@ 0x00000004) Comparator Input Select Register                           */
757 
758     struct {
759       __IOM uint8_t CMPSEL10    : 2;            /*!< [1..0] ACMPLP0 Input (IVCMP0) Selection                                   */
760       __IM  uint8_t             : 2;
761       __IOM uint8_t CMPSEL54    : 2;            /*!< [5..4] ACMPLP1 Input (IVCMP1) Selection                                   */
762     } COMPSEL0_b;
763   } ;
764 
765   union {
766     __IOM uint8_t COMPSEL1;                     /*!< (@ 0x00000005) Comparator Reference voltage Select Register               */
767 
768     struct {
769       __IOM uint8_t CRVS10      : 2;            /*!< [1..0] ACMPLP0 Reference Voltage (IVREF0) Selection                       */
770       __IM  uint8_t             : 2;
771       __IOM uint8_t CRVS54      : 2;            /*!< [5..4] ACMPLP1 Reference Voltage(IVREF1) Selection                        */
772       __IM  uint8_t             : 1;
773       __IOM uint8_t C1VRF2      : 1;            /*!< [7..7] ACMPLP1 Reference Voltage Selection                                */
774     } COMPSEL1_b;
775   } ;
776 } R_ACMPLP_Type;                                /*!< Size = 6 (0x6)                                                            */
777 
778 
779 /* ================================================================================ */
780 /* ================                     R_MMPU                     ================ */
781 /* ================================================================================ */
782 
783 
784 /**
785   * @brief Bus Master MPU (R_MMPU)
786   */
787 
788 typedef struct {                                    /*!< R_MMPU Structure                                                      */
789 
790   union {
791     __IO uint16_t  MMPUCTLA;                        /*!< Bus Master MPU Control Group A Register                               */
792 
793     struct {
794       __IO uint16_t  ENABLE     :  1;               /*!< Master Group enable                                                   */
795       __IO uint16_t  OAD        :  1;               /*!< Operation after detection                                             */
796            uint16_t             :  6;
797       __O  uint16_t  KEY        :  8;               /*!< Write KeywordThe data written to these bits are not stored.           */
798     } MMPUCTLA_b;                                   /*!< BitSize                                                               */
799   };
800   __I  uint32_t  RESERVED[64];
801 
802   union {
803     __IO uint16_t  MMPUPTA;                         /*!< Group A Protection of Register                                        */
804 
805     struct {
806       __IO uint16_t  PROTECT    :  1;               /*!< Protection of register(MMPUSAn, MMPUEAn and MMPUACAn)                 */
807            uint16_t             :  7;
808       __O  uint16_t  KEY        :  8;               /*!< Write KeywordThe data written to these bits are not stored.           */
809     } MMPUPTA_b;                                    /*!< BitSize                                                               */
810   };
811   __I  uint32_t  RESERVED1[63];
812   R_MMPU_MMPUACAnRC0_Type MMPUACAnRC0[32];          /*!< Group A Region %s Access Control Register Cluster 0                   */
813 
814   union {
815     __IO uint16_t  MMPUCTLB;                        /*!< Bus Master MPU Control Group B Register                               */
816 
817     struct {
818       __IO uint16_t  ENABLE     :  1;               /*!< Master Group enable                                                   */
819       __IO uint16_t  OAD        :  1;               /*!< Operation after detection                                             */
820            uint16_t             :  6;
821       __O  uint16_t  KEY        :  8;               /*!< Write KeywordThe data written to these bits are not stored.           */
822     } MMPUCTLB_b;                                   /*!< BitSize                                                               */
823   };
824   __I  uint32_t  RESERVED2[64];
825 
826   union {
827     __IO uint16_t  MMPUPTB;                         /*!< Group B Protection of Register                                        */
828 
829     struct {
830       __IO uint16_t  PROTECT    :  1;               /*!< Protection of register(MMPUSBn, MMPUEBn and MMPUACBn)                 */
831            uint16_t             :  7;
832       __O  uint16_t  KEY        :  8;               /*!< Write KeywordThe data written to these bits are not stored.           */
833     } MMPUPTB_b;                                    /*!< BitSize                                                               */
834   };
835   __I  uint32_t  RESERVED3[63];
836   R_MMPU_MMPUACBnRC0_Type MMPUACBnRC0[8];           /*!< Group B Region %s Access Control Register Cluster 0                   */
837   __I  uint32_t  RESERVED4[96];
838 
839   union {
840     __IO uint16_t  MMPUCTLC;                        /*!< Bus Master MPU Control Group C Register                               */
841 
842     struct {
843       __IO uint16_t  ENABLE     :  1;               /*!< Master Group enable                                                   */
844       __IO uint16_t  OAD        :  1;               /*!< Operation after detection                                             */
845            uint16_t             :  6;
846       __O  uint16_t  KEY        :  8;               /*!< Write KeywordThe data written to these bits are not stored.           */
847     } MMPUCTLC_b;                                   /*!< BitSize                                                               */
848   };
849   __I  uint32_t  RESERVED5[64];
850 
851   union {
852     __IO uint16_t  MMPUPTC;                         /*!< Group C protection of register                                        */
853 
854     struct {
855       __IO uint16_t  PROTECT    :  1;               /*!< Protection of register(MMPUSCn, MMPUECn and MMPUACCn)                 */
856            uint16_t             :  7;
857       __O  uint16_t  KEY        :  8;               /*!< Write KeywordThe data written to these bits are not stored.           */
858     } MMPUPTC_b;                                    /*!< BitSize                                                               */
859   };
860   __I  uint32_t  RESERVED6[63];
861   R_MMPU_MMPUACCnRC0_Type MMPUACCnRC0[8];           /*!< Group C Region %s Access Control Register Cluster 0                   */
862 } R_MMPU_Type;
863 
864 
865 /* ================================================================================ */
866 /* ================                     R_SMPU                     ================ */
867 /* ================================================================================ */
868 
869 
870 /**
871   * @brief Bus Slave MPU (R_SMPU)
872   */
873 
874 typedef struct {                                    /*!< R_SMPU Structure                                                      */
875 
876   union {
877     __IO uint16_t  SMPUCTL;                         /*!< Slave MPU Control Register                                            */
878 
879     struct {
880       __IO uint16_t  OAD        :  1;               /*!< Master Group enable                                                   */
881       __IO uint16_t  PROTECT    :  2;               /*!< Protection of register Protected register SMPUMBIU, SMPUFBIU,
882                                                          SMPUSRAM0, SMPUSRAM1, SMPUP0BIU, SMPUP2BIU, SMPUP6BIU, SMPUP7BIU,
883                                                           SMPUEXBIU, SMPUEXBIU2                                                */
884            uint16_t             :  5;
885       __O  uint16_t  KEY        :  8;               /*!< Key CodeThis bit is used to enable or disable rewriting of the
886                                                          PROTECT and OAD bit.                                                  */
887     } SMPUCTL_b;                                    /*!< BitSize                                                               */
888   };
889   __I  uint16_t  RESERVED[7];
890 
891   union {
892     __IO uint16_t  SMPUMBIU;                        /*!< Access Control Register for MBIU                                      */
893 
894     struct {
895            uint16_t             :  2;
896       __IO uint16_t  RP_GRPA    :  1;               /*!< Master Group A Read protection                                        */
897       __IO uint16_t  WP_GRPA    :  1;               /*!< Master Group A Write protection                                       */
898       __IO uint16_t  RP_GRPB    :  1;               /*!< Master Group B Read protection                                        */
899       __IO uint16_t  WP_GRPB    :  1;               /*!< Master Group B Write protection                                       */
900       __IO uint16_t  RP_GRPC    :  1;               /*!< Master Group C Read protection                                        */
901       __IO uint16_t  WP_GRPC    :  1;               /*!< Master Group C Write protection                                       */
902            uint16_t             :  4;
903       __IO uint16_t  RP_ROMC    :  1;               /*!< ROMC Read protection                                                  */
904       __IO uint16_t  WP_ROMC    :  1;               /*!< ROMC Write protection                                                 */
905       __IO uint16_t  RP_HSSRAM  :  1;               /*!< HSSRAM Read protection                                                */
906       __IO uint16_t  WP_HSSRAM  :  1;               /*!< HSSRAM Write protection                                               */
907     } SMPUMBIU_b;                                   /*!< BitSize                                                               */
908   };
909   __I  uint16_t  RESERVED1;
910 
911   union {
912     __IO uint16_t  SMPUFBIU;                        /*!< Access Control Register for FBIU                                      */
913 
914     struct {
915       __IO uint16_t  RP_CPU     :  1;               /*!< CPU Read protection                                                   */
916       __IO uint16_t  WP_CPU     :  1;               /*!< CPU Write protection                                                  */
917       __IO uint16_t  RP_GRPA    :  1;               /*!< Master Group A Read protection                                        */
918       __IO uint16_t  WP_GRPA    :  1;               /*!< Master Group A Write protection                                       */
919       __IO uint16_t  RP_GRPB    :  1;               /*!< Master Group B Read protection                                        */
920       __IO uint16_t  WP_GRPB    :  1;               /*!< Master Group B Write protection                                       */
921       __IO uint16_t  RP_GRPC    :  1;               /*!< Master Group C Read protection                                        */
922       __IO uint16_t  WP_GRPC    :  1;               /*!< Master Group C Write protection                                       */
923     } SMPUFBIU_b;                                   /*!< BitSize                                                               */
924   };
925   __I  uint16_t  RESERVED2;
926   R_SMPU_SMPUSRAMnRC0_Type SMPUSRAMnRC0[2];         /*!< Access Control Register for SRAM%s Register Cluster 0                 */
927 
928   union {
929     __IO uint16_t  SMPUP0BIU;                       /*!< Access Control Register for P%sBIU                                    */
930 
931     struct {
932       __IO uint16_t  RP_CPU     :  1;               /*!< CPU Read protection                                                   */
933       __IO uint16_t  WP_CPU     :  1;               /*!< CPU Write protection                                                  */
934       __IO uint16_t  RP_GRPA    :  1;               /*!< Master Group A Read protection                                        */
935       __IO uint16_t  WP_GRPA    :  1;               /*!< Master Group A Write protection                                       */
936       __IO uint16_t  RP_GRPB    :  1;               /*!< Master Group B Read protection                                        */
937       __IO uint16_t  WP_GRPB    :  1;               /*!< Master Group B Write protection                                       */
938       __IO uint16_t  RP_GRPC    :  1;               /*!< Master Group C Read protection                                        */
939       __IO uint16_t  WP_GRPC    :  1;               /*!< Master Group C Write protection                                       */
940     } SMPUP0BIU_b;                                  /*!< BitSize                                                               */
941   };
942   __I  uint16_t  RESERVED3;
943 
944   union {
945     __IO uint16_t  SMPUP2BIU;                       /*!< Access Control Register for P%sBIU                                    */
946 
947     struct {
948       __IO uint16_t  RP_CPU     :  1;               /*!< CPU Read protection                                                   */
949       __IO uint16_t  WP_CPU     :  1;               /*!< CPU Write protection                                                  */
950       __IO uint16_t  RP_GRPA    :  1;               /*!< Master Group A Read protection                                        */
951       __IO uint16_t  WP_GRPA    :  1;               /*!< Master Group A Write protection                                       */
952       __IO uint16_t  RP_GRPB    :  1;               /*!< Master Group B Read protection                                        */
953       __IO uint16_t  WP_GRPB    :  1;               /*!< Master Group B Write protection                                       */
954       __IO uint16_t  RP_GRPC    :  1;               /*!< Master Group C Read protection                                        */
955       __IO uint16_t  WP_GRPC    :  1;               /*!< Master Group C Write protection                                       */
956     } SMPUP2BIU_b;                                  /*!< BitSize                                                               */
957   };
958   __I  uint16_t  RESERVED4;
959 
960   union {
961     __IO uint16_t  SMPUP6BIU;                       /*!< Access Control Register for P%sBIU                                    */
962 
963     struct {
964       __IO uint16_t  RP_CPU     :  1;               /*!< CPU Read protection                                                   */
965       __IO uint16_t  WP_CPU     :  1;               /*!< CPU Write protection                                                  */
966       __IO uint16_t  RP_GRPA    :  1;               /*!< Master Group A Read protection                                        */
967       __IO uint16_t  WP_GRPA    :  1;               /*!< Master Group A Write protection                                       */
968       __IO uint16_t  RP_GRPB    :  1;               /*!< Master Group B Read protection                                        */
969       __IO uint16_t  WP_GRPB    :  1;               /*!< Master Group B Write protection                                       */
970       __IO uint16_t  RP_GRPC    :  1;               /*!< Master Group C Read protection                                        */
971       __IO uint16_t  WP_GRPC    :  1;               /*!< Master Group C Write protection                                       */
972     } SMPUP6BIU_b;                                  /*!< BitSize                                                               */
973   };
974   __I  uint16_t  RESERVED5;
975 
976   union {
977     __IO uint16_t  SMPUP7BIU;                       /*!< Access Control Register for P%sBIU                                    */
978 
979     struct {
980       __IO uint16_t  RP_CPU     :  1;               /*!< CPU Read protection                                                   */
981       __IO uint16_t  WP_CPU     :  1;               /*!< CPU Write protection                                                  */
982       __IO uint16_t  RP_GRPA    :  1;               /*!< Master Group A Read protection                                        */
983       __IO uint16_t  WP_GRPA    :  1;               /*!< Master Group A Write protection                                       */
984       __IO uint16_t  RP_GRPB    :  1;               /*!< Master Group B Read protection                                        */
985       __IO uint16_t  WP_GRPB    :  1;               /*!< Master Group B Write protection                                       */
986       __IO uint16_t  RP_GRPC    :  1;               /*!< Master Group C Read protection                                        */
987       __IO uint16_t  WP_GRPC    :  1;               /*!< Master Group C Write protection                                       */
988     } SMPUP7BIU_b;                                  /*!< BitSize                                                               */
989   };
990   __I  uint16_t  RESERVED6;
991 
992   union {
993     __IO uint16_t  SMPUEXBIU;                       /*!< Access Control Register for EXBIU                                     */
994 
995     struct {
996       __IO uint16_t  RP_CPU     :  1;               /*!< CPU Read protection                                                   */
997       __IO uint16_t  WP_CPU     :  1;               /*!< CPU Write protection                                                  */
998       __IO uint16_t  RP_GRPA    :  1;               /*!< Master Group A Read protection                                        */
999       __IO uint16_t  WP_GRPA    :  1;               /*!< Master Group A Write protection                                       */
1000       __IO uint16_t  RP_GRPB    :  1;               /*!< Master Group B Read protection                                        */
1001       __IO uint16_t  WP_GRPB    :  1;               /*!< Master Group B Write protection                                       */
1002       __IO uint16_t  RP_GRPC    :  1;               /*!< Master Group C Read protection                                        */
1003       __IO uint16_t  WP_GRPC    :  1;               /*!< Master Group C Write protection                                       */
1004     } SMPUEXBIU_b;                                  /*!< BitSize                                                               */
1005   };
1006   __I  uint16_t  RESERVED7;
1007 
1008   union {
1009     __IO uint16_t  SMPUEXBIU2;                      /*!< Access Control Register for EXBIU2                                    */
1010 
1011     struct {
1012       __IO uint16_t  RP_CPU     :  1;               /*!< CPU Read protection                                                   */
1013       __IO uint16_t  WP_CPU     :  1;               /*!< CPU Write protection                                                  */
1014       __IO uint16_t  RP_GRPA    :  1;               /*!< Master Group A Read protection                                        */
1015       __IO uint16_t  WP_GRPA    :  1;               /*!< Master Group A Write protection                                       */
1016       __IO uint16_t  RP_GRPB    :  1;               /*!< Master Group B Read protection                                        */
1017       __IO uint16_t  WP_GRPB    :  1;               /*!< Master Group B Write protection                                       */
1018       __IO uint16_t  RP_GRPC    :  1;               /*!< Master Group C Read protection                                        */
1019       __IO uint16_t  WP_GRPC    :  1;               /*!< Master Group C Write protection                                       */
1020     } SMPUEXBIU2_b;                                 /*!< BitSize                                                               */
1021   };
1022 } R_SMPU_Type;
1023 
1024 
1025 /* ================================================================================ */
1026 /* ================                     R_SPMON                    ================ */
1027 /* ================================================================================ */
1028 
1029 
1030 /**
1031   * @brief CPU Stack Pointer Monitor (R_SPMON)
1032   */
1033 
1034 typedef struct {                                    /*!< R_SPMON Structure                                                     */
1035 
1036   union {
1037     __IO uint16_t  MSPMPUOAD;                       /*!< SP_main Monitor Operation After Detection Register                    */
1038 
1039     struct {
1040       __IO uint16_t  OAD        :  1;               /*!< Operation after detection                                             */
1041            uint16_t             :  7;
1042       __O  uint16_t  KEY        :  8;               /*!< Write KeywordThe data written to these bits are not stored.           */
1043     } MSPMPUOAD_b;                                  /*!< BitSize                                                               */
1044   };
1045   __I  uint16_t  RESERVED;
1046 
1047   union {
1048     __IO uint16_t  MSPMPUCTL;                       /*!< SP_main Monitor Access Control Register                               */
1049 
1050     struct {
1051       __IO uint16_t  ENABLE     :  1;               /*!< SP_main monitor enable                                                */
1052            uint16_t             :  7;
1053       __I  uint16_t  ERROR      :  1;               /*!< SP_main monitor error flag                                            */
1054     } MSPMPUCTL_b;                                  /*!< BitSize                                                               */
1055   };
1056 
1057   union {
1058     __IO uint16_t  MSPMPUPT;                        /*!< SP_main Monitor Protection of Register                                */
1059 
1060     struct {
1061       __IO uint16_t  PROTECT    :  1;               /*!< Protection of register(MSPMPUAC, MSPMPUSA and MSPMPUSE)               */
1062            uint16_t             :  7;
1063       __O  uint16_t  KEY        :  8;               /*!< Write KeywordThe data written to these bits are not stored.           */
1064     } MSPMPUPT_b;                                   /*!< BitSize                                                               */
1065   };
1066 
1067   union {
1068     __IO uint32_t  MSPMPUSA;                        /*!< SP_main Monitor Start Address Register                                */
1069 
1070     struct {
1071       __IO uint32_t  MSPMPUSA   : 32;               /*!< Region start address registerAddress where the region starts,
1072                                                          for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFFE
1073                                                           The low-order 2 bits are fixed to 0.                                 */
1074     } MSPMPUSA_b;                                   /*!< BitSize                                                               */
1075   };
1076 
1077   union {
1078     __IO uint32_t  MSPMPUEA;                        /*!< SP_main Monitor End Address Register                                  */
1079 
1080     struct {
1081       __IO uint32_t  MSPMPUEA   : 32;               /*!< Region end address registerAddress where the region starts,
1082                                                          for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFFF
1083                                                           The low-order 2 bits are fixed to 1.                                 */
1084     } MSPMPUEA_b;                                   /*!< BitSize                                                               */
1085   };
1086 
1087   union {
1088     __IO uint16_t  PSPMPUOAD;                       /*!< SP_process Monitor Operation After Detection Register                 */
1089 
1090     struct {
1091       __IO uint16_t  OAD        :  1;               /*!< Operation after detection                                             */
1092            uint16_t             :  7;
1093       __O  uint16_t  KEY        :  8;               /*!< Write KeywordThe data written to these bits are not stored.           */
1094     } PSPMPUOAD_b;                                  /*!< BitSize                                                               */
1095   };
1096   __I  uint16_t  RESERVED1;
1097 
1098   union {
1099     __IO uint16_t  PSPMPUCTL;                       /*!< SP_process Monitor Access Control Register                            */
1100 
1101     struct {
1102       __IO uint16_t  ENABLE     :  1;               /*!< SP_process monitor enable                                             */
1103            uint16_t             :  7;
1104       __I  uint16_t  ERROR      :  1;               /*!< SP_process monitor error flag                                         */
1105     } PSPMPUCTL_b;                                  /*!< BitSize                                                               */
1106   };
1107 
1108   union {
1109     __IO uint16_t  PSPMPUPT;                        /*!< SP_process Monitor Protection of Register                             */
1110 
1111     struct {
1112       __IO uint16_t  PROTECT    :  1;               /*!< Protection of register(PSPMPUAC, PSPMPUSA and PSPMPUSE)               */
1113            uint16_t             :  7;
1114       __O  uint16_t  KEY        :  8;               /*!< Write KeywordThe data written to these bits are not stored.           */
1115     } PSPMPUPT_b;                                   /*!< BitSize                                                               */
1116   };
1117 
1118   union {
1119     __IO uint32_t  PSPMPUSA;                        /*!< SP_process Monitor Start Address Register                             */
1120 
1121     struct {
1122       __IO uint32_t  MSPMPUEA   : 32;               /*!< Region start address registerAddress where the region starts,
1123                                                          for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFFE
1124                                                           The low-order 2 bits are fixed to 0.                                 */
1125     } PSPMPUSA_b;                                   /*!< BitSize                                                               */
1126   };
1127 
1128   union {
1129     __IO uint32_t  PSPMPUEA;                        /*!< SP_process Monitor End Address Register                               */
1130 
1131     struct {
1132       __IO uint32_t  PSPMPUEA   : 32;               /*!< Region end address registerAddress where the region starts,
1133                                                          for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFFF
1134                                                           The low-order 2 bits are fixed to 1.                                 */
1135     } PSPMPUEA_b;                                   /*!< BitSize                                                               */
1136   };
1137 } R_SPMON_Type;
1138 
1139 
1140 
1141 /* ================================================================================ */
1142 /* ================                     R_SRAM                     ================ */
1143 /* ================================================================================ */
1144 
1145 
1146 /**
1147   * @brief SRAM Control (R_SRAM)
1148   */
1149 
1150 typedef struct {                                    /*!< R_SRAM Structure                                                      */
1151 
1152   union {
1153     __IO uint8_t   PARIOAD;                         /*!< RAM Parity Error Operation After Detection Register                   */
1154 
1155     struct {
1156       __IO uint8_t   OAD        :  1;               /*!< Operation after detection                                             */
1157     } PARIOAD_b;                                    /*!< BitSize                                                               */
1158   };
1159   __I  uint8_t   RESERVED[3];
1160 
1161   union {
1162     __IO uint8_t   RAMPRCR;                         /*!< RAM Protection Register                                               */
1163 
1164     struct {
1165       __IO uint8_t   RAMPRCR    :  1;               /*!< Register Write Control                                                */
1166       __O  uint8_t   KEY        :  7;               /*!< Key Code                                                              */
1167     } RAMPRCR_b;                                    /*!< BitSize                                                               */
1168   };
1169 
1170   __I  uint8_t   RESERVED2[187];
1171 
1172   union {
1173     __IO uint8_t   ECCRAMMODE;                      /*!< ECCRAM Operating Mode Control Register                                */
1174 
1175     struct {
1176       __IO uint8_t   RAMMOD     :  2;               /*!< RAM Operating Mode Select                                             */
1177     } ECCRAMMODE_b;                                 /*!< BitSize                                                               */
1178   };
1179 
1180   union {
1181     __IO uint8_t   ECCRAM2STS;                      /*!< ECCRAM 2-Bit Error Status Register                                    */
1182 
1183     struct {
1184       __IO uint8_t   ECCRAM2ERR :  1;               /*!< ECC 2-Bit Error Status                                                */
1185     } ECCRAM2STS_b;                                 /*!< BitSize                                                               */
1186   };
1187 
1188   union {
1189     __IO uint8_t   ECCRAM1STSEN;                    /*!< ECCRAM 1-Bit Error Information Update Enable Register                 */
1190 
1191     struct {
1192       __IO uint8_t   E1STSEN    :  1;               /*!< ECC 1-Bit Error Information Update Enable                             */
1193     } ECCRAM1STSEN_b;                               /*!< BitSize                                                               */
1194   };
1195 
1196   union {
1197     __IO uint8_t   ECCRAM1STS;                      /*!< ECCRAM 1-Bit Error Status Register                                    */
1198 
1199     struct {
1200       __IO uint8_t   ECCRAM1ERR :  1;               /*!< ECC 1-Bit Error Status                                                */
1201     } ECCRAM1STS_b;                                 /*!< BitSize                                                               */
1202   };
1203 
1204   union {
1205     __IO uint8_t   ECCRAMPRCR;                      /*!< ECCRAM Protection Register                                            */
1206 
1207     struct {
1208       __IO uint8_t   ECCRAMPRCR :  1;               /*!< ECCRAMETST Register Write Control                                     */
1209       __O  uint8_t   KEY        :  7;               /*!< Key Code                                                              */
1210     } ECCRAMPRCR_b;                                 /*!< BitSize                                                               */
1211   };
1212   __I  uint8_t   RESERVED3[11];
1213 
1214   union {
1215     __IO uint8_t   ECCRAMPRCR2;                     /*!< ECCRAM Protection Register 2                                          */
1216 
1217     struct {
1218       __IO uint8_t   ECCRAMPRCR2:  1;               /*!< ECCRAMETST Register Write Control                                     */
1219       __O  uint8_t   KEY        :  7;               /*!< Key Code                                                              */
1220     } ECCRAMPRCR2_b;                                /*!< BitSize                                                               */
1221   };
1222   __I  uint8_t   RESERVED4[3];
1223 
1224   union {
1225     __IO uint8_t   ECCRAMETST;                      /*!< ECCRAM Test Control Register                                          */
1226 
1227     struct {
1228       __IO uint8_t   TSTBYP     :  1;               /*!< ECC Bypass Select                                                     */
1229     } ECCRAMETST_b;                                 /*!< BitSize                                                               */
1230   };
1231   __I  uint8_t   RESERVED5[3];
1232 
1233   union {
1234     __IO uint8_t   ECCOAD;                          /*!< RAM ECC Error Operation After Detection Register                      */
1235 
1236     struct {
1237       __IO uint8_t   OAD        :  1;               /*!< Operation after detection                                             */
1238     } ECCOAD_b;                                     /*!< BitSize                                                               */
1239   };
1240 } R_SRAM_Type;
1241 
1242 
1243 /* ================================================================================ */
1244 /* ================                      R_BUS                     ================ */
1245 /* ================================================================================ */
1246 
1247 
1248 /**
1249   * @brief BUS Control (R_BUS)
1250   */
1251 
1252 typedef struct {                                    /*!< R_BUS Structure                                                       */
1253   CSRC0_Type CSRC0[8];                              /*!< CS Registers Cluster 0                                                */
1254   __I  uint32_t  RESERVED[480];
1255   CSRC1_Type CSRC1[8];                              /*!< CS Registers Cluster 1                                                */
1256 
1257   union {
1258     __IO uint16_t  CSRECEN;                         /*!< CS Recovery Cycle Insertion Enable Register                           */
1259 
1260     struct {
1261       __IO uint16_t  RECVEN0    :  1;               /*!< Separate Bus Recovery Cycle Insertion Enable 0                        */
1262       __IO uint16_t  RECVEN1    :  1;               /*!< Separate Bus Recovery Cycle Insertion Enable 1                        */
1263       __IO uint16_t  RECVEN2    :  1;               /*!< Separate Bus Recovery Cycle Insertion Enable 2                        */
1264       __IO uint16_t  RECVEN3    :  1;               /*!< Separate Bus Recovery Cycle Insertion Enable 3                        */
1265       __IO uint16_t  RECVEN4    :  1;               /*!< Separate Bus Recovery Cycle Insertion Enable 4                        */
1266       __IO uint16_t  RECVEN5    :  1;               /*!< Separate Bus Recovery Cycle Insertion Enable 5                        */
1267       __IO uint16_t  RECVEN6    :  1;               /*!< Separate Bus Recovery Cycle Insertion Enable 6                        */
1268       __IO uint16_t  RECVEN7    :  1;               /*!< Separate Bus Recovery Cycle Insertion Enable 7                        */
1269     } CSRECEN_b;                                    /*!< BitSize                                                               */
1270   };
1271   __I  uint16_t  RESERVED1[447];
1272 
1273   union {
1274     __IO uint8_t   SDCCR;                           /*!< SDC Control Register                                                  */
1275 
1276     struct {
1277       __IO uint8_t   EXENB      :  1;               /*!< Operation Enable                                                      */
1278            uint8_t              :  3;
1279       __IO uint8_t   BSIZE      :  2;               /*!< SDRAM Bus Width Select                                                */
1280     } SDCCR_b;                                      /*!< BitSize                                                               */
1281   };
1282 
1283   union {
1284     __IO uint8_t   SDCMOD;                          /*!< SDC Mode Register                                                     */
1285 
1286     struct {
1287       __IO uint8_t   EMODE      :  1;               /*!< Endian Mode                                                           */
1288     } SDCMOD_b;                                     /*!< BitSize                                                               */
1289   };
1290 
1291   union {
1292     __IO uint8_t   SDAMOD;                          /*!< SDRAM Access Mode Register                                            */
1293 
1294     struct {
1295       __IO uint8_t   BE         :  1;               /*!< Continuous Access Enable                                              */
1296     } SDAMOD_b;                                     /*!< BitSize                                                               */
1297   };
1298   __I  uint8_t   RESERVED2[13];
1299 
1300   union {
1301     __IO uint8_t   SDSELF;                          /*!< SDRAM Self-Refresh Control Register                                   */
1302 
1303     struct {
1304       __IO uint8_t   SFEN       :  1;               /*!< SDRAM Self-Refresh Enable                                             */
1305     } SDSELF_b;                                     /*!< BitSize                                                               */
1306   };
1307   __I  uint8_t   RESERVED3[3];
1308 
1309   union {
1310     __IO uint16_t  SDRFCR;                          /*!< SDRAM Refresh Control Register                                        */
1311 
1312     struct {
1313       __IO uint16_t  RFC        : 12;               /*!< Auto-Refresh Request Interval Setting                                 */
1314       __IO uint16_t  REFW       :  4;               /*!< Auto-Refresh Cycle/ Self-Refresh Clearing Cycle Count Setting.
1315                                                          ( REFW+1 Cycles )                                                     */
1316     } SDRFCR_b;                                     /*!< BitSize                                                               */
1317   };
1318 
1319   union {
1320     __IO uint8_t   SDRFEN;                          /*!< SDRAM Auto-Refresh Control Register                                   */
1321 
1322     struct {
1323       __IO uint8_t   RFEN       :  1;               /*!< Auto-Refresh Operation Enable                                         */
1324     } SDRFEN_b;                                     /*!< BitSize                                                               */
1325   };
1326   __I  uint8_t   RESERVED4[9];
1327 
1328   union {
1329     __IO uint8_t   SDICR;                           /*!< SDRAM Initialization Sequence Control Register                        */
1330 
1331     struct {
1332       __IO uint8_t   INIRQ      :  1;               /*!< Initialization Sequence Start                                         */
1333     } SDICR_b;                                      /*!< BitSize                                                               */
1334   };
1335   __I  uint8_t   RESERVED5[3];
1336 
1337   union {
1338     __IO uint16_t  SDIR;                            /*!< SDRAM Initialization Register                                         */
1339 
1340     struct {
1341       __IO uint16_t  ARFI       :  4;               /*!< Initialization Auto-Refresh Interval ( PRF+3 cycles )                 */
1342       __IO uint16_t  ARFC       :  4;               /*!< Initialization Auto-Refresh Count                                     */
1343       __IO uint16_t  PRC        :  3;               /*!< Initialization Precharge Cycle Count ( PRF+3 cycles )                 */
1344     } SDIR_b;                                       /*!< BitSize                                                               */
1345   };
1346   __I  uint16_t  RESERVED6[13];
1347 
1348   union {
1349     __IO uint8_t   SDADR;                           /*!< SDRAM Address Register                                                */
1350 
1351     struct {
1352       __IO uint8_t   MXC        :  2;               /*!< Address Multiplex Select                                              */
1353     } SDADR_b;                                      /*!< BitSize                                                               */
1354   };
1355   __I  uint8_t   RESERVED7[3];
1356 
1357   union {
1358     __IO uint32_t  SDTR;                            /*!< SDRAM Timing Register                                                 */
1359 
1360     struct {
1361       __IO uint32_t  CL         :  3;               /*!< SDRAMC Column Latency                                                 */
1362            uint32_t             :  5;
1363       __IO uint32_t  WR         :  1;               /*!< Write Recovery Interval                                               */
1364       __IO uint32_t  RP         :  3;               /*!< Row Precharge Interval ( RP+1 cycles )                                */
1365       __IO uint32_t  RCD        :  2;               /*!< Row Column Latency ( RCD+1 cycles )                                   */
1366            uint32_t             :  2;
1367       __IO uint32_t  RAS        :  3;               /*!< Row Active Interval                                                   */
1368     } SDTR_b;                                       /*!< BitSize                                                               */
1369   };
1370 
1371   union {
1372     __IO uint16_t  SDMOD;                           /*!< SDRAM Mode Register                                                   */
1373 
1374     struct {
1375       __IO uint16_t  MR         : 15;               /*!< Mode Register SettingWriting to these bits: Mode register set
1376                                                          command is issued.                                                    */
1377     } SDMOD_b;                                      /*!< BitSize                                                               */
1378   };
1379   __I  uint16_t  RESERVED8[3];
1380 
1381   union {
1382     __I  uint8_t   SDSR;                            /*!< SDRAM Status Register                                                 */
1383 
1384     struct {
1385       __I  uint8_t   MRSST      :  1;               /*!< Mode Register Setting Status                                          */
1386            uint8_t              :  2;
1387       __I  uint8_t   INIST      :  1;               /*!< Initialization Status                                                 */
1388       __I  uint8_t   SRFST      :  1;               /*!< Self-Refresh Transition/Recovery Status                               */
1389     } SDSR_b;                                       /*!< BitSize                                                               */
1390   };
1391   __I  uint8_t   RESERVED9[943];
1392 
1393   union {
1394     __IO uint16_t  BUSMCNTM4I;                      /*!< Master Bus Control Register %s                                        */
1395 
1396     struct {
1397            uint16_t             :  8;
1398       __IO uint16_t  EWRES      :  1;               /*!< Early Write ResponseWhether the next write request is accepted
1399                                                          or not until a response for the write transaction comes back.
1400                                                                                                                                */
1401            uint16_t             :  6;
1402       __IO uint16_t  IERES      :  1;               /*!< Ignore Error Responses                                                */
1403     } BUSMCNTM4I_b;                                 /*!< BitSize                                                               */
1404   };
1405   __I  uint16_t  RESERVED10;
1406 
1407   union {
1408     __IO uint16_t  BUSMCNTM4D;                      /*!< Master Bus Control Register %s                                        */
1409 
1410     struct {
1411            uint16_t             :  8;
1412       __IO uint16_t  EWRES      :  1;               /*!< Early Write ResponseWhether the next write request is accepted
1413                                                          or not until a response for the write transaction comes back.
1414                                                                                                                                */
1415            uint16_t             :  6;
1416       __IO uint16_t  IERES      :  1;               /*!< Ignore Error Responses                                                */
1417     } BUSMCNTM4D_b;                                 /*!< BitSize                                                               */
1418   };
1419   __I  uint16_t  RESERVED11;
1420 
1421   union {
1422     __IO uint16_t  BUSMCNTSYS;                      /*!< Master Bus Control Register %s                                        */
1423 
1424     struct {
1425            uint16_t             :  8;
1426       __IO uint16_t  EWRES      :  1;               /*!< Early Write ResponseWhether the next write request is accepted
1427                                                          or not until a response for the write transaction comes back.
1428                                                                                                                                */
1429            uint16_t             :  6;
1430       __IO uint16_t  IERES      :  1;               /*!< Ignore Error Responses                                                */
1431     } BUSMCNTSYS_b;                                 /*!< BitSize                                                               */
1432   };
1433   __I  uint16_t  RESERVED12;
1434 
1435   union {
1436     __IO uint16_t  BUSMCNTDMA;                      /*!< Master Bus Control Register %s                                        */
1437 
1438     struct {
1439            uint16_t             :  8;
1440       __IO uint16_t  EWRES      :  1;               /*!< Early Write ResponseWhether the next write request is accepted
1441                                                          or not until a response for the write transaction comes back.
1442                                                                                                                                */
1443            uint16_t             :  6;
1444       __IO uint16_t  IERES      :  1;               /*!< Ignore Error Responses                                                */
1445     } BUSMCNTDMA_b;                                 /*!< BitSize                                                               */
1446   };
1447   __I  uint16_t  RESERVED13;
1448 
1449   union {
1450     __IO uint16_t  BUSMCNTEDM;                      /*!< Master Bus Control Register %s                                        */
1451 
1452     struct {
1453            uint16_t             :  8;
1454       __IO uint16_t  EWRES      :  1;               /*!< Early Write ResponseWhether the next write request is accepted
1455                                                          or not until a response for the write transaction comes back.
1456                                                                                                                                */
1457            uint16_t             :  6;
1458       __IO uint16_t  IERES      :  1;               /*!< Ignore Error Responses                                                */
1459     } BUSMCNTEDM_b;                                 /*!< BitSize                                                               */
1460   };
1461   __I  uint16_t  RESERVED14;
1462 
1463   union {
1464     __IO uint16_t  BUSMCNTHMI;                      /*!< Master Bus Control Register %s                                        */
1465 
1466     struct {
1467            uint16_t             :  8;
1468       __IO uint16_t  EWRES      :  1;               /*!< Early Write ResponseWhether the next write request is accepted
1469                                                          or not until a response for the write transaction comes back.
1470                                                                                                                                */
1471            uint16_t             :  6;
1472       __IO uint16_t  IERES      :  1;               /*!< Ignore Error Responses                                                */
1473     } BUSMCNTHMI_b;                                 /*!< BitSize                                                               */
1474   };
1475   __I  uint16_t  RESERVED15[117];
1476 
1477   union {
1478     __IO uint16_t  BUSSCNTFLI;                      /*!< Slave Bus Control Register %s                                         */
1479 
1480     struct {
1481            uint16_t             :  4;
1482       __IO uint16_t  ARBMET     :  2;               /*!< Arbitration MethodSpecify the priority between groups                 */
1483            uint16_t             :  2;
1484       __IO uint16_t  EWRES      :  1;               /*!< Early Write ResponseWhether the next write request is accepted
1485                                                          or not until a response for the write transaction comes back.
1486                                                                                                                                */
1487            uint16_t             :  6;
1488       __IO uint16_t  IERES      :  1;               /*!< Ignore Error Responses                                                */
1489     } BUSSCNTFLI_b;                                 /*!< BitSize                                                               */
1490   };
1491   __I  uint16_t  RESERVED16;
1492 
1493   union {
1494     __IO uint16_t  BUSSCNTRAMH;                     /*!< Slave Bus Control Register %s                                         */
1495 
1496     struct {
1497            uint16_t             :  4;
1498       __IO uint16_t  ARBMET     :  2;               /*!< Arbitration MethodSpecify the priority between groups                 */
1499            uint16_t             :  2;
1500       __IO uint16_t  EWRES      :  1;               /*!< Early Write ResponseWhether the next write request is accepted
1501                                                          or not until a response for the write transaction comes back.
1502                                                                                                                                */
1503            uint16_t             :  6;
1504       __IO uint16_t  IERES      :  1;               /*!< Ignore Error Responses                                                */
1505     } BUSSCNTRAMH_b;                                /*!< BitSize                                                               */
1506   };
1507   __I  uint16_t  RESERVED17;
1508 
1509   union {
1510     __IO uint16_t  BUSSCNTMBIU;                     /*!< Slave Bus Control Register %s                                         */
1511 
1512     struct {
1513            uint16_t             :  4;
1514       __IO uint16_t  ARBMET     :  2;               /*!< Arbitration MethodSpecify the priority between groups                 */
1515            uint16_t             :  2;
1516       __IO uint16_t  EWRES      :  1;               /*!< Early Write ResponseWhether the next write request is accepted
1517                                                          or not until a response for the write transaction comes back.
1518                                                                                                                                */
1519            uint16_t             :  6;
1520       __IO uint16_t  IERES      :  1;               /*!< Ignore Error Responses                                                */
1521     } BUSSCNTMBIU_b;                                /*!< BitSize                                                               */
1522   };
1523   __I  uint16_t  RESERVED18;
1524 
1525   union {
1526     __IO uint16_t  BUSSCNTRAM0;                     /*!< Slave Bus Control Register %s                                         */
1527 
1528     struct {
1529            uint16_t             :  4;
1530       __IO uint16_t  ARBMET     :  2;               /*!< Arbitration MethodSpecify the priority between groups                 */
1531            uint16_t             :  2;
1532       __IO uint16_t  EWRES      :  1;               /*!< Early Write ResponseWhether the next write request is accepted
1533                                                          or not until a response for the write transaction comes back.
1534                                                                                                                                */
1535            uint16_t             :  6;
1536       __IO uint16_t  IERES      :  1;               /*!< Ignore Error Responses                                                */
1537     } BUSSCNTRAM0_b;                                /*!< BitSize                                                               */
1538   };
1539   __I  uint16_t  RESERVED19;
1540 
1541   union {
1542     __IO uint16_t  BUSSCNTRAM1;                     /*!< Slave Bus Control Register %s                                         */
1543 
1544     struct {
1545            uint16_t             :  4;
1546       __IO uint16_t  ARBMET     :  2;               /*!< Arbitration MethodSpecify the priority between groups                 */
1547            uint16_t             :  2;
1548       __IO uint16_t  EWRES      :  1;               /*!< Early Write ResponseWhether the next write request is accepted
1549                                                          or not until a response for the write transaction comes back.
1550                                                                                                                                */
1551            uint16_t             :  6;
1552       __IO uint16_t  IERES      :  1;               /*!< Ignore Error Responses                                                */
1553     } BUSSCNTRAM1_b;                                /*!< BitSize                                                               */
1554   };
1555   __I  uint16_t  RESERVED20;
1556 
1557   union {
1558     __IO uint16_t  BUSSCNTP0B;                      /*!< Slave Bus Control Register %s                                         */
1559 
1560     struct {
1561            uint16_t             :  4;
1562       __IO uint16_t  ARBMET     :  2;               /*!< Arbitration MethodSpecify the priority between groups                 */
1563            uint16_t             :  2;
1564       __IO uint16_t  EWRES      :  1;               /*!< Early Write ResponseWhether the next write request is accepted
1565                                                          or not until a response for the write transaction comes back.
1566                                                                                                                                */
1567            uint16_t             :  6;
1568       __IO uint16_t  IERES      :  1;               /*!< Ignore Error Responses                                                */
1569     } BUSSCNTP0B_b;                                 /*!< BitSize                                                               */
1570   };
1571   __I  uint16_t  RESERVED21;
1572 
1573   union {
1574     __IO uint16_t  BUSSCNTP2B;                      /*!< Slave Bus Control Register %s                                         */
1575 
1576     struct {
1577            uint16_t             :  4;
1578       __IO uint16_t  ARBMET     :  2;               /*!< Arbitration MethodSpecify the priority between groups                 */
1579            uint16_t             :  2;
1580       __IO uint16_t  EWRES      :  1;               /*!< Early Write ResponseWhether the next write request is accepted
1581                                                          or not until a response for the write transaction comes back.
1582                                                                                                                                */
1583            uint16_t             :  6;
1584       __IO uint16_t  IERES      :  1;               /*!< Ignore Error Responses                                                */
1585     } BUSSCNTP2B_b;                                 /*!< BitSize                                                               */
1586   };
1587   __I  uint16_t  RESERVED22;
1588 
1589   union {
1590     __IO uint16_t  BUSSCNTP3B;                      /*!< Slave Bus Control Register %s                                         */
1591 
1592     struct {
1593            uint16_t             :  4;
1594       __IO uint16_t  ARBMET     :  2;               /*!< Arbitration MethodSpecify the priority between groups                 */
1595            uint16_t             :  2;
1596       __IO uint16_t  EWRES      :  1;               /*!< Early Write ResponseWhether the next write request is accepted
1597                                                          or not until a response for the write transaction comes back.
1598                                                                                                                                */
1599            uint16_t             :  6;
1600       __IO uint16_t  IERES      :  1;               /*!< Ignore Error Responses                                                */
1601     } BUSSCNTP3B_b;                                 /*!< BitSize                                                               */
1602   };
1603   __I  uint16_t  RESERVED23;
1604 
1605   union {
1606     __IO uint16_t  BUSSCNTP4B;                      /*!< Slave Bus Control Register %s                                         */
1607 
1608     struct {
1609            uint16_t             :  4;
1610       __IO uint16_t  ARBMET     :  2;               /*!< Arbitration MethodSpecify the priority between groups                 */
1611            uint16_t             :  2;
1612       __IO uint16_t  EWRES      :  1;               /*!< Early Write ResponseWhether the next write request is accepted
1613                                                          or not until a response for the write transaction comes back.
1614                                                                                                                                */
1615            uint16_t             :  6;
1616       __IO uint16_t  IERES      :  1;               /*!< Ignore Error Responses                                                */
1617     } BUSSCNTP4B_b;                                 /*!< BitSize                                                               */
1618   };
1619   __I  uint16_t  RESERVED24;
1620 
1621   union {
1622     __IO uint16_t  BUSSCNTP5B;                      /*!< Slave Bus Control Register %s                                         */
1623 
1624     struct {
1625            uint16_t             :  4;
1626       __IO uint16_t  ARBMET     :  2;               /*!< Arbitration MethodSpecify the priority between groups                 */
1627            uint16_t             :  2;
1628       __IO uint16_t  EWRES      :  1;               /*!< Early Write ResponseWhether the next write request is accepted
1629                                                          or not until a response for the write transaction comes back.
1630                                                                                                                                */
1631            uint16_t             :  6;
1632       __IO uint16_t  IERES      :  1;               /*!< Ignore Error Responses                                                */
1633     } BUSSCNTP5B_b;                                 /*!< BitSize                                                               */
1634   };
1635   __I  uint16_t  RESERVED25;
1636 
1637   union {
1638     __IO uint16_t  BUSSCNTP6B;                      /*!< Slave Bus Control Register %s                                         */
1639 
1640     struct {
1641            uint16_t             :  4;
1642       __IO uint16_t  ARBMET     :  2;               /*!< Arbitration MethodSpecify the priority between groups                 */
1643            uint16_t             :  2;
1644       __IO uint16_t  EWRES      :  1;               /*!< Early Write ResponseWhether the next write request is accepted
1645                                                          or not until a response for the write transaction comes back.
1646                                                                                                                                */
1647            uint16_t             :  6;
1648       __IO uint16_t  IERES      :  1;               /*!< Ignore Error Responses                                                */
1649     } BUSSCNTP6B_b;                                 /*!< BitSize                                                               */
1650   };
1651   __I  uint16_t  RESERVED26;
1652 
1653   union {
1654     __IO uint16_t  BUSSCNTP7B;                      /*!< Slave Bus Control Register %s                                         */
1655 
1656     struct {
1657            uint16_t             :  4;
1658       __IO uint16_t  ARBMET     :  2;               /*!< Arbitration MethodSpecify the priority between groups                 */
1659            uint16_t             :  2;
1660       __IO uint16_t  EWRES      :  1;               /*!< Early Write ResponseWhether the next write request is accepted
1661                                                          or not until a response for the write transaction comes back.
1662                                                                                                                                */
1663            uint16_t             :  6;
1664       __IO uint16_t  IERES      :  1;               /*!< Ignore Error Responses                                                */
1665     } BUSSCNTP7B_b;                                 /*!< BitSize                                                               */
1666   };
1667   __I  uint16_t  RESERVED27;
1668 
1669   union {
1670     __IO uint16_t  BUSSCNTFBU;                      /*!< Slave Bus Control Register %s                                         */
1671 
1672     struct {
1673            uint16_t             :  4;
1674       __IO uint16_t  ARBMET     :  2;               /*!< Arbitration MethodSpecify the priority between groups                 */
1675            uint16_t             :  2;
1676       __IO uint16_t  EWRES      :  1;               /*!< Early Write ResponseWhether the next write request is accepted
1677                                                          or not until a response for the write transaction comes back.
1678                                                                                                                                */
1679            uint16_t             :  6;
1680       __IO uint16_t  IERES      :  1;               /*!< Ignore Error Responses                                                */
1681     } BUSSCNTFBU_b;                                 /*!< BitSize                                                               */
1682   };
1683   __I  uint16_t  RESERVED28;
1684 
1685   union {
1686     __IO uint16_t  BUSSCNTEXT;                      /*!< Slave Bus Control Register %s                                         */
1687 
1688     struct {
1689            uint16_t             :  4;
1690       __IO uint16_t  ARBMET     :  2;               /*!< Arbitration MethodSpecify the priority between groups                 */
1691            uint16_t             :  2;
1692       __IO uint16_t  EWRES      :  1;               /*!< Early Write ResponseWhether the next write request is accepted
1693                                                          or not until a response for the write transaction comes back.
1694                                                                                                                                */
1695            uint16_t             :  6;
1696       __IO uint16_t  IERES      :  1;               /*!< Ignore Error Responses                                                */
1697     } BUSSCNTEXT_b;                                 /*!< BitSize                                                               */
1698   };
1699   __I  uint16_t  RESERVED29;
1700 
1701   union {
1702     __IO uint16_t  BUSSCNTEXT2;                     /*!< Slave Bus Control Register %s                                         */
1703 
1704     struct {
1705            uint16_t             :  4;
1706       __IO uint16_t  ARBMET     :  2;               /*!< Arbitration MethodSpecify the priority between groups                 */
1707            uint16_t             :  2;
1708       __IO uint16_t  EWRES      :  1;               /*!< Early Write ResponseWhether the next write request is accepted
1709                                                          or not until a response for the write transaction comes back.
1710                                                                                                                                */
1711            uint16_t             :  6;
1712       __IO uint16_t  IERES      :  1;               /*!< Ignore Error Responses                                                */
1713     } BUSSCNTEXT2_b;                                /*!< BitSize                                                               */
1714   };
1715   __I  uint16_t  RESERVED30;
1716 
1717   union {
1718     __IO uint16_t  BUSSCNTHMI;                      /*!< Slave Bus Control Register %s                                         */
1719 
1720     struct {
1721            uint16_t             :  4;
1722       __IO uint16_t  ARBMET     :  2;               /*!< Arbitration MethodSpecify the priority between groups                 */
1723            uint16_t             :  2;
1724       __IO uint16_t  EWRES      :  1;               /*!< Early Write ResponseWhether the next write request is accepted
1725                                                          or not until a response for the write transaction comes back.
1726                                                                                                                                */
1727            uint16_t             :  6;
1728       __IO uint16_t  IERES      :  1;               /*!< Ignore Error Responses                                                */
1729     } BUSSCNTHMI_b;                                 /*!< BitSize                                                               */
1730   };
1731   __I  uint16_t  RESERVED31[865];
1732   BUSnERRRC0_Type BUSnERRRC0[11];                   /*!< BUS %s Error Registers Cluster 0                                      */
1733 } R_BUS_Type;
1734 
1735 
1736 
1737 
1738 
1739 /* ================================================================================ */
1740 /* ================                      R_DTC                     ================ */
1741 /* ================================================================================ */
1742 
1743 
1744 /**
1745   * @brief Data Transfer Controller (R_DTC)
1746   */
1747 
1748 typedef struct {                                    /*!< R_DTC Structure                                                       */
1749 
1750   union {
1751     __IO uint8_t   DTCCR;                           /*!< DTC Control Register                                                  */
1752 
1753     struct {
1754            uint8_t              :  4;
1755       __IO uint8_t   RRS        :  1;               /*!< DTC Transfer Information Read Skip Enable.                            */
1756     } DTCCR_b;                                      /*!< BitSize                                                               */
1757   };
1758   __I  uint8_t   RESERVED[3];
1759 
1760   union {
1761     __IO uint32_t  DTCVBR;                          /*!< DTC Vector Base Register                                              */
1762 
1763     struct {
1764       __IO uint32_t  DTCVBR     : 32;               /*!< Set DTC Vector Base Address.Note: A value cannot be set in the
1765                                                          lower-order 10 bits. These bits are fixed to 0.                       */
1766     } DTCVBR_b;                                     /*!< BitSize                                                               */
1767   };
1768   __I  uint32_t  RESERVED1;
1769 
1770   union {
1771     __IO uint8_t   DTCST;                           /*!< DTC Module Start Register                                             */
1772 
1773     struct {
1774       __IO uint8_t   DTCST      :  1;               /*!< DTC Module Start                                                      */
1775     } DTCST_b;                                      /*!< BitSize                                                               */
1776   };
1777   __I  uint8_t   RESERVED2;
1778 
1779   union {
1780     __I  uint16_t  DTCSTS;                          /*!< DTC Status Register                                                   */
1781 
1782     struct {
1783       __I  uint16_t  VECN       :  8;               /*!< DTC-Activating Vector Number MonitoringThese bits indicate the
1784                                                          vector number for the activating source when DTC transfer is
1785                                                           in progress.The value is only valid if DTC transfer is in progress
1786                                                           (the value of the ACT flag is 1)                                     */
1787            uint16_t             :  7;
1788       __I  uint16_t  ACT        :  1;               /*!< DTC Active Flag                                                       */
1789     } DTCSTS_b;                                     /*!< BitSize                                                               */
1790   };
1791 } R_DTC_Type;
1792 
1793 
1794 /* ================================================================================ */
1795 /* ================                      R_ICU                     ================ */
1796 /* ================================================================================ */
1797 
1798 
1799 /**
1800   * @brief Interrupt Controller (R_ICU)
1801   */
1802 
1803 typedef struct {                                    /*!< R_ICU Structure                                                       */
1804 
1805   union {
1806     __IO uint8_t   IRQCRn[16];                      /*!< IRQ Control Register %s                                               */
1807 
1808     struct {
1809       __IO uint8_t   IRQMD      :  2;               /*!< IRQ Detection Sense Select                                            */
1810            uint8_t              :  2;
1811       __IO uint8_t   FCLKSEL    :  2;               /*!< IRQ Digital Filter Sampling Clock                                     */
1812            uint8_t              :  1;
1813       __IO uint8_t   FLTEN      :  1;               /*!< IRQ Digital Filter Enable                                             */
1814     } IRQCRn_b[16];                                 /*!< BitSize                                                               */
1815   };
1816   __I  uint32_t  RESERVED[60];
1817 
1818   union {
1819     __IO uint8_t   NMICR;                           /*!< NMI Pin Interrupt Control Register                                    */
1820 
1821     struct {
1822       __IO uint8_t   NMIMD      :  1;               /*!< NMI Detection Set                                                     */
1823            uint8_t              :  3;
1824       __IO uint8_t   NFCLKSEL   :  2;               /*!< NMI Digital Filter Sampling Clock                                     */
1825            uint8_t              :  1;
1826       __IO uint8_t   NFLTEN     :  1;               /*!< NMI Digital Filter Enable                                             */
1827     } NMICR_b;                                      /*!< BitSize                                                               */
1828   };
1829   __I  uint8_t   RESERVED1[31];
1830 
1831   union {
1832     __IO uint16_t  NMIER;                           /*!< Non-Maskable Interrupt Enable Register                                */
1833 
1834     struct {
1835       __IO uint16_t  IWDTEN     :  1;               /*!< IWDT Underflow/Refresh Error Enable                                   */
1836       __IO uint16_t  WDTEN      :  1;               /*!< WDT Underflow/Refresh Error Enable                                    */
1837       __IO uint16_t  LVD1EN     :  1;               /*!< Voltage-Monitoring 1 Interrupt Enable                                 */
1838       __IO uint16_t  LVD2EN     :  1;               /*!< Voltage-Monitoring 2 Interrupt Enable                                 */
1839       __IO uint16_t  VBATTEN    :  1;               /*!< VBATT monitor Interrupt Enable                                        */
1840            uint16_t             :  1;
1841       __IO uint16_t  OSTEN      :  1;               /*!< Oscillation Stop Detection Interrupt Enable                           */
1842       __IO uint16_t  NMIEN      :  1;               /*!< NMI Enable                                                            */
1843       __IO uint16_t  RPEEN      :  1;               /*!< RAM Parity Error Interrupt Enable                                     */
1844       __IO uint16_t  RECCEN     :  1;               /*!< RAM ECC Error Interrupt Enable                                        */
1845       __IO uint16_t  BUSSEN     :  1;               /*!< MPU Bus Slave Error Interrupt Enable                                  */
1846       __IO uint16_t  BUSMEN     :  1;               /*!< MPU Bus Master Error Interrupt Enable                                 */
1847       __IO uint16_t  SPEEN      :  1;               /*!< MPU Stack Error Interrupt Enable                                      */
1848     } NMIER_b;                                      /*!< BitSize                                                               */
1849   };
1850   __I  uint16_t  RESERVED2[7];
1851 
1852   union {
1853     __O  uint16_t  NMICLR;                          /*!< Non-Maskable Interrupt Status Clear Register                          */
1854 
1855     struct {
1856       __O  uint16_t  IWDTCLR    :  1;               /*!< IWDTST Clear                                                          */
1857       __O  uint16_t  WDTCLR     :  1;               /*!< WDTST Clear                                                           */
1858       __O  uint16_t  LVD1CLR    :  1;               /*!< LVD1ST Clear                                                          */
1859       __O  uint16_t  LVD2CLR    :  1;               /*!< LVD2ST Clear                                                          */
1860       __O  uint16_t  VBATTCLR   :  1;               /*!< VBATTST Clear                                                         */
1861            uint16_t             :  1;
1862       __O  uint16_t  OSTCLR     :  1;               /*!< OSTST Clear                                                           */
1863       __O  uint16_t  NMICLR     :  1;               /*!< NMIST Clear                                                           */
1864       __O  uint16_t  RPECLR     :  1;               /*!< RPEST Clear                                                           */
1865       __O  uint16_t  RECCCLR    :  1;               /*!< RECCST Clear                                                          */
1866       __O  uint16_t  BUSSCLR    :  1;               /*!< BUSSST Clear                                                          */
1867       __O  uint16_t  BUSMCLR    :  1;               /*!< BUSMST Clear                                                          */
1868       __O  uint16_t  SPECLR     :  1;               /*!< SPEST Clear                                                           */
1869     } NMICLR_b;                                     /*!< BitSize                                                               */
1870   };
1871   __I  uint16_t  RESERVED3[7];
1872 
1873   union {
1874     __I  uint16_t  NMISR;                           /*!< Non-Maskable Interrupt Status Register                                */
1875 
1876     struct {
1877       __I  uint16_t  IWDTST     :  1;               /*!< IWDT Underflow/Refresh Error Status Flag                              */
1878       __I  uint16_t  WDTST      :  1;               /*!< WDT Underflow/Refresh Error Status Flag                               */
1879       __I  uint16_t  LVD1ST     :  1;               /*!< Voltage-Monitoring 1 Interrupt Status Flag                            */
1880       __I  uint16_t  LVD2ST     :  1;               /*!< Voltage-Monitoring 2 Interrupt Status Flag                            */
1881       __I  uint16_t  VBATTST    :  1;               /*!< VBATT monitor Interrupt Status Flag                                   */
1882            uint16_t             :  1;
1883       __I  uint16_t  OSTST      :  1;               /*!< Oscillation Stop Detection Interrupt Status Flag                      */
1884       __I  uint16_t  NMIST      :  1;               /*!< NMI Status Flag                                                       */
1885       __I  uint16_t  RPEST      :  1;               /*!< RAM Parity Error Interrupt Status Flag                                */
1886       __I  uint16_t  RECCST     :  1;               /*!< RAM ECC Error Interrupt Status Flag                                   */
1887       __I  uint16_t  BUSSST     :  1;               /*!< MPU Bus Slave Error Interrupt Status Flag                             */
1888       __I  uint16_t  BUSMST     :  1;               /*!< MPU Bus Master Error Interrupt Status Flag                            */
1889       __I  uint16_t  SPEST      :  1;               /*!< MPU Stack Error Interrupt Status Flag                                 */
1890     } NMISR_b;                                      /*!< BitSize                                                               */
1891   };
1892   __I  uint16_t  RESERVED4[47];
1893 
1894   union {
1895     __IO uint32_t  WUPEN;                           /*!< Wake Up interrupt enable register                                     */
1896 
1897     struct {
1898       __IO uint32_t  IRQWUPEN0  :  1;               /*!< IRQ0 interrupt S/W standby returns enable bit                         */
1899       __IO uint32_t  IRQWUPEN1  :  1;               /*!< IRQ1 interrupt S/W standby returns enable bit                         */
1900       __IO uint32_t  IRQWUPEN2  :  1;               /*!< IRQ2 interrupt S/W standby returns enable bit                         */
1901       __IO uint32_t  IRQWUPEN3  :  1;               /*!< IRQ3 interrupt S/W standby returns enable bit                         */
1902       __IO uint32_t  IRQWUPEN4  :  1;               /*!< IRQ4 interrupt S/W standby returns enable bit                         */
1903       __IO uint32_t  IRQWUPEN5  :  1;               /*!< IRQ5 interrupt S/W standby returns enable bit                         */
1904       __IO uint32_t  IRQWUPEN6  :  1;               /*!< IRQ6 interrupt S/W standby returns enable bit                         */
1905       __IO uint32_t  IRQWUPEN7  :  1;               /*!< IRQ7 interrupt S/W standby returns enable bit                         */
1906       __IO uint32_t  IRQWUPEN8  :  1;               /*!< IRQ8 interrupt S/W standby returns enable bit                         */
1907       __IO uint32_t  IRQWUPEN9  :  1;               /*!< IRQ9 interrupt S/W standby returns enable bit                         */
1908       __IO uint32_t  IRQWUPEN10 :  1;               /*!< IRQ10 interrupt S/W standby returns enable bit                        */
1909       __IO uint32_t  IRQWUPEN11 :  1;               /*!< IRQ11 interrupt S/W standby returns enable bit                        */
1910       __IO uint32_t  IRQWUPEN12 :  1;               /*!< IRQ12 interrupt S/W standby returns enable bit                        */
1911       __IO uint32_t  IRQWUPEN13 :  1;               /*!< IRQ13 interrupt S/W standby returns enable bit                        */
1912       __IO uint32_t  IRQWUPEN14 :  1;               /*!< IRQ14 interrupt S/W standby returns enable bit                        */
1913       __IO uint32_t  IRQWUPEN15 :  1;               /*!< IRQ15 interrupt S/W standby returns enable bit                        */
1914       __IO uint32_t  IWDTWUPEN  :  1;               /*!< IWDT interrupt S/W standby returns enable bit                         */
1915       __IO uint32_t  KEYWUPEN   :  1;               /*!< Key interrupt S/W standby returns enable bit                          */
1916       __IO uint32_t  LVD1WUPEN  :  1;               /*!< LVD1 interrupt S/W standby returns enable bit                         */
1917       __IO uint32_t  LVD2WUPEN  :  1;               /*!< LVD2 interrupt S/W standby returns enable bit                         */
1918            uint32_t             :  2;
1919       __IO uint32_t  COMPOC0WUPEN:  1;              /*!< Comparator-OC0 interrupt S/W standby returns enable bit               */
1920            uint32_t             :  1;
1921       __IO uint32_t  RTCALMWUPEN:  1;               /*!< RTC alarm interrupt S/W standby returns enable bit                    */
1922       __IO uint32_t  RTCPRDWUPEN:  1;               /*!< RCT period interrupt S/W standby returns enable bit                   */
1923       __IO uint32_t  USBHSWUPEN :  1;               /*!< USBHS interrupt S/W standby returns enable bit                        */
1924       __IO uint32_t  USBFSWUPEN :  1;               /*!< USBFS interrupt S/W standby returns enable bit                        */
1925       __IO uint32_t  AGT1UDWUPEN:  1;               /*!< AGT1 underflow interrupt S/W standby returns enable bit               */
1926       __IO uint32_t  AGT1CAWUPEN:  1;               /*!< AGT1 compare match A interrupt S/W standby returns enable bit         */
1927       __IO uint32_t  AGT1CBWUPEN:  1;               /*!< AGT1 compare match B interrupt S/W standby returns enable bit         */
1928       __IO uint32_t  RIIC0WUPEN :  1;               /*!< RIIC0 address match interrupt S/W standby returns enable bit          */
1929     } WUPEN_b;                                      /*!< BitSize                                                               */
1930   };
1931   __I  uint32_t  RESERVED5[23];
1932 
1933   union {
1934     __IO uint16_t  SELSR0;                          /*!< Event Selection to Cancel Snooze Mode                                 */
1935 
1936     struct {
1937       __IO uint16_t  SELS       :  9;               /*!< Event selection to cancel snooze mode                                 */
1938     } SELSR0_b;                                     /*!< BitSize                                                               */
1939   };
1940   __I  uint16_t  RESERVED6[63];
1941   R_ICU_DELSRn_Type DELSRn[8];                      /*!< DMAC Event Link Setting Register %s                                   */
1942   __I  uint32_t  RESERVED7[24];
1943 
1944   union {
1945     __IO uint32_t  IELSRn[96];                      /*!< INT Event Link Setting Register %s                                    */
1946 
1947     struct {
1948       __IO uint32_t  IELS       :  9;               /*!< Event selection to NVIC                                               */
1949            uint32_t             :  7;
1950       __IO uint32_t  IR         :  1;               /*!< Interrupt Status Flag                                                 */
1951            uint32_t             :  7;
1952       __IO uint32_t  DTCE       :  1;               /*!< DTC Activation Enable                                                 */
1953     } IELSRn_b[96];                                 /*!< BitSize                                                               */
1954   };
1955 } R_ICU_Type;
1956 
1957 
1958 /* ================================================================================ */
1959 /* ================                      R_DBG                     ================ */
1960 /* ================================================================================ */
1961 
1962 
1963 /**
1964   * @brief Debug Function (R_DBG)
1965   */
1966 
1967 typedef struct {                                    /*!< R_DBG Structure                                                       */
1968 
1969   union {
1970     __I  uint32_t  DBGSTR;                          /*!< Debug Status Register                                                 */
1971 
1972     struct {
1973            uint32_t             : 28;
1974       __I  uint32_t  CDBGPWRUPREQ:  1;              /*!< Debug power-up request                                                */
1975       __I  uint32_t  CDBGPWRUPACK:  1;              /*!< Debug power-up acknowledge                                            */
1976     } DBGSTR_b;                                     /*!< BitSize                                                               */
1977   };
1978   __I  uint32_t  RESERVED[3];
1979 
1980   union {
1981     __IO uint32_t  DBGSTOPCR;                       /*!< Debug Stop Control Register                                           */
1982 
1983     struct {
1984       __IO uint32_t  DSIWDT     :  1;               /*!< Mask bit for IWDT reset/interruptNOTE: This bit is regarded
1985                                                          as 0 when debugger is not connected.                                  */
1986       __IO uint32_t  DSWDT      :  1;               /*!< Mask bit for WDT reset/interruptNOTE: This bit is regarded as
1987                                                          0 when debugger is not connected.                                     */
1988            uint32_t             : 14;
1989       __IO uint32_t  DSLVD0     :  1;               /*!< Mask bit for LVD0 reset/interruptNOTE: This bit is regarded
1990                                                          as 0 when debugger is not connected.                                  */
1991       __IO uint32_t  DSLVD1     :  1;               /*!< Mask bit for LVD1 reset/interruptNOTE: This bit is regarded
1992                                                          as 0 when debugger is not connected.                                  */
1993       __IO uint32_t  DSLVD2     :  1;               /*!< Mask bit for LVD2 reset/interruptNOTE: This bit is regarded
1994                                                          as 0 when debugger is not connected.                                  */
1995            uint32_t             :  5;
1996       __IO uint32_t  DSRPER     :  1;               /*!< Mask bit for RAM parity error reset/interruptNOTE: This bit
1997                                                          is regarded as 0 when debugger is not connected.                      */
1998       __IO uint32_t  DSRECCR    :  1;               /*!< Mask bit for RAM ECC error reset/interruptNOTE: This bit is
1999                                                          regarded as 0 when debugger is not connected.                         */
2000     } DBGSTOPCR_b;                                  /*!< BitSize                                                               */
2001   };
2002   __I  uint32_t  RESERVED1[3];
2003 
2004   union {
2005     __IO uint32_t  TRACECTR;                        /*!< Trace Control Register                                                */
2006 
2007     struct {
2008            uint32_t             : 31;
2009       __IO uint32_t  ENETBFULL  :  1;               /*!< Enable bit for halt request by ETB full                               */
2010     } TRACECTR_b;                                   /*!< BitSize                                                               */
2011   };
2012 } R_DBG_Type;
2013 
2014 /* ================================================================================ */
2015 /* ================                     R_ROMC                     ================ */
2016 /* ================================================================================ */
2017 
2018 
2019 /**
2020   * @brief ROM Cache (R_ROMC)
2021   */
2022 
2023 typedef struct {                                    /*!< R_ROMC Structure                                                      */
2024   __I  uint8_t RESERVED[64 * 4];
2025 
2026   union {
2027     __IO uint16_t  ROMCE;                           /*!< ROM Cache Enable                                                      */
2028 
2029     struct {
2030       __IO uint16_t  ROMCEN     :  1;               /*!< ROMC Enable                                                           */
2031     } ROMCE_b;                                      /*!< BitSize                                                               */
2032   };
2033   __I  uint8_t  RESERVED1[2];   // Padding changed from uint16_t
2034 
2035   union {
2036     __IO uint16_t  ROMCIV;                          /*!< ROM Cache Invalidation                                                */
2037 
2038     struct {
2039       __IO uint16_t  ROMCIV     :  1;               /*!< ROM Cache Invalidation                                                */
2040     } ROMCIV_b;                                     /*!< BitSize                                                               */
2041   };
2042   __I  uint8_t RESERVED2[11 * 2];
2043 
2044   union {
2045     __IO uint8_t   ROMWT;                           /*!< ROM wait control register                                             */
2046 
2047     struct {
2048       __IO uint8_t   ROMWT      :  3;               /*!< These bits represent the ratio of the CPU clock period to the
2049                                                          Flash memory access time.                                             */
2050     } ROMWT_b;                                      /*!< BitSize                                                               */
2051   };
2052 } R_ROMC_Type;
2053 
2054 
2055 /* ================================================================================ */
2056 /* ================                    R_SYSTEM                    ================ */
2057 /* ================================================================================ */
2058 
2059 
2060 /**
2061   * @brief System Control (R_SYSTEM)
2062   */
2063 
2064 typedef struct {                                    /*!< R_SYSTEM Structure                                                    */
2065   __I  uint32_t  RESERVED[3];
2066 
2067   union {
2068     __IO uint16_t  SBYCR;                           /*!< Standby Control Register                                              */
2069 
2070     struct {
2071            uint16_t             : 14;
2072       __IO uint16_t  OPE        :  1;               /*!< Output Port Enable                                                    */
2073       __IO uint16_t  SSBY       :  1;               /*!< Software Standby                                                      */
2074     } SBYCR_b;                                      /*!< BitSize                                                               */
2075   };
2076   __I  uint16_t  RESERVED1[7];
2077 
2078   union {
2079     __IO uint32_t  MSTPCRA;                         /*!< Module Stop Control Register A                                        */
2080 
2081     struct {
2082       __IO uint32_t  MSTPA0     :  1;               /*!< RAM0 Module Stop                                                      */
2083       __IO uint32_t  MSTPA1     :  1;               /*!< RAM1 Module Stop                                                      */
2084            uint32_t             :  3;
2085       __IO uint32_t  MSTPA5     :  1;               /*!< High-Speed RAM Module Stop                                            */
2086       __IO uint32_t  MSTPA6     :  1;               /*!< ECCRAM Module Stop                                                    */
2087       __IO uint32_t  MSTPA7     :  1;               /*!< Standby RAM Module Stop                                               */
2088            uint32_t             : 14;
2089       __IO uint32_t  MSTPA22    :  1;               /*!< DMA Controller/Data Transfer Controller Module Stop                   */
2090     } MSTPCRA_b;                                    /*!< BitSize                                                               */
2091   };
2092 
2093   union {
2094     __IO uint32_t  SCKDIVCR;                        /*!< System Clock Division Control Register                                */
2095 
2096     struct {
2097       __IO uint32_t  PCKD       :  3;               /*!< Peripheral Module Clock D (PCLKD) Select                              */
2098            uint32_t             :  1;
2099       __IO uint32_t  PCKC       :  3;               /*!< Peripheral Module Clock C (PCLKC) Select                              */
2100            uint32_t             :  1;
2101       __IO uint32_t  PCKB       :  3;               /*!< Peripheral Module Clock B (PCLKB) Select                              */
2102            uint32_t             :  1;
2103       __IO uint32_t  PCKA       :  3;               /*!< Peripheral Module Clock A (PCLKA) Select                              */
2104            uint32_t             :  1;
2105       __IO uint32_t  BCK        :  3;               /*!< External Bus Clock (BCLK) Select                                      */
2106            uint32_t             :  5;
2107       __IO uint32_t  ICK        :  3;               /*!< System Clock (ICLK) Select                                            */
2108            uint32_t             :  1;
2109       __IO uint32_t  FCK        :  3;               /*!< Flash IF Clock (FCLK) Select                                          */
2110     } SCKDIVCR_b;                                   /*!< BitSize                                                               */
2111   };
2112 
2113   union {
2114     __IO uint8_t   SCKDIVCR2;                       /*!< System Clock Division Control Register 2                              */
2115 
2116     struct {
2117            uint8_t              :  4;
2118       __IO uint8_t   UCK        :  3;               /*!< USB Clock (UCLK) Select                                               */
2119     } SCKDIVCR2_b;                                  /*!< BitSize                                                               */
2120   };
2121   __I  uint8_t   RESERVED2;
2122 
2123   union {
2124     __IO uint8_t   SCKSCR;                          /*!< System Clock Source Control Register                                  */
2125 
2126     struct {
2127       __IO uint8_t   CKSEL      :  3;               /*!< Clock Source Select                                                   */
2128     } SCKSCR_b;                                     /*!< BitSize                                                               */
2129   };
2130   __I  uint8_t   RESERVED3;
2131 
2132   union {
2133     __IO uint16_t  PLLCCR;                          /*!< PLL Clock Control Register                                            */
2134 
2135     struct {
2136       __IO uint16_t  PLIDIV     :  2;               /*!< PLL Input Frequency Division Ratio Select                             */
2137            uint16_t             :  2;
2138       __IO uint16_t  PLLSRCSEL  :  1;               /*!< PLL Clock Source Select                                               */
2139            uint16_t             :  3;
2140       __IO uint16_t  PLLMUL     :  6;               /*!< PLL Frequency Multiplication Factor Select [PLL Frequency Multiplication
2141                                                          Factor] = (PLLUMUL+1) / 2 Range: 0x23 - 0x3B for example 010011:
2142                                                           x10.0 010100: x10.5 010101: x11.0 : 011100: x14.5 011101: x15.0
2143                                                           011110: x15.5 : 111010: x29.5 111011: x30.0                          */
2144     } PLLCCR_b;                                     /*!< BitSize                                                               */
2145   };
2146 
2147   union {
2148     __IO uint8_t   PLLCR;                           /*!< PLL Control Register                                                  */
2149 
2150     struct {
2151       __IO uint8_t   PLLSTP     :  1;               /*!< PLL Stop Control                                                      */
2152       uint8_t                   :  7;
2153 
2154     } PLLCR_b;                                      /*!< BitSize                                                               */
2155   };
2156 
2157   union {
2158      __IO uint8_t  PLLCCR2;                          /*!< PLL Clock Control Register                                            */
2159 
2160      struct {
2161        __IO uint8_t  PLLMUL     :  5;               /*!< PLL Multipler                             */
2162             uint8_t             :  1;
2163        __IO uint8_t  PLODIV     :  2;               /*!< PLL Divider                 */
2164      } PLLCCR2_b;                                   /*!< BitSize                                                               */
2165    };
2166   __I  uint8_t   RESERVED4[4];
2167 
2168   union {
2169     __IO uint8_t   BCKCR;                           /*!< External Bus Clock Control Register                                   */
2170 
2171     struct {
2172       __IO uint8_t   BCLKDIV    :  1;               /*!< BCLK Pin Output Select                                                */
2173     } BCKCR_b;                                      /*!< BitSize                                                               */
2174   };
2175 
2176   union {
2177     __IO uint8_t   MEMWAITCR;                       /*!< Memory Wait Cycle COntrol register                                   */
2178 
2179     struct {
2180       __IO uint8_t MEMWAIT      :  1;               /*!< MEMWAIT Select                                                */
2181     } MEMWAITCR_b;                                  /*!< BitSize                                                               */
2182   };
2183 
2184   union {
2185     __IO uint8_t   MOSCCR;                          /*!< Main Clock Oscillator Control Register                                */
2186 
2187     struct {
2188       __IO uint8_t   MOSTP      :  1;               /*!< Main Clock Oscillator Stop                                            */
2189     } MOSCCR_b;                                     /*!< BitSize                                                               */
2190   };
2191   __I  uint8_t   RESERVED6[3];
2192 
2193   union {
2194     __IO uint8_t   HOCOCR;                          /*!< High-Speed On-Chip Oscillator Control Register                        */
2195 
2196     struct {
2197       __IO uint8_t   HCSTP      :  1;               /*!< HOCO Stop                                                             */
2198     } HOCOCR_b;                                     /*!< BitSize                                                               */
2199   };
2200   __I  uint8_t   RESERVED7;
2201 
2202   union {
2203     __IO uint8_t   MOCOCR;                          /*!< Middle-Speed On-Chip Oscillator Control Register                      */
2204 
2205     struct {
2206       __IO uint8_t   MCSTP      :  1;               /*!< MOCO Stop                                                             */
2207     } MOCOCR_b;                                     /*!< BitSize                                                               */
2208   };
2209   __I  uint8_t   RESERVED8[3];
2210 
2211   union {
2212     __I  uint8_t   OSCSF;                           /*!< Oscillation Stabilization Flag Register                               */
2213 
2214     struct {
2215       __I  uint8_t   HOCOSF     :  1;               /*!< HOCO Clock Oscillation Stabilization FlagNOTE: The HOCOSF bit
2216                                                          value after a reset is 1 when the OFS1.HOCOEN bit is 0. It is
2217                                                           0 when the OFS1.HOCOEN bit is 1.                                     */
2218            uint8_t              :  2;
2219       __I  uint8_t   MOSCSF     :  1;               /*!< Main Clock Oscillation Stabilization Flag                             */
2220            uint8_t              :  1;
2221       __I  uint8_t   PLLSF      :  1;               /*!< PLL Clock Oscillation Stabilization Flag                              */
2222     } OSCSF_b;                                      /*!< BitSize                                                               */
2223   };
2224   __I  uint8_t   RESERVED9;
2225 
2226   union {
2227     __IO uint8_t   CKOCR;                           /*!< Clock Out Control Register                                            */
2228 
2229     struct {
2230       __IO uint8_t   CKOSEL     :  3;               /*!< Clock out source select                                               */
2231            uint8_t              :  1;
2232       __IO uint8_t   CKODIV     :  3;               /*!< Clock out input frequency Division Select                             */
2233       __IO uint8_t   CKOEN      :  1;               /*!< Clock out enable                                                      */
2234     } CKOCR_b;                                      /*!< BitSize                                                               */
2235   };
2236   __I  uint8_t   RESERVED10;
2237 
2238   union {
2239     __IO uint8_t   OSTDCR;                          /*!< Oscillation Stop Detection Control Register                           */
2240 
2241     struct {
2242       __IO uint8_t   OSTDIE     :  1;               /*!< Oscillation Stop Detection Interrupt Enable                           */
2243            uint8_t              :  6;
2244       __IO uint8_t   OSTDE      :  1;               /*!< Oscillation Stop Detection Function Enable                            */
2245     } OSTDCR_b;                                     /*!< BitSize                                                               */
2246   };
2247 
2248   union {
2249     __IO uint8_t   OSTDSR;                          /*!< Oscillation Stop Detection Status Register                            */
2250 
2251     struct {
2252       __IO uint8_t   OSTDF      :  1;               /*!< Oscillation Stop Detection Flag                                       */
2253     } OSTDSR_b;                                     /*!< BitSize                                                               */
2254   };
2255   __I  uint8_t  RESERVED11A[14];
2256 
2257   union {
2258     __IO uint8_t   SLCDSCKCR;                       /*!< Segment LCD Source Clock Control Register                            */
2259 
2260     struct {
2261     __IO uint8_t  LCDSCKSEL     :  4;               /*!< LCD Source Clock                                       */
2262       uint8_t                   :  3;
2263     __IO uint8_t  LCDSCKEN      :  1;               /*!< LCD Source Clock Out Enable                                       */
2264     } SLCDSCKCR_b;                                  /*!< BitSize                                                               */
2265   };
2266 
2267   __I  uint8_t  RESERVED11B[1];
2268   union {
2269     __IO uint8_t   EBCKOCR;                         /*!< External Bus Clock Output Control Register                            */
2270 
2271     struct {
2272       __IO uint8_t   EBCKOEN    :  1;               /*!< BCLK Pin Output Control                                               */
2273     } EBCKOCR_b;                                    /*!< BitSize                                                               */
2274   };
2275 
2276   union {
2277     __IO uint8_t   SDCKOCR;                         /*!< SDRAM Clock Output Control Register                                   */
2278 
2279     struct {
2280       __IO uint8_t   SDCKOEN    :  1;               /*!< SDCLK Pin Output Control                                              */
2281     } SDCKOCR_b;                                    /*!< BitSize                                                               */
2282   };
2283   __I  uint8_t   RESERVED12[13];
2284 
2285   union {
2286     __IO uint8_t   MOCOUTCR;                        /*!< MOCO User Trimming Control Register                                   */
2287 
2288     struct {
2289       __IO uint8_t   MOCOUTRM   :  8;               /*!< MOCO User Trimming 1000_0000 : -128 1000_0001 : -127 1000_0010
2290                                                          : -126 . . . 1111_1111 : -1 0000_0000 : Center Code 0000_0001
2291                                                           : +1 . . . 0111_1101 : +125 0111_1110 : +126 0111_1111 : +127These
2292                                                           bits are added to original MOCO trimming bits                        */
2293     } MOCOUTCR_b;                                   /*!< BitSize                                                               */
2294   };
2295 
2296   union {
2297     __IO uint8_t   HOCOUTCR;                        /*!< HOCO User Trimming Control Register                                   */
2298 
2299     struct {
2300       __IO uint8_t   HOCOUTRM   :  8;               /*!< HOCO User Trimming 1000_0000 : -128 1000_0001 : -127 1000_0010
2301                                                          : -126 . . . 1111_1111 : -1 0000_0000 : Center Code 0000_0001
2302                                                           : +1 . . . 0111_1101 : +125 0111_1110 : +126 0111_1111 : +127These
2303                                                           bits are added to original HOCO trimming bits                        */
2304     } HOCOUTCR_b;                                   /*!< BitSize                                                               */
2305   };
2306   __I  uint8_t   RESERVED13[47];
2307 
2308 
2309 
2310   union {
2311     __IO uint8_t   SNZCR;                           /*!< Snooze Control Register                                               */
2312 
2313     struct {
2314       __IO uint8_t   RXDREQEN   :  1;               /*!< RXD0 Snooze Request EnableNote:Do not set to 1 other than in
2315                                                          asynchronous mode.                                                    */
2316       __IO uint8_t   SNZDTCEN   :  1;               /*!< DTC Enable in Snooze Mode                                             */
2317            uint8_t              :  5;
2318       __IO uint8_t   SNZE       :  1;               /*!< Snooze Mode Enable                                                    */
2319     } SNZCR_b;                                      /*!< BitSize                                                               */
2320   };
2321   __I  uint8_t   RESERVED14;
2322 
2323   union {
2324     __IO uint8_t   SNZEDCR;                         /*!< Snooze End Control Register                                           */
2325 
2326     struct {
2327       __IO uint8_t   AGT1UNFED  :  1;               /*!< AGT1 underflow Snooze End Enable                                      */
2328       __IO uint8_t   DTCZRED    :  1;               /*!< Last DTC transmission completion Snooze End Enable                    */
2329       __IO uint8_t   DTCNZRED   :  1;               /*!< Not Last DTC transmission completion Snooze End Enable                */
2330       __IO uint8_t   AD0MATED   :  1;               /*!< AD ch0 result match Snooze End Enable                                 */
2331       __IO uint8_t   AD0UMTED   :  1;               /*!< AD ch0 result unmatch Snooze End Enable                               */
2332       __IO uint8_t   AD1MATED   :  1;               /*!< AD ch1 result match Snooze End Enable                                 */
2333       __IO uint8_t   AD1UMTED   :  1;               /*!< AD ch1 result unmatch Snooze End Enable                               */
2334       __IO uint8_t   SCI0UMTED  :  1;               /*!< SCI0 address unmatch Snooze End EnableNote: Do not set to 1
2335                                                          other than in asynchronous mode.                                      */
2336     } SNZEDCR_b;                                    /*!< BitSize                                                               */
2337   };
2338   __I  uint8_t   RESERVED15[3];
2339 
2340   union {
2341     __IO uint32_t  SNZREQCR;                        /*!< Snooze Request Control Register                                       */
2342 
2343     struct {
2344       __IO uint32_t  SNZREQEN0  :  1;               /*!< Snooze Request Enable 0Enable IRQ0 pin snooze request                 */
2345       __IO uint32_t  SNZREQEN1  :  1;               /*!< Snooze Request Enable 1Enable IRQ1 pin snooze request                 */
2346       __IO uint32_t  SNZREQEN2  :  1;               /*!< Snooze Request Enable 2Enable IRQ2 pin snooze request                 */
2347       __IO uint32_t  SNZREQEN3  :  1;               /*!< Snooze Request Enable 3Enable IRQ3 pin snooze request                 */
2348       __IO uint32_t  SNZREQEN4  :  1;               /*!< Snooze Request Enable 4Enable IRQ4 pin snooze request                 */
2349       __IO uint32_t  SNZREQEN5  :  1;               /*!< Snooze Request Enable 5Enable IRQ5 pin snooze request                 */
2350       __IO uint32_t  SNZREQEN6  :  1;               /*!< Snooze Request Enable 6Enable IRQ6 pin snooze request                 */
2351       __IO uint32_t  SNZREQEN7  :  1;               /*!< Snooze Request Enable 7Enable IRQ7 pin snooze request                 */
2352       __IO uint32_t  SNZREQEN8  :  1;               /*!< Snooze Request Enable 8Enable IRQ8 pin snooze request                 */
2353       __IO uint32_t  SNZREQEN9  :  1;               /*!< Snooze Request Enable 9Enable IRQ9 pin snooze request                 */
2354       __IO uint32_t  SNZREQEN10 :  1;               /*!< Snooze Request Enable 10Enable IRQ10 pin snooze request               */
2355       __IO uint32_t  SNZREQEN11 :  1;               /*!< Snooze Request Enable 11Enable IRQ11 pin snooze request               */
2356       __IO uint32_t  SNZREQEN12 :  1;               /*!< Snooze Request Enable 12Enable IRQ12 pin snooze request               */
2357       __IO uint32_t  SNZREQEN13 :  1;               /*!< Snooze Request Enable 13Enable IRQ13 pin snooze request               */
2358       __IO uint32_t  SNZREQEN14 :  1;               /*!< Snooze Request Enable 14Enable IRQ14 pin snooze request               */
2359       __IO uint32_t  SNZREQEN15 :  1;               /*!< Snooze Request Enable 15Enable IRQ15 pin snooze request               */
2360            uint32_t             :  1;
2361       __IO uint32_t  SNZREQEN17 :  1;               /*!< Snooze Request Enable 17Enable KR snooze request                      */
2362            uint32_t             :  4;
2363       __IO uint32_t  SNZREQEN22 :  1;               /*!< Snooze Request Enable 22Enable Comparator-OC0 snooze request          */
2364            uint32_t             :  1;
2365       __IO uint32_t  SNZREQEN24 :  1;               /*!< Snooze Request Enable 24Enable RTC alarm snooze request               */
2366       __IO uint32_t  SNZREQEN25 :  1;               /*!< Snooze Request Enable 25Enable RTC period snooze request              */
2367            uint32_t             :  2;
2368       __IO uint32_t  SNZREQEN28 :  1;               /*!< Snooze Request Enable 28Enable AGT1 underflow snooze request          */
2369       __IO uint32_t  SNZREQEN29 :  1;               /*!< Snooze Request Enable 29Enable AGT1 compare match A snooze request    */
2370       __IO uint32_t  SNZREQEN30 :  1;               /*!< Snooze Request Enable 30Enable AGT1 compare match B snooze request    */
2371     } SNZREQCR_b;                                   /*!< BitSize                                                               */
2372   };
2373 
2374   __I  uint8_t  RESERVED16[2];
2375 
2376   union {
2377     __IO uint8_t   FLSTOPCR;                        /*!< Flash Operation Control Register                                      */
2378 
2379     struct {
2380       __IO uint8_t   FLSTOP     :  1;               /*!< Selecting ON/OFF of the Flash Memory Operation                        */
2381            uint8_t              :  3;
2382       __I  uint8_t   FLSTPF     :  1;               /*!< Flash Memory Operation Status Flag                                    */
2383     } FLSTOPCR_b;                                   /*!< BitSize                                                               */
2384   };
2385 
2386   union {
2387     __IO uint8_t   PSMCR;                           /*!< Power Save Memory Control Register                                    */
2388 
2389     struct {
2390       __IO uint8_t   PSMC       :  2;               /*!< Power Save Memory Control                                             */
2391            uint8_t              :  6;
2392     } PSMCR_b;                                      /*!< BitSize                                                               */
2393   };
2394 
2395   union {
2396     __IO uint8_t   OPCCR;                           /*!< Operating Power Control Register                                      */
2397 
2398     struct {
2399       __IO uint8_t   OPCM       :  2;               /*!< Operating Power Control Mode Select                                   */
2400            uint8_t              :  2;
2401       __I  uint8_t   OPCMTSF    :  1;               /*!< Operating Power Control Mode Transition Status Flag                   */
2402     } OPCCR_b;                                      /*!< BitSize                                                               */
2403   };
2404   __I  uint8_t   RESERVED17;
2405 
2406   union {
2407     __IO uint8_t   MOSCWTCR;                        /*!< Main Clock Oscillator Wait Control Register                           */
2408 
2409     struct {
2410       __IO uint8_t   MSTS       :  4;               /*!< Main clock oscillator wait time setting                               */
2411     } MOSCWTCR_b;                                   /*!< BitSize                                                               */
2412   };
2413   __I  uint8_t   RESERVED18a[2];
2414 
2415   union {
2416     __IO uint8_t   HOCOWTCR;                        /*!< HOCO Clock Oscillator Wait Control Register                           */
2417 
2418     struct {
2419       __IO uint8_t   HSTS       :  3;               /*!< HOCO clock oscillator wait time setting                               */
2420     } HOCOWTCR_b;                                   /*!< BitSize                                                               */
2421   };
2422   __I  uint8_t   RESERVED18b[4];
2423 
2424   union {
2425     __IO uint8_t   SOPCCR;                          /*!< Sub Operating Power Control Register                                  */
2426 
2427     struct {
2428       __IO uint8_t   SOPCM      :  1;               /*!< Sub Operating Power Control Mode Select                               */
2429            uint8_t              :  3;
2430       __I  uint8_t   SOPCMTSF   :  1;               /*!< Sub Operating Power Control Mode Transition Status Flag               */
2431     } SOPCCR_b;                                     /*!< BitSize                                                               */
2432   };
2433   __I  uint8_t   RESERVED19[21];
2434 
2435   union {
2436     __IO uint16_t  RSTSR1;                          /*!< Reset Status Register 1                                               */
2437 
2438     struct {
2439       __IO uint16_t  IWDTRF     :  1;               /*!< Independent Watchdog Timer Reset Detect Flag                          */
2440       __IO uint16_t  WDTRF      :  1;               /*!< Watchdog Timer Reset Detect Flag                                      */
2441       __IO uint16_t  SWRF       :  1;               /*!< Software Reset Detect Flag                                            */
2442            uint16_t             :  5;
2443       __IO uint16_t  RPERF      :  1;               /*!< RAM Parity Error Reset Detect Flag                                    */
2444       __IO uint16_t  REERF      :  1;               /*!< RAM ECC Error Reset Detect Flag                                       */
2445       __IO uint16_t  BUSSRF     :  1;               /*!< Bus Slave MPU Reset Detect Flag                                       */
2446       __IO uint16_t  BUSMRF     :  1;               /*!< Bus Master MPU Reset Detect Flag                                      */
2447       __IO uint16_t  SPERF      :  1;               /*!< SP Error Reset Detect Flag                                            */
2448     } RSTSR1_b;                                     /*!< BitSize                                                               */
2449   };
2450   __I  uint16_t  RESERVED20;
2451 
2452   union {
2453     __IO uint8_t   SWRRAGT;                         /*!< Software Reset Register for AGT                                       */
2454 
2455     struct {
2456       __IO uint8_t   AGTRST     :  1;               /*!< AG Timer Software Reset                                               */
2457     } SWRRAGT_b;                                    /*!< BitSize                                                               */
2458   };
2459 
2460   __I  uint8_t   RESERVED21[12];
2461 
2462   union {
2463     __IO uint8_t   SDADCCKCR;                       /*!< 24-bit Sigma-Delta A/D Converter Clock Control Register                            */
2464 
2465     struct {
2466     __IO uint8_t  SDADCCKSEL     :  1;              /*!< SDADC Source Clock                                       */
2467     uint8_t                      :  6;
2468     __IO uint8_t  SDADCCKEN      :  1;              /*!< SDADC Source Clock Out Enable                                       */
2469     } SDADCCKCR_b;                                  /*!< BitSize                                                               */
2470   };
2471 
2472   __I  uint8_t   RESERVED21B[14];
2473 
2474   R_SYSTEM_LVDnRC0_Type LVDnRC0[2];                 /*!< Voltage Monitoring %s Circuit Register Cluster 0                      */
2475   __I  uint16_t  RESERVED22[397];
2476 
2477   union {
2478     __IO uint16_t  PRCR;                            /*!< Protect Register                                                      */
2479 
2480     struct {
2481       __IO uint16_t  PRC0       :  1;               /*!< Enables writing to the registers related to the clock generation
2482                                                          circuit.                                                              */
2483       __IO uint16_t  PRC1       :  1;               /*!< Enables writing to the registers related to the operating modes,
2484                                                          the low power consumption modes and the battery backup function.      */
2485            uint16_t             :  1;
2486       __IO uint16_t  PRC3       :  1;               /*!< Enables writing to the registers related to the LVD.                  */
2487            uint16_t             :  4;
2488       __O  uint16_t  PRKEY      :  8;               /*!< PRKEY Key Code                                                        */
2489     } PRCR_b;                                       /*!< BitSize                                                               */
2490   };
2491 
2492   union {
2493     __IO uint8_t   DPSBYCR;                         /*!< Deep Standby Control Register                                         */
2494 
2495     struct {
2496       __IO uint8_t   DEEPCUT    :  2;               /*!< Power-Supply Control                                                  */
2497            uint8_t              :  4;
2498       __IO uint8_t   IOKEEP     :  1;               /*!< I/O Port Retention                                                    */
2499       __IO uint8_t   DPSBY      :  1;               /*!< Deep Software Standby                                                 */
2500     } DPSBYCR_b;                                    /*!< BitSize                                                               */
2501   };
2502   __I  uint8_t   RESERVED23;
2503 
2504   union {
2505     __IO uint8_t   DPSIER0;                         /*!< Deep Standby Interrupt Enable Register 0                              */
2506 
2507     struct {
2508       __IO uint8_t   DIRQ0E     :  1;               /*!< IRQ0-DS Pin Enable                                                    */
2509       __IO uint8_t   DIRQ1E     :  1;               /*!< IRQ1-DS Pin Enable                                                    */
2510       __IO uint8_t   DIRQ2E     :  1;               /*!< IRQ2-DS Pin Enable                                                    */
2511       __IO uint8_t   DIRQ3E     :  1;               /*!< IRQ3-DS Pin Enable                                                    */
2512       __IO uint8_t   DIRQ4E     :  1;               /*!< IRQ4-DS Pin Enable                                                    */
2513       __IO uint8_t   DIRQ5E     :  1;               /*!< IRQ5-DS Pin Enable                                                    */
2514       __IO uint8_t   DIRQ6E     :  1;               /*!< IRQ6-DS Pin Enable                                                    */
2515       __IO uint8_t   DIRQ7E     :  1;               /*!< IRQ7-DS Pin Enable                                                    */
2516     } DPSIER0_b;                                    /*!< BitSize                                                               */
2517   };
2518 
2519   union {
2520     __IO uint8_t   DPSIER1;                         /*!< Deep Standby Interrupt Enable Register 1                              */
2521 
2522     struct {
2523       __IO uint8_t   DIRQ8E     :  1;               /*!< IRQ8-DS Pin Enable                                                    */
2524       __IO uint8_t   DIRQ9E     :  1;               /*!< IRQ9-DS Pin Enable                                                    */
2525       __IO uint8_t   DIRQ10E    :  1;               /*!< IRQ10-DS Pin Enable                                                   */
2526       __IO uint8_t   DIRQ11E    :  1;               /*!< IRQ11-DS Pin Enable                                                   */
2527       __IO uint8_t   DIRQ12E    :  1;               /*!< IRQ12-DS Pin Enable                                                   */
2528       __IO uint8_t   DIRQ13E    :  1;               /*!< IRQ13-DS Pin Enable                                                   */
2529       __IO uint8_t   DIRQ14E    :  1;               /*!< IRQ14-DS Pin Enable                                                   */
2530       __IO uint8_t   DIRQ15E    :  1;               /*!< IRQ15-DS Pin Enable                                                   */
2531     } DPSIER1_b;                                    /*!< BitSize                                                               */
2532   };
2533 
2534   union {
2535     __IO uint8_t   DPSIER2;                         /*!< Deep Standby Interrupt Enable Register 2                              */
2536 
2537     struct {
2538       __IO uint8_t   DLVD1IE    :  1;               /*!< LVD1 Deep Standby Cancel Signal Enable                                */
2539       __IO uint8_t   DLVD2IE    :  1;               /*!< LVD2 Deep Standby Cancel Signal Enable                                */
2540       __IO uint8_t   DTRTCIIE   :  1;               /*!< RTC Interval interrupt Deep Standby Cancel Signal Enable              */
2541       __IO uint8_t   DRTCAIE    :  1;               /*!< RTC Alarm interrupt Deep Standby Cancel Signal Enable                 */
2542       __IO uint8_t   DNMIE      :  1;               /*!< NMI Pin Enable                                                        */
2543     } DPSIER2_b;                                    /*!< BitSize                                                               */
2544   };
2545 
2546   union {
2547     __IO uint8_t   DPSIER3;                         /*!< Deep Standby Interrupt Enable Register 3                              */
2548 
2549     struct {
2550       __IO uint8_t   DUSBFSIE   :  1;               /*!< USBFS Suspend/Resume Deep Standby Cancel Signal Enable                */
2551       __IO uint8_t   DUSBHSIE   :  1;               /*!< USBHS Suspend/Resume Deep Standby Cancel Signal Enable                */
2552       __IO uint8_t   DAGT1IE    :  1;               /*!< AGT1 Underflow Deep Standby Cancel Signal Enable                      */
2553     } DPSIER3_b;                                    /*!< BitSize                                                               */
2554   };
2555 
2556   union {
2557     __IO uint8_t   DPSIFR0;                         /*!< Deep Standby Interrupt Flag Register 0                                */
2558 
2559     struct {
2560       __IO uint8_t   DIRQ0F     :  1;               /*!< IRQ0-DS Pin Deep Standby Cancel Flag                                  */
2561       __IO uint8_t   DIRQ1F     :  1;               /*!< IRQ1-DS Pin Deep Standby Cancel Flag                                  */
2562       __IO uint8_t   DIRQ2F     :  1;               /*!< IRQ2-DS Pin Deep Standby Cancel Flag                                  */
2563       __IO uint8_t   DIRQ3F     :  1;               /*!< IRQ3-DS Pin Deep Standby Cancel Flag                                  */
2564       __IO uint8_t   DIRQ4F     :  1;               /*!< IRQ4-DS Pin Deep Standby Cancel Flag                                  */
2565       __IO uint8_t   DIRQ5F     :  1;               /*!< IRQ5-DS Pin Deep Standby Cancel Flag                                  */
2566       __IO uint8_t   DIRQ6F     :  1;               /*!< IRQ6-DS Pin Deep Standby Cancel Flag                                  */
2567       __IO uint8_t   DIRQ7F     :  1;               /*!< IRQ7-DS Pin Deep Standby Cancel Flag                                  */
2568     } DPSIFR0_b;                                    /*!< BitSize                                                               */
2569   };
2570 
2571   union {
2572     __IO uint8_t   DPSIFR1;                         /*!< Deep Standby Interrupt Flag Register 1                                */
2573 
2574     struct {
2575       __IO uint8_t   DIRQ8F     :  1;               /*!< IRQ8-DS Pin Deep Standby Cancel Flag                                  */
2576       __IO uint8_t   DIRQ9F     :  1;               /*!< IRQ9-DS Pin Deep Standby Cancel Flag                                  */
2577       __IO uint8_t   DIRQ10F    :  1;               /*!< IRQ10-DS Pin Deep Standby Cancel Flag                                 */
2578       __IO uint8_t   DIRQ11F    :  1;               /*!< IRQ11-DS Pin Deep Standby Cancel Flag                                 */
2579       __IO uint8_t   DIRQ12F    :  1;               /*!< IRQ12-DS Pin Deep Standby Cancel Flag                                 */
2580       __IO uint8_t   DIRQ13F    :  1;               /*!< IRQ13-DS Pin Deep Standby Cancel Flag                                 */
2581       __IO uint8_t   DIRQ14F    :  1;               /*!< IRQ14-DS Pin Deep Standby Cancel Flag                                 */
2582       __IO uint8_t   DIRQ15F    :  1;               /*!< IRQ15-DS Pin Deep Standby Cancel Flag                                 */
2583     } DPSIFR1_b;                                    /*!< BitSize                                                               */
2584   };
2585 
2586   union {
2587     __IO uint8_t   DPSIFR2;                         /*!< Deep Standby Interrupt Flag Register 2                                */
2588 
2589     struct {
2590       __IO uint8_t   DLVD1IF    :  1;               /*!< LVD1 Deep Standby Cancel Flag                                         */
2591       __IO uint8_t   DLVD2IF    :  1;               /*!< LVD2 Deep Standby Cancel Flag                                         */
2592       __IO uint8_t   DTRTCIIF   :  1;               /*!< RTC Interval interrupt Deep Standby Cancel Flag                       */
2593       __IO uint8_t   DRTCAIF    :  1;               /*!< RTC Alarm interrupt Deep Standby Cancel Flag                          */
2594       __IO uint8_t   DNMIF      :  1;               /*!< NMI Pin Deep Standby Cancel Flag                                      */
2595     } DPSIFR2_b;                                    /*!< BitSize                                                               */
2596   };
2597 
2598   union {
2599     __IO uint8_t   DPSIFR3;                         /*!< Deep Standby Interrupt Flag Register 3                                */
2600 
2601     struct {
2602       __IO uint8_t   DUSBFSIF   :  1;               /*!< USBFS Suspend/Resume Deep Standby Cancel Flag                         */
2603       __IO uint8_t   DUSBHSIF   :  1;               /*!< USBHS Suspend/Resume Deep Standby Cancel Flag                         */
2604       __IO uint8_t   DAGT1IF    :  1;               /*!< AGT1 Underflow Deep Standby Cancel Flag                               */
2605     } DPSIFR3_b;                                    /*!< BitSize                                                               */
2606   };
2607 
2608   union {
2609     __IO uint8_t   DPSIEGR0;                        /*!< Deep Standby Interrupt Edge Register 0                                */
2610 
2611     struct {
2612       __IO uint8_t   DIRQ0EG    :  1;               /*!< IRQ0-DS Pin Edge Select                                               */
2613       __IO uint8_t   DIRQ1EG    :  1;               /*!< IRQ1-DS Pin Edge Select                                               */
2614       __IO uint8_t   DIRQ2EG    :  1;               /*!< IRQ2-DS Pin Edge Select                                               */
2615       __IO uint8_t   DIRQ3EG    :  1;               /*!< IRQ3-DS Pin Edge Select                                               */
2616       __IO uint8_t   DIRQ4EG    :  1;               /*!< IRQ4-DS Pin Edge Select                                               */
2617       __IO uint8_t   DIRQ5EG    :  1;               /*!< IRQ5-DS Pin Edge Select                                               */
2618       __IO uint8_t   DIRQ6EG    :  1;               /*!< IRQ6-DS Pin Edge Select                                               */
2619       __IO uint8_t   DIRQ7EG    :  1;               /*!< IRQ7-DS Pin Edge Select                                               */
2620     } DPSIEGR0_b;                                   /*!< BitSize                                                               */
2621   };
2622 
2623   union {
2624     __IO uint8_t   DPSIEGR1;                        /*!< Deep Standby Interrupt Edge Register 1                                */
2625 
2626     struct {
2627       __IO uint8_t   DIRQ8EG    :  1;               /*!< IRQ8-DS Pin Edge Select                                               */
2628       __IO uint8_t   DIRQ9EG    :  1;               /*!< IRQ9-DS Pin Edge Select                                               */
2629       __IO uint8_t   DIRQ10EG   :  1;               /*!< IRQ10-DS Pin Edge Select                                              */
2630       __IO uint8_t   DIRQ11EG   :  1;               /*!< IRQ11-DS Pin Edge Select                                              */
2631       __IO uint8_t   DIRQ12EG   :  1;               /*!< IRQ12-DS Pin Edge Select                                              */
2632       __IO uint8_t   DIRQ13EG   :  1;               /*!< IRQ13-DS Pin Edge Select                                              */
2633       __IO uint8_t   DIRQ14EG   :  1;               /*!< IRQ14-DS Pin Edge Select                                              */
2634       __IO uint8_t   DIRQ15EG   :  1;               /*!< IRQ15-DS Pin Edge Select                                              */
2635     } DPSIEGR1_b;                                   /*!< BitSize                                                               */
2636   };
2637 
2638   union {
2639     __IO uint8_t   DPSIEGR2;                        /*!< Deep Standby Interrupt Edge Register 2                                */
2640 
2641     struct {
2642       __IO uint8_t   DLVD1IEG   :  1;               /*!< LVD1 Edge Select                                                      */
2643       __IO uint8_t   DLVD2IEG   :  1;               /*!< LVD2 Edge Select                                                      */
2644            uint8_t              :  2;
2645       __IO uint8_t   DNMIEG     :  1;               /*!< NMI Pin Edge Select                                                   */
2646     } DPSIEGR2_b;                                   /*!< BitSize                                                               */
2647   };
2648   __I  uint8_t   RESERVED24;
2649 
2650   union {
2651     __IO uint8_t   SYOCDCR;                         /*!< System Control OCD Control Register                                */
2652 
2653     struct {
2654            uint8_t              :  7;
2655       __IO uint8_t   DBGEN      :  1;               /*!< Debugger Enable bit                                                   */
2656     } SYOCDCR_b;                                    /*!< BitSize                                                               */
2657   };
2658   __I  uint8_t   RESERVED25;
2659 
2660   union {
2661     __IO uint8_t   RSTSR0;                          /*!< Reset Status Register 0                                               */
2662 
2663     struct {
2664       __IO uint8_t   PORF       :  1;               /*!< Power-On Reset Detect Flag                                            */
2665       __IO uint8_t   LVD0RF     :  1;               /*!< Voltage-Monitoring 0 Reset Detect Flag                                */
2666       __IO uint8_t   LVD1RF     :  1;               /*!< Voltage-Monitoring 1 Reset Detect Flag                                */
2667       __IO uint8_t   LVD2RF     :  1;               /*!< Voltage-Monitoring 2 Reset Detect Flag                                */
2668            uint8_t              :  3;
2669       __IO uint8_t   DPSRSTF    :  1;               /*!< Deep Software Standby Reset Flag                                      */
2670     } RSTSR0_b;                                     /*!< BitSize                                                               */
2671   };
2672 
2673   union {
2674     __IO uint8_t   RSTSR2;                          /*!< Reset Status Register 2                                               */
2675 
2676     struct {
2677       __IO uint8_t   CWSF       :  1;               /*!< Cold/Warm Start Determination Flag                                    */
2678     } RSTSR2_b;                                     /*!< BitSize                                                               */
2679   };
2680   __I  uint8_t   RESERVED26;
2681 
2682   union {
2683     __IO uint8_t   MOMCR;                           /*!< Main Clock Oscillator Mode Oscillation Control Register               */
2684 
2685     struct {
2686            uint8_t              :  4;
2687       __IO uint8_t   MODRV0     :  2;               /*!< Main Clock Oscillator DriveCapability 0 Switching                     */
2688       __IO uint8_t   MOSEL      :  1;               /*!< Main Clock Oscillator Switching                                       */
2689     } MOMCR_b;                                      /*!< BitSize                                                               */
2690   };
2691   __I  uint8_t   RESERVED27[3];
2692 
2693   union {
2694     __IO uint8_t   LVCMPCR;                         /*!< Voltage Monitoring Circuit Control Register                           */
2695 
2696     struct {
2697            uint8_t              :  5;
2698       __IO uint8_t   LVD1E      :  1;               /*!< Voltage Detection 1 Enable                                            */
2699       __IO uint8_t   LVD2E      :  1;               /*!< Voltage Detection 2 Enable                                            */
2700     } LVCMPCR_b;                                    /*!< BitSize                                                               */
2701   };
2702 
2703   union {
2704     __IO uint8_t   LVDLVLR;                         /*!< Voltage Detection Level Select Register                               */
2705 
2706     struct {
2707       __IO uint8_t   LVD1LVL    :  5;               /*!< Voltage Detection 1 Level Select (Standard voltage during drop
2708                                                          in voltage)                                                           */
2709       __IO uint8_t   LVD2LVL    :  3;               /*!< Voltage Detection 2 Level Select (Standard voltage during drop
2710                                                          in voltage)                                                           */
2711     } LVDLVLR_b;                                    /*!< BitSize                                                               */
2712   };
2713   __I  uint8_t   RESERVED31;
2714 
2715   union {
2716     __IO uint8_t   LVDnCR0[2];                      /*!< Voltage Monitoring %s Circuit Control Register 0                      */
2717 
2718     struct {
2719       __IO uint8_t   RIE        :  1;               /*!< Voltage Monitoring Interrupt/Reset Enable                             */
2720       __IO uint8_t   DFDIS      :  1;               /*!< Voltage Monitoring Digital Filter Disable Mode Select                 */
2721       __IO uint8_t   CMPE       :  1;               /*!< Voltage Monitoring Circuit Comparison Result Output Enable            */
2722            uint8_t              :  1;
2723       __IO uint8_t   FSAMP      :  2;               /*!< Sampling Clock Select                                                 */
2724       __IO uint8_t   RI         :  1;               /*!< Voltage Monitoring Circuit Mode Select                                */
2725       __IO uint8_t   RN         :  1;               /*!< Voltage Monitoring Reset Negate Select                                */
2726     } LVDnCR0_b[2];                                 /*!< BitSize                                                               */
2727   };
2728 
2729   __I  uint8_t RESERVED33[25 * 4];
2730 
2731   union {
2732     __IO uint8_t   SOSCCR;                          /*!< Sub-clock oscillator control register                                 */
2733 
2734     struct {
2735       __IO uint8_t   SOSTP      :  1;               /*!< Sub-Clock Oscillator Stop                                             */
2736     } SOSCCR_b;                                     /*!< BitSize                                                               */
2737   };
2738 
2739   union {
2740     __IO uint8_t   SOMCR;                           /*!< Sub Clock Oscillator Mode Control Register                            */
2741 
2742     struct {
2743       __IO uint8_t   SODRV      :  2;               /*!< Sub Clock Oscillator Drive Capability Switching                       */
2744     } SOMCR_b;                                      /*!< BitSize                                                               */
2745   };
2746   __I  uint8_t RESERVED28[7 * 2];
2747 
2748   union {
2749     __IO uint8_t   LOCOCR;                          /*!< Low-Speed On-Chip Oscillator Control Register                         */
2750 
2751     struct {
2752       __IO uint8_t   LCSTP      :  1;               /*!< LOCO Stop                                                             */
2753     } LOCOCR_b;                                     /*!< BitSize                                                               */
2754   };
2755   __I  uint8_t   RESERVED29;
2756 
2757   union {
2758     __IO uint8_t   LOCOUTCR;                        /*!< LOCO User Trimming Control Register                                   */
2759 
2760     struct {
2761       __IO uint8_t   LOCOUTRM   :  8;               /*!< LOCO User Trimming 1000_0000 : -128 1000_0001 : -127 1000_0010
2762                                                          : -126 . . . 1111_1111 : -1 0000_0000 : Center Code 0000_0001
2763                                                           : +1 . . . 0111_1101 : +125 0111_1110 : +126 0111_1111 : +127These
2764                                                           bits are added to original LOCO trimming bits                        */
2765     } LOCOUTCR_b;                                   /*!< BitSize                                                               */
2766   };
2767   __I  uint8_t RESERVED32[109];
2768 
2769   union {
2770     __IO uint8_t   VBTBKRn[512];                    /*!< VBATT Backup Register %s                                              */
2771 
2772     struct {
2773       __IO uint8_t   VBTBKR     :  8;               /*!< VBTBKR is a 512-byte readable/writeable register to store data
2774                                                          powered by VBATT.The value of this register is retained even
2775                                                           when VCC is not powered but VBATT is powered.VBTBKR is initialized
2776                                                           by VBATT selected voltage power-on-reset.                            */
2777     } VBTBKRn_b[512];                               /*!< BitSize                                                               */
2778   };
2779 } R_SYSTEM_Type;
2780 
2781 
2782 /* ================================================================================ */
2783 /* ================                    R_IOPORT0                   ================ */
2784 /* ================================================================================ */
2785 
2786 
2787 /**
2788   * @brief Port 0 Control Registers (R_IOPORT0)
2789   */
2790 
2791 typedef struct {                                    /*!< R_IOPORT0 Structure                                                   */
2792   __IO uint32_t  PCNTR1;                            /*!< Port Control Register 1                                               */
2793   __I  uint32_t  PCNTR2;                            /*!< Port Control Register 2                                               */
2794   __O  uint32_t  PCNTR3;                            /*!< Port Control Register 3                                               */
2795 } R_IOPORT0_Type;
2796 
2797 
2798 /* ================================================================================ */
2799 /* ================                    R_IOPORT1                   ================ */
2800 /* ================================================================================ */
2801 
2802 
2803 /**
2804   * @brief Port 1 Control Registers (R_IOPORT1)
2805   */
2806 
2807 typedef struct {                                    /*!< R_IOPORT1 Structure                                                   */
2808   __IO uint32_t  PCNTR1;                            /*!< Port Control Register 1                                               */
2809   __I  uint32_t  PCNTR2;                            /*!< Port Control Register 2                                               */
2810   __O  uint32_t  PCNTR3;                            /*!< Port Control Register 3                                               */
2811   __IO uint32_t  PCNTR4;                            /*!< Port Control Register 4                                               */
2812 } R_IOPORT1_Type;
2813 
2814 
2815 /* ================================================================================ */
2816 /* ================                      R_PFS                     ================ */
2817 /* ================================================================================ */
2818 
2819 
2820 /**
2821   * @brief Pmn Pin Function Control Register (PmnPFS) (m = 0 to B, n=0 to 15) (R_PFS)
2822   */
2823 
2824 typedef struct {                                    /*!< R_PFS Structure                                                       */
2825 
2826   union {
2827     __IO uint32_t  P000PFS;                         /*!< P00%s Pin Function Control Register                                   */
2828 
2829     struct {
2830       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
2831       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
2832       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
2833            uint32_t             :  1;
2834       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
2835            uint32_t             :  1;
2836       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
2837       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
2838            uint32_t             :  2;
2839       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
2840            uint32_t             :  2;
2841       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
2842       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
2843       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
2844            uint32_t             :  7;
2845       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
2846                                                          For individual pin functions, see the MPC table                       */
2847     } P000PFS_b;                                    /*!< BitSize                                                               */
2848   };
2849 
2850   union {
2851     __IO uint32_t  P001PFS;                         /*!< P00%s Pin Function Control Register                                   */
2852 
2853     struct {
2854       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
2855       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
2856       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
2857            uint32_t             :  1;
2858       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
2859            uint32_t             :  1;
2860       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
2861       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
2862            uint32_t             :  2;
2863       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
2864            uint32_t             :  2;
2865       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
2866       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
2867       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
2868            uint32_t             :  7;
2869       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
2870                                                          For individual pin functions, see the MPC table                       */
2871     } P001PFS_b;                                    /*!< BitSize                                                               */
2872   };
2873 
2874   union {
2875     __IO uint32_t  P002PFS;                         /*!< P00%s Pin Function Control Register                                   */
2876 
2877     struct {
2878       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
2879       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
2880       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
2881            uint32_t             :  1;
2882       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
2883            uint32_t             :  1;
2884       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
2885       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
2886            uint32_t             :  2;
2887       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
2888            uint32_t             :  2;
2889       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
2890       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
2891       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
2892            uint32_t             :  7;
2893       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
2894                                                          For individual pin functions, see the MPC table                       */
2895     } P002PFS_b;                                    /*!< BitSize                                                               */
2896   };
2897 
2898   union {
2899     __IO uint32_t  P003PFS;                         /*!< P00%s Pin Function Control Register                                   */
2900 
2901     struct {
2902       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
2903       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
2904       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
2905            uint32_t             :  1;
2906       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
2907            uint32_t             :  1;
2908       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
2909       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
2910            uint32_t             :  2;
2911       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
2912            uint32_t             :  2;
2913       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
2914       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
2915       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
2916            uint32_t             :  7;
2917       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
2918                                                          For individual pin functions, see the MPC table                       */
2919     } P003PFS_b;                                    /*!< BitSize                                                               */
2920   };
2921 
2922   union {
2923     __IO uint32_t  P004PFS;                         /*!< P00%s Pin Function Control Register                                   */
2924 
2925     struct {
2926       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
2927       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
2928       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
2929            uint32_t             :  1;
2930       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
2931            uint32_t             :  1;
2932       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
2933       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
2934            uint32_t             :  2;
2935       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
2936            uint32_t             :  2;
2937       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
2938       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
2939       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
2940            uint32_t             :  7;
2941       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
2942                                                          For individual pin functions, see the MPC table                       */
2943     } P004PFS_b;                                    /*!< BitSize                                                               */
2944   };
2945 
2946   union {
2947     __IO uint32_t  P005PFS;                         /*!< P00%s Pin Function Control Register                                   */
2948 
2949     struct {
2950       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
2951       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
2952       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
2953            uint32_t             :  1;
2954       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
2955            uint32_t             :  1;
2956       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
2957       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
2958            uint32_t             :  2;
2959       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
2960            uint32_t             :  2;
2961       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
2962       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
2963       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
2964            uint32_t             :  7;
2965       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
2966                                                          For individual pin functions, see the MPC table                       */
2967     } P005PFS_b;                                    /*!< BitSize                                                               */
2968   };
2969 
2970   union {
2971     __IO uint32_t  P006PFS;                         /*!< P00%s Pin Function Control Register                                   */
2972 
2973     struct {
2974       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
2975       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
2976       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
2977            uint32_t             :  1;
2978       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
2979            uint32_t             :  1;
2980       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
2981       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
2982            uint32_t             :  2;
2983       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
2984            uint32_t             :  2;
2985       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
2986       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
2987       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
2988            uint32_t             :  7;
2989       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
2990                                                          For individual pin functions, see the MPC table                       */
2991     } P006PFS_b;                                    /*!< BitSize                                                               */
2992   };
2993 
2994   union {
2995     __IO uint32_t  P007PFS;                         /*!< P00%s Pin Function Control Register                                   */
2996 
2997     struct {
2998       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
2999       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
3000       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
3001            uint32_t             :  1;
3002       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
3003            uint32_t             :  1;
3004       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
3005       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
3006            uint32_t             :  2;
3007       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
3008            uint32_t             :  2;
3009       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
3010       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
3011       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
3012            uint32_t             :  7;
3013       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
3014                                                          For individual pin functions, see the MPC table                       */
3015     } P007PFS_b;                                    /*!< BitSize                                                               */
3016   };
3017 
3018   union {
3019     __IO uint32_t  P008PFS;                         /*!< P00%s Pin Function Control Register                                   */
3020 
3021     struct {
3022       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
3023       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
3024       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
3025            uint32_t             :  1;
3026       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
3027            uint32_t             :  1;
3028       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
3029       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
3030            uint32_t             :  2;
3031       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
3032            uint32_t             :  2;
3033       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
3034       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
3035       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
3036            uint32_t             :  7;
3037       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
3038                                                          For individual pin functions, see the MPC table                       */
3039     } P008PFS_b;                                    /*!< BitSize                                                               */
3040   };
3041 
3042   union {
3043     __IO uint32_t  P009PFS;                         /*!< P00%s Pin Function Control Register                                   */
3044 
3045     struct {
3046       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
3047       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
3048       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
3049            uint32_t             :  1;
3050       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
3051            uint32_t             :  1;
3052       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
3053       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
3054            uint32_t             :  2;
3055       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
3056            uint32_t             :  2;
3057       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
3058       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
3059       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
3060            uint32_t             :  7;
3061       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
3062                                                          For individual pin functions, see the MPC table                       */
3063     } P009PFS_b;                                    /*!< BitSize                                                               */
3064   };
3065 
3066   union {
3067     __IO uint32_t  P010PFS;                         /*!< P0%s Pin Function Control Register                                    */
3068 
3069     struct {
3070       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
3071       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
3072       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
3073            uint32_t             :  1;
3074       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
3075            uint32_t             :  1;
3076       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
3077       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
3078            uint32_t             :  2;
3079       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
3080            uint32_t             :  2;
3081       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
3082       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
3083       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
3084            uint32_t             :  7;
3085       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
3086                                                          For individual pin functions, see the MPC table                       */
3087     } P010PFS_b;                                    /*!< BitSize                                                               */
3088   };
3089 
3090   union {
3091     __IO uint32_t  P011PFS;                         /*!< P0%s Pin Function Control Register                                    */
3092 
3093     struct {
3094       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
3095       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
3096       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
3097            uint32_t             :  1;
3098       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
3099            uint32_t             :  1;
3100       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
3101       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
3102            uint32_t             :  2;
3103       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
3104            uint32_t             :  2;
3105       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
3106       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
3107       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
3108            uint32_t             :  7;
3109       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
3110                                                          For individual pin functions, see the MPC table                       */
3111     } P011PFS_b;                                    /*!< BitSize                                                               */
3112   };
3113   __I  uint8_t RESERVED24[2 * 4];                   // Added MEF 08/25/2015 P012 and P013 are not present
3114 
3115   union {
3116     __IO uint32_t  P014PFS;                         /*!< P0%s Pin Function Control Register                                    */
3117 
3118     struct {
3119       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
3120       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
3121       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
3122            uint32_t             :  1;
3123       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
3124            uint32_t             :  1;
3125       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
3126       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
3127            uint32_t             :  2;
3128       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
3129            uint32_t             :  2;
3130       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
3131       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
3132       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
3133            uint32_t             :  7;
3134       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
3135                                                          For individual pin functions, see the MPC table                       */
3136     } P014PFS_b;                                    /*!< BitSize                                                               */
3137   };
3138 
3139   union {
3140     __IO uint32_t  P015PFS;                         /*!< P0%s Pin Function Control Register                                    */
3141 
3142     struct {
3143       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
3144       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
3145       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
3146            uint32_t             :  1;
3147       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
3148            uint32_t             :  1;
3149       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
3150       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
3151            uint32_t             :  2;
3152       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
3153            uint32_t             :  2;
3154       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
3155       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
3156       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
3157            uint32_t             :  7;
3158       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
3159                                                          For individual pin functions, see the MPC table                       */
3160     } P015PFS_b;                                    /*!< BitSize                                                               */
3161   };
3162 //  __I  uint32_t  RESERVED[2];                     // MEF 8/26/2015 - This is the wrong place for this
3163 
3164   union {
3165     __IO uint32_t  P100PFS;                         /*!< P10%s Pin Function Control Register                                   */
3166 
3167     struct {
3168       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
3169       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
3170       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
3171            uint32_t             :  1;
3172       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
3173            uint32_t             :  1;
3174       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
3175       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
3176            uint32_t             :  2;
3177       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
3178       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
3179       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
3180       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
3181       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
3182            uint32_t             :  7;
3183       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
3184                                                          For individual pin functions, see the MPC table                       */
3185     } P100PFS_b;                                    /*!< BitSize                                                               */
3186   };
3187 
3188   union {
3189     __IO uint32_t  P101PFS;                         /*!< P10%s Pin Function Control Register                                   */
3190 
3191     struct {
3192       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
3193       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
3194       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
3195            uint32_t             :  1;
3196       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
3197            uint32_t             :  1;
3198       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
3199       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
3200            uint32_t             :  2;
3201       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
3202       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
3203       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
3204       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
3205       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
3206            uint32_t             :  7;
3207       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
3208                                                          For individual pin functions, see the MPC table                       */
3209     } P101PFS_b;                                    /*!< BitSize                                                               */
3210   };
3211 
3212   union {
3213     __IO uint32_t  P102PFS;                         /*!< P10%s Pin Function Control Register                                   */
3214 
3215     struct {
3216       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
3217       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
3218       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
3219            uint32_t             :  1;
3220       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
3221            uint32_t             :  1;
3222       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
3223       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
3224            uint32_t             :  2;
3225       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
3226       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
3227       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
3228       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
3229       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
3230            uint32_t             :  7;
3231       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
3232                                                          For individual pin functions, see the MPC table                       */
3233     } P102PFS_b;                                    /*!< BitSize                                                               */
3234   };
3235 
3236   union {
3237     __IO uint32_t  P103PFS;                         /*!< P10%s Pin Function Control Register                                   */
3238 
3239     struct {
3240       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
3241       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
3242       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
3243            uint32_t             :  1;
3244       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
3245            uint32_t             :  1;
3246       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
3247       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
3248            uint32_t             :  2;
3249       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
3250       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
3251       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
3252       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
3253       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
3254            uint32_t             :  7;
3255       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
3256                                                          For individual pin functions, see the MPC table                       */
3257     } P103PFS_b;                                    /*!< BitSize                                                               */
3258   };
3259 
3260   union {
3261     __IO uint32_t  P104PFS;                         /*!< P10%s Pin Function Control Register                                   */
3262 
3263     struct {
3264       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
3265       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
3266       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
3267            uint32_t             :  1;
3268       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
3269            uint32_t             :  1;
3270       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
3271       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
3272            uint32_t             :  2;
3273       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
3274       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
3275       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
3276       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
3277       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
3278            uint32_t             :  7;
3279       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
3280                                                          For individual pin functions, see the MPC table                       */
3281     } P104PFS_b;                                    /*!< BitSize                                                               */
3282   };
3283 
3284   union {
3285     __IO uint32_t  P105PFS;                         /*!< P10%s Pin Function Control Register                                   */
3286 
3287     struct {
3288       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
3289       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
3290       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
3291            uint32_t             :  1;
3292       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
3293            uint32_t             :  1;
3294       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
3295       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
3296            uint32_t             :  2;
3297       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
3298       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
3299       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
3300       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
3301       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
3302            uint32_t             :  7;
3303       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
3304                                                          For individual pin functions, see the MPC table                       */
3305     } P105PFS_b;                                    /*!< BitSize                                                               */
3306   };
3307 
3308   union {
3309     __IO uint32_t  P106PFS;                         /*!< P10%s Pin Function Control Register                                   */
3310 
3311     struct {
3312       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
3313       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
3314       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
3315            uint32_t             :  1;
3316       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
3317            uint32_t             :  1;
3318       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
3319       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
3320            uint32_t             :  2;
3321       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
3322       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
3323       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
3324       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
3325       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
3326            uint32_t             :  7;
3327       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
3328                                                          For individual pin functions, see the MPC table                       */
3329     } P106PFS_b;                                    /*!< BitSize                                                               */
3330   };
3331 
3332   union {
3333     __IO uint32_t  P107PFS;                         /*!< P10%s Pin Function Control Register                                   */
3334 
3335     struct {
3336       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
3337       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
3338       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
3339            uint32_t             :  1;
3340       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
3341            uint32_t             :  1;
3342       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
3343       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
3344            uint32_t             :  2;
3345       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
3346       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
3347       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
3348       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
3349       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
3350            uint32_t             :  7;
3351       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
3352                                                          For individual pin functions, see the MPC table                       */
3353     } P107PFS_b;                                    /*!< BitSize                                                               */
3354   };
3355 
3356   union {
3357     __IO uint32_t  P108PFS;                         /*!< P10%s Pin Function Control Register                                   */
3358 
3359     struct {
3360       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
3361       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
3362       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
3363            uint32_t             :  1;
3364       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
3365            uint32_t             :  1;
3366       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
3367       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
3368            uint32_t             :  2;
3369       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
3370       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
3371       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
3372       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
3373       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
3374            uint32_t             :  7;
3375       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
3376                                                          For individual pin functions, see the MPC table                       */
3377     } P108PFS_b;                                    /*!< BitSize                                                               */
3378   };
3379 
3380   union {
3381     __IO uint32_t  P109PFS;                         /*!< P10%s Pin Function Control Register                                   */
3382 
3383     struct {
3384       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
3385       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
3386       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
3387            uint32_t             :  1;
3388       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
3389            uint32_t             :  1;
3390       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
3391       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
3392            uint32_t             :  2;
3393       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
3394       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
3395       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
3396       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
3397       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
3398            uint32_t             :  7;
3399       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
3400                                                          For individual pin functions, see the MPC table                       */
3401     } P109PFS_b;                                    /*!< BitSize                                                               */
3402   };
3403 
3404   union {
3405     __IO uint32_t  P110PFS;                         /*!< P1%s Pin Function Control Register                                    */
3406 
3407     struct {
3408       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
3409       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
3410       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
3411            uint32_t             :  1;
3412       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
3413            uint32_t             :  1;
3414       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
3415       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
3416            uint32_t             :  2;
3417       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
3418       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
3419       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
3420       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
3421       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
3422            uint32_t             :  7;
3423       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
3424                                                          For individual pin functions, see the MPC table                       */
3425     } P110PFS_b;                                    /*!< BitSize                                                               */
3426   };
3427 
3428   union {
3429     __IO uint32_t  P111PFS;                         /*!< P1%s Pin Function Control Register                                    */
3430 
3431     struct {
3432       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
3433       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
3434       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
3435            uint32_t             :  1;
3436       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
3437            uint32_t             :  1;
3438       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
3439       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
3440            uint32_t             :  2;
3441       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
3442       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
3443       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
3444       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
3445       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
3446            uint32_t             :  7;
3447       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
3448                                                          For individual pin functions, see the MPC table                       */
3449     } P111PFS_b;                                    /*!< BitSize                                                               */
3450   };
3451 
3452   union {
3453     __IO uint32_t  P112PFS;                         /*!< P1%s Pin Function Control Register                                    */
3454 
3455     struct {
3456       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
3457       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
3458       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
3459            uint32_t             :  1;
3460       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
3461            uint32_t             :  1;
3462       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
3463       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
3464            uint32_t             :  2;
3465       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
3466       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
3467       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
3468       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
3469       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
3470            uint32_t             :  7;
3471       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
3472                                                          For individual pin functions, see the MPC table                       */
3473     } P112PFS_b;                                    /*!< BitSize                                                               */
3474   };
3475 
3476   union {
3477     __IO uint32_t  P113PFS;                         /*!< P1%s Pin Function Control Register                                    */
3478 
3479     struct {
3480       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
3481       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
3482       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
3483            uint32_t             :  1;
3484       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
3485            uint32_t             :  1;
3486       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
3487       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
3488            uint32_t             :  2;
3489       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
3490       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
3491       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
3492       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
3493       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
3494            uint32_t             :  7;
3495       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
3496                                                          For individual pin functions, see the MPC table                       */
3497     } P113PFS_b;                                    /*!< BitSize                                                               */
3498   };
3499 
3500   union {
3501     __IO uint32_t  P114PFS;                         /*!< P1%s Pin Function Control Register                                    */
3502 
3503     struct {
3504       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
3505       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
3506       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
3507            uint32_t             :  1;
3508       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
3509            uint32_t             :  1;
3510       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
3511       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
3512            uint32_t             :  2;
3513       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
3514       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
3515       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
3516       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
3517       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
3518            uint32_t             :  7;
3519       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
3520                                                          For individual pin functions, see the MPC table                       */
3521     } P114PFS_b;                                    /*!< BitSize                                                               */
3522   };
3523 
3524   union {
3525     __IO uint32_t  P115PFS;                         /*!< P1%s Pin Function Control Register                                    */
3526 
3527     struct {
3528       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
3529       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
3530       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
3531            uint32_t             :  1;
3532       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
3533            uint32_t             :  1;
3534       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
3535       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
3536            uint32_t             :  2;
3537       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
3538       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
3539       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
3540       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
3541       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
3542            uint32_t             :  7;
3543       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
3544                                                          For individual pin functions, see the MPC table                       */
3545     } P115PFS_b;                                    /*!< BitSize                                                               */
3546   };
3547 
3548   union {
3549     __IO uint32_t  P200PFS;                         /*!< P20%s Pin Function Control Register                                   */
3550 
3551     struct {
3552       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
3553       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
3554       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
3555            uint32_t             :  1;
3556       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
3557            uint32_t             :  1;
3558       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
3559       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
3560            uint32_t             :  2;
3561       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
3562       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
3563       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
3564       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
3565       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
3566            uint32_t             :  7;
3567       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
3568                                                          For individual pin functions, see the MPC table                       */
3569     } P200PFS_b;                                    /*!< BitSize                                                               */
3570   };
3571 
3572   union {
3573     __IO uint32_t  P201PFS;                         /*!< P20%s Pin Function Control Register                                   */
3574 
3575     struct {
3576       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
3577       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
3578       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
3579            uint32_t             :  1;
3580       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
3581            uint32_t             :  1;
3582       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
3583       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
3584            uint32_t             :  2;
3585       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
3586       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
3587       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
3588       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
3589       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
3590            uint32_t             :  7;
3591       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
3592                                                          For individual pin functions, see the MPC table                       */
3593     } P201PFS_b;                                    /*!< BitSize                                                               */
3594   };
3595 
3596   union {
3597     __IO uint32_t  P202PFS;                         /*!< P20%s Pin Function Control Register                                   */
3598 
3599     struct {
3600       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
3601       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
3602       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
3603            uint32_t             :  1;
3604       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
3605            uint32_t             :  1;
3606       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
3607       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
3608            uint32_t             :  2;
3609       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
3610       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
3611       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
3612       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
3613       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
3614            uint32_t             :  7;
3615       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
3616                                                          For individual pin functions, see the MPC table                       */
3617     } P202PFS_b;                                    /*!< BitSize                                                               */
3618   };
3619 
3620   union {
3621     __IO uint32_t  P203PFS;                         /*!< P20%s Pin Function Control Register                                   */
3622 
3623     struct {
3624       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
3625       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
3626       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
3627            uint32_t             :  1;
3628       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
3629            uint32_t             :  1;
3630       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
3631       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
3632            uint32_t             :  2;
3633       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
3634       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
3635       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
3636       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
3637       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
3638            uint32_t             :  7;
3639       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
3640                                                          For individual pin functions, see the MPC table                       */
3641     } P203PFS_b;                                    /*!< BitSize                                                               */
3642   };
3643 
3644   union {
3645     __IO uint32_t  P204PFS;                         /*!< P20%s Pin Function Control Register                                   */
3646 
3647     struct {
3648       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
3649       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
3650       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
3651            uint32_t             :  1;
3652       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
3653            uint32_t             :  1;
3654       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
3655       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
3656            uint32_t             :  2;
3657       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
3658       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
3659       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
3660       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
3661       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
3662            uint32_t             :  7;
3663       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
3664                                                          For individual pin functions, see the MPC table                       */
3665     } P204PFS_b;                                    /*!< BitSize                                                               */
3666   };
3667 
3668   union {
3669     __IO uint32_t  P205PFS;                         /*!< P20%s Pin Function Control Register                                   */
3670 
3671     struct {
3672       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
3673       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
3674       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
3675            uint32_t             :  1;
3676       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
3677            uint32_t             :  1;
3678       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
3679       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
3680            uint32_t             :  2;
3681       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
3682       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
3683       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
3684       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
3685       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
3686            uint32_t             :  7;
3687       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
3688                                                          For individual pin functions, see the MPC table                       */
3689     } P205PFS_b;                                    /*!< BitSize                                                               */
3690   };
3691 
3692   union {
3693     __IO uint32_t  P206PFS;                         /*!< P20%s Pin Function Control Register                                   */
3694 
3695     struct {
3696       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
3697       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
3698       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
3699            uint32_t             :  1;
3700       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
3701            uint32_t             :  1;
3702       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
3703       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
3704            uint32_t             :  2;
3705       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
3706       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
3707       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
3708       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
3709       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
3710            uint32_t             :  7;
3711       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
3712                                                          For individual pin functions, see the MPC table                       */
3713     } P206PFS_b;                                    /*!< BitSize                                                               */
3714   };
3715 
3716   union {
3717     __IO uint32_t  P207PFS;                         /*!< P20%s Pin Function Control Register                                   */
3718 
3719     struct {
3720       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
3721       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
3722       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
3723            uint32_t             :  1;
3724       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
3725            uint32_t             :  1;
3726       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
3727       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
3728            uint32_t             :  2;
3729       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
3730       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
3731       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
3732       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
3733       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
3734            uint32_t             :  7;
3735       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
3736                                                          For individual pin functions, see the MPC table                       */
3737     } P207PFS_b;                                    /*!< BitSize                                                               */
3738   };
3739   __I  uint8_t RESERVED1[4 * 4];                    // Added MEF 08/25/2015 P208, 209, 210, 211 are not present
3740 
3741   union {
3742     __IO uint32_t  P212PFS;                         /*!< P2%s Pin Function Control Register                                    */
3743 
3744     struct {
3745       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
3746       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
3747       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
3748            uint32_t             :  1;
3749       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
3750            uint32_t             :  1;
3751       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
3752       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
3753            uint32_t             :  2;
3754       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
3755       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
3756       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
3757       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
3758       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
3759            uint32_t             :  7;
3760       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
3761                                                          For individual pin functions, see the MPC table                       */
3762     } P212PFS_b;                                    /*!< BitSize                                                               */
3763   };
3764 
3765   union {
3766     __IO uint32_t  P213PFS;                         /*!< P2%s Pin Function Control Register                                    */
3767 
3768     struct {
3769       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
3770       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
3771       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
3772            uint32_t             :  1;
3773       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
3774            uint32_t             :  1;
3775       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
3776       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
3777            uint32_t             :  2;
3778       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
3779       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
3780       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
3781       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
3782       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
3783            uint32_t             :  7;
3784       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
3785                                                          For individual pin functions, see the MPC table                       */
3786     } P213PFS_b;                                    /*!< BitSize                                                               */
3787   };
3788   __I  uint8_t RESERVED2[2 * 4];                    // Added MEF 09/02/2015 P214, 215 are not present
3789 
3790   union {
3791     __IO uint32_t  P300PFS;                         /*!< P30%s Pin Function Control Register                                   */
3792 
3793     struct {
3794       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
3795       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
3796       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
3797            uint32_t             :  1;
3798       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
3799            uint32_t             :  1;
3800       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
3801       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
3802            uint32_t             :  2;
3803       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
3804       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
3805       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
3806       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
3807       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
3808            uint32_t             :  7;
3809       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
3810                                                          For individual pin functions, see the MPC table                       */
3811     } P300PFS_b;                                    /*!< BitSize                                                               */
3812   };
3813 
3814   union {
3815     __IO uint32_t  P301PFS;                         /*!< P30%s Pin Function Control Register                                   */
3816 
3817     struct {
3818       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
3819       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
3820       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
3821            uint32_t             :  1;
3822       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
3823            uint32_t             :  1;
3824       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
3825       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
3826            uint32_t             :  2;
3827       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
3828       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
3829       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
3830       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
3831       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
3832            uint32_t             :  7;
3833       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
3834                                                          For individual pin functions, see the MPC table                       */
3835     } P301PFS_b;                                    /*!< BitSize                                                               */
3836   };
3837 
3838   union {
3839     __IO uint32_t  P302PFS;                         /*!< P30%s Pin Function Control Register                                   */
3840 
3841     struct {
3842       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
3843       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
3844       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
3845            uint32_t             :  1;
3846       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
3847            uint32_t             :  1;
3848       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
3849       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
3850            uint32_t             :  2;
3851       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
3852       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
3853       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
3854       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
3855       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
3856            uint32_t             :  7;
3857       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
3858                                                          For individual pin functions, see the MPC table                       */
3859     } P302PFS_b;                                    /*!< BitSize                                                               */
3860   };
3861 
3862   union {
3863     __IO uint32_t  P303PFS;                         /*!< P30%s Pin Function Control Register                                   */
3864 
3865     struct {
3866       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
3867       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
3868       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
3869            uint32_t             :  1;
3870       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
3871            uint32_t             :  1;
3872       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
3873       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
3874            uint32_t             :  2;
3875       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
3876       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
3877       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
3878       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
3879       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
3880            uint32_t             :  7;
3881       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
3882                                                          For individual pin functions, see the MPC table                       */
3883     } P303PFS_b;                                    /*!< BitSize                                                               */
3884   };
3885 
3886   union {
3887     __IO uint32_t  P304PFS;                         /*!< P30%s Pin Function Control Register                                   */
3888 
3889     struct {
3890       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
3891       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
3892       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
3893            uint32_t             :  1;
3894       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
3895            uint32_t             :  1;
3896       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
3897       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
3898            uint32_t             :  2;
3899       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
3900       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
3901       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
3902       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
3903       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
3904            uint32_t             :  7;
3905       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
3906                                                          For individual pin functions, see the MPC table                       */
3907     } P304PFS_b;                                    /*!< BitSize                                                               */
3908   };
3909 
3910   union {
3911     __IO uint32_t  P305PFS;                         /*!< P30%s Pin Function Control Register                                   */
3912 
3913     struct {
3914       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
3915       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
3916       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
3917            uint32_t             :  1;
3918       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
3919            uint32_t             :  1;
3920       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
3921       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
3922            uint32_t             :  2;
3923       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
3924       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
3925       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
3926       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
3927       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
3928            uint32_t             :  7;
3929       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
3930                                                          For individual pin functions, see the MPC table                       */
3931     } P305PFS_b;                                    /*!< BitSize                                                               */
3932   };
3933 
3934   union {
3935     __IO uint32_t  P306PFS;                         /*!< P30%s Pin Function Control Register                                   */
3936 
3937     struct {
3938       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
3939       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
3940       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
3941            uint32_t             :  1;
3942       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
3943            uint32_t             :  1;
3944       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
3945       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
3946            uint32_t             :  2;
3947       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
3948       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
3949       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
3950       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
3951       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
3952            uint32_t             :  7;
3953       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
3954                                                          For individual pin functions, see the MPC table                       */
3955     } P306PFS_b;                                    /*!< BitSize                                                               */
3956   };
3957 
3958   union {
3959     __IO uint32_t  P307PFS;                         /*!< P30%s Pin Function Control Register                                   */
3960 
3961     struct {
3962       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
3963       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
3964       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
3965            uint32_t             :  1;
3966       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
3967            uint32_t             :  1;
3968       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
3969       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
3970            uint32_t             :  2;
3971       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
3972       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
3973       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
3974       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
3975       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
3976            uint32_t             :  7;
3977       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
3978                                                          For individual pin functions, see the MPC table                       */
3979     } P307PFS_b;                                    /*!< BitSize                                                               */
3980   };
3981 
3982   union {
3983     __IO uint32_t  P308PFS;                         /*!< P30%s Pin Function Control Register                                   */
3984 
3985     struct {
3986       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
3987       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
3988       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
3989            uint32_t             :  1;
3990       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
3991            uint32_t             :  1;
3992       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
3993       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
3994            uint32_t             :  2;
3995       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
3996       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
3997       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
3998       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
3999       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
4000            uint32_t             :  7;
4001       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
4002                                                          For individual pin functions, see the MPC table                       */
4003     } P308PFS_b;                                    /*!< BitSize                                                               */
4004   };
4005 
4006   union {
4007     __IO uint32_t  P309PFS;                         /*!< P30%s Pin Function Control Register                                   */
4008 
4009     struct {
4010       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
4011       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
4012       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
4013            uint32_t             :  1;
4014       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
4015            uint32_t             :  1;
4016       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
4017       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
4018            uint32_t             :  2;
4019       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
4020       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
4021       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
4022       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
4023       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
4024            uint32_t             :  7;
4025       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
4026                                                          For individual pin functions, see the MPC table                       */
4027     } P309PFS_b;                                    /*!< BitSize                                                               */
4028   };
4029 
4030   union {
4031     __IO uint32_t  P310PFS;                         /*!< P3%s Pin Function Control Register                                    */
4032 
4033     struct {
4034       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
4035       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
4036       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
4037            uint32_t             :  1;
4038       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
4039            uint32_t             :  1;
4040       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
4041       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
4042            uint32_t             :  2;
4043       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
4044       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
4045       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
4046       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
4047       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
4048            uint32_t             :  7;
4049       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
4050                                                          For individual pin functions, see the MPC table                       */
4051     } P310PFS_b;                                    /*!< BitSize                                                               */
4052   };
4053 
4054   union {
4055     __IO uint32_t  P311PFS;                         /*!< P3%s Pin Function Control Register                                    */
4056 
4057     struct {
4058       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
4059       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
4060       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
4061            uint32_t             :  1;
4062       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
4063            uint32_t             :  1;
4064       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
4065       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
4066            uint32_t             :  2;
4067       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
4068       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
4069       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
4070       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
4071       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
4072            uint32_t             :  7;
4073       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
4074                                                          For individual pin functions, see the MPC table                       */
4075     } P311PFS_b;                                    /*!< BitSize                                                               */
4076   };
4077 
4078   union {
4079     __IO uint32_t  P312PFS;                         /*!< P3%s Pin Function Control Register                                    */
4080 
4081     struct {
4082       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
4083       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
4084       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
4085            uint32_t             :  1;
4086       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
4087            uint32_t             :  1;
4088       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
4089       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
4090            uint32_t             :  2;
4091       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
4092       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
4093       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
4094       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
4095       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
4096            uint32_t             :  7;
4097       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
4098                                                          For individual pin functions, see the MPC table                       */
4099     } P312PFS_b;                                    /*!< BitSize                                                               */
4100   };
4101 
4102   union {
4103     __IO uint32_t  P313PFS;                         /*!< P3%s Pin Function Control Register                                    */
4104 
4105     struct {
4106       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
4107       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
4108       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
4109            uint32_t             :  1;
4110       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
4111            uint32_t             :  1;
4112       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
4113       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
4114            uint32_t             :  2;
4115       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
4116       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
4117       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
4118       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
4119       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
4120            uint32_t             :  7;
4121       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
4122                                                          For individual pin functions, see the MPC table                       */
4123     } P313PFS_b;                                    /*!< BitSize                                                               */
4124   };
4125 
4126   union {
4127     __IO uint32_t  P314PFS;                         /*!< P3%s Pin Function Control Register                                    */
4128 
4129     struct {
4130       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
4131       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
4132       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
4133            uint32_t             :  1;
4134       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
4135            uint32_t             :  1;
4136       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
4137       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
4138            uint32_t             :  2;
4139       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
4140       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
4141       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
4142       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
4143       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
4144            uint32_t             :  7;
4145       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
4146                                                          For individual pin functions, see the MPC table                       */
4147     } P314PFS_b;                                    /*!< BitSize                                                               */
4148   };
4149 
4150   union {
4151     __IO uint32_t  P315PFS;                         /*!< P3%s Pin Function Control Register                                    */
4152 
4153     struct {
4154       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
4155       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
4156       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
4157            uint32_t             :  1;
4158       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
4159            uint32_t             :  1;
4160       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
4161       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
4162            uint32_t             :  2;
4163       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
4164       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
4165       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
4166       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
4167       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
4168            uint32_t             :  7;
4169       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
4170                                                          For individual pin functions, see the MPC table                       */
4171     } P315PFS_b;                                    /*!< BitSize                                                               */
4172   };
4173 
4174   union {
4175     __IO uint32_t  P400PFS;                         /*!< P40%s Pin Function Control Register                                   */
4176 
4177     struct {
4178       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
4179       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
4180       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
4181            uint32_t             :  1;
4182       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
4183            uint32_t             :  1;
4184       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
4185       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
4186            uint32_t             :  2;
4187       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
4188       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
4189       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
4190       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
4191       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
4192            uint32_t             :  7;
4193       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
4194                                                          For individual pin functions, see the MPC table                       */
4195     } P400PFS_b;                                    /*!< BitSize                                                               */
4196   };
4197 
4198   union {
4199     __IO uint32_t  P401PFS;                         /*!< P40%s Pin Function Control Register                                   */
4200 
4201     struct {
4202       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
4203       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
4204       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
4205            uint32_t             :  1;
4206       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
4207            uint32_t             :  1;
4208       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
4209       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
4210            uint32_t             :  2;
4211       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
4212       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
4213       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
4214       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
4215       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
4216            uint32_t             :  7;
4217       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
4218                                                          For individual pin functions, see the MPC table                       */
4219     } P401PFS_b;                                    /*!< BitSize                                                               */
4220   };
4221 
4222   union {
4223     __IO uint32_t  P402PFS;                         /*!< P40%s Pin Function Control Register                                   */
4224 
4225     struct {
4226       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
4227       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
4228       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
4229            uint32_t             :  1;
4230       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
4231            uint32_t             :  1;
4232       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
4233       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
4234            uint32_t             :  2;
4235       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
4236       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
4237       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
4238       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
4239       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
4240            uint32_t             :  7;
4241       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
4242                                                          For individual pin functions, see the MPC table                       */
4243     } P402PFS_b;                                    /*!< BitSize                                                               */
4244   };
4245 
4246   union {
4247     __IO uint32_t  P403PFS;                         /*!< P40%s Pin Function Control Register                                   */
4248 
4249     struct {
4250       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
4251       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
4252       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
4253            uint32_t             :  1;
4254       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
4255            uint32_t             :  1;
4256       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
4257       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
4258            uint32_t             :  2;
4259       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
4260       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
4261       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
4262       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
4263       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
4264            uint32_t             :  7;
4265       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
4266                                                          For individual pin functions, see the MPC table                       */
4267     } P403PFS_b;                                    /*!< BitSize                                                               */
4268   };
4269 
4270   union {
4271     __IO uint32_t  P404PFS;                         /*!< P40%s Pin Function Control Register                                   */
4272 
4273     struct {
4274       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
4275       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
4276       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
4277            uint32_t             :  1;
4278       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
4279            uint32_t             :  1;
4280       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
4281       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
4282            uint32_t             :  2;
4283       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
4284       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
4285       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
4286       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
4287       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
4288            uint32_t             :  7;
4289       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
4290                                                          For individual pin functions, see the MPC table                       */
4291     } P404PFS_b;                                    /*!< BitSize                                                               */
4292   };
4293 
4294   union {
4295     __IO uint32_t  P405PFS;                         /*!< P40%s Pin Function Control Register                                   */
4296 
4297     struct {
4298       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
4299       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
4300       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
4301            uint32_t             :  1;
4302       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
4303            uint32_t             :  1;
4304       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
4305       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
4306            uint32_t             :  2;
4307       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
4308       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
4309       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
4310       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
4311       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
4312            uint32_t             :  7;
4313       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
4314                                                          For individual pin functions, see the MPC table                       */
4315     } P405PFS_b;                                    /*!< BitSize                                                               */
4316   };
4317 
4318   union {
4319     __IO uint32_t  P406PFS;                         /*!< P40%s Pin Function Control Register                                   */
4320 
4321     struct {
4322       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
4323       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
4324       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
4325            uint32_t             :  1;
4326       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
4327            uint32_t             :  1;
4328       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
4329       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
4330            uint32_t             :  2;
4331       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
4332       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
4333       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
4334       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
4335       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
4336            uint32_t             :  7;
4337       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
4338                                                          For individual pin functions, see the MPC table                       */
4339     } P406PFS_b;                                    /*!< BitSize                                                               */
4340   };
4341 
4342   union {
4343     __IO uint32_t  P407PFS;                         /*!< P40%s Pin Function Control Register                                   */
4344 
4345     struct {
4346       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
4347       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
4348       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
4349            uint32_t             :  1;
4350       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
4351            uint32_t             :  1;
4352       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
4353       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
4354            uint32_t             :  2;
4355       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
4356       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
4357       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
4358       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
4359       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
4360            uint32_t             :  7;
4361       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
4362                                                          For individual pin functions, see the MPC table                       */
4363     } P407PFS_b;                                    /*!< BitSize                                                               */
4364   };
4365 
4366   union {
4367     __IO uint32_t  P408PFS;                         /*!< P40%s Pin Function Control Register                                   */
4368 
4369     struct {
4370       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
4371       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
4372       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
4373            uint32_t             :  1;
4374       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
4375            uint32_t             :  1;
4376       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
4377       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
4378            uint32_t             :  2;
4379       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
4380       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
4381       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
4382       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
4383       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
4384            uint32_t             :  7;
4385       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
4386                                                          For individual pin functions, see the MPC table                       */
4387     } P408PFS_b;                                    /*!< BitSize                                                               */
4388   };
4389 
4390   union {
4391     __IO uint32_t  P409PFS;                         /*!< P40%s Pin Function Control Register                                   */
4392 
4393     struct {
4394       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
4395       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
4396       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
4397            uint32_t             :  1;
4398       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
4399            uint32_t             :  1;
4400       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
4401       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
4402            uint32_t             :  2;
4403       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
4404       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
4405       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
4406       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
4407       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
4408            uint32_t             :  7;
4409       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
4410                                                          For individual pin functions, see the MPC table                       */
4411     } P409PFS_b;                                    /*!< BitSize                                                               */
4412   };
4413 
4414   union {
4415     __IO uint32_t  P410PFS;                         /*!< P4%s Pin Function Control Register                                    */
4416 
4417     struct {
4418       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
4419       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
4420       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
4421            uint32_t             :  1;
4422       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
4423            uint32_t             :  1;
4424       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
4425       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
4426            uint32_t             :  2;
4427       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
4428       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
4429       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
4430       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
4431       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
4432            uint32_t             :  7;
4433       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
4434                                                          For individual pin functions, see the MPC table                       */
4435     } P410PFS_b;                                    /*!< BitSize                                                               */
4436   };
4437 
4438   union {
4439     __IO uint32_t  P411PFS;                         /*!< P4%s Pin Function Control Register                                    */
4440 
4441     struct {
4442       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
4443       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
4444       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
4445            uint32_t             :  1;
4446       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
4447            uint32_t             :  1;
4448       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
4449       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
4450            uint32_t             :  2;
4451       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
4452       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
4453       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
4454       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
4455       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
4456            uint32_t             :  7;
4457       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
4458                                                          For individual pin functions, see the MPC table                       */
4459     } P411PFS_b;                                    /*!< BitSize                                                               */
4460   };
4461 
4462   union {
4463     __IO uint32_t  P412PFS;                         /*!< P4%s Pin Function Control Register                                    */
4464 
4465     struct {
4466       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
4467       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
4468       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
4469            uint32_t             :  1;
4470       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
4471            uint32_t             :  1;
4472       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
4473       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
4474            uint32_t             :  2;
4475       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
4476       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
4477       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
4478       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
4479       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
4480            uint32_t             :  7;
4481       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
4482                                                          For individual pin functions, see the MPC table                       */
4483     } P412PFS_b;                                    /*!< BitSize                                                               */
4484   };
4485 
4486   union {
4487     __IO uint32_t  P413PFS;                         /*!< P4%s Pin Function Control Register                                    */
4488 
4489     struct {
4490       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
4491       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
4492       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
4493            uint32_t             :  1;
4494       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
4495            uint32_t             :  1;
4496       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
4497       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
4498            uint32_t             :  2;
4499       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
4500       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
4501       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
4502       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
4503       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
4504            uint32_t             :  7;
4505       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
4506                                                          For individual pin functions, see the MPC table                       */
4507     } P413PFS_b;                                    /*!< BitSize                                                               */
4508   };
4509 
4510   union {
4511     __IO uint32_t  P414PFS;                         /*!< P4%s Pin Function Control Register                                    */
4512 
4513     struct {
4514       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
4515       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
4516       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
4517            uint32_t             :  1;
4518       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
4519            uint32_t             :  1;
4520       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
4521       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
4522            uint32_t             :  2;
4523       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
4524       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
4525       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
4526       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
4527       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
4528            uint32_t             :  7;
4529       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
4530                                                          For individual pin functions, see the MPC table                       */
4531     } P414PFS_b;                                    /*!< BitSize                                                               */
4532   };
4533 
4534   union {
4535     __IO uint32_t  P415PFS;                         /*!< P4%s Pin Function Control Register                                    */
4536 
4537     struct {
4538       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
4539       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
4540       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
4541            uint32_t             :  1;
4542       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
4543            uint32_t             :  1;
4544       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
4545       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
4546            uint32_t             :  2;
4547       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
4548       __IO uint32_t  EOFR       :  2;               /*!< Event on Falling/Event on Rising                                      */
4549       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
4550       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
4551       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
4552            uint32_t             :  7;
4553       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
4554                                                          For individual pin functions, see the MPC table                       */
4555     } P415PFS_b;                                    /*!< BitSize                                                               */
4556   };
4557 
4558   union {
4559     __IO uint32_t  P500PFS;                         /*!< P50%s Pin Function Control Register                                   */
4560 
4561     struct {
4562       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
4563       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
4564       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
4565            uint32_t             :  1;
4566       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
4567            uint32_t             :  1;
4568       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
4569       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
4570            uint32_t             :  2;
4571       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
4572            uint32_t             :  2;
4573       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
4574       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
4575       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
4576            uint32_t             :  7;
4577       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
4578                                                          For individual pin functions, see the MPC table                       */
4579     } P500PFS_b;                                    /*!< BitSize                                                               */
4580   };
4581 
4582   union {
4583     __IO uint32_t  P501PFS;                         /*!< P50%s Pin Function Control Register                                   */
4584 
4585     struct {
4586       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
4587       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
4588       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
4589            uint32_t             :  1;
4590       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
4591            uint32_t             :  1;
4592       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
4593       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
4594            uint32_t             :  2;
4595       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
4596            uint32_t             :  2;
4597       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
4598       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
4599       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
4600            uint32_t             :  7;
4601       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
4602                                                          For individual pin functions, see the MPC table                       */
4603     } P501PFS_b;                                    /*!< BitSize                                                               */
4604   };
4605 
4606   union {
4607     __IO uint32_t  P502PFS;                         /*!< P50%s Pin Function Control Register                                   */
4608 
4609     struct {
4610       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
4611       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
4612       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
4613            uint32_t             :  1;
4614       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
4615            uint32_t             :  1;
4616       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
4617       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
4618            uint32_t             :  2;
4619       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
4620            uint32_t             :  2;
4621       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
4622       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
4623       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
4624            uint32_t             :  7;
4625       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
4626                                                          For individual pin functions, see the MPC table                       */
4627     } P502PFS_b;                                    /*!< BitSize                                                               */
4628   };
4629 
4630   union {
4631     __IO uint32_t  P503PFS;                         /*!< P50%s Pin Function Control Register                                   */
4632 
4633     struct {
4634       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
4635       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
4636       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
4637            uint32_t             :  1;
4638       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
4639            uint32_t             :  1;
4640       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
4641       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
4642            uint32_t             :  2;
4643       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
4644            uint32_t             :  2;
4645       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
4646       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
4647       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
4648            uint32_t             :  7;
4649       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
4650                                                          For individual pin functions, see the MPC table                       */
4651     } P503PFS_b;                                    /*!< BitSize                                                               */
4652   };
4653 
4654   union {
4655     __IO uint32_t  P504PFS;                         /*!< P50%s Pin Function Control Register                                   */
4656 
4657     struct {
4658       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
4659       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
4660       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
4661            uint32_t             :  1;
4662       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
4663            uint32_t             :  1;
4664       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
4665       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
4666            uint32_t             :  2;
4667       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
4668            uint32_t             :  2;
4669       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
4670       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
4671       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
4672            uint32_t             :  7;
4673       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
4674                                                          For individual pin functions, see the MPC table                       */
4675     } P504PFS_b;                                    /*!< BitSize                                                               */
4676   };
4677 
4678   union {
4679     __IO uint32_t  P505PFS;                         /*!< P50%s Pin Function Control Register                                   */
4680 
4681     struct {
4682       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
4683       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
4684       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
4685            uint32_t             :  1;
4686       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
4687            uint32_t             :  1;
4688       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
4689       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
4690            uint32_t             :  2;
4691       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
4692            uint32_t             :  2;
4693       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
4694       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
4695       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
4696            uint32_t             :  7;
4697       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
4698                                                          For individual pin functions, see the MPC table                       */
4699     } P505PFS_b;                                    /*!< BitSize                                                               */
4700   };
4701 
4702   union {
4703     __IO uint32_t  P506PFS;                         /*!< P50%s Pin Function Control Register                                   */
4704 
4705     struct {
4706       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
4707       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
4708       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
4709            uint32_t             :  1;
4710       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
4711            uint32_t             :  1;
4712       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
4713       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
4714            uint32_t             :  2;
4715       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
4716            uint32_t             :  2;
4717       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
4718       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
4719       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
4720            uint32_t             :  7;
4721       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
4722                                                          For individual pin functions, see the MPC table                       */
4723     } P506PFS_b;                                    /*!< BitSize                                                               */
4724   };
4725 
4726   union {
4727     __IO uint32_t  P507PFS;                         /*!< P50%s Pin Function Control Register                                   */
4728 
4729     struct {
4730       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
4731       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
4732       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
4733            uint32_t             :  1;
4734       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
4735            uint32_t             :  1;
4736       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
4737       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
4738            uint32_t             :  2;
4739       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
4740            uint32_t             :  2;
4741       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
4742       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
4743       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
4744            uint32_t             :  7;
4745       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
4746                                                          For individual pin functions, see the MPC table                       */
4747     } P507PFS_b;                                    /*!< BitSize                                                               */
4748   };
4749 
4750   union {
4751     __IO uint32_t  P508PFS;                         /*!< P50%s Pin Function Control Register                                   */
4752 
4753     struct {
4754       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
4755       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
4756       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
4757            uint32_t             :  1;
4758       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
4759            uint32_t             :  1;
4760       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
4761       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
4762            uint32_t             :  2;
4763       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
4764            uint32_t             :  2;
4765       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
4766       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
4767       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
4768            uint32_t             :  7;
4769       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
4770                                                          For individual pin functions, see the MPC table                       */
4771     } P508PFS_b;                                    /*!< BitSize                                                               */
4772   };
4773 
4774   union {
4775     __IO uint32_t  P509PFS;                         /*!< P50%s Pin Function Control Register                                   */
4776 
4777     struct {
4778       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
4779       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
4780       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
4781            uint32_t             :  1;
4782       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
4783            uint32_t             :  1;
4784       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
4785       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
4786            uint32_t             :  2;
4787       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
4788            uint32_t             :  2;
4789       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
4790       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
4791       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
4792            uint32_t             :  7;
4793       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
4794                                                          For individual pin functions, see the MPC table                       */
4795     } P509PFS_b;                                    /*!< BitSize                                                               */
4796   };
4797 
4798   union {
4799     __IO uint32_t  P510PFS;                         /*!< P5%s Pin Function Control Register                                    */
4800 
4801     struct {
4802       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
4803       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
4804       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
4805            uint32_t             :  1;
4806       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
4807            uint32_t             :  1;
4808       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
4809       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
4810            uint32_t             :  2;
4811       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
4812            uint32_t             :  2;
4813       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
4814       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
4815       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
4816            uint32_t             :  7;
4817       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
4818                                                          For individual pin functions, see the MPC table                       */
4819     } P510PFS_b;                                    /*!< BitSize                                                               */
4820   };
4821 
4822   union {
4823     __IO uint32_t  P511PFS;                         /*!< P5%s Pin Function Control Register                                    */
4824 
4825     struct {
4826       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
4827       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
4828       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
4829            uint32_t             :  1;
4830       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
4831            uint32_t             :  1;
4832       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
4833       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
4834            uint32_t             :  2;
4835       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
4836            uint32_t             :  2;
4837       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
4838       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
4839       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
4840            uint32_t             :  7;
4841       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
4842                                                          For individual pin functions, see the MPC table                       */
4843     } P511PFS_b;                                    /*!< BitSize                                                               */
4844   };
4845 
4846   union {
4847     __IO uint32_t  P512PFS;                         /*!< P5%s Pin Function Control Register                                    */
4848 
4849     struct {
4850       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
4851       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
4852       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
4853            uint32_t             :  1;
4854       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
4855            uint32_t             :  1;
4856       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
4857       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
4858            uint32_t             :  2;
4859       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
4860            uint32_t             :  2;
4861       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
4862       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
4863       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
4864            uint32_t             :  7;
4865       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
4866                                                          For individual pin functions, see the MPC table                       */
4867     } P512PFS_b;                                    /*!< BitSize                                                               */
4868   };
4869 
4870   union {
4871     __IO uint32_t  P513PFS;                         /*!< P5%s Pin Function Control Register                                    */
4872 
4873     struct {
4874       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
4875       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
4876       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
4877            uint32_t             :  1;
4878       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
4879            uint32_t             :  1;
4880       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
4881       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
4882            uint32_t             :  2;
4883       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
4884            uint32_t             :  2;
4885       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
4886       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
4887       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
4888            uint32_t             :  7;
4889       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
4890                                                          For individual pin functions, see the MPC table                       */
4891     } P513PFS_b;                                    /*!< BitSize                                                               */
4892   };
4893 
4894   union {
4895     __IO uint32_t  P514PFS;                         /*!< P5%s Pin Function Control Register                                    */
4896 
4897     struct {
4898       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
4899       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
4900       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
4901            uint32_t             :  1;
4902       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
4903            uint32_t             :  1;
4904       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
4905       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
4906            uint32_t             :  2;
4907       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
4908            uint32_t             :  2;
4909       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
4910       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
4911       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
4912            uint32_t             :  7;
4913       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
4914                                                          For individual pin functions, see the MPC table                       */
4915     } P514PFS_b;                                    /*!< BitSize                                                               */
4916   };
4917 
4918   union {
4919     __IO uint32_t  P515PFS;                         /*!< P5%s Pin Function Control Register                                    */
4920 
4921     struct {
4922       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
4923       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
4924       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
4925            uint32_t             :  1;
4926       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
4927            uint32_t             :  1;
4928       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
4929       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
4930            uint32_t             :  2;
4931       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
4932            uint32_t             :  2;
4933       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
4934       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
4935       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
4936            uint32_t             :  7;
4937       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
4938                                                          For individual pin functions, see the MPC table                       */
4939     } P515PFS_b;                                    /*!< BitSize                                                               */
4940   };
4941 
4942   union {
4943     __IO uint32_t  P600PFS;                         /*!< P60%s Pin Function Control Register                                   */
4944 
4945     struct {
4946       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
4947       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
4948       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
4949            uint32_t             :  1;
4950       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
4951            uint32_t             :  1;
4952       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
4953       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
4954            uint32_t             :  2;
4955       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
4956            uint32_t             :  2;
4957       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
4958       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
4959       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
4960            uint32_t             :  7;
4961       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
4962                                                          For individual pin functions, see the MPC table                       */
4963     } P600PFS_b;                                    /*!< BitSize                                                               */
4964   };
4965 
4966   union {
4967     __IO uint32_t  P601PFS;                         /*!< P60%s Pin Function Control Register                                   */
4968 
4969     struct {
4970       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
4971       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
4972       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
4973            uint32_t             :  1;
4974       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
4975            uint32_t             :  1;
4976       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
4977       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
4978            uint32_t             :  2;
4979       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
4980            uint32_t             :  2;
4981       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
4982       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
4983       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
4984            uint32_t             :  7;
4985       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
4986                                                          For individual pin functions, see the MPC table                       */
4987     } P601PFS_b;                                    /*!< BitSize                                                               */
4988   };
4989 
4990   union {
4991     __IO uint32_t  P602PFS;                         /*!< P60%s Pin Function Control Register                                   */
4992 
4993     struct {
4994       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
4995       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
4996       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
4997            uint32_t             :  1;
4998       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
4999            uint32_t             :  1;
5000       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
5001       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
5002            uint32_t             :  2;
5003       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
5004            uint32_t             :  2;
5005       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
5006       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
5007       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
5008            uint32_t             :  7;
5009       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
5010                                                          For individual pin functions, see the MPC table                       */
5011     } P602PFS_b;                                    /*!< BitSize                                                               */
5012   };
5013 
5014   union {
5015     __IO uint32_t  P603PFS;                         /*!< P60%s Pin Function Control Register                                   */
5016 
5017     struct {
5018       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
5019       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
5020       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
5021            uint32_t             :  1;
5022       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
5023            uint32_t             :  1;
5024       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
5025       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
5026            uint32_t             :  2;
5027       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
5028            uint32_t             :  2;
5029       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
5030       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
5031       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
5032            uint32_t             :  7;
5033       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
5034                                                          For individual pin functions, see the MPC table                       */
5035     } P603PFS_b;                                    /*!< BitSize                                                               */
5036   };
5037 
5038   union {
5039     __IO uint32_t  P604PFS;                         /*!< P60%s Pin Function Control Register                                   */
5040 
5041     struct {
5042       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
5043       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
5044       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
5045            uint32_t             :  1;
5046       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
5047            uint32_t             :  1;
5048       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
5049       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
5050            uint32_t             :  2;
5051       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
5052            uint32_t             :  2;
5053       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
5054       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
5055       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
5056            uint32_t             :  7;
5057       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
5058                                                          For individual pin functions, see the MPC table                       */
5059     } P604PFS_b;                                    /*!< BitSize                                                               */
5060   };
5061 
5062   union {
5063     __IO uint32_t  P605PFS;                         /*!< P60%s Pin Function Control Register                                   */
5064 
5065     struct {
5066       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
5067       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
5068       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
5069            uint32_t             :  1;
5070       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
5071            uint32_t             :  1;
5072       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
5073       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
5074            uint32_t             :  2;
5075       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
5076            uint32_t             :  2;
5077       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
5078       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
5079       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
5080            uint32_t             :  7;
5081       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
5082                                                          For individual pin functions, see the MPC table                       */
5083     } P605PFS_b;                                    /*!< BitSize                                                               */
5084   };
5085 
5086   union {
5087     __IO uint32_t  P606PFS;                         /*!< P60%s Pin Function Control Register                                   */
5088 
5089     struct {
5090       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
5091       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
5092       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
5093            uint32_t             :  1;
5094       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
5095            uint32_t             :  1;
5096       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
5097       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
5098            uint32_t             :  2;
5099       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
5100            uint32_t             :  2;
5101       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
5102       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
5103       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
5104            uint32_t             :  7;
5105       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
5106                                                          For individual pin functions, see the MPC table                       */
5107     } P606PFS_b;                                    /*!< BitSize                                                               */
5108   };
5109 
5110   union {
5111     __IO uint32_t  P607PFS;                         /*!< P60%s Pin Function Control Register                                   */
5112 
5113     struct {
5114       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
5115       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
5116       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
5117            uint32_t             :  1;
5118       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
5119            uint32_t             :  1;
5120       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
5121       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
5122            uint32_t             :  2;
5123       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
5124            uint32_t             :  2;
5125       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
5126       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
5127       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
5128            uint32_t             :  7;
5129       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
5130                                                          For individual pin functions, see the MPC table                       */
5131     } P607PFS_b;                                    /*!< BitSize                                                               */
5132   };
5133 
5134   union {
5135     __IO uint32_t  P608PFS;                         /*!< P60%s Pin Function Control Register                                   */
5136 
5137     struct {
5138       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
5139       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
5140       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
5141            uint32_t             :  1;
5142       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
5143            uint32_t             :  1;
5144       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
5145       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
5146            uint32_t             :  2;
5147       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
5148            uint32_t             :  2;
5149       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
5150       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
5151       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
5152            uint32_t             :  7;
5153       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
5154                                                          For individual pin functions, see the MPC table                       */
5155     } P608PFS_b;                                    /*!< BitSize                                                               */
5156   };
5157 
5158   union {
5159     __IO uint32_t  P609PFS;                         /*!< P60%s Pin Function Control Register                                   */
5160 
5161     struct {
5162       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
5163       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
5164       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
5165            uint32_t             :  1;
5166       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
5167            uint32_t             :  1;
5168       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
5169       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
5170            uint32_t             :  2;
5171       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
5172            uint32_t             :  2;
5173       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
5174       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
5175       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
5176            uint32_t             :  7;
5177       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
5178                                                          For individual pin functions, see the MPC table                       */
5179     } P609PFS_b;                                    /*!< BitSize                                                               */
5180   };
5181 
5182   union {
5183     __IO uint32_t  P610PFS;                         /*!< P6%s Pin Function Control Register                                    */
5184 
5185     struct {
5186       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
5187       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
5188       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
5189            uint32_t             :  1;
5190       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
5191            uint32_t             :  1;
5192       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
5193       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
5194            uint32_t             :  2;
5195       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
5196            uint32_t             :  2;
5197       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
5198       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
5199       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
5200            uint32_t             :  7;
5201       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
5202                                                          For individual pin functions, see the MPC table                       */
5203     } P610PFS_b;                                    /*!< BitSize                                                               */
5204   };
5205 
5206   union {
5207     __IO uint32_t  P611PFS;                         /*!< P6%s Pin Function Control Register                                    */
5208 
5209     struct {
5210       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
5211       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
5212       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
5213            uint32_t             :  1;
5214       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
5215            uint32_t             :  1;
5216       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
5217       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
5218            uint32_t             :  2;
5219       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
5220            uint32_t             :  2;
5221       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
5222       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
5223       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
5224            uint32_t             :  7;
5225       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
5226                                                          For individual pin functions, see the MPC table                       */
5227     } P611PFS_b;                                    /*!< BitSize                                                               */
5228   };
5229 
5230   union {
5231     __IO uint32_t  P612PFS;                         /*!< P6%s Pin Function Control Register                                    */
5232 
5233     struct {
5234       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
5235       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
5236       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
5237            uint32_t             :  1;
5238       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
5239            uint32_t             :  1;
5240       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
5241       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
5242            uint32_t             :  2;
5243       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
5244            uint32_t             :  2;
5245       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
5246       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
5247       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
5248            uint32_t             :  7;
5249       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
5250                                                          For individual pin functions, see the MPC table                       */
5251     } P612PFS_b;                                    /*!< BitSize                                                               */
5252   };
5253 
5254   union {
5255     __IO uint32_t  P613PFS;                         /*!< P6%s Pin Function Control Register                                    */
5256 
5257     struct {
5258       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
5259       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
5260       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
5261            uint32_t             :  1;
5262       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
5263            uint32_t             :  1;
5264       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
5265       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
5266            uint32_t             :  2;
5267       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
5268            uint32_t             :  2;
5269       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
5270       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
5271       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
5272            uint32_t             :  7;
5273       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
5274                                                          For individual pin functions, see the MPC table                       */
5275     } P613PFS_b;                                    /*!< BitSize                                                               */
5276   };
5277 
5278   union {
5279     __IO uint32_t  P614PFS;                         /*!< P6%s Pin Function Control Register                                    */
5280 
5281     struct {
5282       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
5283       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
5284       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
5285            uint32_t             :  1;
5286       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
5287            uint32_t             :  1;
5288       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
5289       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
5290            uint32_t             :  2;
5291       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
5292            uint32_t             :  2;
5293       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
5294       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
5295       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
5296            uint32_t             :  7;
5297       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
5298                                                          For individual pin functions, see the MPC table                       */
5299     } P614PFS_b;                                    /*!< BitSize                                                               */
5300   };
5301 
5302   union {
5303     __IO uint32_t  P615PFS;                         /*!< P6%s Pin Function Control Register                                    */
5304 
5305     struct {
5306       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
5307       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
5308       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
5309            uint32_t             :  1;
5310       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
5311            uint32_t             :  1;
5312       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
5313       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
5314            uint32_t             :  2;
5315       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
5316            uint32_t             :  2;
5317       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
5318       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
5319       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
5320            uint32_t             :  7;
5321       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
5322                                                          For individual pin functions, see the MPC table                       */
5323     } P615PFS_b;                                    /*!< BitSize                                                               */
5324   };
5325 
5326   union {
5327     __IO uint32_t  P700PFS;                         /*!< P70%s Pin Function Control Register                                   */
5328 
5329     struct {
5330       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
5331       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
5332       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
5333            uint32_t             :  1;
5334       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
5335            uint32_t             :  1;
5336       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
5337       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
5338            uint32_t             :  2;
5339       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
5340            uint32_t             :  2;
5341       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
5342       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
5343       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
5344            uint32_t             :  7;
5345       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
5346                                                          For individual pin functions, see the MPC table                       */
5347     } P700PFS_b;                                    /*!< BitSize                                                               */
5348   };
5349 
5350   union {
5351     __IO uint32_t  P701PFS;                         /*!< P70%s Pin Function Control Register                                   */
5352 
5353     struct {
5354       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
5355       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
5356       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
5357            uint32_t             :  1;
5358       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
5359            uint32_t             :  1;
5360       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
5361       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
5362            uint32_t             :  2;
5363       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
5364            uint32_t             :  2;
5365       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
5366       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
5367       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
5368            uint32_t             :  7;
5369       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
5370                                                          For individual pin functions, see the MPC table                       */
5371     } P701PFS_b;                                    /*!< BitSize                                                               */
5372   };
5373 
5374   union {
5375     __IO uint32_t  P702PFS;                         /*!< P70%s Pin Function Control Register                                   */
5376 
5377     struct {
5378       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
5379       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
5380       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
5381            uint32_t             :  1;
5382       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
5383            uint32_t             :  1;
5384       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
5385       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
5386            uint32_t             :  2;
5387       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
5388            uint32_t             :  2;
5389       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
5390       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
5391       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
5392            uint32_t             :  7;
5393       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
5394                                                          For individual pin functions, see the MPC table                       */
5395     } P702PFS_b;                                    /*!< BitSize                                                               */
5396   };
5397 
5398   union {
5399     __IO uint32_t  P703PFS;                         /*!< P70%s Pin Function Control Register                                   */
5400 
5401     struct {
5402       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
5403       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
5404       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
5405            uint32_t             :  1;
5406       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
5407            uint32_t             :  1;
5408       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
5409       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
5410            uint32_t             :  2;
5411       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
5412            uint32_t             :  2;
5413       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
5414       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
5415       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
5416            uint32_t             :  7;
5417       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
5418                                                          For individual pin functions, see the MPC table                       */
5419     } P703PFS_b;                                    /*!< BitSize                                                               */
5420   };
5421 
5422   union {
5423     __IO uint32_t  P704PFS;                         /*!< P70%s Pin Function Control Register                                   */
5424 
5425     struct {
5426       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
5427       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
5428       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
5429            uint32_t             :  1;
5430       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
5431            uint32_t             :  1;
5432       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
5433       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
5434            uint32_t             :  2;
5435       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
5436            uint32_t             :  2;
5437       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
5438       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
5439       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
5440            uint32_t             :  7;
5441       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
5442                                                          For individual pin functions, see the MPC table                       */
5443     } P704PFS_b;                                    /*!< BitSize                                                               */
5444   };
5445 
5446   union {
5447     __IO uint32_t  P705PFS;                         /*!< P70%s Pin Function Control Register                                   */
5448 
5449     struct {
5450       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
5451       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
5452       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
5453            uint32_t             :  1;
5454       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
5455            uint32_t             :  1;
5456       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
5457       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
5458            uint32_t             :  2;
5459       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
5460            uint32_t             :  2;
5461       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
5462       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
5463       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
5464            uint32_t             :  7;
5465       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
5466                                                          For individual pin functions, see the MPC table                       */
5467     } P705PFS_b;                                    /*!< BitSize                                                               */
5468   };
5469 
5470   union {
5471     __IO uint32_t  P706PFS;                         /*!< P70%s Pin Function Control Register                                   */
5472 
5473     struct {
5474       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
5475       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
5476       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
5477            uint32_t             :  1;
5478       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
5479            uint32_t             :  1;
5480       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
5481       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
5482            uint32_t             :  2;
5483       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
5484            uint32_t             :  2;
5485       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
5486       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
5487       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
5488            uint32_t             :  7;
5489       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
5490                                                          For individual pin functions, see the MPC table                       */
5491     } P706PFS_b;                                    /*!< BitSize                                                               */
5492   };
5493 
5494   union {
5495     __IO uint32_t  P707PFS;                         /*!< P70%s Pin Function Control Register                                   */
5496 
5497     struct {
5498       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
5499       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
5500       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
5501            uint32_t             :  1;
5502       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
5503            uint32_t             :  1;
5504       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
5505       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
5506            uint32_t             :  2;
5507       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
5508            uint32_t             :  2;
5509       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
5510       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
5511       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
5512            uint32_t             :  7;
5513       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
5514                                                          For individual pin functions, see the MPC table                       */
5515     } P707PFS_b;                                    /*!< BitSize                                                               */
5516   };
5517 
5518   union {
5519     __IO uint32_t  P708PFS;                         /*!< P70%s Pin Function Control Register                                   */
5520 
5521     struct {
5522       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
5523       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
5524       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
5525            uint32_t             :  1;
5526       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
5527            uint32_t             :  1;
5528       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
5529       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
5530            uint32_t             :  2;
5531       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
5532            uint32_t             :  2;
5533       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
5534       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
5535       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
5536            uint32_t             :  7;
5537       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
5538                                                          For individual pin functions, see the MPC table                       */
5539     } P708PFS_b;                                    /*!< BitSize                                                               */
5540   };
5541 
5542   union {
5543     __IO uint32_t  P709PFS;                         /*!< P70%s Pin Function Control Register                                   */
5544 
5545     struct {
5546       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
5547       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
5548       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
5549            uint32_t             :  1;
5550       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
5551            uint32_t             :  1;
5552       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
5553       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
5554            uint32_t             :  2;
5555       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
5556            uint32_t             :  2;
5557       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
5558       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
5559       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
5560            uint32_t             :  7;
5561       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
5562                                                          For individual pin functions, see the MPC table                       */
5563     } P709PFS_b;                                    /*!< BitSize                                                               */
5564   };
5565 
5566   union {
5567     __IO uint32_t  P710PFS;                         /*!< P7%s Pin Function Control Register                                    */
5568 
5569     struct {
5570       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
5571       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
5572       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
5573            uint32_t             :  1;
5574       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
5575            uint32_t             :  1;
5576       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
5577       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
5578            uint32_t             :  2;
5579       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
5580            uint32_t             :  2;
5581       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
5582       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
5583       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
5584            uint32_t             :  7;
5585       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
5586                                                          For individual pin functions, see the MPC table                       */
5587     } P710PFS_b;                                    /*!< BitSize                                                               */
5588   };
5589 
5590   union {
5591     __IO uint32_t  P711PFS;                         /*!< P7%s Pin Function Control Register                                    */
5592 
5593     struct {
5594       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
5595       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
5596       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
5597            uint32_t             :  1;
5598       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
5599            uint32_t             :  1;
5600       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
5601       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
5602            uint32_t             :  2;
5603       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
5604            uint32_t             :  2;
5605       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
5606       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
5607       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
5608            uint32_t             :  7;
5609       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
5610                                                          For individual pin functions, see the MPC table                       */
5611     } P711PFS_b;                                    /*!< BitSize                                                               */
5612   };
5613 
5614   union {
5615     __IO uint32_t  P712PFS;                         /*!< P7%s Pin Function Control Register                                    */
5616 
5617     struct {
5618       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
5619       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
5620       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
5621            uint32_t             :  1;
5622       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
5623            uint32_t             :  1;
5624       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
5625       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
5626            uint32_t             :  2;
5627       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
5628            uint32_t             :  2;
5629       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
5630       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
5631       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
5632            uint32_t             :  7;
5633       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
5634                                                          For individual pin functions, see the MPC table                       */
5635     } P712PFS_b;                                    /*!< BitSize                                                               */
5636   };
5637 
5638   union {
5639     __IO uint32_t  P713PFS;                         /*!< P7%s Pin Function Control Register                                    */
5640 
5641     struct {
5642       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
5643       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
5644       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
5645            uint32_t             :  1;
5646       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
5647            uint32_t             :  1;
5648       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
5649       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
5650            uint32_t             :  2;
5651       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
5652            uint32_t             :  2;
5653       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
5654       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
5655       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
5656            uint32_t             :  7;
5657       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
5658                                                          For individual pin functions, see the MPC table                       */
5659     } P713PFS_b;                                    /*!< BitSize                                                               */
5660   };
5661   __I  uint32_t  RESERVED3[2];
5662 
5663   union {
5664     __IO uint32_t  P800PFS;                         /*!< P80%s Pin Function Control Register                                   */
5665 
5666     struct {
5667       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
5668       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
5669       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
5670            uint32_t             :  1;
5671       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
5672            uint32_t             :  1;
5673       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
5674       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
5675            uint32_t             :  2;
5676       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
5677            uint32_t             :  2;
5678       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
5679       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
5680       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
5681            uint32_t             :  7;
5682       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
5683                                                          For individual pin functions, see the MPC table                       */
5684     } P800PFS_b;                                    /*!< BitSize                                                               */
5685   };
5686 
5687   union {
5688     __IO uint32_t  P801PFS;                         /*!< P80%s Pin Function Control Register                                   */
5689 
5690     struct {
5691       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
5692       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
5693       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
5694            uint32_t             :  1;
5695       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
5696            uint32_t             :  1;
5697       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
5698       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
5699            uint32_t             :  2;
5700       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
5701            uint32_t             :  2;
5702       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
5703       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
5704       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
5705            uint32_t             :  7;
5706       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
5707                                                          For individual pin functions, see the MPC table                       */
5708     } P801PFS_b;                                    /*!< BitSize                                                               */
5709   };
5710 
5711   union {
5712     __IO uint32_t  P802PFS;                         /*!< P80%s Pin Function Control Register                                   */
5713 
5714     struct {
5715       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
5716       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
5717       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
5718            uint32_t             :  1;
5719       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
5720            uint32_t             :  1;
5721       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
5722       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
5723            uint32_t             :  2;
5724       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
5725            uint32_t             :  2;
5726       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
5727       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
5728       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
5729            uint32_t             :  7;
5730       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
5731                                                          For individual pin functions, see the MPC table                       */
5732     } P802PFS_b;                                    /*!< BitSize                                                               */
5733   };
5734 
5735   union {
5736     __IO uint32_t  P803PFS;                         /*!< P80%s Pin Function Control Register                                   */
5737 
5738     struct {
5739       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
5740       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
5741       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
5742            uint32_t             :  1;
5743       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
5744            uint32_t             :  1;
5745       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
5746       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
5747            uint32_t             :  2;
5748       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
5749            uint32_t             :  2;
5750       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
5751       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
5752       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
5753            uint32_t             :  7;
5754       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
5755                                                          For individual pin functions, see the MPC table                       */
5756     } P803PFS_b;                                    /*!< BitSize                                                               */
5757   };
5758 
5759   union {
5760     __IO uint32_t  P804PFS;                         /*!< P80%s Pin Function Control Register                                   */
5761 
5762     struct {
5763       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
5764       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
5765       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
5766            uint32_t             :  1;
5767       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
5768            uint32_t             :  1;
5769       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
5770       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
5771            uint32_t             :  2;
5772       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
5773            uint32_t             :  2;
5774       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
5775       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
5776       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
5777            uint32_t             :  7;
5778       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
5779                                                          For individual pin functions, see the MPC table                       */
5780     } P804PFS_b;                                    /*!< BitSize                                                               */
5781   };
5782 
5783   union {
5784     __IO uint32_t  P805PFS;                         /*!< P80%s Pin Function Control Register                                   */
5785 
5786     struct {
5787       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
5788       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
5789       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
5790            uint32_t             :  1;
5791       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
5792            uint32_t             :  1;
5793       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
5794       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
5795            uint32_t             :  2;
5796       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
5797            uint32_t             :  2;
5798       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
5799       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
5800       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
5801            uint32_t             :  7;
5802       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
5803                                                          For individual pin functions, see the MPC table                       */
5804     } P805PFS_b;                                    /*!< BitSize                                                               */
5805   };
5806 
5807   union {
5808     __IO uint32_t  P806PFS;                         /*!< P80%s Pin Function Control Register                                   */
5809 
5810     struct {
5811       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
5812       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
5813       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
5814            uint32_t             :  1;
5815       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
5816            uint32_t             :  1;
5817       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
5818       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
5819            uint32_t             :  2;
5820       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
5821            uint32_t             :  2;
5822       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
5823       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
5824       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
5825            uint32_t             :  7;
5826       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
5827                                                          For individual pin functions, see the MPC table                       */
5828     } P806PFS_b;                                    /*!< BitSize                                                               */
5829   };
5830 
5831   union {
5832     __IO uint32_t  P807PFS;                         /*!< P80%s Pin Function Control Register                                   */
5833 
5834     struct {
5835       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
5836       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
5837       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
5838            uint32_t             :  1;
5839       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
5840            uint32_t             :  1;
5841       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
5842       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
5843            uint32_t             :  2;
5844       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
5845            uint32_t             :  2;
5846       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
5847       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
5848       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
5849            uint32_t             :  7;
5850       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
5851                                                          For individual pin functions, see the MPC table                       */
5852     } P807PFS_b;                                    /*!< BitSize                                                               */
5853   };
5854 
5855   union {
5856     __IO uint32_t  P808PFS;                         /*!< P80%s Pin Function Control Register                                   */
5857 
5858     struct {
5859       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
5860       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
5861       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
5862            uint32_t             :  1;
5863       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
5864            uint32_t             :  1;
5865       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
5866       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
5867            uint32_t             :  2;
5868       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
5869            uint32_t             :  2;
5870       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
5871       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
5872       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
5873            uint32_t             :  7;
5874       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
5875                                                          For individual pin functions, see the MPC table                       */
5876     } P808PFS_b;                                    /*!< BitSize                                                               */
5877   };
5878 
5879   union {
5880     __IO uint32_t  P809PFS;                         /*!< P80%s Pin Function Control Register                                   */
5881 
5882     struct {
5883       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
5884       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
5885       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
5886            uint32_t             :  1;
5887       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
5888            uint32_t             :  1;
5889       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
5890       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
5891            uint32_t             :  2;
5892       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
5893            uint32_t             :  2;
5894       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
5895       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
5896       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
5897            uint32_t             :  7;
5898       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
5899                                                          For individual pin functions, see the MPC table                       */
5900     } P809PFS_b;                                    /*!< BitSize                                                               */
5901   };
5902 
5903   union {
5904     __IO uint32_t  P810PFS;                         /*!< P8%s Pin Function Control Register                                    */
5905 
5906     struct {
5907       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
5908       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
5909       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
5910            uint32_t             :  1;
5911       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
5912            uint32_t             :  1;
5913       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
5914       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
5915            uint32_t             :  2;
5916       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
5917            uint32_t             :  2;
5918       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
5919       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
5920       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
5921            uint32_t             :  7;
5922       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
5923                                                          For individual pin functions, see the MPC table                       */
5924     } P810PFS_b;                                    /*!< BitSize                                                               */
5925   };
5926 
5927   union {
5928     __IO uint32_t  P811PFS;                         /*!< P8%s Pin Function Control Register                                    */
5929 
5930     struct {
5931       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
5932       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
5933       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
5934            uint32_t             :  1;
5935       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
5936            uint32_t             :  1;
5937       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
5938       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
5939            uint32_t             :  2;
5940       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
5941            uint32_t             :  2;
5942       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
5943       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
5944       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
5945            uint32_t             :  7;
5946       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
5947                                                          For individual pin functions, see the MPC table                       */
5948     } P811PFS_b;                                    /*!< BitSize                                                               */
5949   };
5950 
5951   union {
5952     __IO uint32_t  P812PFS;                         /*!< P8%s Pin Function Control Register                                    */
5953 
5954     struct {
5955       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
5956       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
5957       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
5958            uint32_t             :  1;
5959       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
5960            uint32_t             :  1;
5961       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
5962       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
5963            uint32_t             :  2;
5964       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
5965            uint32_t             :  2;
5966       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
5967       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
5968       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
5969            uint32_t             :  7;
5970       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
5971                                                          For individual pin functions, see the MPC table                       */
5972     } P812PFS_b;                                    /*!< BitSize                                                               */
5973   };
5974 
5975   union {
5976     __IO uint32_t  P813PFS;                         /*!< P8%s Pin Function Control Register                                    */
5977 
5978     struct {
5979       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
5980       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
5981       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
5982            uint32_t             :  1;
5983       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
5984            uint32_t             :  1;
5985       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
5986       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
5987            uint32_t             :  2;
5988       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
5989            uint32_t             :  2;
5990       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
5991       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
5992       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
5993            uint32_t             :  7;
5994       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
5995                                                          For individual pin functions, see the MPC table                       */
5996     } P813PFS_b;                                    /*!< BitSize                                                               */
5997   };
5998   __I  uint32_t  RESERVED4[2];
5999 
6000   union {
6001     __IO uint32_t  P900PFS;                         /*!< P90%s Pin Function Control Register                                   */
6002 
6003     struct {
6004       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
6005       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
6006       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
6007            uint32_t             :  1;
6008       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
6009            uint32_t             :  1;
6010       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
6011       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
6012            uint32_t             :  2;
6013       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
6014            uint32_t             :  2;
6015       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
6016       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
6017       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
6018            uint32_t             :  7;
6019       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
6020                                                          For individual pin functions, see the MPC table                       */
6021     } P900PFS_b;                                    /*!< BitSize                                                               */
6022   };
6023 
6024   union {
6025     __IO uint32_t  P901PFS;                         /*!< P90%s Pin Function Control Register                                   */
6026 
6027     struct {
6028       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
6029       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
6030       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
6031            uint32_t             :  1;
6032       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
6033            uint32_t             :  1;
6034       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
6035       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
6036            uint32_t             :  2;
6037       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
6038            uint32_t             :  2;
6039       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
6040       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
6041       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
6042            uint32_t             :  7;
6043       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
6044                                                          For individual pin functions, see the MPC table                       */
6045     } P901PFS_b;                                    /*!< BitSize                                                               */
6046   };
6047 
6048   union {
6049     __IO uint32_t  P902PFS;                         /*!< P90%s Pin Function Control Register                                   */
6050 
6051     struct {
6052       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
6053       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
6054       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
6055            uint32_t             :  1;
6056       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
6057            uint32_t             :  1;
6058       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
6059       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
6060            uint32_t             :  2;
6061       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
6062            uint32_t             :  2;
6063       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
6064       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
6065       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
6066            uint32_t             :  7;
6067       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
6068                                                          For individual pin functions, see the MPC table                       */
6069     } P902PFS_b;                                    /*!< BitSize                                                               */
6070   };
6071 
6072   union {
6073     __IO uint32_t  P903PFS;                         /*!< P90%s Pin Function Control Register                                   */
6074 
6075     struct {
6076       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
6077       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
6078       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
6079            uint32_t             :  1;
6080       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
6081            uint32_t             :  1;
6082       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
6083       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
6084            uint32_t             :  2;
6085       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
6086            uint32_t             :  2;
6087       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
6088       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
6089       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
6090            uint32_t             :  7;
6091       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
6092                                                          For individual pin functions, see the MPC table                       */
6093     } P903PFS_b;                                    /*!< BitSize                                                               */
6094   };
6095 
6096   union {
6097     __IO uint32_t  P904PFS;                         /*!< P90%s Pin Function Control Register                                   */
6098 
6099     struct {
6100       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
6101       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
6102       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
6103            uint32_t             :  1;
6104       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
6105            uint32_t             :  1;
6106       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
6107       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
6108            uint32_t             :  2;
6109       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
6110            uint32_t             :  2;
6111       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
6112       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
6113       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
6114            uint32_t             :  7;
6115       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
6116                                                          For individual pin functions, see the MPC table                       */
6117     } P904PFS_b;                                    /*!< BitSize                                                               */
6118   };
6119 
6120   union {
6121     __IO uint32_t  P905PFS;                         /*!< P90%s Pin Function Control Register                                   */
6122 
6123     struct {
6124       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
6125       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
6126       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
6127            uint32_t             :  1;
6128       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
6129            uint32_t             :  1;
6130       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
6131       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
6132            uint32_t             :  2;
6133       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
6134            uint32_t             :  2;
6135       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
6136       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
6137       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
6138            uint32_t             :  7;
6139       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
6140                                                          For individual pin functions, see the MPC table                       */
6141     } P905PFS_b;                                    /*!< BitSize                                                               */
6142   };
6143 
6144   union {
6145     __IO uint32_t  P906PFS;                         /*!< P90%s Pin Function Control Register                                   */
6146 
6147     struct {
6148       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
6149       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
6150       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
6151            uint32_t             :  1;
6152       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
6153            uint32_t             :  1;
6154       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
6155       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
6156            uint32_t             :  2;
6157       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
6158            uint32_t             :  2;
6159       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
6160       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
6161       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
6162            uint32_t             :  7;
6163       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
6164                                                          For individual pin functions, see the MPC table                       */
6165     } P906PFS_b;                                    /*!< BitSize                                                               */
6166   };
6167 
6168   union {
6169     __IO uint32_t  P907PFS;                         /*!< P90%s Pin Function Control Register                                   */
6170 
6171     struct {
6172       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
6173       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
6174       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
6175            uint32_t             :  1;
6176       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
6177            uint32_t             :  1;
6178       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
6179       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
6180            uint32_t             :  2;
6181       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
6182            uint32_t             :  2;
6183       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
6184       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
6185       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
6186            uint32_t             :  7;
6187       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
6188                                                          For individual pin functions, see the MPC table                       */
6189     } P907PFS_b;                                    /*!< BitSize                                                               */
6190   };
6191 
6192   union {
6193     __IO uint32_t  P908PFS;                         /*!< P90%s Pin Function Control Register                                   */
6194 
6195     struct {
6196       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
6197       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
6198       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
6199            uint32_t             :  1;
6200       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
6201            uint32_t             :  1;
6202       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
6203       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
6204            uint32_t             :  2;
6205       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
6206            uint32_t             :  2;
6207       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
6208       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
6209       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
6210            uint32_t             :  7;
6211       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
6212                                                          For individual pin functions, see the MPC table                       */
6213     } P908PFS_b;                                    /*!< BitSize                                                               */
6214   };
6215 
6216   union {
6217     __IO uint32_t  P909PFS;                         /*!< P90%s Pin Function Control Register                                   */
6218 
6219     struct {
6220       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
6221       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
6222       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
6223            uint32_t             :  1;
6224       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
6225            uint32_t             :  1;
6226       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
6227       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
6228            uint32_t             :  2;
6229       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
6230            uint32_t             :  2;
6231       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
6232       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
6233       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
6234            uint32_t             :  7;
6235       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
6236                                                          For individual pin functions, see the MPC table                       */
6237     } P909PFS_b;                                    /*!< BitSize                                                               */
6238   };
6239 
6240   union {
6241     __IO uint32_t  P910PFS;                         /*!< P9%s Pin Function Control Register                                    */
6242 
6243     struct {
6244       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
6245       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
6246       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
6247            uint32_t             :  1;
6248       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
6249            uint32_t             :  1;
6250       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
6251       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
6252            uint32_t             :  2;
6253       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
6254            uint32_t             :  2;
6255       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
6256       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
6257       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
6258            uint32_t             :  7;
6259       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
6260                                                          For individual pin functions, see the MPC table                       */
6261     } P910PFS_b;                                    /*!< BitSize                                                               */
6262   };
6263 
6264   union {
6265     __IO uint32_t  P911PFS;                         /*!< P9%s Pin Function Control Register                                    */
6266 
6267     struct {
6268       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
6269       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
6270       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
6271            uint32_t             :  1;
6272       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
6273            uint32_t             :  1;
6274       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
6275       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
6276            uint32_t             :  2;
6277       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
6278            uint32_t             :  2;
6279       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
6280       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
6281       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
6282            uint32_t             :  7;
6283       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
6284                                                          For individual pin functions, see the MPC table                       */
6285     } P911PFS_b;                                    /*!< BitSize                                                               */
6286   };
6287 
6288   union {
6289     __IO uint32_t  P912PFS;                         /*!< P9%s Pin Function Control Register                                    */
6290 
6291     struct {
6292       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
6293       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
6294       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
6295            uint32_t             :  1;
6296       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
6297            uint32_t             :  1;
6298       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
6299       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
6300            uint32_t             :  2;
6301       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
6302            uint32_t             :  2;
6303       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
6304       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
6305       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
6306            uint32_t             :  7;
6307       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
6308                                                          For individual pin functions, see the MPC table                       */
6309     } P912PFS_b;                                    /*!< BitSize                                                               */
6310   };
6311 
6312   union {
6313     __IO uint32_t  P913PFS;                         /*!< P9%s Pin Function Control Register                                    */
6314 
6315     struct {
6316       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
6317       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
6318       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
6319            uint32_t             :  1;
6320       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
6321            uint32_t             :  1;
6322       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
6323       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
6324            uint32_t             :  2;
6325       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
6326            uint32_t             :  2;
6327       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
6328       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
6329       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
6330            uint32_t             :  7;
6331       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
6332                                                          For individual pin functions, see the MPC table                       */
6333     } P913PFS_b;                                    /*!< BitSize                                                               */
6334   };
6335 
6336   union {
6337     __IO uint32_t  P914PFS;                         /*!< P9%s Pin Function Control Register                                    */
6338 
6339     struct {
6340       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
6341       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
6342       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
6343            uint32_t             :  1;
6344       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
6345            uint32_t             :  1;
6346       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
6347       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
6348            uint32_t             :  2;
6349       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
6350            uint32_t             :  2;
6351       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
6352       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
6353       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
6354            uint32_t             :  7;
6355       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
6356                                                          For individual pin functions, see the MPC table                       */
6357     } P914PFS_b;                                    /*!< BitSize                                                               */
6358   };
6359 
6360   union {
6361     __IO uint32_t  P915PFS;                         /*!< P9%s Pin Function Control Register                                    */
6362 
6363     struct {
6364       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
6365       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
6366       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
6367            uint32_t             :  1;
6368       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
6369            uint32_t             :  1;
6370       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
6371       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
6372            uint32_t             :  2;
6373       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
6374            uint32_t             :  2;
6375       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
6376       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
6377       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
6378            uint32_t             :  7;
6379       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
6380                                                          For individual pin functions, see the MPC table                       */
6381     } P915PFS_b;                                    /*!< BitSize                                                               */
6382   };
6383 
6384   union {
6385     __IO uint32_t  PA00PFS;                         /*!< PA0%s Pin Function Control Register                                   */
6386 
6387     struct {
6388       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
6389       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
6390       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
6391            uint32_t             :  1;
6392       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
6393            uint32_t             :  1;
6394       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
6395       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
6396            uint32_t             :  2;
6397       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
6398            uint32_t             :  2;
6399       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
6400       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
6401       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
6402            uint32_t             :  7;
6403       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
6404                                                          For individual pin functions, see the MPC table                       */
6405     } PA00PFS_b;                                    /*!< BitSize                                                               */
6406   };
6407 
6408   union {
6409     __IO uint32_t  PA01PFS;                         /*!< PA0%s Pin Function Control Register                                   */
6410 
6411     struct {
6412       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
6413       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
6414       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
6415            uint32_t             :  1;
6416       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
6417            uint32_t             :  1;
6418       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
6419       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
6420            uint32_t             :  2;
6421       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
6422            uint32_t             :  2;
6423       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
6424       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
6425       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
6426            uint32_t             :  7;
6427       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
6428                                                          For individual pin functions, see the MPC table                       */
6429     } PA01PFS_b;                                    /*!< BitSize                                                               */
6430   };
6431 
6432   union {
6433     __IO uint32_t  PA02PFS;                         /*!< PA0%s Pin Function Control Register                                   */
6434 
6435     struct {
6436       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
6437       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
6438       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
6439            uint32_t             :  1;
6440       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
6441            uint32_t             :  1;
6442       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
6443       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
6444            uint32_t             :  2;
6445       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
6446            uint32_t             :  2;
6447       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
6448       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
6449       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
6450            uint32_t             :  7;
6451       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
6452                                                          For individual pin functions, see the MPC table                       */
6453     } PA02PFS_b;                                    /*!< BitSize                                                               */
6454   };
6455 
6456   union {
6457     __IO uint32_t  PA03PFS;                         /*!< PA0%s Pin Function Control Register                                   */
6458 
6459     struct {
6460       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
6461       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
6462       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
6463            uint32_t             :  1;
6464       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
6465            uint32_t             :  1;
6466       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
6467       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
6468            uint32_t             :  2;
6469       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
6470            uint32_t             :  2;
6471       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
6472       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
6473       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
6474            uint32_t             :  7;
6475       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
6476                                                          For individual pin functions, see the MPC table                       */
6477     } PA03PFS_b;                                    /*!< BitSize                                                               */
6478   };
6479 
6480   union {
6481     __IO uint32_t  PA04PFS;                         /*!< PA0%s Pin Function Control Register                                   */
6482 
6483     struct {
6484       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
6485       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
6486       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
6487            uint32_t             :  1;
6488       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
6489            uint32_t             :  1;
6490       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
6491       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
6492            uint32_t             :  2;
6493       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
6494            uint32_t             :  2;
6495       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
6496       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
6497       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
6498            uint32_t             :  7;
6499       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
6500                                                          For individual pin functions, see the MPC table                       */
6501     } PA04PFS_b;                                    /*!< BitSize                                                               */
6502   };
6503 
6504   union {
6505     __IO uint32_t  PA05PFS;                         /*!< PA0%s Pin Function Control Register                                   */
6506 
6507     struct {
6508       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
6509       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
6510       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
6511            uint32_t             :  1;
6512       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
6513            uint32_t             :  1;
6514       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
6515       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
6516            uint32_t             :  2;
6517       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
6518            uint32_t             :  2;
6519       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
6520       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
6521       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
6522            uint32_t             :  7;
6523       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
6524                                                          For individual pin functions, see the MPC table                       */
6525     } PA05PFS_b;                                    /*!< BitSize                                                               */
6526   };
6527 
6528   union {
6529     __IO uint32_t  PA06PFS;                         /*!< PA0%s Pin Function Control Register                                   */
6530 
6531     struct {
6532       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
6533       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
6534       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
6535            uint32_t             :  1;
6536       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
6537            uint32_t             :  1;
6538       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
6539       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
6540            uint32_t             :  2;
6541       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
6542            uint32_t             :  2;
6543       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
6544       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
6545       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
6546            uint32_t             :  7;
6547       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
6548                                                          For individual pin functions, see the MPC table                       */
6549     } PA06PFS_b;                                    /*!< BitSize                                                               */
6550   };
6551 
6552   union {
6553     __IO uint32_t  PA07PFS;                         /*!< PA0%s Pin Function Control Register                                   */
6554 
6555     struct {
6556       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
6557       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
6558       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
6559            uint32_t             :  1;
6560       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
6561            uint32_t             :  1;
6562       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
6563       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
6564            uint32_t             :  2;
6565       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
6566            uint32_t             :  2;
6567       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
6568       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
6569       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
6570            uint32_t             :  7;
6571       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
6572                                                          For individual pin functions, see the MPC table                       */
6573     } PA07PFS_b;                                    /*!< BitSize                                                               */
6574   };
6575 
6576   union {
6577     __IO uint32_t  PA08PFS;                         /*!< PA0%s Pin Function Control Register                                   */
6578 
6579     struct {
6580       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
6581       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
6582       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
6583            uint32_t             :  1;
6584       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
6585            uint32_t             :  1;
6586       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
6587       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
6588            uint32_t             :  2;
6589       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
6590            uint32_t             :  2;
6591       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
6592       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
6593       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
6594            uint32_t             :  7;
6595       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
6596                                                          For individual pin functions, see the MPC table                       */
6597     } PA08PFS_b;                                    /*!< BitSize                                                               */
6598   };
6599 
6600   union {
6601     __IO uint32_t  PA09PFS;                         /*!< PA0%s Pin Function Control Register                                   */
6602 
6603     struct {
6604       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
6605       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
6606       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
6607            uint32_t             :  1;
6608       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
6609            uint32_t             :  1;
6610       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
6611       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
6612            uint32_t             :  2;
6613       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
6614            uint32_t             :  2;
6615       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
6616       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
6617       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
6618            uint32_t             :  7;
6619       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
6620                                                          For individual pin functions, see the MPC table                       */
6621     } PA09PFS_b;                                    /*!< BitSize                                                               */
6622   };
6623 
6624   union {
6625     __IO uint32_t  PA10PFS;                         /*!< PA%s Pin Function Control Register                                    */
6626 
6627     struct {
6628       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
6629       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
6630       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
6631            uint32_t             :  1;
6632       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
6633            uint32_t             :  1;
6634       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
6635       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
6636            uint32_t             :  2;
6637       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
6638            uint32_t             :  2;
6639       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
6640       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
6641       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
6642            uint32_t             :  7;
6643       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
6644                                                          For individual pin functions, see the MPC table                       */
6645     } PA10PFS_b;                                    /*!< BitSize                                                               */
6646   };
6647 
6648   union {
6649     __IO uint32_t  PA11PFS;                         /*!< PA%s Pin Function Control Register                                    */
6650 
6651     struct {
6652       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
6653       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
6654       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
6655            uint32_t             :  1;
6656       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
6657            uint32_t             :  1;
6658       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
6659       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
6660            uint32_t             :  2;
6661       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
6662            uint32_t             :  2;
6663       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
6664       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
6665       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
6666            uint32_t             :  7;
6667       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
6668                                                          For individual pin functions, see the MPC table                       */
6669     } PA11PFS_b;                                    /*!< BitSize                                                               */
6670   };
6671 
6672   union {
6673     __IO uint32_t  PA12PFS;                         /*!< PA%s Pin Function Control Register                                    */
6674 
6675     struct {
6676       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
6677       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
6678       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
6679            uint32_t             :  1;
6680       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
6681            uint32_t             :  1;
6682       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
6683       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
6684            uint32_t             :  2;
6685       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
6686            uint32_t             :  2;
6687       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
6688       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
6689       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
6690            uint32_t             :  7;
6691       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
6692                                                          For individual pin functions, see the MPC table                       */
6693     } PA12PFS_b;                                    /*!< BitSize                                                               */
6694   };
6695 
6696   union {
6697     __IO uint32_t  PA13PFS;                         /*!< PA%s Pin Function Control Register                                    */
6698 
6699     struct {
6700       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
6701       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
6702       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
6703            uint32_t             :  1;
6704       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
6705            uint32_t             :  1;
6706       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
6707       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
6708            uint32_t             :  2;
6709       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
6710            uint32_t             :  2;
6711       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
6712       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
6713       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
6714            uint32_t             :  7;
6715       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
6716                                                          For individual pin functions, see the MPC table                       */
6717     } PA13PFS_b;                                    /*!< BitSize                                                               */
6718   };
6719 
6720   union {
6721     __IO uint32_t  PA14PFS;                         /*!< PA%s Pin Function Control Register                                    */
6722 
6723     struct {
6724       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
6725       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
6726       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
6727            uint32_t             :  1;
6728       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
6729            uint32_t             :  1;
6730       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
6731       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
6732            uint32_t             :  2;
6733       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
6734            uint32_t             :  2;
6735       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
6736       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
6737       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
6738            uint32_t             :  7;
6739       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
6740                                                          For individual pin functions, see the MPC table                       */
6741     } PA14PFS_b;                                    /*!< BitSize                                                               */
6742   };
6743 
6744   union {
6745     __IO uint32_t  PA15PFS;                         /*!< PA%s Pin Function Control Register                                    */
6746 
6747     struct {
6748       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
6749       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
6750       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
6751            uint32_t             :  1;
6752       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
6753            uint32_t             :  1;
6754       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
6755       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
6756            uint32_t             :  2;
6757       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
6758            uint32_t             :  2;
6759       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
6760       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
6761       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
6762            uint32_t             :  7;
6763       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
6764                                                          For individual pin functions, see the MPC table                       */
6765     } PA15PFS_b;                                    /*!< BitSize                                                               */
6766   };
6767 
6768   union {
6769     __IO uint32_t  PB00PFS;                         /*!< PB0%s Pin Function Control Register                                   */
6770 
6771     struct {
6772       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
6773       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
6774       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
6775            uint32_t             :  1;
6776       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
6777            uint32_t             :  1;
6778       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
6779       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
6780            uint32_t             :  2;
6781       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
6782            uint32_t             :  2;
6783       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
6784       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
6785       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
6786            uint32_t             :  7;
6787       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
6788                                                          For individual pin functions, see the MPC table                       */
6789     } PB00PFS_b;                                    /*!< BitSize                                                               */
6790   };
6791 
6792   union {
6793     __IO uint32_t  PB01PFS;                         /*!< PB0%s Pin Function Control Register                                   */
6794 
6795     struct {
6796       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
6797       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
6798       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
6799            uint32_t             :  1;
6800       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
6801            uint32_t             :  1;
6802       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
6803       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
6804            uint32_t             :  2;
6805       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
6806            uint32_t             :  2;
6807       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
6808       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
6809       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
6810            uint32_t             :  7;
6811       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
6812                                                          For individual pin functions, see the MPC table                       */
6813     } PB01PFS_b;                                    /*!< BitSize                                                               */
6814   };
6815 
6816   union {
6817     __IO uint32_t  PB02PFS;                         /*!< PB0%s Pin Function Control Register                                   */
6818 
6819     struct {
6820       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
6821       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
6822       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
6823            uint32_t             :  1;
6824       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
6825            uint32_t             :  1;
6826       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
6827       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
6828            uint32_t             :  2;
6829       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
6830            uint32_t             :  2;
6831       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
6832       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
6833       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
6834            uint32_t             :  7;
6835       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
6836                                                          For individual pin functions, see the MPC table                       */
6837     } PB02PFS_b;                                    /*!< BitSize                                                               */
6838   };
6839 
6840   union {
6841     __IO uint32_t  PB03PFS;                         /*!< PB0%s Pin Function Control Register                                   */
6842 
6843     struct {
6844       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
6845       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
6846       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
6847            uint32_t             :  1;
6848       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
6849            uint32_t             :  1;
6850       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
6851       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
6852            uint32_t             :  2;
6853       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
6854            uint32_t             :  2;
6855       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
6856       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
6857       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
6858            uint32_t             :  7;
6859       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
6860                                                          For individual pin functions, see the MPC table                       */
6861     } PB03PFS_b;                                    /*!< BitSize                                                               */
6862   };
6863 
6864   union {
6865     __IO uint32_t  PB04PFS;                         /*!< PB0%s Pin Function Control Register                                   */
6866 
6867     struct {
6868       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
6869       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
6870       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
6871            uint32_t             :  1;
6872       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
6873            uint32_t             :  1;
6874       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
6875       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
6876            uint32_t             :  2;
6877       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
6878            uint32_t             :  2;
6879       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
6880       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
6881       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
6882            uint32_t             :  7;
6883       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
6884                                                          For individual pin functions, see the MPC table                       */
6885     } PB04PFS_b;                                    /*!< BitSize                                                               */
6886   };
6887 
6888   union {
6889     __IO uint32_t  PB05PFS;                         /*!< PB0%s Pin Function Control Register                                   */
6890 
6891     struct {
6892       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
6893       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
6894       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
6895            uint32_t             :  1;
6896       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
6897            uint32_t             :  1;
6898       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
6899       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
6900            uint32_t             :  2;
6901       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
6902            uint32_t             :  2;
6903       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
6904       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
6905       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
6906            uint32_t             :  7;
6907       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
6908                                                          For individual pin functions, see the MPC table                       */
6909     } PB05PFS_b;                                    /*!< BitSize                                                               */
6910   };
6911 
6912   union {
6913     __IO uint32_t  PB06PFS;                         /*!< PB0%s Pin Function Control Register                                   */
6914 
6915     struct {
6916       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
6917       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
6918       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
6919            uint32_t             :  1;
6920       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
6921            uint32_t             :  1;
6922       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
6923       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
6924            uint32_t             :  2;
6925       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
6926            uint32_t             :  2;
6927       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
6928       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
6929       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
6930            uint32_t             :  7;
6931       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
6932                                                          For individual pin functions, see the MPC table                       */
6933     } PB06PFS_b;                                    /*!< BitSize                                                               */
6934   };
6935 
6936   union {
6937     __IO uint32_t  PB07PFS;                         /*!< PB0%s Pin Function Control Register                                   */
6938 
6939     struct {
6940       __IO uint32_t  PODR       :  1;               /*!< Port Output Data                                                      */
6941       __I  uint32_t  PIDR       :  1;               /*!< Port Input Data                                                       */
6942       __IO uint32_t  PDR        :  1;               /*!< Port Direction                                                        */
6943            uint32_t             :  1;
6944       __IO uint32_t  PCR        :  1;               /*!< Pull-up Control                                                       */
6945            uint32_t             :  1;
6946       __IO uint32_t  NCODR      :  1;               /*!< N-Channel Open Drain Control                                          */
6947       __IO uint32_t  PCODR      :  1;               /*!< P-Channel Open Drain Control                                          */
6948            uint32_t             :  2;
6949       __IO uint32_t  DSCR       :  2;               /*!< Drive Strength Control Register                                       */
6950            uint32_t             :  2;
6951       __IO uint32_t  ISEL       :  1;               /*!< IRQ input enable                                                      */
6952       __IO uint32_t  ASEL       :  1;               /*!< Analog Input enable                                                   */
6953       __IO uint32_t  PMR        :  1;               /*!< Port Mode Control                                                     */
6954            uint32_t             :  7;
6955       __IO uint32_t  PSEL       :  5;               /*!< Port Function SelectThese bits select the peripheral function.
6956                                                          For individual pin functions, see the MPC table                       */
6957     } PB07PFS_b;                                    /*!< BitSize                                                               */
6958   };
6959 } R_PFS_Type;
6960 
6961 
6962 /* ================================================================================ */
6963 /* ================                     R_PMISC                    ================ */
6964 /* ================================================================================ */
6965 
6966 
6967 /**
6968   * @brief Miscellaneous Port Control Register (R_PMISC)
6969   */
6970 
6971 typedef struct {                                    /*!< R_PMISC Structure                                                     */
6972 
6973   union {
6974     __IO uint8_t   PFENET;                          /*!< Ethernet Control Register                                             */
6975 
6976     struct {
6977            uint8_t              :  4;
6978       __IO uint8_t   PHYMODE0   :  1;               /*!< Ethernet Mode Setting ch0                                             */
6979       __IO uint8_t   PHYMODE1   :  1;               /*!< Ethernet Mode Setting ch1                                             */
6980     } PFENET_b;                                     /*!< BitSize                                                               */
6981   };
6982   __I  uint8_t  RESERVED[2];
6983 
6984   union {
6985     __IO uint8_t   PWPR;                            /*!< Write-Protect Register                                                */
6986 
6987     struct {
6988            uint8_t              :  6;
6989       __IO uint8_t   PFSWE      :  1;               /*!< PFS Register Write Enable                                             */
6990       __IO uint8_t   BOWI       :  1;               /*!< PFSWE Bit Write Disable                                               */
6991     } PWPR_b;                                       /*!< BitSize                                                               */
6992   };
6993 } R_PMISC_Type;
6994 
6995 
6996 /* ================================================================================ */
6997 /* ================                      R_ELC                     ================ */
6998 /* ================================================================================ */
6999 
7000 
7001 /**
7002   * @brief Event Link Controller  (R_ELC)
7003   */
7004 
7005 typedef struct {                                    /*!< R_ELC Structure                                                       */
7006     union {
7007       __IO uint8_t   ELCR;                          /*!< Event Link Controller Register                                        */
7008 
7009       struct {
7010              uint8_t            :  7;
7011         __IO uint8_t   ELCON    :  1;               /*!< All Event Link Enable                                                 */
7012       } ELCR_b;                                     /*!< BitSize                                                               */
7013     };
7014   union {
7015     __I  uint16_t  RESERVED;
7016     R_ELC_ELSEGRnRC0_Type ELSEGRnRC0[2];            /*!< Event Link Software Event Generation Register %s Register Cluster
7017                                                         0                                                                     */
7018   };
7019   __I  uint16_t  RESERVED1[5];
7020   R_ELC_ELSRnRC0_Type ELSRnRC0[19];                 /*!< Event Link Setting Register %s Register Cluster 0                     */
7021 } R_ELC_Type;
7022 
7023 
7024 /* ================================================================================ */
7025 /* ================                     R_POEG                     ================ */
7026 /* ================================================================================ */
7027 
7028 
7029 /**
7030   * @brief Port Output Enable Module for GPT (R_POEG)
7031   */
7032 
7033 typedef struct {                                    /*!< R_POEG Structure                                                      */
7034 
7035   union {
7036     __IO uint32_t  POEGGA;                          /*!< POEG Group %s Setting Register                                        */
7037 
7038     struct {
7039       __IO uint32_t  PIDF       :  1;               /*!< Port Input Detection Flag                                             */
7040       __IO uint32_t  IOCF       :  1;               /*!< Real Time Overcurrent Detection Flag                                  */
7041       __IO uint32_t  OSTPF      :  1;               /*!< Oscillation Stop Detection Flag                                       */
7042       __IO uint32_t  SSF        :  1;               /*!< Software Stop Flag                                                    */
7043       __IO uint32_t  PIDE       :  1;               /*!< Port Input Detection EnableNote: Can be modified only once after
7044                                                          a reset.                                                              */
7045       __IO uint32_t  IOCE       :  1;               /*!< Real Time Overcurrent EnableNote: Can be modified only once
7046                                                          after a reset.                                                        */
7047       __IO uint32_t  OSTPE      :  1;               /*!< Oscillation Stop Detection EnableNote: Can be modified only
7048                                                          once after a reset.                                                   */
7049            uint32_t             :  1;
7050       __IO uint32_t  CDRE0      :  1;               /*!< Comparator Disable Request Enable 0Note: Can be modified only
7051                                                          once after a reset.                                                   */
7052       __IO uint32_t  CDRE1      :  1;               /*!< Comparator Disable Request Enable 1Note: Can be modified only
7053                                                          once after a reset.                                                   */
7054       __IO uint32_t  CDRE2      :  1;               /*!< Comparator Disable Request Enable 2Note: Can be modified only
7055                                                          once after a reset.                                                   */
7056       __IO uint32_t  CDRE3      :  1;               /*!< Comparator Disable Request Enable 3Note: Can be modified only
7057                                                          once after a reset.                                                   */
7058       __IO uint32_t  CDRE4      :  1;               /*!< Comparator Disable Request Enable 4Note: Can be modified only
7059                                                          once after a reset.                                                   */
7060       __IO uint32_t  CDRE5      :  1;               /*!< Comparator Disable Request Enable 5Note: Can be modified only
7061                                                          once after a reset.                                                   */
7062            uint32_t             :  2;
7063       __I  uint32_t  ST         :  1;               /*!< GTETRG Input Status Flag                                              */
7064            uint32_t             : 11;
7065       __IO uint32_t  INV        :  1;               /*!< GTETRG Input Reverse                                                  */
7066       __IO uint32_t  NFEN       :  1;               /*!< Noise Filter Enable                                                   */
7067       __IO uint32_t  NFCS       :  2;               /*!< Noise Filter Clock Select                                             */
7068     } POEGGA_b;                                     /*!< BitSize                                                               */
7069   };
7070   __I  uint32_t  RESERVED[63];
7071 
7072   union {
7073     __IO uint32_t  POEGGB;                          /*!< POEG Group %s Setting Register                                        */
7074 
7075     struct {
7076       __IO uint32_t  PIDF       :  1;               /*!< Port Input Detection Flag                                             */
7077       __IO uint32_t  IOCF       :  1;               /*!< Real Time Overcurrent Detection Flag                                  */
7078       __IO uint32_t  OSTPF      :  1;               /*!< Oscillation Stop Detection Flag                                       */
7079       __IO uint32_t  SSF        :  1;               /*!< Software Stop Flag                                                    */
7080       __IO uint32_t  PIDE       :  1;               /*!< Port Input Detection EnableNote: Can be modified only once after
7081                                                          a reset.                                                              */
7082       __IO uint32_t  IOCE       :  1;               /*!< Real Time Overcurrent EnableNote: Can be modified only once
7083                                                          after a reset.                                                        */
7084       __IO uint32_t  OSTPE      :  1;               /*!< Oscillation Stop Detection EnableNote: Can be modified only
7085                                                          once after a reset.                                                   */
7086            uint32_t             :  1;
7087       __IO uint32_t  CDRE0      :  1;               /*!< Comparator Disable Request Enable 0Note: Can be modified only
7088                                                          once after a reset.                                                   */
7089       __IO uint32_t  CDRE1      :  1;               /*!< Comparator Disable Request Enable 1Note: Can be modified only
7090                                                          once after a reset.                                                   */
7091       __IO uint32_t  CDRE2      :  1;               /*!< Comparator Disable Request Enable 2Note: Can be modified only
7092                                                          once after a reset.                                                   */
7093       __IO uint32_t  CDRE3      :  1;               /*!< Comparator Disable Request Enable 3Note: Can be modified only
7094                                                          once after a reset.                                                   */
7095       __IO uint32_t  CDRE4      :  1;               /*!< Comparator Disable Request Enable 4Note: Can be modified only
7096                                                          once after a reset.                                                   */
7097       __IO uint32_t  CDRE5      :  1;               /*!< Comparator Disable Request Enable 5Note: Can be modified only
7098                                                          once after a reset.                                                   */
7099            uint32_t             :  2;
7100       __I  uint32_t  ST         :  1;               /*!< GTETRG Input Status Flag                                              */
7101            uint32_t             : 11;
7102       __IO uint32_t  INV        :  1;               /*!< GTETRG Input Reverse                                                  */
7103       __IO uint32_t  NFEN       :  1;               /*!< Noise Filter Enable                                                   */
7104       __IO uint32_t  NFCS       :  2;               /*!< Noise Filter Clock Select                                             */
7105     } POEGGB_b;                                     /*!< BitSize                                                               */
7106   };
7107   __I  uint32_t  RESERVED1[63];
7108 
7109   union {
7110     __IO uint32_t  POEGGC;                          /*!< POEG Group %s Setting Register                                        */
7111 
7112     struct {
7113       __IO uint32_t  PIDF       :  1;               /*!< Port Input Detection Flag                                             */
7114       __IO uint32_t  IOCF       :  1;               /*!< Real Time Overcurrent Detection Flag                                  */
7115       __IO uint32_t  OSTPF      :  1;               /*!< Oscillation Stop Detection Flag                                       */
7116       __IO uint32_t  SSF        :  1;               /*!< Software Stop Flag                                                    */
7117       __IO uint32_t  PIDE       :  1;               /*!< Port Input Detection EnableNote: Can be modified only once after
7118                                                          a reset.                                                              */
7119       __IO uint32_t  IOCE       :  1;               /*!< Real Time Overcurrent EnableNote: Can be modified only once
7120                                                          after a reset.                                                        */
7121       __IO uint32_t  OSTPE      :  1;               /*!< Oscillation Stop Detection EnableNote: Can be modified only
7122                                                          once after a reset.                                                   */
7123            uint32_t             :  1;
7124       __IO uint32_t  CDRE0      :  1;               /*!< Comparator Disable Request Enable 0Note: Can be modified only
7125                                                          once after a reset.                                                   */
7126       __IO uint32_t  CDRE1      :  1;               /*!< Comparator Disable Request Enable 1Note: Can be modified only
7127                                                          once after a reset.                                                   */
7128       __IO uint32_t  CDRE2      :  1;               /*!< Comparator Disable Request Enable 2Note: Can be modified only
7129                                                          once after a reset.                                                   */
7130       __IO uint32_t  CDRE3      :  1;               /*!< Comparator Disable Request Enable 3Note: Can be modified only
7131                                                          once after a reset.                                                   */
7132       __IO uint32_t  CDRE4      :  1;               /*!< Comparator Disable Request Enable 4Note: Can be modified only
7133                                                          once after a reset.                                                   */
7134       __IO uint32_t  CDRE5      :  1;               /*!< Comparator Disable Request Enable 5Note: Can be modified only
7135                                                          once after a reset.                                                   */
7136            uint32_t             :  2;
7137       __I  uint32_t  ST         :  1;               /*!< GTETRG Input Status Flag                                              */
7138            uint32_t             : 11;
7139       __IO uint32_t  INV        :  1;               /*!< GTETRG Input Reverse                                                  */
7140       __IO uint32_t  NFEN       :  1;               /*!< Noise Filter Enable                                                   */
7141       __IO uint32_t  NFCS       :  2;               /*!< Noise Filter Clock Select                                             */
7142     } POEGGC_b;                                     /*!< BitSize                                                               */
7143   };
7144   __I  uint32_t  RESERVED2[63];
7145 
7146   union {
7147     __IO uint32_t  POEGGD;                          /*!< POEG Group %s Setting Register                                        */
7148 
7149     struct {
7150       __IO uint32_t  PIDF       :  1;               /*!< Port Input Detection Flag                                             */
7151       __IO uint32_t  IOCF       :  1;               /*!< Real Time Overcurrent Detection Flag                                  */
7152       __IO uint32_t  OSTPF      :  1;               /*!< Oscillation Stop Detection Flag                                       */
7153       __IO uint32_t  SSF        :  1;               /*!< Software Stop Flag                                                    */
7154       __IO uint32_t  PIDE       :  1;               /*!< Port Input Detection EnableNote: Can be modified only once after
7155                                                          a reset.                                                              */
7156       __IO uint32_t  IOCE       :  1;               /*!< Real Time Overcurrent EnableNote: Can be modified only once
7157                                                          after a reset.                                                        */
7158       __IO uint32_t  OSTPE      :  1;               /*!< Oscillation Stop Detection EnableNote: Can be modified only
7159                                                          once after a reset.                                                   */
7160            uint32_t             :  1;
7161       __IO uint32_t  CDRE0      :  1;               /*!< Comparator Disable Request Enable 0Note: Can be modified only
7162                                                          once after a reset.                                                   */
7163       __IO uint32_t  CDRE1      :  1;               /*!< Comparator Disable Request Enable 1Note: Can be modified only
7164                                                          once after a reset.                                                   */
7165       __IO uint32_t  CDRE2      :  1;               /*!< Comparator Disable Request Enable 2Note: Can be modified only
7166                                                          once after a reset.                                                   */
7167       __IO uint32_t  CDRE3      :  1;               /*!< Comparator Disable Request Enable 3Note: Can be modified only
7168                                                          once after a reset.                                                   */
7169       __IO uint32_t  CDRE4      :  1;               /*!< Comparator Disable Request Enable 4Note: Can be modified only
7170                                                          once after a reset.                                                   */
7171       __IO uint32_t  CDRE5      :  1;               /*!< Comparator Disable Request Enable 5Note: Can be modified only
7172                                                          once after a reset.                                                   */
7173            uint32_t             :  2;
7174       __I  uint32_t  ST         :  1;               /*!< GTETRG Input Status Flag                                              */
7175            uint32_t             : 11;
7176       __IO uint32_t  INV        :  1;               /*!< GTETRG Input Reverse                                                  */
7177       __IO uint32_t  NFEN       :  1;               /*!< Noise Filter Enable                                                   */
7178       __IO uint32_t  NFCS       :  2;               /*!< Noise Filter Clock Select                                             */
7179     } POEGGD_b;                                     /*!< BitSize                                                               */
7180   };
7181 } R_POEG_Type;
7182 
7183 
7184 /* ================================================================================ */
7185 /* ================                      R_RTC                     ================ */
7186 /* ================================================================================ */
7187 
7188 
7189 /**
7190   * @brief Realtime Clock (R_RTC)
7191   */
7192 
7193 typedef struct {                                    /*!< R_RTC Structure                                                       */
7194 
7195   union {
7196     __I  uint8_t   R64CNT;                          /*!< 64-Hz Counter                                                         */
7197 
7198     struct {
7199       __I  uint8_t   F64HZ      :  1;               /*!< 64Hz                                                                  */
7200       __I  uint8_t   F32HZ      :  1;               /*!< 32Hz                                                                  */
7201       __I  uint8_t   F16HZ      :  1;               /*!< 16Hz                                                                  */
7202       __I  uint8_t   F8HZ       :  1;               /*!< 8Hz                                                                   */
7203       __I  uint8_t   F4HZ       :  1;               /*!< 4Hz                                                                   */
7204       __I  uint8_t   F2HZ       :  1;               /*!< 2Hz                                                                   */
7205       __I  uint8_t   F1HZ       :  1;               /*!< 1Hz                                                                   */
7206     } R64CNT_b;                                     /*!< BitSize                                                               */
7207   };
7208   __I  uint8_t   RESERVED;
7209 
7210   union {
7211     union {
7212       __IO uint8_t   BCNT0;                         /*!< Binary Counter 0                                                      */
7213 
7214       struct {
7215         __IO uint8_t   BCNT0    :  8;               /*!< The BCNT0 counter is a readable/writeable 32-bit binary counter
7216                                                          b7 to b0.                                                             */
7217       } BCNT0_b;                                    /*!< BitSize                                                               */
7218     };
7219 
7220     union {
7221       __IO uint8_t   RSECCNT;                       /*!< Second Counter                                                        */
7222 
7223       struct {
7224         __IO uint8_t   SEC1     :  4;               /*!< 1-Second CountCounts from 0 to 9 every second. When a carry
7225                                                          is generated, 1 is added to the tens place.                           */
7226         __IO uint8_t   SEC10    :  3;               /*!< 10-Second CountCounts from 0 to 5 for 60-second counting.             */
7227       } RSECCNT_b;                                  /*!< BitSize                                                               */
7228     };
7229   };
7230   __I  uint8_t   RESERVED1;
7231 
7232   union {
7233     union {
7234       __IO uint8_t   BCNT1;                         /*!< Binary Counter 1                                                      */
7235 
7236       struct {
7237         __IO uint8_t   BCNT1    :  8;               /*!< The BCNT1 counter is a readable/writeable 32-bit binary counter
7238                                                          b15 to b8.                                                            */
7239       } BCNT1_b;                                    /*!< BitSize                                                               */
7240     };
7241 
7242     union {
7243       __IO uint8_t   RMINCNT;                       /*!< Minute Counter                                                        */
7244 
7245       struct {
7246         __IO uint8_t   MIN1     :  4;               /*!< 1-Minute CountCounts from 0 to 9 every minute. When a carry
7247                                                          is generated, 1 is added to the tens place.                           */
7248         __IO uint8_t   MIN10    :  3;               /*!< 10-Minute CountCounts from 0 to 5 for 60-minute counting.             */
7249       } RMINCNT_b;                                  /*!< BitSize                                                               */
7250     };
7251   };
7252   __I  uint8_t   RESERVED2;
7253 
7254   union {
7255     union {
7256       __IO uint8_t   BCNT2;                         /*!< Binary Counter 2                                                      */
7257 
7258       struct {
7259         __IO uint8_t   BCNT2    :  8;               /*!< The BCNT2 counter is a readable/writeable 32-bit binary counter
7260                                                          b23 to b16.                                                           */
7261       } BCNT2_b;                                    /*!< BitSize                                                               */
7262     };
7263 
7264     union {
7265       __IO uint8_t   RHRCNT;                        /*!< Hour Counter                                                          */
7266 
7267       struct {
7268         __IO uint8_t   HR1      :  4;               /*!< 1-Hour CountCounts from 0 to 9 once per hour. When a carry is
7269                                                          generated, 1 is added to the tens place.                              */
7270         __IO uint8_t   HR10     :  2;               /*!< 10-Hour CountCounts from 0 to 2 once per carry from the ones
7271                                                          place.                                                                */
7272         __IO uint8_t   PM       :  1;               /*!< Time Counter Setting for a.m./p.m.                                    */
7273       } RHRCNT_b;                                   /*!< BitSize                                                               */
7274     };
7275   };
7276   __I  uint8_t   RESERVED3;
7277 
7278   union {
7279     union {
7280       __IO uint8_t   BCNT3;                         /*!< Binary Counter 3                                                      */
7281 
7282       struct {
7283         __IO uint8_t   BCNT3    :  8;               /*!< The BCNT3 counter is a readable/writeable 32-bit binary counter
7284                                                          b31 to b24.                                                           */
7285       } BCNT3_b;                                    /*!< BitSize                                                               */
7286     };
7287 
7288     union {
7289       __IO uint8_t   RWKCNT;                        /*!< Day-of-Week Counter                                                   */
7290 
7291       struct {
7292         __IO uint8_t   DAYW     :  3;               /*!< Day-of-Week Counting                                                  */
7293       } RWKCNT_b;                                   /*!< BitSize                                                               */
7294     };
7295   };
7296   __I  uint8_t   RESERVED4;
7297 
7298   union {
7299     __IO uint8_t   RDAYCNT;                         /*!< Date Counter                                                          */
7300 
7301     struct {
7302       __IO uint8_t   DATE1      :  4;               /*!< 1-Day CountCounts from 0 to 9 once per day. When a carry is
7303                                                          generated, 1 is added to the tens place.                              */
7304       __IO uint8_t   DATE10     :  2;               /*!< 10-Day CountCounts from 0 to 3 once per carry from the ones
7305                                                          place.                                                                */
7306     } RDAYCNT_b;                                    /*!< BitSize                                                               */
7307   };
7308   __I  uint8_t   RESERVED5;
7309 
7310   union {
7311     __IO uint8_t   RMONCNT;                         /*!< Month Counter                                                         */
7312 
7313     struct {
7314       __IO uint8_t   MON1       :  4;               /*!< 1-Month CountCounts from 0 to 9 once per month. When a carry
7315                                                          is generated, 1 is added to the tens place.                           */
7316       __IO uint8_t   MON10      :  1;               /*!< 10-Month CountCounts from 0 to 1 once per carry from the ones
7317                                                          place.                                                                */
7318     } RMONCNT_b;                                    /*!< BitSize                                                               */
7319   };
7320   __I  uint8_t   RESERVED6;
7321 
7322   union {
7323     __IO uint16_t  RYRCNT;                          /*!< Year Counter                                                          */
7324 
7325     struct {
7326       __IO uint16_t  YR1        :  4;               /*!< 1-Year CountCounts from 0 to 9 once per year. When a carry is
7327                                                          generated, 1 is added to the tens place.                              */
7328       __IO uint16_t  YR10       :  4;               /*!< 10-Year CountCounts from 0 to 9 once per carry from ones place.
7329                                                          When a carry is generated in the tens place, 1 is added to the
7330                                                           hundreds place.                                                      */
7331     } RYRCNT_b;                                     /*!< BitSize                                                               */
7332   };
7333 
7334   union {
7335     union {
7336       __IO uint8_t   BCNT0AR;                       /*!< Binary Counter 0 Alarm Register                                       */
7337 
7338       struct {
7339         __IO uint8_t   BCNT0AR  :  8;               /*!< he BCNT0AR counter is a readable/writeable alarm register corresponding
7340                                                          to 32-bit binary counter b7 to b0.                                    */
7341       } BCNT0AR_b;                                  /*!< BitSize                                                               */
7342     };
7343 
7344     union {
7345       __IO uint8_t   RSECAR;                        /*!< Second Alarm Register                                                 */
7346 
7347       struct {
7348         __O  uint8_t   SEC1     :  4;               /*!< 1-SecondValue for the ones place of seconds                           */
7349         __IO uint8_t   SEC10    :  3;               /*!< 10-SecondsValue for the tens place of seconds                         */
7350         __IO uint8_t   ENB      :  1;               /*!< Compare enable                                                        */
7351       } RSECAR_b;                                   /*!< BitSize                                                               */
7352     };
7353   };
7354   __I  uint8_t   RESERVED7;
7355 
7356   union {
7357     union {
7358       __IO uint8_t   BCNT1AR;                       /*!< Binary Counter 1 Alarm Register                                       */
7359 
7360       struct {
7361         __IO uint8_t   BCNT1AR  :  8;               /*!< he BCNT1AR counter is a readable/writeable alarm register corresponding
7362                                                          to 32-bit binary counter b15 to b8.                                   */
7363       } BCNT1AR_b;                                  /*!< BitSize                                                               */
7364     };
7365 
7366     union {
7367       __IO uint8_t   RMINAR;                        /*!< Minute Alarm Register                                                 */
7368 
7369       struct {
7370         __IO uint8_t   MIN1     :  4;               /*!< 1-Minute CountValue for the ones place of minutes                     */
7371         __IO uint8_t   MIN10    :  3;               /*!< 10-Minute CountValue for the tens place of minutes                    */
7372         __IO uint8_t   ENB      :  1;               /*!< Compare enable                                                        */
7373       } RMINAR_b;                                   /*!< BitSize                                                               */
7374     };
7375   };
7376   __I  uint8_t   RESERVED8;
7377 
7378   union {
7379     union {
7380       __IO uint8_t   BCNT2AR;                       /*!< Binary Counter 2 Alarm Register                                       */
7381 
7382       struct {
7383         __IO uint8_t   BCNT2AR  :  8;               /*!< The BCNT2AR counter is a readable/writeable 32-bit binary counter
7384                                                          b23 to b16.                                                           */
7385       } BCNT2AR_b;                                  /*!< BitSize                                                               */
7386     };
7387 
7388     union {
7389       __IO uint8_t   RHRAR;                         /*!< Hour Alarm Register                                                   */
7390 
7391       struct {
7392         __IO uint8_t   HR1      :  4;               /*!< 1-Hour CountValue for the ones place of hours                         */
7393         __IO uint8_t   HR10     :  2;               /*!< 10-Hour CountValue for the tens place of hours                        */
7394         __IO uint8_t   PM       :  1;               /*!< Time Counter Setting for a.m./p.m.                                    */
7395         __IO uint8_t   ENB      :  1;               /*!< Compare enable                                                        */
7396       } RHRAR_b;                                    /*!< BitSize                                                               */
7397     };
7398   };
7399   __I  uint8_t   RESERVED9;
7400 
7401   union {
7402     union {
7403       __IO uint8_t   BCNT3AR;                       /*!< Binary Counter 3 Alarm Register                                       */
7404 
7405       struct {
7406         __IO uint8_t   BCNT3AR  :  8;               /*!< The BCNT3AR counter is a readable/writeable 32-bit binary counter
7407                                                          b31 to b24.                                                           */
7408       } BCNT3AR_b;                                  /*!< BitSize                                                               */
7409     };
7410 
7411     union {
7412       __IO uint8_t   RWKAR;                         /*!< Day-of-Week Alarm Register                                            */
7413 
7414       struct {
7415         __IO uint8_t   DAYW     :  3;               /*!< Day-of-Week Counting                                                  */
7416              uint8_t            :  4;
7417         __IO uint8_t   ENB      :  1;               /*!< Compare enable                                                        */
7418       } RWKAR_b;                                    /*!< BitSize                                                               */
7419     };
7420   };
7421   __I  uint8_t   RESERVED10;
7422 
7423   union {
7424     union {
7425       __IO uint8_t   BCNT0AER;                      /*!< Binary Counter 0 Alarm Enable Register                                */
7426 
7427       struct {
7428         __IO uint8_t   ENB      :  8;               /*!< The BCNT0AER register is a readable/writeable register for setting
7429                                                          the alarm enable corresponding to 32-bit binary counter b7 to
7430                                                           b0.                                                                  */
7431       } BCNT0AER_b;                                 /*!< BitSize                                                               */
7432     };
7433 
7434     union {
7435       __IO uint8_t   RDAYAR;                        /*!< Date Alarm Register                                                   */
7436 
7437       struct {
7438         __IO uint8_t   DATE1    :  4;               /*!< 1 DayValue for the ones place of days                                 */
7439         __IO uint8_t   DATE10   :  2;               /*!< 10 DaysValue for the tens place of days                               */
7440              uint8_t            :  1;
7441         __IO uint8_t   ENB      :  1;               /*!< Compare enable                                                        */
7442       } RDAYAR_b;                                   /*!< BitSize                                                               */
7443     };
7444   };
7445   __I  uint8_t   RESERVED11;
7446 
7447   union {
7448     union {
7449       __IO uint8_t   BCNT1AER;                      /*!< Binary Counter 1 Alarm Enable Register                                */
7450 
7451       struct {
7452         __IO uint8_t   ENB      :  8;               /*!< The BCNT1AER register is a readable/writeable register for setting
7453                                                          the alarm enable corresponding to 32-bit binary counter b15
7454                                                           to b8.                                                               */
7455       } BCNT1AER_b;                                 /*!< BitSize                                                               */
7456     };
7457 
7458     union {
7459       __IO uint8_t   RMONAR;                        /*!< Month Alarm Register                                                  */
7460 
7461       struct {
7462         __IO uint8_t   MON1     :  4;               /*!< 1 MonthValue for the ones place of months                             */
7463         __IO uint8_t   MON10    :  1;               /*!< 10 MonthsValue for the tens place of months                           */
7464              uint8_t            :  2;
7465         __IO uint8_t   ENB      :  1;               /*!< Compare enable                                                        */
7466       } RMONAR_b;                                   /*!< BitSize                                                               */
7467     };
7468   };
7469   __I  uint8_t   RESERVED12;
7470 
7471   union {
7472     union {
7473       __IO uint16_t  BCNT2AER;                      /*!< Binary Counter 2 Alarm Enable Register                                */
7474 
7475       struct {
7476         __IO uint16_t  ENB      :  8;               /*!< The BCNT2AER register is a readable/writeable register for setting
7477                                                          the alarm enable corresponding to 32-bit binary counter b23
7478                                                           to b16.                                                              */
7479       } BCNT2AER_b;                                 /*!< BitSize                                                               */
7480     };
7481 
7482     union {
7483       __IO uint16_t  RYRAR;                         /*!< Year Alarm Register                                                   */
7484 
7485       struct {
7486         __IO uint16_t  YR1      :  4;               /*!< 1 YearValue for the ones place of years                               */
7487         __IO uint16_t  YR10     :  4;               /*!< 10 YearsValue for the tens place of years                             */
7488       } RYRAR_b;                                    /*!< BitSize                                                               */
7489     };
7490   };
7491 
7492   union {
7493     union {
7494       __IO uint8_t   BCNT3AER;                      /*!< Binary Counter 3 Alarm Enable Register                                */
7495 
7496       struct {
7497         __IO uint8_t   ENB      :  8;               /*!< The BCNT3AER register is a readable/writeable register for setting
7498                                                          the alarm enable corresponding to 32-bit binary counter b31
7499                                                           to b24.                                                              */
7500       } BCNT3AER_b;                                 /*!< BitSize                                                               */
7501     };
7502 
7503     union {
7504       __IO uint8_t   RYRAREN;                       /*!< Year Alarm Enable Register                                            */
7505 
7506       struct {
7507              uint8_t            :  7;
7508         __IO uint8_t   ENB      :  1;               /*!< Compare enable                                                        */
7509       } RYRAREN_b;                                  /*!< BitSize                                                               */
7510     };
7511   };
7512   __I  uint8_t   RESERVED13[3];
7513 
7514   union {
7515     __IO uint8_t   RCR1;                            /*!< RTC Control Register 1                                                */
7516 
7517     struct {
7518       __IO uint8_t   AIE        :  1;               /*!< Alarm Interrupt Enable                                                */
7519       __IO uint8_t   CIE        :  1;               /*!< Carry Interrupt Enable                                                */
7520       __IO uint8_t   PIE        :  1;               /*!< Periodic Interrupt Enable                                             */
7521       __IO uint8_t   RTCOS      :  1;               /*!< RTCOUT Output Select                                                  */
7522       __IO uint8_t   PES        :  4;               /*!< Periodic Interrupt Select                                             */
7523     } RCR1_b;                                       /*!< BitSize                                                               */
7524   };
7525   __I  uint8_t   RESERVED14;
7526 
7527   union {
7528     __IO uint8_t   RCR2;                            /*!< RTC Control Register 2                                                */
7529 
7530     struct {
7531       __IO uint8_t   START      :  1;               /*!< Start                                                                 */
7532       __IO uint8_t   RESET      :  1;               /*!< RTC Software Reset                                                    */
7533       __IO uint8_t   ADJ30      :  1;               /*!< 30-Second Adjustment                                                  */
7534       __IO uint8_t   RTCOE      :  1;               /*!< RTCOUT Output Enable                                                  */
7535       __IO uint8_t   AADJE      :  1;               /*!< Automatic Adjustment Enable (When the LOCO clock is selected,
7536                                                          the setting of this bit is disabled.)                                 */
7537       __IO uint8_t   AADJP      :  1;               /*!< Automatic Adjustment Period Select (When the LOCO clock is selected,
7538                                                          the setting of this bit is disabled.)                                 */
7539       __IO uint8_t   HR24       :  1;               /*!< Hours Mode                                                            */
7540       __IO uint8_t   CNTMD      :  1;               /*!< Count Mode Select                                                     */
7541     } RCR2_b;                                       /*!< BitSize                                                               */
7542   };
7543   __I  uint8_t   RESERVED15[3];
7544 
7545   union {
7546     __IO uint8_t   RCR4;                            /*!< RTC Control Register 4                                                */
7547 
7548     struct {
7549       __IO uint8_t   RCKSEL     :  1;               /*!< Count Source Select                                                   */
7550     } RCR4_b;                                       /*!< BitSize                                                               */
7551   };
7552   __I  uint8_t   RESERVED16;
7553 
7554   union {
7555     __IO uint16_t  RFRH;                            /*!< Frequency Register H                                                  */
7556 
7557     struct {
7558       __IO uint16_t  RFC16      :  1;               /*!< Frequency Comparison Value (b16)To generate the operating clock
7559                                                          from the LOCOclock, this bit sets the comparison value of the
7560                                                           128-Hz clock cycle.                                                  */
7561     } RFRH_b;                                       /*!< BitSize                                                               */
7562   };
7563 
7564   union {
7565     __IO uint16_t  RFRL;                            /*!< Frequency Register L                                                  */
7566 
7567     struct {
7568       __IO uint16_t  RFC        : 16;               /*!< Frequency Comparison Value(b15-b0)To generate the operating
7569                                                          clock from the main clock, this bit sets the comparison value
7570                                                           of the 128-Hz clock cycle.                                           */
7571     } RFRL_b;                                       /*!< BitSize                                                               */
7572   };
7573 
7574   union {
7575     __IO uint8_t   RADJ;                            /*!< Time Error Adjustment Register                                        */
7576 
7577     struct {
7578       __IO uint8_t   ADJ        :  6;               /*!< Adjustment ValueThese bits specify the adjustment value from
7579                                                          the prescaler.                                                        */
7580       __IO uint8_t   PMADJ      :  2;               /*!< Plus-Minus                                                            */
7581     } RADJ_b;                                       /*!< BitSize                                                               */
7582   };
7583   __I  uint8_t   RESERVED17[17];
7584   R_RTC_RTCCRnRC0_Type RTCCRnRC0[3];                /*!< Time Capture Control Register %s Register Cluster 0                   */
7585   __I  uint8_t RESERVED18[3 * 4];
7586   R_RTC_CnRC0_Type CnRC0[3];                        /*!< Capture %s Register Cluster 0                                         */
7587 } R_RTC_Type;
7588 
7589 
7590 /* ================================================================================ */
7591 /* ================                      R_WDT                     ================ */
7592 /* ================================================================================ */
7593 
7594 
7595 /**
7596   * @brief Watchdog Timer  (R_WDT)
7597   */
7598 
7599 typedef struct {                                    /*!< R_WDT Structure                                                       */
7600 
7601   union {
7602     __IO uint8_t   WDTRR;                           /*!< WDT Refresh Register                                                  */
7603 
7604     struct {
7605       __IO uint8_t   WDTRR      :  8;               /*!< WDTRR is an 8-bit register that refreshes the down-counter of
7606                                                          the WDT.                                                              */
7607     } WDTRR_b;                                      /*!< BitSize                                                               */
7608   };
7609   __I  uint8_t   RESERVED;
7610 
7611   union {
7612     __IO uint16_t  WDTCR;                           /*!< WDT Control Register                                                  */
7613 
7614     struct {
7615       __IO uint16_t  TOPS       :  2;               /*!< Timeout Period Selection                                              */
7616            uint16_t             :  2;
7617       __IO uint16_t  CKS        :  4;               /*!< Clock Division Ratio Selection                                        */
7618       __IO uint16_t  RPES       :  2;               /*!< Window End Position Selection                                         */
7619            uint16_t             :  2;
7620       __IO uint16_t  RPSS       :  2;               /*!< Window Start Position Selection                                       */
7621     } WDTCR_b;                                      /*!< BitSize                                                               */
7622   };
7623 
7624   union {
7625     __IO uint16_t  WDTSR;                           /*!< WDT Status Register                                                   */
7626 
7627     struct {
7628       __I  uint16_t  CNTVAL     : 14;               /*!< Down-Counter ValueValue counted by the down-counter                   */
7629       __IO uint16_t  UNDFF      :  1;               /*!< Underflow Flag                                                        */
7630       __IO uint16_t  REFEF      :  1;               /*!< Refresh Error Flag                                                    */
7631     } WDTSR_b;                                      /*!< BitSize                                                               */
7632   };
7633 
7634   union {
7635     __IO uint8_t   WDTRCR;                          /*!< WDT Reset Control Register                                            */
7636 
7637     struct {
7638            uint8_t              :  7;
7639       __IO uint8_t   RSTIRQS    :  1;               /*!< Reset Interrupt Request Selection                                     */
7640     } WDTRCR_b;                                     /*!< BitSize                                                               */
7641   };
7642   __I  uint8_t   RESERVED1;
7643 
7644   union {
7645     __IO uint8_t   WDTCSTPR;                        /*!< WDT Count Stop Control Register                                       */
7646 
7647     struct {
7648            uint8_t              :  7;
7649       __IO uint8_t   SLCSTP     :  1;               /*!< Sleep-Mode Count Stop Control                                         */
7650     } WDTCSTPR_b;                                   /*!< BitSize                                                               */
7651   };
7652 } R_WDT_Type;
7653 
7654 
7655 /* ================================================================================ */
7656 /* ================                     R_IWDT                     ================ */
7657 /* ================================================================================ */
7658 
7659 
7660 /**
7661   * @brief Independent Watchdog Timer (R_IWDT)
7662   */
7663 
7664 typedef struct {                                    /*!< R_IWDT Structure                                                      */
7665 
7666   union {
7667     __IO uint8_t   IWDTRR;                          /*!< IWDT Refresh Register                                                 */
7668 
7669     struct {
7670       __IO uint8_t   IWDTRR     :  8;               /*!< The counter is refreshed by writing 0x00 and then writing 0xFF
7671                                                          to this register.                                                     */
7672     } IWDTRR_b;                                     /*!< BitSize                                                               */
7673   };
7674   __I  uint8_t   RESERVED[3];
7675 
7676   union {
7677     __IO uint16_t  IWDTSR;                          /*!< IWDT Status Register                                                  */
7678 
7679     struct {
7680       __I  uint16_t  CNTVAL     : 14;               /*!< Counter ValueValue counted by the counter                             */
7681       __IO uint16_t  UNDFF      :  1;               /*!< Underflow Flag                                                        */
7682       __IO uint16_t  REFEF      :  1;               /*!< Refresh Error Flag                                                    */
7683     } IWDTSR_b;                                     /*!< BitSize                                                               */
7684   };
7685 } R_IWDT_Type;
7686 
7687 
7688 /* ================================================================================ */
7689 /* ================                      R_CAC                     ================ */
7690 /* ================================================================================ */
7691 
7692 
7693 /**
7694   * @brief Clock Frequency Accuracy Measurement Circuit  (R_CAC)
7695   */
7696 
7697 typedef struct {                                    /*!< R_CAC Structure                                                       */
7698 
7699   union {
7700     __IO uint8_t   CACR0;                           /*!< CAC Control Register 0                                                */
7701 
7702     struct {
7703       __IO uint8_t   CFME       :  1;               /*!< Clock Frequency Measurement Enable.                                   */
7704     } CACR0_b;                                      /*!< BitSize                                                               */
7705   };
7706 
7707   union {
7708     __IO uint8_t   CACR1;                           /*!< CAC Control Register 1                                                */
7709 
7710     struct {
7711       __IO uint8_t   CACREFE    :  1;               /*!< CACREF Pin Input Enable                                               */
7712       __IO uint8_t   FMCS       :  3;               /*!< Frequency Measurement Output Clock Select                             */
7713       __IO uint8_t   TCSS       :  2;               /*!< Timer Count Clock Source Select                                       */
7714       __IO uint8_t   EDGES      :  2;               /*!< Valid Edge Select                                                     */
7715     } CACR1_b;                                      /*!< BitSize                                                               */
7716   };
7717 
7718   union {
7719     __IO uint8_t   CACR2;                           /*!< CAC Control Register 2                                                */
7720 
7721     struct {
7722       __IO uint8_t   RPS        :  1;               /*!< Reference Signal Select                                               */
7723       __IO uint8_t   RSCS       :  3;               /*!< Reference Signal Generation Output Clock Select                       */
7724       __IO uint8_t   RCDS       :  2;               /*!< Reference Signal Generation Clock Frequency Division Ratio Select
7725                                                                                                                                */
7726       __IO uint8_t   DFS        :  2;               /*!< Digital Filter Selection                                              */
7727     } CACR2_b;                                      /*!< BitSize                                                               */
7728   };
7729 
7730   union {
7731     __IO uint8_t   CAICR;                           /*!< CAC Interrupt Control Register                                        */
7732 
7733     struct {
7734       __IO uint8_t   FERRIE     :  1;               /*!< Frequency Error Interrupt Enable                                      */
7735       __IO uint8_t   MENDIE     :  1;               /*!< Measurement End Interrupt Enable                                      */
7736       __IO uint8_t   OVFIE      :  1;               /*!< Overflow Interrupt Enable                                             */
7737            uint8_t              :  1;
7738       __O  uint8_t   FERRFCL    :  1;               /*!< FERRF Clear                                                           */
7739       __O  uint8_t   MENDFCL    :  1;               /*!< MENDF Clear                                                           */
7740       __O  uint8_t   OVFFCL     :  1;               /*!< OVFF Clear                                                            */
7741     } CAICR_b;                                      /*!< BitSize                                                               */
7742   };
7743 
7744   union {
7745     __IO uint8_t   CASTR;                           /*!< CAC Status Register                                                   */
7746 
7747     struct {
7748       __I  uint8_t   FERRF      :  1;               /*!< Frequency Error Flag                                                  */
7749       __I  uint8_t   MENDF      :  1;               /*!< Measurement End Flag                                                  */
7750       __I  uint8_t   OVFF       :  1;               /*!< Counter Overflow Flag                                                 */
7751     } CASTR_b;                                      /*!< BitSize                                                               */
7752   };
7753   __I  uint8_t   RESERVED;
7754 
7755   union {
7756     __IO uint16_t  CAULVR;                          /*!< CAC Upper-Limit Value Setting Register                                */
7757 
7758     struct {
7759       __IO uint16_t  CAULVR     : 16;               /*!< CAULVR is a 16-bit readable/writeable register that stores the
7760                                                          upper-limit value of the frequency.                                   */
7761     } CAULVR_b;                                     /*!< BitSize                                                               */
7762   };
7763 
7764   union {
7765     __IO uint16_t  CALLVR;                          /*!< CAC Lower-Limit Value Setting Register                                */
7766 
7767     struct {
7768       __IO uint16_t  CALLVR     : 16;               /*!< CALLVR is a 16-bit readable/writeable register that stores the
7769                                                          lower-limit value of the frequency.                                   */
7770     } CALLVR_b;                                     /*!< BitSize                                                               */
7771   };
7772 
7773   union {
7774     __I  uint16_t  CACNTBR;                         /*!< CAC Counter Buffer Register                                           */
7775 
7776     struct {
7777       __I  uint16_t  CACNTBR    : 16;               /*!< CACNTBR is a 16-bit read-only register that retains the counter
7778                                                          value at the time a valid reference signal edge is input              */
7779     } CACNTBR_b;                                    /*!< BitSize                                                               */
7780   };
7781 } R_CAC_Type;
7782 
7783 
7784 /* ================================================================================ */
7785 /* ================                     R_MSTP                     ================ */
7786 /* ================================================================================ */
7787 
7788 
7789 /**
7790   * @brief Module Stop Control B,C,D (R_MSTP)
7791   */
7792 
7793 typedef struct {                                    /*!< R_MSTP Structure                                                      */
7794 
7795   union {
7796     __IO uint32_t  MSTPCRB;                         /*!< Module Stop Control Register B                                        */
7797 
7798     struct {
7799            uint32_t             :  1;
7800       __IO uint32_t  MSTPB1     :  1;               /*!< RCAN1 Module Stop                                                     */
7801       __IO uint32_t  MSTPB2     :  1;               /*!< RCAN0 Module Stop                                                     */
7802            uint32_t             :  2;
7803       __IO uint32_t  MSTPB5     :  1;               /*!< IrDA Module Stop                                                      */
7804       __IO uint32_t  MSTPB6     :  1;               /*!< Queued Serial Peripheral Interface Module Stop                        */
7805       __IO uint32_t  MSTPB7     :  1;               /*!< I2C Bus Interface 2 Module Stop                                       */
7806       __IO uint32_t  MSTPB8     :  1;               /*!< I2C Bus Interface 1 Module Stop                                       */
7807       __IO uint32_t  MSTPB9     :  1;               /*!< I2C Bus Interface 0 Module Stop                                       */
7808            uint32_t             :  1;
7809       __IO uint32_t  MSTPB11    :  1;               /*!< Universal Serial Bus 2.0 FS Interface Module Stop                     */
7810       __IO uint32_t  MSTPB12    :  1;               /*!< Universal Serial Bus 2.0 HS Interface Module Stop                     */
7811       __IO uint32_t  MSTPB13    :  1;               /*!< EPTPC and PTPEDMAC Module Stop                                        */
7812       __IO uint32_t  MSTPB14    :  1;               /*!< ETHERC1 and EDMAC1 Module Stop                                        */
7813       __IO uint32_t  MSTPB15    :  1;               /*!< ETHERC0 and EDMAC0 Module Stop                                        */
7814            uint32_t             :  2;
7815       __IO uint32_t  MSTPB18    :  1;               /*!< Serial Peripheral Interface Module Stop                               */
7816       __IO uint32_t  MSTPB19    :  1;               /*!< Serial Peripheral Interface 0 Module Stop                             */
7817            uint32_t             :  2;
7818       __IO uint32_t  MSTPB22    :  1;               /*!< Serial Communication Interface 9 Module Stop                          */
7819       __IO uint32_t  MSTPB23    :  1;               /*!< Serial Communication Interface 8 Module Stop                          */
7820       __IO uint32_t  MSTPB24    :  1;               /*!< Serial Communication Interface 7 Module Stop                          */
7821       __IO uint32_t  MSTPB25    :  1;               /*!< Serial Communication Interface 6 Module Stop                          */
7822       __IO uint32_t  MSTPB26    :  1;               /*!< Serial Communication Interface 5 Module Stop                          */
7823       __IO uint32_t  MSTPB27    :  1;               /*!< Serial Communication Interface 4 Module Stop                          */
7824       __IO uint32_t  MSTPB28    :  1;               /*!< Serial Communication Interface 3 Module Stop                          */
7825       __IO uint32_t  MSTPB29    :  1;               /*!< Serial Communication Interface 2 Module Stop                          */
7826       __IO uint32_t  MSTPB30    :  1;               /*!< Serial Communication Interface 1 Module Stop                          */
7827       __IO uint32_t  MSTPB31    :  1;               /*!< Serial Communication Interface 0 Module Stop                          */
7828     } MSTPCRB_b;                                    /*!< BitSize                                                               */
7829   };
7830 
7831   union {
7832     __IO uint32_t  MSTPCRC;                         /*!< Module Stop Control Register C                                        */
7833 
7834     struct {
7835       __IO uint32_t  MSTPC0     :  1;               /*!< CAC Module Stop                                                       */
7836       __IO uint32_t  MSTPC1     :  1;               /*!< CRC Calculator Module Stop                                            */
7837       __IO uint32_t  MSTPC2     :  1;               /*!< Parallel Data Capture Module Stop                                     */
7838       __IO uint32_t  MSTPC3     :  1;               /*!< Capacitive Touch Sensing Unit Module Stop                             */
7839       __IO uint32_t  MSTPC4     :  1;               /*!< Graphic LCD Controller Module Stop                                    */
7840       __IO uint32_t  MSTPC5     :  1;               /*!< JPEG codec engine Module Stop                                         */
7841       __IO uint32_t  MSTPC6     :  1;               /*!< 2DG engine Module Stop                                                */
7842       __IO uint32_t  MSTPC7     :  1;               /*!< Synchronous Serial Interface 1 Module Stop                            */
7843       __IO uint32_t  MSTPC8     :  1;               /*!< Synchronous Serial Interface 0 Module Stop                            */
7844       __IO uint32_t  MSTPC9     :  1;               /*!< Sampling Rate Converter Module Stop                                   */
7845            uint32_t             :  1;
7846       __IO uint32_t  MSTPC11    :  1;               /*!< Synchronous Digital Hierarchy/ Multi Media Card 1 Module Stop         */
7847       __IO uint32_t  MSTPC12    :  1;               /*!< Synchronous Digital Hierarchy/ Multi Media Card 0 Module Stop         */
7848       __IO uint32_t  MSTPC13    :  1;               /*!< Data Operation Circuit Module Stop                                    */
7849       __IO uint32_t  MSTPC14    :  1;               /*!< Event Link Controller Module Stop                                     */
7850            uint32_t             : 13;
7851       __IO uint32_t  MSTPC28    :  1;               /*!< TRNG Module Stop                                                      */
7852            uint32_t             :  2;
7853       __IO uint32_t  MSTPC31    :  1;               /*!< TSIP Module Stop                                                      */
7854     } MSTPCRC_b;                                    /*!< BitSize                                                               */
7855   };
7856 
7857   union {
7858     __IO uint32_t  MSTPCRD;                         /*!< Module Stop Control Register D                                        */
7859 
7860     struct {
7861            uint32_t             :  2;
7862       __IO uint32_t  MSTPD2     :  1;               /*!< AGT1 Module StopNote: AGT1 is in the module stop state when
7863                                                          the count source is either of PCLKB, PCLKB/2 or PCLKB/8. In
7864                                                           case the count source is sub-clock or LOCO, this bit should
7865                                                           be set to 1 except when accessing the registers of AGT1.             */
7866       __IO uint32_t  MSTPD3     :  1;               /*!< AGT0 Module StopNote: AGT0 is in the module stop state when
7867                                                          the count source is either of PCLKB, PCLKB/2 or PCLKB/8. In
7868                                                           case the count source is sub-clock or LOCO, this bit should
7869                                                           be set to 1 except when accessing the registers of AGT0.             */
7870            uint32_t             :  1;
7871       __IO uint32_t  MSTPD5     :  1;               /*!< GPT ch7-ch0 Module Stop                                               */
7872       __IO uint32_t  MSTPD6     :  1;               /*!< GPT ch13-ch8 Module Stop                                              */
7873            uint32_t             :  7;
7874       __IO uint32_t  MSTPD14    :  1;               /*!< PGI Module Stop                                                       */
7875       __IO uint32_t  MSTPD15    :  1;               /*!< 12-bit A/D Converter 1 Module Stop                                    */
7876       __IO uint32_t  MSTPD16    :  1;               /*!< 12-bit A/D Converter 0 Module Stop                                    */
7877            uint32_t             :  3;
7878       __IO uint32_t  MSTPD20    :  1;               /*!< D/A Converter 0 Module Stop                                           */
7879            uint32_t             :  1;
7880       __IO uint32_t  MSTPD22    :  1;               /*!< Temperature Sensor Module Stop                                        */
7881       __IO uint32_t  MSTPD23    :  1;               /*!< Comparator-OC5 Module Stop                                            */
7882       __IO uint32_t  MSTPD24    :  1;               /*!< Comparator-OC4 Module Stop                                            */
7883       __IO uint32_t  MSTPD25    :  1;               /*!< Comparator-OC3 Module Stop                                            */
7884       __IO uint32_t  MSTPD26    :  1;               /*!< Comparator-OC2 Module Stop                                            */
7885       __IO uint32_t  MSTPD27    :  1;               /*!< Comparator-OC1 Module Stop                                            */
7886       __IO uint32_t  MSTPD28    :  1;               /*!< Comparator-OC0 Module Stop                                            */
7887     } MSTPCRD_b;                                    /*!< BitSize                                                               */
7888   };
7889 } R_MSTP_Type;
7890 
7891 /* ================================================================================ */
7892 /* ================                     R_SSI0                     ================ */
7893 /* ================================================================================ */
7894 
7895 
7896 /**
7897   * @brief Serial Sound Interface 0 (R_SSI0)
7898   */
7899 
7900 typedef struct {                                    /*!< R_SSI0 Structure                                                      */
7901 
7902   union {
7903     __IO uint32_t  SSICR;                           /*!< Control Register                                                      */
7904 
7905     struct {
7906       __IO uint32_t  REN        :  1;               /*!< Receive Enable                                                        */
7907       __IO uint32_t  TEN        :  1;               /*!< Transmit Enable                                                       */
7908            uint32_t             :  1;
7909       __IO uint32_t  MUEN       :  1;               /*!< Mute EnableNOTE: When this module is muted, the value of outputting
7910                                                          serial data is rewritten to 0 but data transmission is not stopped.
7911                                                           Write dummy data to the SSIFTDR not to generate a transmit underflow
7912                                                           because the number of data in the transmit FIFO is decreasing.       */
7913       __IO uint32_t  CKDV       :  4;               /*!< Serial Oversampling Clock Division Ratio                              */
7914       __IO uint32_t  DEL        :  1;               /*!< Serial Data Delay                                                     */
7915       __IO uint32_t  PDTA       :  1;               /*!< Parallel Data Alignment                                               */
7916       __IO uint32_t  SDTA       :  1;               /*!< Serial Data Alignment                                                 */
7917       __IO uint32_t  SPDP       :  1;               /*!< Serial Padding Polarity                                               */
7918       __IO uint32_t  SWSP       :  1;               /*!< Serial WS Polarity                                                    */
7919       __IO uint32_t  SCKP       :  1;               /*!< Serial Bit Clock Polarity                                             */
7920       __IO uint32_t  SWSD       :  1;               /*!< Serial WS DirectionNOTE: Only the following settings are allowed:
7921                                                          (SCKD, SWSD) = (0, 0) and (1, 1). Other settings are prohibited.      */
7922       __IO uint32_t  SCKD       :  1;               /*!< Serial Bit Clock DirectionNOTE: Only the following settings
7923                                                          are allowed: (SCKD, SWSD) = (0, 0) and (1, 1). Other settings
7924                                                           are prohibited.                                                      */
7925       __IO uint32_t  SWL        :  3;               /*!< System Word LengthSet the system word length to the bit clock
7926                                                          frequency/2 fs.                                                       */
7927       __IO uint32_t  DWL        :  3;               /*!< Data Word Length                                                      */
7928       __IO uint32_t  CHNL       :  2;               /*!< Channels                                                              */
7929            uint32_t             :  1;
7930       __IO uint32_t  IIEN       :  1;               /*!< Idle Mode Interrupt Enable                                            */
7931       __IO uint32_t  ROIEN      :  1;               /*!< Receive Overflow Interrupt Enable                                     */
7932       __IO uint32_t  RUIEN      :  1;               /*!< Receive Underflow Interrupt Enable                                    */
7933       __IO uint32_t  TOIEN      :  1;               /*!< Transmit Overflow Interrupt Enable                                    */
7934       __IO uint32_t  TUIEN      :  1;               /*!< Transmit Underflow Interrupt Enable                                   */
7935       __IO uint32_t  CKS        :  1;               /*!< Oversampling Clock Select                                             */
7936     } SSICR_b;                                      /*!< BitSize                                                               */
7937   };
7938 
7939   union {
7940     __IO uint32_t  SSISR;                           /*!< Status Register                                                       */
7941 
7942     struct {
7943       __I  uint32_t  IDST       :  1;               /*!< Idle Mode Status Flag                                                 */
7944       __I  uint32_t  RSWNO      :  1;               /*!< Receive Serial Word Number                                            */
7945       __I  uint32_t  RCHNO      :  2;               /*!< Receive Channel Number.These bits are read as 00b.                    */
7946       __I  uint32_t  TSWNO      :  1;               /*!< Transmit Serial Word Number                                           */
7947       __I  uint32_t  TCHNO      :  2;               /*!< Transmit Channel Number                                               */
7948            uint32_t             : 18;
7949       __I  uint32_t  IIRQ       :  1;               /*!< Idle Mode Interrupt Status Flag                                       */
7950       __IO uint32_t  ROIRQ      :  1;               /*!< Receive Overflow Error Interrupt Status FlagNOTE: This bit can
7951                                                          be set to 0 by writing 0 after reading it as 1.                       */
7952       __IO uint32_t  RUIRQ      :  1;               /*!< Receive Underflow Error Interrupt Status FlagNOTE: This bit
7953                                                          can be set to 0 by writing 0 after reading it as 1.                   */
7954       __IO uint32_t  TOIRQ      :  1;               /*!< Transmit Overflow Error Interrupt Status FlagNOTE: This bit
7955                                                          can be set to 0 by writing 0 after reading it as 1.                   */
7956       __IO uint32_t  TUIRQ      :  1;               /*!< Transmit Underflow Error Interrupt Status FlagNOTE: This bit
7957                                                          can be set to 0 by writing 0 after reading it as 1.                   */
7958     } SSISR_b;                                      /*!< BitSize                                                               */
7959   };
7960   __I  uint32_t  RESERVED[2];
7961 
7962   union {
7963     __IO uint32_t  SSIFCR;                          /*!< FIFO Control Register                                                 */
7964 
7965     struct {
7966       __IO uint32_t  RFRST      :  1;               /*!< Receive FIFO Data Register Reset                                      */
7967       __IO uint32_t  TFRST      :  1;               /*!< Transmit FIFO Data Register Reset                                     */
7968       __IO uint32_t  RIE        :  1;               /*!< Receive Interrupt EnableNOTE: RXI can be cleared by clearing
7969                                                          either the RDF flag (see the description of the RDF bit for
7970                                                           details) or RIE bit.                                                 */
7971       __IO uint32_t  TIE        :  1;               /*!< Transmit Interrupt EnableNOTE: TXI can be cleared by clearing
7972                                                          either the TDE flag (see the description of the TDE bit for
7973                                                           details) or TIE bit.                                                 */
7974       __IO uint32_t  RTRG       :  2;               /*!< Receive Data Trigger Number                                           */
7975       __IO uint32_t  TTRG       :  2;               /*!< Transmit Data Trigger NumberNOTE: The values in parenthesis
7976                                                          are the number of empty stages in SSIFTDR at which the TDE flag
7977                                                           is set.                                                              */
7978            uint32_t             :  8;
7979       __IO uint32_t  SSIRST     :  1;               /*!< SSI soft ware reset                                                   */
7980            uint32_t             : 14;
7981       __IO uint32_t  AUCKE      :  1;               /*!< Oversampling Clock Enable                                             */
7982     } SSIFCR_b;                                     /*!< BitSize                                                               */
7983   };
7984 
7985   union {
7986     __IO uint32_t  SSIFSR;                          /*!< FIFO Status Register                                                  */
7987 
7988     struct {
7989       __IO uint32_t  RDF        :  1;               /*!< Receive Data Full FlagNOTE: Since the SSIFRDR register is a
7990                                                          32-byte FIFO register, the maximum number of data bytes that
7991                                                           can be read from it while the RDF flag is 1 is indicated in
7992                                                           the RDC[3:0] flags. If reading data from the SSIFRDR register
7993                                                           is continued after all the data is read, undefined values will
7994                                                           be read.                                                             */
7995            uint32_t             :  7;
7996       __I  uint32_t  RDC        :  4;               /*!< Receive Data Indicate Flag(Indicates the number of data units
7997                                                          stored in SSIFRDR)                                                    */
7998            uint32_t             :  4;
7999       __IO uint32_t  TDE        :  1;               /*!< Transmit Data Empty FlagNOTE: Since the SSIFTDR register is
8000                                                          a 32-byte FIFO register, the maximum number of bytes that can
8001                                                           be written to it while the TDE flag is 1 is 8 - TDC[3:0]. If
8002                                                           writing data to the SSIFTDR register is continued after all
8003                                                           the data is written, writing will be invalid and an overflow
8004                                                           occurs.                                                              */
8005            uint32_t             :  7;
8006       __I  uint32_t  TDC        :  4;               /*!< Transmit Data Indicate Flag(Indicates the number of data units
8007                                                          stored in SSIFTDR)                                                    */
8008     } SSIFSR_b;                                     /*!< BitSize                                                               */
8009   };
8010 
8011   union {
8012     __O  uint32_t  SSIFTDR;                         /*!< Transmit FIFO Data Register                                           */
8013 
8014     struct {
8015       __O  uint32_t  SSIFTDR    : 32;               /*!< SSIFTDR is a write-only FIFO register consisting of eight stages
8016                                                          of 32-bit registers for storing data to be serially transmitted.
8017                                                           NOTE: that when the SSIFTDR register is full of data (32 bytes),
8018                                                           the next data cannot be written to it. If writing is attempted,
8019                                                           it will be ignored and an overflow occurs.                           */
8020     } SSIFTDR_b;                                    /*!< BitSize                                                               */
8021   };
8022 
8023   union {
8024     __I  uint32_t  SSIFRDR;                         /*!< Receive FIFO Data Register                                            */
8025 
8026     struct {
8027       __I  uint32_t  SSIFRDR    : 32;               /*!< SSIFRDR is a read-only FIFO register consisting of eight stages
8028                                                          of 32-bit registers for storing serially received data.               */
8029     } SSIFRDR_b;                                    /*!< BitSize                                                               */
8030   };
8031 
8032   union {
8033     __IO uint32_t  SSITDMR;                         /*!< TDM Mode Register                                                     */
8034 
8035     struct {
8036            uint32_t             :  8;
8037       __IO uint32_t  CONT       :  1;               /*!< WS Continue Mode                                                      */
8038     } SSITDMR_b;                                    /*!< BitSize                                                               */
8039   };
8040 } R_SSI0_Type;
8041 
8042 /* ================================================================================ */
8043 /* ================                     R_CAN0                     ================ */
8044 /* ================================================================================ */
8045 
8046 
8047 /**
8048   * @brief Controller Area Network 0 Module (R_CAN0)
8049   */
8050 
8051 typedef struct {                                    /*!< R_CAN0 Structure                                                      */
8052   __I  uint32_t  RESERVED[128];
8053   R_CAN0_MBn_Type MBn[32];                          /*!< Mailbox %s                                                            */
8054 
8055   union {
8056     __IO uint32_t  MKRn[8];                         /*!< Mask Register %s                                                      */
8057 
8058     struct {
8059       __IO uint32_t  EID        : 18;               /*!< Extended ID                                                           */
8060       __IO uint32_t  SID        : 11;               /*!< Standard ID                                                           */
8061     } MKRn_b[8];                                    /*!< BitSize                                                               */
8062   };
8063 
8064   union {
8065     __IO uint32_t  FIDCRn[2];                       /*!< FIFO Received ID Compare Registers %s                                 */
8066 
8067     struct {
8068       __IO uint32_t  EID        : 18;               /*!< Extended ID                                                           */
8069       __IO uint32_t  SID        : 11;               /*!< Standard ID                                                           */
8070            uint32_t             :  1;
8071       __IO uint32_t  RTR        :  1;               /*!< Remote Transmission Request                                           */
8072       __IO uint32_t  IDE        :  1;               /*!< ID Extension                                                          */
8073     } FIDCRn_b[2];                                  /*!< BitSize                                                               */
8074   };
8075 
8076   union {
8077     __IO uint32_t  MKIVLR;                          /*!< Mask Invalid Register                                                 */
8078 
8079     struct {
8080       __IO uint32_t  MB0        :  1;               /*!< mailbox 0 Mask Invalid                                                */
8081       __IO uint32_t  MB1        :  1;               /*!< mailbox 1 Mask Invalid                                                */
8082       __IO uint32_t  MB2        :  1;               /*!< mailbox 2 Mask Invalid                                                */
8083       __IO uint32_t  MB3        :  1;               /*!< mailbox 3 Mask Invalid                                                */
8084       __IO uint32_t  MB4        :  1;               /*!< mailbox 4 Mask Invalid                                                */
8085       __IO uint32_t  MB5        :  1;               /*!< mailbox 5 Mask Invalid                                                */
8086       __IO uint32_t  MB6        :  1;               /*!< mailbox 6 Mask Invalid                                                */
8087       __IO uint32_t  MB7        :  1;               /*!< mailbox 7 Mask Invalid                                                */
8088       __IO uint32_t  MB8        :  1;               /*!< mailbox 8 Mask Invalid                                                */
8089       __IO uint32_t  MB9        :  1;               /*!< mailbox 9 Mask Invalid                                                */
8090       __IO uint32_t  MB10       :  1;               /*!< mailbox 10 Mask Invalid                                               */
8091       __IO uint32_t  MB11       :  1;               /*!< mailbox 11 Mask Invalid                                               */
8092       __IO uint32_t  MB12       :  1;               /*!< mailbox 12 Mask Invalid                                               */
8093       __IO uint32_t  MB13       :  1;               /*!< mailbox 13 Mask Invalid                                               */
8094       __IO uint32_t  MB14       :  1;               /*!< mailbox 14 Mask Invalid                                               */
8095       __IO uint32_t  MB15       :  1;               /*!< mailbox 15 Mask Invalid                                               */
8096       __IO uint32_t  MB16       :  1;               /*!< mailbox 16 Mask Invalid                                               */
8097       __IO uint32_t  MB17       :  1;               /*!< mailbox 17 Mask Invalid                                               */
8098       __IO uint32_t  MB18       :  1;               /*!< mailbox 18 Mask Invalid                                               */
8099       __IO uint32_t  MB19       :  1;               /*!< mailbox 19 Mask Invalid                                               */
8100       __IO uint32_t  MB20       :  1;               /*!< mailbox 20 Mask Invalid                                               */
8101       __IO uint32_t  MB21       :  1;               /*!< mailbox 21 Mask Invalid                                               */
8102       __IO uint32_t  MB22       :  1;               /*!< mailbox 22 Mask Invalid                                               */
8103       __IO uint32_t  MB23       :  1;               /*!< mailbox 23 Mask Invalid                                               */
8104       __IO uint32_t  MB24       :  1;               /*!< mailbox 24 Mask Invalid                                               */
8105       __IO uint32_t  MB25       :  1;               /*!< mailbox 25 Mask Invalid                                               */
8106       __IO uint32_t  MB26       :  1;               /*!< mailbox 26 Mask Invalid                                               */
8107       __IO uint32_t  MB27       :  1;               /*!< mailbox 27 Mask Invalid                                               */
8108       __IO uint32_t  MB28       :  1;               /*!< mailbox 28 Mask Invalid                                               */
8109       __IO uint32_t  MB29       :  1;               /*!< mailbox 29 Mask Invalid                                               */
8110       __IO uint32_t  MB30       :  1;               /*!< mailbox 30 Mask Invalid                                               */
8111       __IO uint32_t  MB31       :  1;               /*!< mailbox 31 Mask Invalid                                               */
8112     } MKIVLR_b;                                     /*!< BitSize                                                               */
8113   };
8114 
8115   union {
8116     union {
8117       __IO uint32_t  MIER_FIFO;                     /*!< Mailbox Interrupt Enable Register (FIFO mailbox mode)                 */
8118 
8119       struct {
8120         __IO uint32_t  MB0      :  1;               /*!< mailbox 0 Interrupt Enable                                            */
8121         __IO uint32_t  MB1      :  1;               /*!< mailbox 1 Interrupt Enable                                            */
8122         __IO uint32_t  MB2      :  1;               /*!< mailbox 2 Interrupt Enable                                            */
8123         __IO uint32_t  MB3      :  1;               /*!< mailbox 3 Interrupt Enable                                            */
8124         __IO uint32_t  MB4      :  1;               /*!< mailbox 4 Interrupt Enable                                            */
8125         __IO uint32_t  MB5      :  1;               /*!< mailbox 5 Interrupt Enable                                            */
8126         __IO uint32_t  MB6      :  1;               /*!< mailbox 6 Interrupt Enable                                            */
8127         __IO uint32_t  MB7      :  1;               /*!< mailbox 7 Interrupt Enable                                            */
8128         __IO uint32_t  MB8      :  1;               /*!< mailbox 8 Interrupt Enable                                            */
8129         __IO uint32_t  MB9      :  1;               /*!< mailbox 9 Interrupt Enable                                            */
8130         __IO uint32_t  MB10     :  1;               /*!< mailbox 10 Interrupt Enable                                           */
8131         __IO uint32_t  MB11     :  1;               /*!< mailbox 11 Interrupt Enable                                           */
8132         __IO uint32_t  MB12     :  1;               /*!< mailbox 12 Interrupt Enable                                           */
8133         __IO uint32_t  MB13     :  1;               /*!< mailbox 13 Interrupt Enable                                           */
8134         __IO uint32_t  MB14     :  1;               /*!< mailbox 14 Interrupt Enable                                           */
8135         __IO uint32_t  MB15     :  1;               /*!< mailbox 15 Interrupt Enable                                           */
8136         __IO uint32_t  MB16     :  1;               /*!< mailbox 16 Interrupt Enable                                           */
8137         __IO uint32_t  MB17     :  1;               /*!< mailbox 17 Interrupt Enable                                           */
8138         __IO uint32_t  MB18     :  1;               /*!< mailbox 18 Interrupt Enable                                           */
8139         __IO uint32_t  MB19     :  1;               /*!< mailbox 19 Interrupt Enable                                           */
8140         __IO uint32_t  MB20     :  1;               /*!< mailbox 20 Interrupt Enable                                           */
8141         __IO uint32_t  MB21     :  1;               /*!< mailbox 21 Interrupt Enable                                           */
8142         __IO uint32_t  MB22     :  1;               /*!< mailbox 22 Interrupt Enable                                           */
8143         __IO uint32_t  MB23     :  1;               /*!< mailbox 23 Interrupt Enable                                           */
8144         __IO uint32_t  MB24     :  1;               /*!< Transmit FIFO Interrupt Enable                                        */
8145         __IO uint32_t  MB25     :  1;               /*!< Transmit FIFO Interrupt Generation Timing Control                     */
8146              uint32_t           :  2;
8147         __IO uint32_t  MB28     :  1;               /*!< Receive FIFO Interrupt Enable                                         */
8148         __IO uint32_t  MB29     :  1;               /*!< Receive FIFO Interrupt Generation Timing Control                      */
8149       } MIER_FIFO_b;                                /*!< BitSize                                                               */
8150     };
8151 
8152     union {
8153       __IO uint32_t  MIER;                          /*!< Mailbox Interrupt Enable Register (Normal mailbox mode)               */
8154 
8155       struct {
8156         __IO uint32_t  MB0      :  1;               /*!< mailbox 0 Interrupt Enable                                            */
8157         __IO uint32_t  MB1      :  1;               /*!< mailbox 1 Interrupt Enable                                            */
8158         __IO uint32_t  MB2      :  1;               /*!< mailbox 2 Interrupt Enable                                            */
8159         __IO uint32_t  MB3      :  1;               /*!< mailbox 3 Interrupt Enable                                            */
8160         __IO uint32_t  MB4      :  1;               /*!< mailbox 4 Interrupt Enable                                            */
8161         __IO uint32_t  MB5      :  1;               /*!< mailbox 5 Interrupt Enable                                            */
8162         __IO uint32_t  MB6      :  1;               /*!< mailbox 6 Interrupt Enable                                            */
8163         __IO uint32_t  MB7      :  1;               /*!< mailbox 7 Interrupt Enable                                            */
8164         __IO uint32_t  MB8      :  1;               /*!< mailbox 8 Interrupt Enable                                            */
8165         __IO uint32_t  MB9      :  1;               /*!< mailbox 9 Interrupt Enable                                            */
8166         __IO uint32_t  MB10     :  1;               /*!< mailbox 10 Interrupt Enable                                           */
8167         __IO uint32_t  MB11     :  1;               /*!< mailbox 11 Interrupt Enable                                           */
8168         __IO uint32_t  MB12     :  1;               /*!< mailbox 12 Interrupt Enable                                           */
8169         __IO uint32_t  MB13     :  1;               /*!< mailbox 13 Interrupt Enable                                           */
8170         __IO uint32_t  MB14     :  1;               /*!< mailbox 14 Interrupt Enable                                           */
8171         __IO uint32_t  MB15     :  1;               /*!< mailbox 15 Interrupt Enable                                           */
8172         __IO uint32_t  MB16     :  1;               /*!< mailbox 16 Interrupt Enable                                           */
8173         __IO uint32_t  MB17     :  1;               /*!< mailbox 17 Interrupt Enable                                           */
8174         __IO uint32_t  MB18     :  1;               /*!< mailbox 18 Interrupt Enable                                           */
8175         __IO uint32_t  MB19     :  1;               /*!< mailbox 19 Interrupt Enable                                           */
8176         __IO uint32_t  MB20     :  1;               /*!< mailbox 20 Interrupt Enable                                           */
8177         __IO uint32_t  MB21     :  1;               /*!< mailbox 21 Interrupt Enable                                           */
8178         __IO uint32_t  MB22     :  1;               /*!< mailbox 22 Interrupt Enable                                           */
8179         __IO uint32_t  MB23     :  1;               /*!< mailbox 23 Interrupt Enable                                           */
8180         __IO uint32_t  MB24     :  1;               /*!< mailbox 24 Interrupt Enable                                           */
8181         __IO uint32_t  MB25     :  1;               /*!< mailbox 25 Interrupt Enable                                           */
8182         __IO uint32_t  MB26     :  1;               /*!< mailbox 26 Interrupt Enable                                           */
8183         __IO uint32_t  MB27     :  1;               /*!< mailbox 27 Interrupt Enable                                           */
8184         __IO uint32_t  MB28     :  1;               /*!< mailbox 28 Interrupt Enable                                           */
8185         __IO uint32_t  MB29     :  1;               /*!< mailbox 29 Interrupt Enable                                           */
8186         __IO uint32_t  MB30     :  1;               /*!< mailbox 30 Interrupt Enable                                           */
8187         __IO uint32_t  MB31     :  1;               /*!< mailbox 31 Interrupt Enable                                           */
8188       } MIER_b;                                     /*!< BitSize                                                               */
8189     };
8190   };
8191   __I  uint32_t  RESERVED1[252];
8192 
8193   union {
8194     union {
8195       __IO uint8_t   MCTLn_RX[32];                  /*!< Message Control Register( Receive mode (when the TRMREQ bit
8196                                                          is 0 and the RECREQ bit is 1))                                        */
8197 
8198       struct {
8199         __IO uint8_t   NEWDATA  :  1;               /*!< Reception Complete Flag                                               */
8200         __I  uint8_t   INVALDATA:  1;               /*!< Reception-in-Progress Status Flag (Receive mailbox setting enabled)   */
8201         __IO uint8_t   MSGLOST  :  1;               /*!< Message Lost Flag(Receive mailbox setting enabled)                    */
8202              uint8_t            :  1;
8203         __IO uint8_t   ONESHOT  :  1;               /*!< One-Shot Enable                                                       */
8204              uint8_t            :  1;
8205         __IO uint8_t   RECREQ   :  1;               /*!< Receive Mailbox Request                                               */
8206         __IO uint8_t   TRMREQ   :  1;               /*!< Transmit Mailbox Request                                              */
8207       } MCTLn_RX_b[32];                             /*!< BitSize                                                               */
8208     };
8209 
8210     union {
8211       __IO uint8_t   MCTLn_TX[32];                  /*!< Message Control Register(Transmit mode (when the TRMREQ bit
8212                                                          is 1 and the RECREQ bit is 0))                                        */
8213 
8214       struct {
8215         __IO uint8_t   SENTDATA :  1;               /*!< Transmission Complete Flag                                            */
8216         __I  uint8_t   TRMACTIVE:  1;               /*!< Transmission-in-Progress Status Flag(Transmit mailbox setting
8217                                                          enabled)                                                              */
8218         __IO uint8_t   TRMABT   :  1;               /*!< Transmission Abort Complete Flag(Transmit mailbox setting enabled)    */
8219              uint8_t            :  1;
8220         __IO uint8_t   ONESHOT  :  1;               /*!< One-Shot Enable                                                       */
8221              uint8_t            :  1;
8222         __IO uint8_t   RECREQ   :  1;               /*!< Receive Mailbox Request                                               */
8223         __IO uint8_t   TRMREQ   :  1;               /*!< Transmit Mailbox Request                                              */
8224       } MCTLn_TX_b[32];                             /*!< BitSize                                                               */
8225     };
8226   };
8227 
8228   union {
8229     __IO uint16_t  CTLR;                            /*!< Control Register                                                      */
8230 
8231     struct {
8232       __IO uint16_t  MBM        :  1;               /*!< CAN Mailbox Mode Select                                               */
8233       __IO uint16_t  IDFM       :  2;               /*!< ID Format Mode Select                                                 */
8234       __IO uint16_t  MLM        :  1;               /*!< Message Lost Mode Select                                              */
8235       __IO uint16_t  TPM        :  1;               /*!< Transmission Priority Mode Select                                     */
8236       __IO uint16_t  TSRC       :  1;               /*!< Time Stamp Counter Reset Command                                      */
8237       __IO uint16_t  TSPS       :  2;               /*!< Time Stamp Prescaler Select                                           */
8238       __IO uint16_t  CANM       :  2;               /*!< CAN Operating Mode Select                                             */
8239       __IO uint16_t  SLPM       :  1;               /*!< CAN Sleep Mode                                                        */
8240       __IO uint16_t  BOM        :  2;               /*!< Bus-Off Recovery Mode by a program request                            */
8241       __IO uint16_t  RBOC       :  1;               /*!< Forcible Return From Bus-Off                                          */
8242     } CTLR_b;                                       /*!< BitSize                                                               */
8243   };
8244 
8245   union {
8246     __I  uint16_t  STR;                             /*!< Status Register                                                       */
8247 
8248     struct {
8249       __I  uint16_t  NDST       :  1;               /*!< NEWDATA Status Flag                                                   */
8250       __I  uint16_t  SDST       :  1;               /*!< SENTDATA Status Flag                                                  */
8251       __I  uint16_t  RFST       :  1;               /*!< Receive FIFO Status Flag                                              */
8252       __I  uint16_t  TFST       :  1;               /*!< Transmit FIFO Status Flag                                             */
8253       __I  uint16_t  NMLST      :  1;               /*!< Normal Mailbox Message Lost Status Flag                               */
8254       __I  uint16_t  FMLST      :  1;               /*!< FIFO Mailbox Message Lost Status Flag                                 */
8255       __I  uint16_t  TABST      :  1;               /*!< Transmission Abort Status Flag                                        */
8256       __I  uint16_t  EST        :  1;               /*!< Error Status Flag                                                     */
8257       __I  uint16_t  RSTST      :  1;               /*!< CAN Reset Status Flag                                                 */
8258       __I  uint16_t  HLTST      :  1;               /*!< CAN Halt Status Flag                                                  */
8259       __I  uint16_t  SLPST      :  1;               /*!< CAN Sleep Status Flag                                                 */
8260       __I  uint16_t  EPST       :  1;               /*!< Error-Passive Status Flag                                             */
8261       __I  uint16_t  BOST       :  1;               /*!< Bus-Off Status Flag                                                   */
8262       __I  uint16_t  TRMST      :  1;               /*!< Transmit Status Flag (transmitter)                                    */
8263       __I  uint16_t  RECST      :  1;               /*!< Receive Status Flag (receiver)                                        */
8264     } STR_b;                                        /*!< BitSize                                                               */
8265   };
8266 
8267   union {
8268     __IO uint32_t  BCR;                             /*!< Bit Configuration Register                                            */
8269 
8270     struct {
8271       __IO uint32_t  CCLKS      :  1;               /*!< CAN Clock Source Selection                                            */
8272            uint32_t             :  7;
8273       __IO uint32_t  TSEG2      :  3;               /*!< Time Segment 2 Control                                                */
8274            uint32_t             :  1;
8275       __IO uint32_t  SJW        :  2;               /*!< Resynchronization Jump Width Control                                  */
8276            uint32_t             :  2;
8277       __IO uint32_t  BRP        : 10;               /*!< Prescaler Division Ratio Select . These bits set the frequency
8278                                                          of the CAN communication clock (fCANCLK).                             */
8279            uint32_t             :  2;
8280       __IO uint32_t  TSEG1      :  4;               /*!< Time Segment 1 Control                                                */
8281     } BCR_b;                                        /*!< BitSize                                                               */
8282   };
8283 
8284   union {
8285     __IO uint8_t   RFCR;                            /*!< Receive FIFO Control Register                                         */
8286 
8287     struct {
8288       __IO uint8_t   RFE        :  1;               /*!< Receive FIFO Enable                                                   */
8289       __I  uint8_t   RFUST      :  3;               /*!< Receive FIFO Unread Message Number Status                             */
8290       __IO uint8_t   RFMLF      :  1;               /*!< Receive FIFO Message Lost Flag                                        */
8291       __I  uint8_t   RFFST      :  1;               /*!< Receive FIFO Full Status Flag                                         */
8292       __I  uint8_t   RFWST      :  1;               /*!< Receive FIFO Buffer Warning Status Flag                               */
8293       __I  uint8_t   RFEST      :  1;               /*!< Receive FIFO Empty Status Flag                                        */
8294     } RFCR_b;                                       /*!< BitSize                                                               */
8295   };
8296 
8297   union {
8298     __O  uint8_t   RFPCR;                           /*!< Receive FIFO Pointer Control Register                                 */
8299 
8300     struct {
8301       __O  uint8_t   RFPCR      :  8;               /*!< The CPU-side pointer for the receive FIFO is incremented by
8302                                                          writing FFh to RFPCR.                                                 */
8303     } RFPCR_b;                                      /*!< BitSize                                                               */
8304   };
8305 
8306   union {
8307     __IO uint8_t   TFCR;                            /*!< Transmit FIFO Control Register                                        */
8308 
8309     struct {
8310       __IO uint8_t   TFE        :  1;               /*!< Transmit FIFO Enable                                                  */
8311       __I  uint8_t   TFUST      :  3;               /*!< Transmit FIFO Unsent Message Number Status                            */
8312            uint8_t              :  2;
8313       __I  uint8_t   TFFST      :  1;               /*!< Transmit FIFO Full Status                                             */
8314       __I  uint8_t   TFEST      :  1;               /*!< Transmit FIFO Empty Status                                            */
8315     } TFCR_b;                                       /*!< BitSize                                                               */
8316   };
8317 
8318   union {
8319     __O  uint8_t   TFPCR;                           /*!< Transmit FIFO Pointer Control Register                                */
8320 
8321     struct {
8322       __O  uint8_t   TFPCR      :  8;               /*!< The CPU-side pointer for the transmit FIFO is incremented by
8323                                                          writing FFh to TFPCR.                                                 */
8324     } TFPCR_b;                                      /*!< BitSize                                                               */
8325   };
8326 
8327   union {
8328     __IO uint8_t   EIER;                            /*!< Error Interrupt Enable Register                                       */
8329 
8330     struct {
8331       __IO uint8_t   BEIE       :  1;               /*!< Bus Error Interrupt Enable                                            */
8332       __IO uint8_t   EWIE       :  1;               /*!< Error-Warning Interrupt Enable                                        */
8333       __IO uint8_t   EPIE       :  1;               /*!< Error-Passive Interrupt Enable                                        */
8334       __IO uint8_t   BOEIE      :  1;               /*!< Bus-Off Entry Interrupt Enable                                        */
8335       __IO uint8_t   BORIE      :  1;               /*!< Bus-Off Recovery Interrupt Enable                                     */
8336       __IO uint8_t   ORIE       :  1;               /*!< Overrun Interrupt Enable                                              */
8337       __IO uint8_t   OLIE       :  1;               /*!< Overload Frame Transmit Interrupt Enable                              */
8338       __IO uint8_t   BLIE       :  1;               /*!< Bus Lock Interrupt Enable                                             */
8339     } EIER_b;                                       /*!< BitSize                                                               */
8340   };
8341 
8342   union {
8343     __IO uint8_t   EIFR;                            /*!< Error Interrupt Factor Judge Register                                 */
8344 
8345     struct {
8346       __IO uint8_t   BEIF       :  1;               /*!< Bus Error Detect Flag                                                 */
8347       __IO uint8_t   EWIF       :  1;               /*!< Error-Warning Detect Flag                                             */
8348       __IO uint8_t   EPIF       :  1;               /*!< Error-Passive Detect Flag                                             */
8349       __IO uint8_t   BOEIF      :  1;               /*!< Bus-Off Entry Detect Flag                                             */
8350       __IO uint8_t   BORIF      :  1;               /*!< Bus-Off Recovery Detect Flag                                          */
8351       __IO uint8_t   ORIF       :  1;               /*!< Receive Overrun Detect Flag                                           */
8352       __IO uint8_t   OLIF       :  1;               /*!< Overload Frame Transmission Detect Flag                               */
8353       __IO uint8_t   BLIF       :  1;               /*!< Bus Lock Detect Flag                                                  */
8354     } EIFR_b;                                       /*!< BitSize                                                               */
8355   };
8356 
8357   union {
8358     __I  uint8_t   RECR;                            /*!< Receive Error Count Register                                          */
8359 
8360     struct {
8361       __I  uint8_t   RECR       :  8;               /*!< Receive error count functionRECR increments or decrements the
8362                                                          counter value according to the error status of the CAN module
8363                                                           during reception.                                                    */
8364     } RECR_b;                                       /*!< BitSize                                                               */
8365   };
8366 
8367   union {
8368     __I  uint8_t   TECR;                            /*!< Transmit Error Count Register                                         */
8369 
8370     struct {
8371       __I  uint8_t   TECR       :  8;               /*!< Transmit error count functionTECR increments or decrements the
8372                                                          counter value according to the error status of the CAN module
8373                                                           during transmission.                                                 */
8374     } TECR_b;                                       /*!< BitSize                                                               */
8375   };
8376 
8377   union {
8378     __IO uint8_t   ECSR;                            /*!< Error Code Store Register                                             */
8379 
8380     struct {
8381       __IO uint8_t   SEF        :  1;               /*!< Stuff Error Flag                                                      */
8382       __IO uint8_t   FEF        :  1;               /*!< Form Error Flag                                                       */
8383       __IO uint8_t   AEF        :  1;               /*!< ACK Error Flag                                                        */
8384       __IO uint8_t   CEF        :  1;               /*!< CRC Error Flag                                                        */
8385       __IO uint8_t   BE1F       :  1;               /*!< Bit Error (recessive) Flag                                            */
8386       __IO uint8_t   BE0F       :  1;               /*!< Bit Error (dominant) Flag                                             */
8387       __IO uint8_t   ADEF       :  1;               /*!< ACK Delimiter Error Flag                                              */
8388       __IO uint8_t   EDPM       :  1;               /*!< Error Display Mode Select                                             */
8389     } ECSR_b;                                       /*!< BitSize                                                               */
8390   };
8391 
8392   union {
8393     __IO uint8_t   CSSR;                            /*!< Channel Search Support Register                                       */
8394 
8395     struct {
8396       __IO uint8_t   CSSR       :  8;               /*!< When the value for the channel search is input, the channel
8397                                                          number is output to MSSR.                                             */
8398     } CSSR_b;                                       /*!< BitSize                                                               */
8399   };
8400 
8401   union {
8402     __I  uint8_t   MSSR;                            /*!< Mailbox Search Status Register                                        */
8403 
8404     struct {
8405       __I  uint8_t   MBNST      :  5;               /*!< Search Result Mailbox Number Status These bits output the smallest
8406                                                          mailbox number that is searched in each mode of MSMR.                 */
8407            uint8_t              :  2;
8408       __I  uint8_t   SEST       :  1;               /*!< Search Result Status                                                  */
8409     } MSSR_b;                                       /*!< BitSize                                                               */
8410   };
8411 
8412   union {
8413     __IO uint8_t   MSMR;                            /*!< Mailbox Search Mode Register                                          */
8414 
8415     struct {
8416       __IO uint8_t   MBSM       :  2;               /*!< Mailbox Search Mode Select                                            */
8417     } MSMR_b;                                       /*!< BitSize                                                               */
8418   };
8419 
8420   union {
8421     __I  uint16_t  TSR;                             /*!< Time Stamp Register                                                   */
8422 
8423     struct {
8424       __I  uint16_t  TSR        : 16;               /*!< Free-running counter value for the time stamp function                */
8425     } TSR_b;                                        /*!< BitSize                                                               */
8426   };
8427 
8428   union {
8429     __IO uint16_t  AFSR;                            /*!< Acceptance Filter Support Register                                    */
8430 
8431     struct {
8432       __IO uint16_t  AFSR       : 16;               /*!< After the standard ID of a received message is written, the
8433                                                          value converted for data table search can be read.                    */
8434     } AFSR_b;                                       /*!< BitSize                                                               */
8435   };
8436 
8437   union {
8438     __IO uint8_t   TCR;                             /*!< Test Control Register                                                 */
8439 
8440     struct {
8441       __IO uint8_t   TSTE       :  1;               /*!< CAN Test Mode Enable                                                  */
8442       __IO uint8_t   TSTM       :  2;               /*!< CAN Test Mode Select                                                  */
8443     } TCR_b;                                        /*!< BitSize                                                               */
8444   };
8445 } R_CAN0_Type;
8446 
8447 
8448 /* ================================================================================ */
8449 /* ================                     R_IIC0                     ================ */
8450 /* ================================================================================ */
8451 
8452 /**
8453   * @brief Inter-Integrated Circuit 0 (R_IIC0)
8454   */
8455 
8456 typedef struct {                                    /*!< R_IIC0 Structure                                                      */
8457 
8458   union {
8459     __IO uint8_t   ICCR1;                           /*!< I2C Bus Control Register 1                                            */
8460 
8461     struct {
8462       __I  uint8_t   SDAI       :  1;               /*!< SDA Line Monitor                                                      */
8463       __I  uint8_t   SCLI       :  1;               /*!< SCL Line Monitor                                                      */
8464       __IO uint8_t   SDAO       :  1;               /*!< SDA Output Control/Monitor                                            */
8465       __IO uint8_t   SCLO       :  1;               /*!< SCL Output Control/Monitor                                            */
8466       __O  uint8_t   SOWP       :  1;               /*!< SCLO/SDAO Write Protect (This bit is read as 1.)                      */
8467       __IO uint8_t   CLO        :  1;               /*!< Extra SCL Clock Cycle Output                                          */
8468       __IO uint8_t   IICRST     :  1;               /*!< I2C Bus Interface Internal ResetNote:If an internal reset is
8469                                                          initiated using the IICRST bit for a bus hang-up occurred during
8470                                                           communication with the master device in slave mode, the states
8471                                                           may become different between the slave device and the master
8472                                                           device (due to the difference in the bit counter information).       */
8473       __IO uint8_t   ICE        :  1;               /*!< I2C Bus Interface Enable                                              */
8474     } ICCR1_b;                                      /*!< BitSize                                                               */
8475   };
8476 
8477   union {
8478     __IO uint8_t   ICCR2;                           /*!< I2C Bus Control Register 2                                            */
8479 
8480     struct {
8481            uint8_t              :  1;
8482       __IO uint8_t   ST         :  1;               /*!< Start Condition Issuance RequestSet the ST bit to 1 (start condition
8483                                                          issuance request) when the BBSY flag is set to 0 (bus free state).    */
8484       __IO uint8_t   RS         :  1;               /*!< Restart Condition Issuance RequestNote: Do not set the RS bit
8485                                                          to 1 while issuing a stop condition.                                  */
8486       __IO uint8_t   SP         :  1;               /*!< Stop Condition Issuance RequestNote: Writing to the SP bit is
8487                                                          not possible while the setting of the BBSY flag is 0 (bus free
8488                                                           state).Note: Do not set the SP bit to 1 while a restart condition
8489                                                           is being issued.                                                     */
8490            uint8_t              :  1;
8491       __IO uint8_t   TRS        :  1;               /*!< Transmit/Receive Mode                                                 */
8492       __IO uint8_t   MST        :  1;               /*!< Master/Slave Mode                                                     */
8493       __I  uint8_t   BBSY       :  1;               /*!< Bus Busy Detection Flag                                               */
8494     } ICCR2_b;                                      /*!< BitSize                                                               */
8495   };
8496 
8497   union {
8498     __IO uint8_t   ICMR1;                           /*!< I2C Bus Mode Register 1                                               */
8499 
8500     struct {
8501       __IO uint8_t   BC         :  3;               /*!< Bit Counter                                                           */
8502       __O  uint8_t   BCWP       :  1;               /*!< BC Write Protect(This bit is read as 1.)                              */
8503       __IO uint8_t   CKS        :  3;               /*!< Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB / 2^CKS
8504                                                          )                                                                     */
8505       __IO uint8_t   MTWP       :  1;               /*!< MST/TRS Write Protect                                                 */
8506     } ICMR1_b;                                      /*!< BitSize                                                               */
8507   };
8508 
8509   union {
8510     __IO uint8_t   ICMR2;                           /*!< I2C Bus Mode Register 2                                               */
8511 
8512     struct {
8513       __IO uint8_t   TMOS       :  1;               /*!< Timeout Detection Time Selection                                      */
8514       __IO uint8_t   TMOL       :  1;               /*!< Timeout L Count Control                                               */
8515       __IO uint8_t   TMOH       :  1;               /*!< Timeout H Count Control                                               */
8516            uint8_t              :  1;
8517       __IO uint8_t   SDDL       :  3;               /*!< SDA Output Delay Counter                                              */
8518       __IO uint8_t   DLCS       :  1;               /*!< SDA Output Delay Clock Source Selection                               */
8519     } ICMR2_b;                                      /*!< BitSize                                                               */
8520   };
8521 
8522   union {
8523     __IO uint8_t   ICMR3;                           /*!< I2C Bus Mode Register 3                                               */
8524 
8525     struct {
8526       __IO uint8_t   NF         :  2;               /*!< Noise Filter Stage Selection                                          */
8527       __I  uint8_t   ACKBR      :  1;               /*!< Receive Acknowledge                                                   */
8528       __IO uint8_t   ACKBT      :  1;               /*!< Transmit Acknowledge                                                  */
8529       __IO uint8_t   ACKWP      :  1;               /*!< ACKBT Write Protect                                                   */
8530       __IO uint8_t   RDRFS      :  1;               /*!< RDRF Flag Set Timing Selection                                        */
8531       __IO uint8_t   WAIT       :  1;               /*!< WAITNote: When the value of the WAIT bit is to be read, be sure
8532                                                          to read the ICDRR beforehand.                                         */
8533       __IO uint8_t   SMBE       :  1;               /*!< SMBus/I2C Bus Selection                                               */
8534     } ICMR3_b;                                      /*!< BitSize                                                               */
8535   };
8536 
8537   union {
8538     __IO uint8_t   ICFER;                           /*!< I2C Bus Function Enable Register                                      */
8539 
8540     struct {
8541       __IO uint8_t   TMOE       :  1;               /*!< Timeout Function Enable                                               */
8542       __IO uint8_t   MALE       :  1;               /*!< Master Arbitration-Lost Detection Enable                              */
8543       __IO uint8_t   NALE       :  1;               /*!< NACK Transmission Arbitration-Lost Detection Enable                   */
8544       __IO uint8_t   SALE       :  1;               /*!< Slave Arbitration-Lost Detection Enable                               */
8545       __IO uint8_t   NACKE      :  1;               /*!< NACK Reception Transfer Suspension Enable                             */
8546       __IO uint8_t   NFE        :  1;               /*!< Digital Noise Filter Circuit Enable                                   */
8547       __IO uint8_t   SCLE       :  1;               /*!< SCL Synchronous Circuit Enable                                        */
8548       __IO uint8_t   FMPE       :  1;               /*!< Fast-mode Plus Enable                                                 */
8549     } ICFER_b;                                      /*!< BitSize                                                               */
8550   };
8551 
8552   union {
8553     __IO uint8_t   ICSER;                           /*!< I2C Bus Status Enable Register                                        */
8554 
8555     struct {
8556       __IO uint8_t   SAR0       :  1;               /*!< Slave Address Register 0 Enable                                       */
8557       __IO uint8_t   SAR1       :  1;               /*!< Slave Address Register 1 Enable                                       */
8558       __IO uint8_t   SAR2       :  1;               /*!< Slave Address Register 2 Enable                                       */
8559       __IO uint8_t   GCE        :  1;               /*!< General Call Address Enable                                           */
8560            uint8_t              :  1;
8561       __IO uint8_t   DIDE       :  1;               /*!< Device-ID Address Detection Enable                                    */
8562            uint8_t              :  1;
8563       __IO uint8_t   HOAE       :  1;               /*!< Host Address Enable                                                   */
8564     } ICSER_b;                                      /*!< BitSize                                                               */
8565   };
8566 
8567   union {
8568     __IO uint8_t   ICIER;                           /*!< I2C Bus Interrupt Enable Register                                     */
8569 
8570     struct {
8571       __IO uint8_t   TMOIE      :  1;               /*!< Timeout Interrupt Request Enable                                      */
8572       __IO uint8_t   ALIE       :  1;               /*!< Arbitration-Lost Interrupt Request Enable                             */
8573       __IO uint8_t   STIE       :  1;               /*!< Start Condition Detection Interrupt Request Enable                    */
8574       __IO uint8_t   SPIE       :  1;               /*!< Stop Condition Detection Interrupt Request Enable                     */
8575       __IO uint8_t   NAKIE      :  1;               /*!< NACK Reception Interrupt Request Enable                               */
8576       __IO uint8_t   RIE        :  1;               /*!< Receive Data Full Interrupt Request Enable                            */
8577       __IO uint8_t   TEIE       :  1;               /*!< Transmit End Interrupt Request Enable                                 */
8578       __IO uint8_t   TIE        :  1;               /*!< Transmit Data Empty Interrupt Request Enable                          */
8579     } ICIER_b;                                      /*!< BitSize                                                               */
8580   };
8581 
8582   union {
8583     __IO uint8_t   ICSR1;                           /*!< I2C Bus Status Register 1                                             */
8584 
8585     struct {
8586       __IO uint8_t   AAS0   :  1;                   /*!< Slave Address 0 Detection Flag                                        */
8587       __IO uint8_t   AAS1   :  1;                   /*!< Slave Address 1 Detection Flag                                        */
8588       __IO uint8_t   AAS2   :  1;                   /*!< Slave Address 2 Detection Flag                                        */
8589       __IO uint8_t   ADZ    :  1;                   /*!< General Call Address Detection Flag                                   */
8590            uint8_t          :  1;
8591       __IO uint8_t   DID    :  1;                   /*!< Device-ID Address Detection Flag                                      */
8592            uint8_t          :  1;
8593       __IO uint8_t   HOA    :  1;                   /*!< Host Address Detection Flag                                           */
8594     } ICSR1_b;                                      /*!< BitSize                                                               */
8595   };
8596 
8597   union {
8598     __IO uint8_t   ICSR2;                           /*!< I2C Bus Status Register 2                                             */
8599 
8600     struct {
8601       __IO uint8_t   TMOF   :  1;                   /*!< Timeout Detection Flag                                                */
8602       __IO uint8_t   AL     :  1;                   /*!< Arbitration-Lost Flag                                                 */
8603       __IO uint8_t   START  :  1;                   /*!< Start Condition Detection Flag                                        */
8604       __IO uint8_t   STOP   :  1;                   /*!< Stop Condition Detection Flag                                         */
8605       __IO uint8_t   NACKF  :  1;                   /*!< NACK Detection Flag                                                   */
8606       __IO uint8_t   RDRF   :  1;                   /*!< Receive Data Full Flag                                                */
8607       __IO uint8_t   TEND   :  1;                   /*!< Transmit End Flag                                                     */
8608       __I  uint8_t   TDRE   :  1;                   /*!< Transmit Data Empty Flag                                              */
8609     } ICSR2_b;                                      /*!< BitSize                                                               */
8610   };
8611 
8612   R_IIC0_SARLnRC0_Type SARLnRC0[3];                 /*!< Slave Address Register L%s                                            */
8613 
8614   union {
8615     __IO uint8_t   ICBRL;                           /*!< I2C Bus Bit Rate Low-Level Register                                   */
8616 
8617     struct {
8618       __IO uint8_t   BRL        :  5;               /*!< Bit Rate Low-Level Period(Low-level period of SCL clock)              */
8619     } ICBRL_b;                                      /*!< BitSize                                                               */
8620   };
8621 
8622   union {
8623     __IO uint8_t   ICBRH;                           /*!< I2C Bus Bit Rate High-Level Register                                  */
8624 
8625     struct {
8626       __IO uint8_t   BRH        :  5;               /*!< Bit Rate High-Level Period(High-level period of SCL clock)            */
8627     } ICBRH_b;                                      /*!< BitSize                                                               */
8628   };
8629 
8630   union {
8631     __IO uint8_t   ICDRT;                           /*!< I2C Bus Transmit Data Register                                        */
8632 
8633     struct {
8634       __IO uint8_t   ICDRT      :  8;               /*!< 8-bit read-write register that stores transmit data.                  */
8635     } ICDRT_b;                                      /*!< BitSize                                                               */
8636   };
8637 
8638   union {
8639     __I  uint8_t   ICDRR;                           /*!< I2C Bus Receive Data Register                                         */
8640 
8641     struct {
8642       __I  uint8_t   ICDRR      :  8;               /*!< 8-bit register that stores the received data                          */
8643     } ICDRR_b;                                      /*!< BitSize                                                               */
8644   };
8645   __I  uint8_t  RESERVED1[2];   // Padding changed from uint16_t
8646 
8647   union {
8648     __IO uint8_t   ICWUR;                           /*!< I2C Bus Wake Up Unit Register                                         */
8649 
8650     struct {
8651       __IO uint8_t   WUAFA      :  1;               /*!< Wake-Up Analog Filter Additional Selection                            */
8652            uint8_t              :  2;
8653       __I  uint8_t   WUBFR      :  1;               /*!< Bus Free During Wake-Up Mode                                          */
8654       __IO uint8_t   WUACK      :  1;               /*!< Asynchronous/Synchronous Operation State Flag                         */
8655       __IO uint8_t   WUF        :  1;               /*!< Wake-Up Event Occurrence Flag                                         */
8656       __IO uint8_t   WUIE       :  1;               /*!< Wake Up Interrupt Request Enable                                      */
8657       __IO uint8_t   WUE        :  1;               /*!< Wake Up function Enable                                               */
8658     } ICWUR_b;                                      /*!< BitSize                                                               */
8659   };
8660 } R_IIC0_Type;
8661 
8662 /* ================================================================================ */
8663 /* ================                      R_DOC                     ================ */
8664 /* ================================================================================ */
8665 
8666 
8667 /**
8668   * @brief Data Operation Circuit (R_DOC)
8669   */
8670 
8671 typedef struct {                                    /*!< R_DOC Structure                                                       */
8672 
8673   union {
8674     __IO uint8_t   DOCR;                            /*!< DOC Control Register                                                  */
8675 
8676     struct {
8677       __IO uint8_t   OMS        :  2;               /*!< Operating Mode Select                                                 */
8678       __IO uint8_t   DCSEL      :  1;               /*!< Detection Condition Select Result of data comparison. Note:
8679                                                          Valid only when data comparison mode is selected.                     */
8680            uint8_t              :  2;
8681       __I  uint8_t   DOPCF      :  1;               /*!< Data Operation Circuit FlagIndicates the result of an operation.      */
8682       __IO uint8_t   DOPCFCL    :  1;               /*!< DOPCF Clear                                                           */
8683     } DOCR_b;                                       /*!< BitSize                                                               */
8684   };
8685   __I  uint8_t   RESERVED;
8686 
8687   union {
8688     __IO uint16_t  DODIR;                           /*!< DOC Data Input Register                                               */
8689 
8690     struct {
8691       __IO uint16_t  DODIR      : 16;               /*!< 16-bit read-write register in which 16-bit data for use in the
8692                                                          operations are stored.                                                */
8693     } DODIR_b;                                      /*!< BitSize                                                               */
8694   };
8695 
8696   union {
8697     __IO uint16_t  DODSR;                           /*!< DOC Data Setting Register                                             */
8698 
8699     struct {
8700       __IO uint16_t  DODSR      : 16;               /*!< This register stores 16-bit data for use as a reference in data
8701                                                          comparison mode. This register also stores the results of operations
8702                                                           in data addition and data subtraction modes.                         */
8703     } DODSR_b;                                      /*!< BitSize                                                               */
8704   };
8705 } R_DOC_Type;
8706 
8707 
8708 /* ================================================================================ */
8709 /* ================                    R_S16ADC                    ================ */
8710 /* ================================================================================ */
8711 
8712 
8713 /**
8714   * @brief 16bit A/D Converter (R_S16ADC)
8715   */
8716 
8717 typedef struct {                                    /*!< R_S16ADC Structure                                                    */
8718 
8719   union {
8720     __IO uint16_t  ADCSR;                           /*!< A/D Control Register                                                  */
8721 
8722     struct {
8723       __IO uint16_t  DBLANS     :  5;               /*!< Double Trigger Channel SelectThese bits select one analog input
8724                                                          channel for double triggered operation. The setting is only
8725                                                           effective while double trigger mode is selected.                     */
8726            uint16_t             :  1;
8727       __IO uint16_t  GBADIE     :  1;               /*!< Group B Scan End Interrupt Enable                                     */
8728       __IO uint16_t  DBLE       :  1;               /*!< Double Trigger Mode Select                                            */
8729       __IO uint16_t  EXTRG      :  1;               /*!< Trigger Select                                                        */
8730       __IO uint16_t  TRGE       :  1;               /*!< Trigger Start Enable                                                  */
8731            uint16_t             :  3;
8732       __IO uint16_t  ADCS       :  2;               /*!< Scan Mode Select                                                      */
8733       __IO uint16_t  ADST       :  1;               /*!< A/D Conversion Start                                                  */
8734     } ADCSR_b;                                      /*!< BitSize                                                               */
8735   };
8736   __I  uint16_t  RESERVED;
8737 
8738   union {
8739     __IO uint16_t  ADANSA0;                         /*!< A/D Channel Select Register A0                                        */
8740 
8741     struct {
8742       __IO uint16_t  ANSA00     :  1;               /*!< AN000 Select                                                          */
8743       __IO uint16_t  ANSA01     :  1;               /*!< AN001 Select                                                          */
8744       __IO uint16_t  ANSA02     :  1;               /*!< AN002 Select                                                          */
8745       __IO uint16_t  ANSA03     :  1;               /*!< AN003 Select                                                          */
8746       __IO uint16_t  ANSA04     :  1;               /*!< AN004 Select                                                          */
8747       __IO uint16_t  ANSA05     :  1;               /*!< AN005 Select                                                          */
8748       __IO uint16_t  ANSA06     :  1;               /*!< AN006 Select                                                          */
8749       __IO uint16_t  ANSA07     :  1;               /*!< AN007 Select                                                          */
8750       __IO uint16_t  ANSA08     :  1;               /*!< AN008 Select                                                          */
8751       __IO uint16_t  ANSA09     :  1;               /*!< AN009 Select                                                          */
8752       __IO uint16_t  ANSA010    :  1;               /*!< AN010 Select                                                          */
8753       __IO uint16_t  ANSA011    :  1;               /*!< AN011 Select                                                          */
8754       __IO uint16_t  ANSA012    :  1;               /*!< AN012 Select                                                          */
8755       __IO uint16_t  ANSA013    :  1;               /*!< AN013 Select                                                          */
8756       __IO uint16_t  ANSA014    :  1;               /*!< AN014 Select                                                          */
8757       __IO uint16_t  ANSA015    :  1;               /*!< AN015 Select                                                          */
8758     } ADANSA0_b;                                    /*!< BitSize                                                               */
8759   };
8760 
8761   union {
8762     __IO uint16_t  ADANSA1;                         /*!< A/D Channel Select Register A1                                        */
8763 
8764     struct {
8765       __IO uint16_t  ANSA16     :  1;               /*!< AN016 Select                                                          */
8766       __IO uint16_t  ANSA17     :  1;               /*!< AN017 Select                                                          */
8767       __IO uint16_t  ANSA18     :  1;               /*!< AN018 Select                                                          */
8768       __IO uint16_t  ANSA19     :  1;               /*!< AN019 Select                                                          */
8769       __IO uint16_t  ANSA20     :  1;               /*!< AN020 Select                                                          */
8770       __IO uint16_t  ANSA21     :  1;               /*!< AN021 Select                                                          */
8771       __IO uint16_t  ANSA22     :  1;               /*!< AN022 Select                                                          */
8772       __IO uint16_t  ANSA23     :  1;               /*!< AN023 Select                                                          */
8773       __IO uint16_t  ANSA24     :  1;               /*!< AN024 Select                                                          */
8774       __IO uint16_t  ANSA25     :  1;               /*!< AN025 Select                                                          */
8775       __IO uint16_t  ANSA26     :  1;               /*!< AN026 Select                                                          */
8776       __IO uint16_t  ANSA27     :  1;               /*!< AN027 Select                                                          */
8777     } ADANSA1_b;                                    /*!< BitSize                                                               */
8778   };
8779 
8780   union {
8781     __IO uint16_t  ADADS0;                          /*!< A/D-Converted Value Addition/Average Channel Select Register
8782                                                          0                                                                     */
8783 
8784     struct {
8785       __IO uint16_t  ADS00      :  1;               /*!< A/D-Converted Value Average Channel AN000 Select             */
8786       __IO uint16_t  ADS01      :  1;               /*!< A/D-Converted Value Average Channel AN001 Select             */
8787       __IO uint16_t  ADS02      :  1;               /*!< A/D-Converted Value Average Channel AN002 Select             */
8788       __IO uint16_t  ADS03      :  1;               /*!< A/D-Converted Value Average Channel AN003 Select             */
8789       __IO uint16_t  ADS04      :  1;               /*!< A/D-Converted Value Average Channel AN004 Select             */
8790       __IO uint16_t  ADS05      :  1;               /*!< A/D-Converted Value Average Channel AN005 Select             */
8791       __IO uint16_t  ADS06      :  1;               /*!< A/D-Converted Value Average Channel AN006 Select             */
8792       __IO uint16_t  ADS07      :  1;               /*!< A/D-Converted Value Average Channel AN007 Select             */
8793       __IO uint16_t  ADS08      :  1;               /*!< A/D-Converted Value Average Channel AN008 Select             */
8794       __IO uint16_t  ADS09      :  1;               /*!< A/D-Converted Value Average Channel AN009 Select             */
8795       __IO uint16_t  ADS10      :  1;               /*!< A/D-Converted Value Average Channel AN010 Select             */
8796       __IO uint16_t  ADS11      :  1;               /*!< A/D-Converted Value Average Channel AN011 Select             */
8797       __IO uint16_t  ADS12      :  1;               /*!< A/D-Converted Value Average Channel AN012 Select             */
8798       __IO uint16_t  ADS13      :  1;               /*!< A/D-Converted Value Average Channel AN013 Select             */
8799       __IO uint16_t  ADS14      :  1;               /*!< A/D-Converted Value Average Channel AN014 Select             */
8800       __IO uint16_t  ADS15      :  1;               /*!< A/D-Converted Value Average Channel AN015 Select             */
8801     } ADADS0_b;                                     /*!< BitSize                                                               */
8802   };
8803 
8804   union {
8805     __IO uint16_t  ADADS1;                          /*!< A/D-Converted Value Average Channel Select Register
8806                                                          1                                                                     */
8807 
8808     struct {
8809       __IO uint16_t  ADS16      :  1;               /*!< A/D-Converted Value Average Channel AN016 Select             */
8810       __IO uint16_t  ADS17      :  1;               /*!< A/D-Converted Value Average Channel AN017 Select             */
8811       __IO uint16_t  ADS18      :  1;               /*!< A/D-Converted Value Average Channel AN018 Select             */
8812       __IO uint16_t  ADS19      :  1;               /*!< A/D-Converted Value Average Channel AN019 Select             */
8813       __IO uint16_t  ADS20      :  1;               /*!< A/D-Converted Value Average Channel AN020 Select             */
8814       __IO uint16_t  ADS21      :  1;               /*!< A/D-Converted Value Average Channel AN021 Select             */
8815       __IO uint16_t  ADS22      :  1;               /*!< A/D-Converted Value Average Channel AN021 Select             */
8816       __IO uint16_t  ADS23      :  1;               /*!< A/D-Converted Value Average Channel AN021 Select             */
8817       __IO uint16_t  ADS24      :  1;               /*!< A/D-Converted Value Average Channel AN021 Select             */
8818       __IO uint16_t  ADS25      :  1;               /*!< A/D-Converted Value Average Channel AN021 Select             */
8819       __IO uint16_t  ADS26      :  1;               /*!< A/D-Converted Value Average Channel AN021 Select             */
8820       __IO uint16_t  ADS27      :  1;               /*!< A/D-Converted Value Average Channel AN021 Select             */
8821     } ADADS1_b;                                     /*!< BitSize                                                               */
8822   };
8823 
8824   union {
8825     __IO uint8_t   ADADC;                           /*!< A/D-Converted Value Average Count Select Register            */
8826 
8827     struct {
8828       __IO uint8_t   ADC        :  3;               /*!< Addition frequency selection bit.NOTE: AVEE bit is valid at
8829                                                          the only setting of ADC[2:0] bits = 001b or 011b. When average
8830                                                           mode is selected by setting the ADADC.AVEE bit to 1, do not
8831                                                           set the addition count to three times (ADADC.ADC[2:0] = 010b)        */
8832            uint8_t              :  5;
8833     } ADADC_b;                                      /*!< BitSize                                                               */
8834   };
8835   __I  uint8_t   RESERVED1;
8836 
8837   union {
8838     __IO uint16_t  ADCER;                           /*!< A/D Control Extended Register                                         */
8839 
8840     struct {
8841            uint16_t             :  5;
8842       __IO uint16_t  ACE        :  1;               /*!< A/D Data Register Automatic Clearing Enable                           */
8843            uint16_t             :  2;
8844       __IO uint16_t  DIAGVAL    :  2;               /*!< Self-Diagnosis Conversion Voltage Select                              */
8845       __IO uint16_t  DIAGLD     :  1;               /*!< Self-Diagnosis Mode Select                                            */
8846       __IO uint16_t  DIAGM      :  1;               /*!< Self-Diagnosis Enable                                                 */
8847            uint16_t             :  2;
8848       __IO uint16_t  ADINV      :  1;               /*!< Single-End Input A/D Converted Data Inversion Select                  */
8849            uint16_t             :  1;
8850     } ADCER_b;                                      /*!< BitSize                                                               */
8851   };
8852 
8853   union {
8854     __IO uint16_t  ADSTRGR;                         /*!< A/D Conversion Start Trigger Select Register                          */
8855 
8856     struct {
8857       __IO uint16_t  TRSB       :  6;               /*!< A/D Conversion Start Trigger Select for Group B Select the A/D
8858                                                          conversion start trigger for group B in group scan mode.              */
8859            uint16_t             :  2;
8860       __IO uint16_t  TRSA       :  6;               /*!< A/D Conversion Start Trigger Select Select the A/D conversion
8861                                                          start trigger in single scan mode and continuous mode. In group
8862                                                           scan mode, the A/D conversion start trigger for group A is selected. */
8863            uint16_t             :  2;
8864     } ADSTRGR_b;                                    /*!< BitSize                                                               */
8865   };
8866 
8867   union {
8868     __IO uint16_t  ADEXICR;                         /*!< A/D Conversion Extended Input Control Register                        */
8869 
8870     struct {
8871       __IO uint16_t  TSSAD      :  1;               /*!< Temperature Sensor Output A/D converted Value Average
8872                                                          Mode Select                                                           */
8873       __IO uint16_t  OCSAD      :  1;               /*!< Internal Reference Voltage A/D converted Value Average
8874                                                          Mode Select                                                           */
8875            uint16_t             :  6;
8876       __IO uint16_t  TSSA       :  1;               /*!< Temperature Sensor Output A/D Conversion Select                       */
8877       __IO uint16_t  OCSA       :  1;               /*!< Internal Reference Voltage A/D Conversion Select                      */
8878       __IO uint16_t  TSSB       :  1;               /*!< Temperature Sensor Output A/D Conversion Select for Group B           */
8879       __IO uint16_t  OCSB       :  1;               /*!< Internal Reference Voltage A/D Conversion Select for Group B          */
8880     } ADEXICR_b;                                    /*!< BitSize                                                               */
8881   };
8882 
8883   union {
8884     __IO uint16_t  ADANSB0;                         /*!< A/D Channel Select Register B0                                        */
8885 
8886     struct {
8887       __IO uint16_t  ANSB00     :  1;               /*!< AN000 Select                                                          */
8888       __IO uint16_t  ANSB01     :  1;               /*!< AN001 Select                                                          */
8889       __IO uint16_t  ANSB02     :  1;               /*!< AN002 Select                                                          */
8890       __IO uint16_t  ANSB03     :  1;               /*!< AN003 Select                                                          */
8891       __IO uint16_t  ANSB04     :  1;               /*!< AN004 Select                                                          */
8892       __IO uint16_t  ANSB05     :  1;               /*!< AN005 Select                                                          */
8893       __IO uint16_t  ANSB06     :  1;               /*!< AN006 Select                                                          */
8894       __IO uint16_t  ANSB07     :  1;               /*!< AN007 Select                                                          */
8895       __IO uint16_t  ANSB08     :  1;               /*!< AN008 Select                                                          */
8896       __IO uint16_t  ANSB09     :  1;               /*!< AN009 Select                                                          */
8897       __IO uint16_t  ANSB10     :  1;               /*!< AN010 Select                                                          */
8898       __IO uint16_t  ANSB11     :  1;               /*!< AN011 Select                                                          */
8899       __IO uint16_t  ANSB12     :  1;               /*!< AN012 Select                                                          */
8900       __IO uint16_t  ANSB13     :  1;               /*!< AN013 Select                                                          */
8901       __IO uint16_t  ANSB14     :  1;               /*!< AN014 Select                                                          */
8902       __IO uint16_t  ANSB15     :  1;               /*!< AN015 Select                                                          */
8903     } ADANSB0_b;                                    /*!< BitSize                                                               */
8904   };
8905 
8906   union {
8907     __IO uint16_t  ADANSB1;                         /*!< A/D Channel Select Register B1                                        */
8908 
8909     struct {
8910       __IO uint16_t  ANSB16     :  1;               /*!< AN016 Select                                                          */
8911       __IO uint16_t  ANSB17     :  1;               /*!< AN017 Select                                                          */
8912       __IO uint16_t  ANSB18     :  1;               /*!< AN018 Select                                                          */
8913       __IO uint16_t  ANSB19     :  1;               /*!< AN019 Select                                                          */
8914       __IO uint16_t  ANSB20     :  1;               /*!< AN020 Select                                                          */
8915       __IO uint16_t  ANSB21     :  1;               /*!< AN021 Select                                                          */
8916       __IO uint16_t  ANSB22     :  1;               /*!< AN021 Select                                                          */
8917       __IO uint16_t  ANSB23     :  1;               /*!< AN021 Select                                                          */
8918       __IO uint16_t  ANSB24     :  1;               /*!< AN021 Select                                                          */
8919       __IO uint16_t  ANSB25     :  1;               /*!< AN021 Select                                                          */
8920       __IO uint16_t  ANSB26     :  1;               /*!< AN021 Select                                                          */
8921       __IO uint16_t  ANSB27     :  1;               /*!< AN021 Select                                                          */
8922     } ADANSB1_b;                                    /*!< BitSize                                                               */
8923   };
8924 
8925   union {
8926     __I  uint16_t  ADDBLDR;                         /*!< A/D Data Duplication Register                                         */
8927 
8928     struct {
8929       __I  uint16_t  ADDBLDR    : 16;               /*!< This is a 16-bit read-only register for storing the result of
8930                                                          A/D conversion in response to the second trigger in double trigger
8931                                                           mode.                                                                */
8932     } ADDBLDR_b;                                    /*!< BitSize                                                               */
8933   };
8934 
8935   union {
8936     __I  uint16_t  ADTSDR;                          /*!< A/D Temperature Sensor Data Register                                  */
8937 
8938     struct {
8939       __I  uint16_t  ADTSDR     : 16;               /*!< This is a 16-bit read-only register for storing the A/D conversion
8940                                                          result of temperature sensor output.                                  */
8941     } ADTSDR_b;                                     /*!< BitSize                                                               */
8942   };
8943 
8944   union {
8945     __I  uint16_t  ADOCDR;                          /*!< A/D Internal Reference Voltage Data Register                          */
8946 
8947     struct {
8948       __I  uint16_t  ADOCDR     : 16;               /*!< This is a 16-bit read-only register for storing the A/D result
8949                                                          of internal reference voltage.                                        */
8950     } ADOCDR_b;                                     /*!< BitSize                                                               */
8951   };
8952 
8953   __I  uint16_t RESERVED16;
8954 
8955   union {
8956     __I  uint16_t  ADDRn[28];                       /*!< A/D Data Register %s                                                  */
8957 
8958     struct {
8959       __I  uint16_t  ADDR       : 16;               /*!< The ADDR register is a 16-bit read-only registers for storing
8960                                                          the result of A/D conversion.                                         */
8961     } ADDRn_b[28];                                  /*!< BitSize                                                               */
8962   };
8963   __I  uint16_t  RESERVED2[7];
8964 
8965   union {
8966     __IO uint16_t  ADSHCR;                          /*!< A/D Sample and Hold Circuit Control Register                          */
8967 
8968     struct {
8969       __IO uint16_t  SSTSH      :  8;               /*!< Channel-Dedicated Sample-and-Hold Circuit Sampling Time Setting
8970                                                          Set the sampling time (4 to 255 states)                               */
8971       __IO uint16_t  SHANS      :  3;               /*!< ANn0m sample-and-hold circuit Select                                  */
8972     } ADSHCR_b;                                     /*!< BitSize                                                               */
8973   };
8974   __I  uint16_t  RESERVED3[9];
8975 
8976   union {
8977     __IO uint8_t   ADDISCR;                         /*!< A/D Disconnection Detection Control Register                          */
8978 
8979     struct {
8980       __IO uint8_t   ADNDIS     :  4;               /*!< The charging time                                                     */
8981       __IO uint8_t   PCHG       :  2;               /*!< Precharge/Discharge select                                            */
8982            uint8_t              :  2;
8983     } ADDISCR_b;                                    /*!< BitSize                                                               */
8984   };
8985   __I  uint8_t   RESERVED4;
8986 
8987   union {
8988     __IO uint8_t   ADSHMSR;                         /*!< A/D Sample and Hold Operation Mode Select Register                    */
8989 
8990     struct {
8991       __IO uint8_t   SHMD       :  1;               /*!< Channel-Dedicated Sample-and-Hold Circuit Operation Mode Select       */
8992     } ADSHMSR_b;                                    /*!< BitSize                                                               */
8993   };
8994 
8995 
8996   union {
8997       __IO uint8_t   ADICR;                         /*!< A/D Interrupt Control Register                                        */
8998 
8999       struct{
9000       __IO uint8_t   ADIC       :  2;               /*!< A/D Interrupt Control                                                 */
9001            uint8_t              :  6;
9002       } ADICR_b;
9003   };
9004 
9005   union {
9006     __IO uint8_t   ADELCCR;                         /*!< A/D Event Link Control Register                                       */
9007 
9008     struct {
9009       __IO uint8_t   ELCC       :  2;               /*!< Event Link Control                                                    */
9010     } ADELCCR_b;                                    /*!< BitSize                                                               */
9011   };
9012   __I  uint8_t  RESERVED5;
9013 
9014   union {
9015     __IO uint16_t  ADGSPCR;                         /*!< A/D Group Scan Priority Control Register                              */
9016 
9017     struct {
9018       __IO uint16_t  PGS        :  1;               /*!< Group A priority control setting bit.Note: When the PGS bit
9019                                                          is to be set to 1, the ADCSR.ADCS[1:0] bits must be set to 01b
9020                                                           (group scan mode). If the bits are set to any other values,
9021                                                           proper operation is not guaranteed.                                  */
9022       __IO uint16_t  GBRSCN     :  1;               /*!< Group B Restart Setting(Enabled only when PGS = 1. Reserved
9023                                                          when PGS = 0.)                                                        */
9024            uint16_t             : 13;
9025       __IO uint16_t  GBRP       :  1;               /*!< Group B Single Scan Continuous Start(Enabled only when PGS =
9026                                                          1. Reserved when PGS = 0.)Note: When the GBRP bit has been set
9027                                                           to 1, single scan is performed continuously for group B regardless
9028                                                           of the setting of the GBRSCN bit.                                    */
9029     } ADGSPCR_b;                                    /*!< BitSize                                                               */
9030   };
9031   __I  uint16_t  RESERVED6;
9032 
9033   union {
9034     __I  uint16_t  ADDBLDRA;                        /*!< A/D Data Duplication Register A                                       */
9035 
9036     struct {
9037       __I  uint16_t  ADDBLDRA   : 16;               /*!< This register is a 16-bit read-only registers for storing the
9038                                                          result of A/D conversion in response to the respective triggers
9039                                                           during extended operation in double trigger mode.                    */
9040     } ADDBLDRA_b;                                   /*!< BitSize                                                               */
9041   };
9042 
9043   union {
9044     __I  uint16_t  ADDBLDRB;                        /*!< A/D Data Duplication Register B                                       */
9045 
9046     struct {
9047       __I  uint16_t  ADDBLDRB   : 16;               /*!< This register is a 16-bit read-only registers for storing the
9048                                                          result of A/D conversion in response to the respective triggers
9049                                                           during extended operation in double trigger mode.                    */
9050     } ADDBLDRB_b;                                   /*!< BitSize                                                               */
9051   };
9052 
9053   __I  uint16_t  RESERVED7a;
9054 
9055 
9056   union {
9057       __I  uint8_t  ADHVREFCNT;                      /*!<A/D High-Potential/Low-Potential Reference Voltage Control Register */
9058 
9059    struct {
9060      __IO uint8_t  HVSEL        :  2;               /*!<High-Potential Reference Voltage Select bits
9061                                                     used to specify the high-potential reference voltage as AVCC0, VREFH0, or the internal reference voltage
9062                                                     (1.45 V).*/
9063           uint8_t               :  2;
9064      __IO uint8_t  LVSEL        :  1;              /*!<LVSEL bit specifies the low-potential reference voltage as AVSS0 or VREFL0*/
9065           uint8_t               :  2;
9066      __IO uint8_t  ADSLP        :  1;              /*!<The ADSLP bit transitions the A/D converter to the standby state. Set the ADSLP bit to 1 only when modifying the
9067                                                      ADCSR.ADHSC bit. In other cases, setting the ADSLP bit to 1 is prohibited.*/
9068       } ADHVREFCNT_b;                                   /*!< BitSize                                                               */
9069     };
9070 
9071    __I  uint8_t  RESERVED7;
9072 
9073 
9074   union {
9075     __IO uint8_t   ADWINMON;                        /*!< A/D Compare Function Window A/B Status Monitor Register               */
9076 
9077     struct {
9078       __IO uint8_t   MONCOMB    :  1;               /*!< Combination result monitorThis bit indicates the combination
9079                                                          result.This bit is valid when both window A operation and window
9080                                                           B operation are enabled.                                             */
9081            uint8_t              :  3;
9082       __IO uint8_t   MONCMPA    :  1;               /*!< Comparison Result Monitor A                                           */
9083       __IO uint8_t   MONCMPB    :  1;               /*!< Comparison Result Monitor B                                           */
9084     } ADWINMON_b;                                   /*!< BitSize                                                               */
9085   };
9086   __I  uint8_t   RESERVED8[3];
9087 
9088   union {
9089     __IO uint16_t  ADCMPCR;                         /*!< A/D Compare Function Control Register                                 */
9090 
9091     struct {
9092       __IO uint16_t  CMPAB      :  2;               /*!< Window A/B Composite Conditions SettingNOTE: These bits are
9093                                                          valid when both window A and window B are enabled (CMPAE = 1
9094                                                           and CMPBE = 1).                                                      */
9095            uint16_t             :  7;
9096       __IO uint16_t  CMPBE      :  1;               /*!< Compare Window B Operation Enable                                     */
9097            uint16_t             :  1;
9098       __IO uint16_t  CMPAE      :  1;               /*!< Compare Window A Operation Enable                                     */
9099            uint16_t             :  1;
9100       __IO uint16_t  CMPBIE     :  1;               /*!< Compare B Interrupt Enable                                            */
9101       __IO uint16_t  WCMPE      :  1;               /*!< Window Function Setting                                               */
9102       __IO uint16_t  CMPAIE     :  1;               /*!< Compare A Interrupt Enable                                            */
9103     } ADCMPCR_b;                                    /*!< BitSize                                                               */
9104   };
9105 
9106   union {
9107     __IO uint8_t   ADCMPANSER;                      /*!< A/D Compare Function Window A Extended Input Select Register          */
9108 
9109     struct {
9110       __IO uint8_t   CMPTSA     :  1;               /*!< Temperature sensor output Compare selection bit.                      */
9111       __IO uint8_t   CMPOCA     :  1;               /*!< Internal reference voltage Compare selection bit.                     */
9112     } ADCMPANSER_b;                                 /*!< BitSize                                                               */
9113   };
9114 
9115   union {
9116     __IO uint8_t   ADCMPLER;                        /*!< A/D Compare Function Window A Extended Input Comparison Condition
9117                                                          Setting Register                                                      */
9118 
9119     struct {
9120       __IO uint8_t   CMPLTSA    :  1;               /*!< Compare Window A Temperature Sensor Output Comparison Condition
9121                                                          Select                                                                */
9122       __IO uint8_t   CMPLOCA    :  1;               /*!< Compare Window A Internal Reference Voltage ComparisonCondition
9123                                                          Select                                                                */
9124     } ADCMPLER_b;                                   /*!< BitSize                                                               */
9125   };
9126 
9127   union {
9128     __IO uint16_t  ADCMPANSR0;                      /*!< A/D Compare Function Window A Channel Select Register 0               */
9129 
9130     struct {
9131       __IO uint16_t  CMPCHA00   :  1;               /*!< AN000 Select                                                          */
9132       __IO uint16_t  CMPCHA01   :  1;               /*!< AN001 Select                                                          */
9133       __IO uint16_t  CMPCHA02   :  1;               /*!< AN002 Select                                                          */
9134       __IO uint16_t  CMPCHA03   :  1;               /*!< AN003 Select                                                          */
9135       __IO uint16_t  CMPCHA04   :  1;               /*!< AN004 Select                                                          */
9136       __IO uint16_t  CMPCHA05   :  1;               /*!< AN005 Select                                                          */
9137       __IO uint16_t  CMPCHA06   :  1;               /*!< AN006 Select                                                          */
9138       __IO uint16_t  CMPCHA07   :  1;               /*!< AN007 Select                                                          */
9139       __IO uint16_t  CMPCHA08   :  1;               /*!< AN008 Select                                                          */
9140       __IO uint16_t  CMPCHA09   :  1;               /*!< AN009 Select                                                          */
9141       __IO uint16_t  CMPCHA10   :  1;               /*!< AN010 Select                                                          */
9142       __IO uint16_t  CMPCHA11   :  1;               /*!< AN011 Select                                                          */
9143       __IO uint16_t  CMPCHA12   :  1;               /*!< AN012 Select                                                          */
9144       __IO uint16_t  CMPCHA13   :  1;               /*!< AN013 Select                                                          */
9145       __IO uint16_t  CMPCHA14   :  1;               /*!< AN014 Select                                                          */
9146       __IO uint16_t  CMPCHA15   :  1;               /*!< AN015 Select                                                          */
9147     } ADCMPANSR0_b;                                 /*!< BitSize                                                               */
9148   };
9149 
9150   union {
9151     __IO uint16_t  ADCMPANSR1;                      /*!< A/D Compare Function Window A Channel Select Register 1               */
9152 
9153     struct {
9154       __IO uint16_t  CMPCHA16   :  1;               /*!< AN016 Select                                                          */
9155       __IO uint16_t  CMPCHA17   :  1;               /*!< AN017 Select                                                          */
9156       __IO uint16_t  CMPCHA18   :  1;               /*!< AN018 Select                                                          */
9157       __IO uint16_t  CMPCHA19   :  1;               /*!< AN019 Select                                                          */
9158       __IO uint16_t  CMPCHA20   :  1;               /*!< AN020 Select                                                          */
9159       __IO uint16_t  CMPCHA21   :  1;               /*!< AN021 Select                                                          */
9160       __IO uint16_t  CMPCHA22   :  1;               /*!< AN021 Select                                                          */
9161       __IO uint16_t  CMPCHA23   :  1;               /*!< AN021 Select                                                          */
9162       __IO uint16_t  CMPCHA24   :  1;               /*!< AN021 Select                                                          */
9163       __IO uint16_t  CMPCHA25   :  1;               /*!< AN021 Select                                                          */
9164       __IO uint16_t  CMPCHA26   :  1;               /*!< AN021 Select                                                          */
9165       __IO uint16_t  CMPCHA27   :  1;               /*!< AN021 Select                                                          */
9166     } ADCMPANSR1_b;                                 /*!< BitSize                                                               */
9167   };
9168 
9169   union {
9170     __IO uint16_t  ADCMPLR0;                        /*!< A/D Compare Function Window A Comparison Condition Setting Register
9171                                                          0                                                                     */
9172 
9173     struct {
9174       __IO uint16_t  CMPLCHA00  :  1;               /*!< Comparison condition of AN000                                         */
9175       __IO uint16_t  CMPLCHA01  :  1;               /*!< Comparison condition of AN001                                         */
9176       __IO uint16_t  CMPLCHA02  :  1;               /*!< Comparison condition of AN002                                         */
9177       __IO uint16_t  CMPLCHA03  :  1;               /*!< Comparison condition of AN003                                         */
9178       __IO uint16_t  CMPLCHA04  :  1;               /*!< Comparison condition of AN004                                         */
9179       __IO uint16_t  CMPLCHA05  :  1;               /*!< Comparison condition of AN005                                         */
9180       __IO uint16_t  CMPLCHA06  :  1;               /*!< Comparison condition of AN006                                         */
9181       __IO uint16_t  CMPLCHA07  :  1;               /*!< Comparison condition of AN007                                         */
9182       __IO uint16_t  CMPLCHA08  :  1;               /*!< Comparison condition of AN008                                         */
9183       __IO uint16_t  CMPLCHA09  :  1;               /*!< Comparison condition of AN009                                         */
9184       __IO uint16_t  CMPLCHA10  :  1;               /*!< Comparison condition of AN010                                         */
9185       __IO uint16_t  CMPLCHA11  :  1;               /*!< Comparison condition of AN011                                         */
9186       __IO uint16_t  CMPLCHA12  :  1;               /*!< Comparison condition of AN012                                         */
9187       __IO uint16_t  CMPLCHA13  :  1;               /*!< Comparison condition of AN013                                         */
9188       __IO uint16_t  CMPLCHA14  :  1;               /*!< Comparison condition of AN014                                         */
9189       __IO uint16_t  CMPLCHA15  :  1;               /*!< Comparison condition of AN015                                         */
9190     } ADCMPLR0_b;                                   /*!< BitSize                                                               */
9191   };
9192 
9193   union {
9194     __IO uint16_t  ADCMPLR1;                        /*!< A/D Compare Function Window A Comparison Condition Setting Register
9195                                                          1                                                                     */
9196 
9197     struct {
9198       __IO uint16_t  CMPLCHA16  :  1;               /*!< Comparison condition of AN016                                         */
9199       __IO uint16_t  CMPLCHA17  :  1;               /*!< Comparison condition of AN017                                         */
9200       __IO uint16_t  CMPLCHA18  :  1;               /*!< Comparison condition of AN018                                         */
9201       __IO uint16_t  CMPLCHA19  :  1;               /*!< Comparison condition of AN019                                         */
9202       __IO uint16_t  CMPLCHA20  :  1;               /*!< Comparison condition of AN020                                         */
9203       __IO uint16_t  CMPLCHA21  :  1;               /*!< Comparison condition of AN021                                         */
9204       __IO uint16_t  CMPLCHA22  :  1;               /*!< Comparison condition of AN022                                         */
9205       __IO uint16_t  CMPLCHA23  :  1;               /*!< Comparison condition of AN023                                         */
9206       __IO uint16_t  CMPLCHA24  :  1;               /*!< Comparison condition of AN024                                         */
9207       __IO uint16_t  CMPLCHA25  :  1;               /*!< Comparison condition of AN025                                         */
9208       __IO uint16_t  CMPLCHA26  :  1;               /*!< Comparison condition of AN026                                         */
9209       __IO uint16_t  CMPLCHA27  :  1;               /*!< Comparison condition of AN027                                         */
9210     } ADCMPLR1_b;                                   /*!< BitSize                                                               */
9211   };
9212 
9213   union {
9214     __IO uint16_t  ADCMPDR0;                        /*!< A/D Compare Function Window A Lower-Side Level Setting Register       */
9215 
9216     struct {
9217       __IO uint16_t  ADCMPDR0   : 16;               /*!< The ADCMPDR0 register sets the reference data when the compare
9218                                                          window A function is used. ADCMPDR0 sets the lower-side level
9219                                                           of window A.                                                         */
9220     } ADCMPDR0_b;                                   /*!< BitSize                                                               */
9221   };
9222 
9223   union {
9224     __IO uint16_t  ADCMPDR1;                        /*!< A/D Compare Function Window A Upper-Side Level Setting Register       */
9225 
9226     struct {
9227       __IO uint16_t  ADCMPDR1   : 16;               /*!< The ADCMPDR1 register sets the reference data when the compare
9228                                                          window A function is used. ADCMPDR1 sets the upper-side level
9229                                                           of window A..                                                        */
9230     } ADCMPDR1_b;                                   /*!< BitSize                                                               */
9231   };
9232 
9233   union {
9234     __IO uint16_t  ADCMPSR0;                        /*!< A/D Compare Function Window A Channel Status Register 0               */
9235 
9236     struct {
9237       __IO uint16_t  CMPSTCHA00 :  1;               /*!< Compare window A flag of AN000                                        */
9238       __IO uint16_t  CMPSTCHA01 :  1;               /*!< Compare window A flag of AN001                                        */
9239       __IO uint16_t  CMPSTCHA02 :  1;               /*!< Compare window A flag of AN002                                        */
9240       __IO uint16_t  CMPSTCHA03 :  1;               /*!< Compare window A flag of AN003                                        */
9241       __IO uint16_t  CMPSTCHA04 :  1;               /*!< Compare window A flag of AN004                                        */
9242       __IO uint16_t  CMPSTCHA05 :  1;               /*!< Compare window A flag of AN005                                        */
9243       __IO uint16_t  CMPSTCHA06 :  1;               /*!< Compare window A flag of AN006                                        */
9244       __IO uint16_t  CMPSTCHA07 :  1;               /*!< Compare window A flag of AN007                                        */
9245       __IO uint16_t  CMPSTCHA08 :  1;               /*!< Compare window A flag of AN008                                        */
9246       __IO uint16_t  CMPSTCHA09 :  1;               /*!< Compare window A flag of AN009                                        */
9247       __IO uint16_t  CMPSTCHA10 :  1;               /*!< Compare window A flag of AN010                                        */
9248       __IO uint16_t  CMPSTCHA11 :  1;               /*!< Compare window A flag of AN011                                        */
9249       __IO uint16_t  CMPSTCHA12 :  1;               /*!< Compare window A flag of AN012                                        */
9250       __IO uint16_t  CMPSTCHA13 :  1;               /*!< Compare window A flag of AN013                                        */
9251       __IO uint16_t  CMPSTCHA14 :  1;               /*!< Compare window A flag of AN014                                        */
9252       __IO uint16_t  CMPSTCHA15 :  1;               /*!< Compare window A flag of AN015                                        */
9253     } ADCMPSR0_b;                                   /*!< BitSize                                                               */
9254   };
9255 
9256   union {
9257     __IO uint16_t  ADCMPSR1;                        /*!< A/D Compare Function Window A Channel Status Register 1               */
9258 
9259     struct {
9260       __IO uint16_t  CMPSTCHA16 :  1;               /*!< Compare window A flag of AN016                                        */
9261       __IO uint16_t  CMPSTCHA17 :  1;               /*!< Compare window A flag of AN017                                        */
9262       __IO uint16_t  CMPSTCHA18 :  1;               /*!< Compare window A flag of AN018                                        */
9263       __IO uint16_t  CMPSTCHA19 :  1;               /*!< Compare window A flag of AN019                                        */
9264       __IO uint16_t  CMPSTCHA20 :  1;               /*!< Compare window A flag of AN020                                        */
9265       __IO uint16_t  CMPSTCHA21 :  1;               /*!< Compare window A flag of AN021                                        */
9266       __IO uint16_t  CMPSTCHA22 :  1;               /*!< Compare window A flag of AN022                                        */
9267       __IO uint16_t  CMPSTCHA23 :  1;               /*!< Compare window A flag of AN023                                        */
9268       __IO uint16_t  CMPSTCHA24 :  1;               /*!< Compare window A flag of AN024                                        */
9269       __IO uint16_t  CMPSTCHA25 :  1;               /*!< Compare window A flag of AN025                                        */
9270       __IO uint16_t  CMPSTCHA26 :  1;               /*!< Compare window A flag of AN026                                        */
9271       __IO uint16_t  CMPSTCHA27 :  1;               /*!< Compare window A flag of AN027                                        */
9272     } ADCMPSR1_b;                                   /*!< BitSize                                                               */
9273   };
9274 
9275   union {
9276     __IO uint8_t   ADCMPSER;                        /*!< A/D Compare Function Window A Extended Input Channel Status
9277                                                          Register                                                              */
9278 
9279     struct {
9280       __IO uint8_t   CMPSTTSA   :  1;               /*!< Compare window A Temperature Sensor Output Compare FlagWhen
9281                                                          window A operation is enabled (ADCMPCR.CMPAE = 1b), this bit
9282                                                           indicates the temperature sensor output comparison result. When
9283                                                           window A operation is disabled (ADCMPCR.CMPAE = 0b), comparison
9284                                                           conditions for CMPSTTSA are not met any time.                        */
9285       __IO uint8_t   CMPSTOCA   :  1;               /*!< Compare Window A Internal Reference Voltage Compare FlagWhen
9286                                                          window A operation is enabled (ADCMPCR.CMPAE = 1b), this bit
9287                                                           indicates the temperature sensor output comparison result. When
9288                                                           window A operation is disabled (ADCMPCR.CMPAE = 0b), comparison
9289                                                           conditions for CMPSTTSA are not met any time.                        */
9290     } ADCMPSER_b;                                   /*!< BitSize                                                               */
9291   };
9292   __I  uint8_t   RESERVED9;
9293 
9294   union {
9295     __IO uint8_t   ADCMPBNSR;                       /*!< A/D Compare Function Window B Channel Selection Register              */
9296 
9297     struct {
9298       __IO uint8_t   CMPCHB     :  6;               /*!< Compare window B channel selection bit.The channel that compares
9299                                                          it on the condition of compare window B is selected.                  */
9300            uint8_t              :  1;
9301       __IO uint8_t   CMPLB      :  1;               /*!< Compare window B Compare condition setting bit.                       */
9302     } ADCMPBNSR_b;                                  /*!< BitSize                                                               */
9303   };
9304   __I  uint8_t   RESERVED10;
9305 
9306   union {
9307     __IO uint16_t  ADWINLLB;                        /*!< A/D Compare Function Window B Lower-Side Level Setting Register       */
9308 
9309     struct {
9310       __IO uint16_t  ADWINLLB   : 16;               /*!< This register is used to compare A window function is used to
9311                                                          set the lower level of the window B.                                  */
9312     } ADWINLLB_b;                                   /*!< BitSize                                                               */
9313   };
9314 
9315   union {
9316     __IO uint16_t  ADWINULB;                        /*!< A/D Compare Function Window B Upper-Side Level Setting Register       */
9317 
9318     struct {
9319       __IO uint16_t  ADWINULB   : 16;               /*!< This register is used to compare A window function is used to
9320                                                          set the higher level of the window B.                                 */
9321     } ADWINULB_b;                                   /*!< BitSize                                                               */
9322   };
9323 
9324   union {
9325     __IO uint16_t  ADCMPBSR;                        /*!< A/D Compare Function Window B Status Register                         */
9326 
9327     struct {
9328       __IO uint16_t  CMPSTB     :  1;               /*!< Compare window B flag.It is a status flag that shows the comparative
9329                                                          result of CH (AN000-AN027, temperature sensor, and internal
9330                                                           reference voltage) made the object of window B relation condition.   */
9331     } ADCMPBSR_b;                                   /*!< BitSize                                                               */
9332   };
9333   __I  uint16_t  RESERVED11;
9334 
9335   union {
9336     __I  uint16_t  ADBUFn[16];                      /*!< A/D Data Buffer Register [%s]                                         */
9337 
9338     struct {
9339       __I  uint16_t  ADBUF      : 16;               /*!< A/D data buffer registers (ADBUF) are 16-bit read-only registers
9340                                                          that sequentially store all A/D converted values. The automatic
9341                                                           clear function is not applied to these registers.                    */
9342     } ADBUFn_b[16];                                 /*!< BitSize                                                               */
9343   };
9344 
9345   union {
9346     __IO uint8_t   ADBUFEN;                         /*!< A/D Data Buffer Enable Register                                       */
9347 
9348     struct {
9349       __IO uint8_t   BUFEN      :  1;               /*!< Data Buffer Enable                                                    */
9350     } ADBUFEN_b;                                    /*!< BitSize                                                               */
9351   };
9352   __I  uint8_t   RESERVED12;
9353 
9354   union {
9355     __IO uint8_t   ADBUFPTR;                        /*!< A/D Data Buffer Pointer Register                                      */
9356 
9357     struct {
9358       __I  uint8_t   BUFPTR     :  4;               /*!< Data Buffer PointerThese bits indicate the number of data buffer
9359                                                          to which the next A/D converted data is transferred.                  */
9360       __I  uint8_t   PTROVF     :  1;               /*!< Pointer Overflow Flag                                                 */
9361     } ADBUFPTR_b;                                   /*!< BitSize                                                               */
9362   };
9363   __I  uint8_t  RESERVED13[10];
9364 
9365   union {
9366     __IO uint8_t   ADSSTRL;                         /*!< A/D Sampling State Register L                                         */
9367 
9368     struct {
9369       __IO uint8_t   SST        :  8;               /*!< Sampling Time Setting (AN016-AN027)                                   */
9370     } ADSSTRL_b;                                    /*!< BitSize                                                               */
9371   };
9372 
9373   union {
9374     __IO uint8_t   ADSSTRT;                         /*!< A/D Sampling State Register T                                         */
9375 
9376     struct {
9377       __IO uint8_t   SST        :  8;               /*!< Sampling Time Setting (temperature sensor output)                     */
9378     } ADSSTRT_b;                                    /*!< BitSize                                                               */
9379   };
9380 
9381   union {
9382     __IO uint8_t   ADSSTRO;                         /*!< A/D Sampling State Register O                                         */
9383 
9384     struct {
9385       __IO uint8_t   SST        :  8;               /*!< Sampling Time Setting (Internal reference voltage)                    */
9386     } ADSSTRO_b;                                    /*!< BitSize                                                               */
9387   };
9388 
9389   union {
9390     __IO uint8_t   ADSSTR0n[16];                    /*!< A/D Sampling State Register %s (Corresponding Channel is AN00%s
9391                                                          )                                                                     */
9392 
9393     struct {
9394       __IO uint8_t   SST        :  8;               /*!< Sampling time setting                                                 */
9395     } ADSSTR0n_b[16];                               /*!< BitSize                                                               */
9396   };
9397 
9398 
9399   union {
9400       __IO uint16_t   ADANIM;                        /*!< A/D Channel Input Mode Select Register                               */
9401 
9402       struct{
9403       __IO uint16_t   ANIM       :  4;               /*!< Analog Channel Input Mode Select                                     */
9404            uint16_t              :  12;
9405       } ADANIM_b;
9406   };
9407 
9408   union {
9409       __IO uint8_t   ADCALEXE;                       /*!< A/D Calibration Execution Register                                   */
9410 
9411       struct{
9412              uint8_t                :  6;
9413         __IO uint8_t   CALMON       :  1;            /*!< Calibration Status Flag                                              */
9414         __IO uint8_t   CALEXE       :  1;            /*!< Calibration Start                                                    */
9415       } ADCALEXE_b;
9416   };
9417 
9418   __I  uint8_t RESERVED14;
9419 
9420   union {
9421       __IO uint8_t   VREFAMPCNT;                     /*!< A/D Dedicated Reference Voltage Circuit Control Register             */
9422 
9423       struct{
9424         __IO uint8_t   OLDETEN      :  1;            /*!< OLDET Enable                                                         */
9425         __IO uint8_t   VREFADCG     :  2;            /*!< VREFADCG                                                             */
9426         __IO uint8_t   VREFADCEN    :  1;            /*!< VREFADCEN                                                            */
9427         __IO uint8_t   BGREN        :  1;            /*!< BGR Enable                                                           */
9428              uint8_t                :  3;
9429       } VREFAMPCNT_b;
9430   };
9431 
9432   __I  uint16_t RESERVED15;
9433 
9434   union {
9435     __IO  uint16_t  ADRD;                            /*!< A/D Self-Diagnosis Data Register                                      */
9436 
9437     struct {
9438       __IO  uint16_t  AD         : 16;              /*!< A/D-converted value (right-justified)NOTE: Unused bits in the
9439                                                          AD bit field are fixed "0"                                            */
9440     } ADRD_b;                                       /*!< BitSize                                                               */
9441   };
9442 
9443   union {
9444       __IO uint8_t   ADRST;                        /*!< A/D Self-Diagnostic Status Register                                    */
9445 
9446       struct{
9447       __IO uint8_t   DIAGST     :  2;               /*!< Self-Diagnosis Status                                                 */
9448            uint8_t              :  6;
9449       } ADRST_b;
9450   };
9451 
9452   /* PGA registers added even though PGA is not present on MCU to allow SSP driver to be written
9453     * cleanly. The padding bits are removed since they do not mean anything anyway in this MCUs address space.*/
9454    union {
9455       __IO uint16_t  ADPGACR;                         /*!< A/D Programmable Gain Amplifier Control Register                      */
9456 
9457       struct {
9458         __IO uint16_t  P000SEL0   :  1;               /*!< A through amplifier is enable for PGA P000                            */
9459         __IO uint16_t  P000SEL1   :  1;               /*!< The amplifier passing is enable for PGA P000                          */
9460         __IO uint16_t  P000ENAMP  :  1;               /*!< Amplifier enable bit for PGA P000                                     */
9461         __IO uint16_t  P000GEN    :  1;               /*!< PGA P000 gain setting and enable bit                                  */
9462         __IO uint16_t  P001SEL0   :  1;               /*!< A through amplifier is enable for PGA P001                            */
9463         __IO uint16_t  P001SEL1   :  1;               /*!< The amplifier passing is enable for PGA P001                          */
9464         __IO uint16_t  P001ENAMP  :  1;               /*!< Amplifier enable bit for PGA P001                                     */
9465         __IO uint16_t  P001GEN    :  1;               /*!< PGA P001 gain setting and enable bit                                  */
9466         __IO uint16_t  P002SEL0   :  1;               /*!< A through amplifier is enable for PGA P002                            */
9467         __IO uint16_t  P002SEL1   :  1;               /*!< The amplifier passing is enable for PGA P002                          */
9468         __IO uint16_t  P002ENAMP  :  1;               /*!< Amplifier enable bit for PGA P002                                     */
9469         __IO uint16_t  P002GEN    :  1;               /*!< PGA P002 gain setting and enable bit                                  */
9470         __IO uint16_t  P003SEL0   :  1;               /*!< A through amplifier is enable for PGA P003                            */
9471         __IO uint16_t  P003SEL1   :  1;               /*!< The amplifier passing is enable for PGA P003                          */
9472         __IO uint16_t  P003ENAMP  :  1;               /*!< Amplifier enable bit for PGA P003                                     */
9473         __IO uint16_t  P003GEN    :  1;               /*!< PGA P003 gain setting and enable bit                                  */
9474       } ADPGACR_b;                                    /*!< BitSize                                                               */
9475     };
9476 
9477     union {
9478       __IO uint16_t  ADPGAGS0;                        /*!< A/D Programmable Gain Amplifier Gain Setting Register 0               */
9479 
9480       struct {
9481         __IO uint16_t  P000GAIN   :  4;               /*!< PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN=0b)
9482                                                            when the shingle end is input and each PGA P000 is set. When
9483                                                             the differential motion is input, (ADPGSDCR0.P000GEN=1b) sets
9484                                                             the gain magnification when the differential motion is input
9485                                                             by the combination with ADPGSDCR0.P000DG 1:0.                        */
9486         __IO uint16_t  P001GAIN   :  4;               /*!< PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN=0b)
9487                                                            when the shingle end is input and each PGA P001 is set. When
9488                                                             the differential motion is input, (ADPGSDCR0.P001GEN=1b) sets
9489                                                             the gain magnification when the differential motion is input
9490                                                             by the combination with ADPGSDCR0.P001DG 1:0.                        */
9491         __IO uint16_t  P002GAIN   :  4;               /*!< PGA P002 gain setting bit.The gain magnification of (ADPGSDCR0.P002GEN=0b)
9492                                                            when the shingle end is input and each PGA P002 is set. When
9493                                                             the differential motion is input, (ADPGSDCR0.P002GEN=1b) sets
9494                                                             the gain magnification when the differential motion is input
9495                                                             by the combination with ADPGSDCR0.P002DG 1:0.                        */
9496         __IO uint16_t  P003GAIN   :  4;               /*!< PGA P003 gain setting bit.The gain magnification of (ADPGSDCR0.P003GEN=0b)
9497                                                            when the shingle end is input and each PGA P003 is set. When
9498                                                             the differential motion is input, (ADPGSDCR0.P003GEN=1b) sets
9499                                                             the gain magnification when the differential motion is input
9500                                                             by the combination with ADPGSDCR0.P003DG 1:0.                        */
9501       } ADPGAGS0_b;                                   /*!< BitSize                                                               */
9502     };
9503 
9504     union {
9505       __IO uint16_t  ADPGADCR0;                       /*!< A/D Programmable Gain Amplifier Differential Input Control Register   */
9506 
9507       struct {
9508         __IO uint16_t  P000DG     :  2;               /*!< P000 Differential Input Gain SettingNOTE: When these bits are
9509                                                            used, set {P000DEN, P000GEN} to 11b.                                  */
9510              uint16_t             :  1;
9511         __IO uint16_t  P000DEN    :  1;               /*!< P000 Differential Input Enable                                        */
9512         __IO uint16_t  P001DG     :  2;               /*!< P001 Differential Input Gain SettingNOTE: When these bits are
9513                                                            used, set {P001DEN, P001GEN} to 11b.                                  */
9514              uint16_t             :  1;
9515         __IO uint16_t  P001DEN    :  1;               /*!< P001 Differential Input Enable                                        */
9516         __IO uint16_t  P002DG     :  2;               /*!< P002 Differential Input Gain SettingNOTE: When these bits are
9517                                                            used, set {P002DEN, P002GEN} to 11b.                                  */
9518              uint16_t             :  1;
9519         __IO uint16_t  P002DEN    :  1;               /*!< P002 Differential Input Enable                                        */
9520         __IO uint16_t  P003DG     :  2;               /*!< P003 Differential Input Gain SettingNOTE: When these bits are
9521                                                            used, set {P003DEN, P003GEN} to 11b.                                  */
9522              uint16_t             :  1;
9523         __IO uint16_t  P003DEN    :  1;               /*!< P003 Differential Input Enable                                        */
9524       } ADPGADCR0_b;                                  /*!< BitSize                                                               */
9525     };
9526 
9527     union {
9528       __IO uint8_t   ADPGADBS0;                       /*!< A/D Programmable Gain Amplifier Differential Input Bias Select
9529                                                            Register 0                                                            */
9530 
9531       struct {
9532         __IO uint8_t   P0BIAS     :  1;               /*!< Programmable Gain Amplifiers P000 to P002 Bias Voltage SelectNOTE:
9533                                                            This bit selects the input bias voltage value when differential
9534                                                             inputs are used.                                                     */
9535       } ADPGADBS0_b;                                  /*!< BitSize                                                               */
9536     };
9537 
9538     union {
9539       __IO uint8_t   ADPGADBS1;                       /*!< A/D Programmable Gain Amplifier Differential Input Bias Select
9540                                                            Register 1                                                            */
9541 
9542       struct {
9543         __IO uint8_t   P3BIAS     :  1;               /*!< Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: This
9544                                                            bit selects the input bias voltage value when differential inputs
9545                                                             are used.                                                            */
9546       } ADPGADBS1_b;                                  /*!< BitSize                                                               */
9547     };
9548 
9549     union {
9550       __IO uint8_t   ADREFMON;                        /*!< A/D External Reference Voltage Monitor Register                       */
9551 
9552       struct {
9553         __IO uint8_t   PGAMON     :  3;               /*!< PGA Monitor Output Enable                                             */
9554              uint8_t              :  1;
9555         __IO uint8_t   MONSEL     :  4;               /*!< Monitor output selection bit.                                         */
9556       } ADREFMON_b;                                   /*!< BitSize                                                               */
9557     };
9558 } R_S16ADC_Type;
9559 
9560 
9561 /* ================================================================================ */
9562 /* ================                      R_DAC                     ================ */
9563 /* ================================================================================ */
9564 
9565 
9566 /**
9567   * @brief 12-bit D/A converter (R_DAC)
9568   */
9569 
9570 typedef struct {                                    /*!< R_DAC Structure                                                       */
9571 
9572   union {
9573     __IO uint16_t  DADRn[2];                        /*!< D/A Data Register %s                                                  */
9574 
9575     struct {
9576       __IO uint16_t  DADR       : 16;               /*!< D/A Data RegisterNOTE: When DADPR.DPSEL = 0, the high-order
9577                                                          4 bits are fixed to 0: right justified format. When DADPR.DPSEL
9578                                                           = 1, the low-order 4 bits are fixed to 0: left justified format.     */
9579     } DADRn_b[2];                                   /*!< BitSize                                                               */
9580   };
9581 
9582   union {
9583     __IO uint8_t   DACR;                            /*!< D/A Control Register                                                  */
9584 
9585     struct {
9586            uint8_t              :  5;
9587       __IO uint8_t   DAE        :  1;               /*!< D/A Enable                                                            */
9588       __IO uint8_t   DAOE0      :  1;               /*!< D/A Output Enable 0                                                   */
9589       __IO uint8_t   DAOE1      :  1;               /*!< D/A Output Enable 1                                                   */
9590     } DACR_b;                                       /*!< BitSize                                                               */
9591   };
9592 
9593   union {
9594     __IO uint8_t   DADPR;                           /*!< DADRm Format Select Register                                          */
9595 
9596     struct {
9597            uint8_t              :  7;
9598       __IO uint8_t   DPSEL      :  1;               /*!< DADRm Format Select                                                   */
9599     } DADPR_b;                                      /*!< BitSize                                                               */
9600   };
9601 
9602   union {
9603     __IO uint8_t   DAADSCR;                         /*!< D/A-A/D Synchronous Start Control Register                            */
9604 
9605     struct {
9606            uint8_t              :  7;
9607       __IO uint8_t   DAADST     :  1;               /*!< D/A-A/D Synchronous Conversion                                        */
9608     } DAADSCR_b;                                    /*!< BitSize                                                               */
9609   };
9610 
9611   union {
9612     __IO uint8_t   DAVREFCR;                        /*!< D/A VREF Control Register                                             */
9613 
9614     struct {
9615       __IO uint8_t   REF        :  3;               /*!< D/A Reference Voltage Select                                          */
9616            uint8_t              :  5;
9617     } DAVREFCR_b;                                   /*!< BitSize                                                               */
9618   };
9619 
9620   union {
9621     __IO uint8_t   DAAMPCR;                         /*!< D/A Output Amplifier Control Register                                 */
9622 
9623     struct {
9624            uint8_t              :  6;
9625       __IO uint8_t   DAAMP0     :  1;               /*!< Amplifier Control 0                                                   */
9626       __IO uint8_t   DAAMP1     :  1;               /*!< Amplifier Control 1                                                   */
9627     } DAAMPCR_b;                                    /*!< BitSize                                                               */
9628   };
9629 
9630   union {
9631     __IO uint8_t  DAPC;                             /*!< DAPC Charge Pump Control                                              */
9632 
9633     struct {
9634       __IO uint8_t  PUMPEN :  1;                    /*!< D/A Charge Pump Enable                                                */
9635     } DAPC_b;                                       /*!< BitSize                                                               */
9636   };
9637 } R_DAC_Type;
9638 
9639 /* ================================================================================ */
9640 /* ================                      R_DAC8                    ================ */
9641 /* ================================================================================ */
9642 
9643 
9644 /**
9645   * @brief 8-bit D/A converter (R_DAC8)
9646   */
9647 
9648 typedef struct                                      /*!< DAC8 Structure */
9649 {
9650     __IO uint8_t   DADRn[3];                      /*!< D/A Data Register %s */
9651 
9652     union
9653     {
9654         __IO uint8_t  DAM;                             /*!< D/A Mode Register */
9655 
9656         struct
9657         {
9658             __IO uint8_t  DAMD0 :  1;                   /*!< D/A Operation Mode 0 */
9659             __IO uint8_t  DAMD1 :  1;                   /*!< D/A Operation Mode 1 */
9660             __IO uint8_t  DAMD2 :  1;                   /*!< D/A Operation Mode 2 */
9661 
9662             uint8_t             :  1;
9663 
9664             __IO uint8_t  DACE0 :  1;                   /*!< D/A Operation Enable 0 */
9665             __IO uint8_t  DACE1 :  1;                   /*!< D/A Operation Enable 1 */
9666             __IO uint8_t  DACE2 :  1;                   /*!< D/A Operation Enable 2 */
9667         }  DACR_b;                                      /*!< BitSize */
9668     };
9669 
9670     uint8_t RESERVED2[2];
9671 
9672     union
9673     {
9674         __IO uint8_t DACADSCR;                          /*!< Synchronous Start Control Register */
9675 
9676         struct
9677         {
9678             __IO uint8_t DACADST : 1;                   /*!< Synchronize D/A with A/D */
9679         } DACADSCR_b;
9680     };
9681 
9682     union
9683     {
9684         __IO uint8_t  DACPC;                            /*!< DACPC Charge Pump Control */
9685 
9686         struct
9687         {
9688             __IO uint8_t  PUMPEN :  1;                   /*!< D/A Charge Pump Enable */
9689         } DACPC_b;
9690     };
9691 } R_DAC8_Type;
9692 
9693 
9694 /* ================================================================================ */
9695 /* ================                      R_TSN                     ================ */
9696 /* ================================================================================ */
9697 
9698 
9699 /**
9700   * @brief Temperature Sensor (R_TSN_Control_Type).
9701   * This structure defines the control structure for the TSN peripheral.
9702   * This register is only present on the CM4 devices
9703   */
9704 
9705 typedef struct {                                    /*!< R_TSN Structure                                                       */
9706                                                     /*!< Enable/Disable registers. Valid only on the CM4 devices             */
9707     union {
9708     __IO uint8_t   TSCR;                            /*!< Temperature Sensor Control Register                                   */
9709 
9710     struct {
9711     uint8_t              :  4;
9712     __IO uint8_t   TSOE       :  1;               /*!< Temperature Sensor Enable                                             */
9713     uint8_t              :  2;
9714     __IO uint8_t   TSEN       :  1;               /*!< Temperature Sensor Output Enable                                      */
9715     } TSCR_b;                                       /*!< BitSize                                                               */
9716     };
9717 } R_TSN_Control_Type;
9718 
9719 /**
9720   * @brief Temperature Sensor (R_TSN).
9721   * This structure defines the calibration structure for the TSN peripheral.
9722   * This register is only present on the CM0 devices and S5 devices
9723   */
9724 typedef struct {                                    /*!< R_TSN Structure                                                       */
9725                                                         /*!< Calibration data registers. Valid only on the CM0 devices and S5 devices */
9726 	union {
9727         struct{
9728            union {
9729               __I  uint8_t   TSCDRL;                            /*!< Calibration data register (Low)                                         */
9730               struct {
9731                 __I  uint8_t   TSCDRL       :  8;               /*!< Lower byte of the calibration data.                                   */
9732               } TSCDRL_b;                                       /*!< BitSize                                                               */
9733             };
9734 
9735             union {
9736               __I  uint8_t   TSCDRH;                            /*!< Calibration data register (High)                                        */
9737               struct {
9738                 __I  uint8_t   TSCDRH       :  8;               /*!< Higher byte of the calibration data. Only lower 4 bytes are valid     */
9739               } TSCDRH_b;                                       /*!< BitSize                                                               */
9740             };
9741             __I  uint16_t  RESERVED;
9742         } TSCDR_b;
9743       __I  uint32_t  TSCDR;
9744     };
9745 
9746 } R_TSN_Calibration_Type;
9747 
9748 
9749 /* ================================================================================ */
9750 /* ================                     R_SCI0                     ================ */
9751 /* ================================================================================ */
9752 
9753 
9754 /**
9755   * @brief Serial Communication Interface 0 (R_SCI0)
9756   */
9757 
9758 typedef struct {                                    /*!< R_SCI0 Structure                                                      */
9759 
9760   union {
9761     union {
9762       __IO uint8_t   SMR_SMCI;                      /*!< Serial mode register (SCMR.SMIF = 1)                                  */
9763 
9764       struct {
9765         __IO uint8_t   CKS      :  2;               /*!< Clock Select                                                          */
9766         __IO uint8_t   BCP      :  2;               /*!< Stop Bit Length(Valid only in asynchronous mode)                      */
9767         __IO uint8_t   PM       :  1;               /*!< Parity Mode (Valid only when the PE bit is 1)                         */
9768         __IO uint8_t   PE       :  1;               /*!< Parity Enable(Valid only in asynchronous mode)                        */
9769         __IO uint8_t   BLK      :  1;               /*!< Block Transfer Mode                                                   */
9770         __IO uint8_t   GM       :  1;               /*!< GSM Mode                                                              */
9771       } SMR_SMCI_b;                                 /*!< BitSize                                                               */
9772     };
9773 
9774     union {
9775       __IO uint8_t   SMR;                           /*!< Serial Mode Register (SCMR.SMIF = 0)                                  */
9776 
9777       struct {
9778         __IO uint8_t   CKS      :  2;               /*!< Clock Select                                                          */
9779         __IO uint8_t   MP       :  1;               /*!< Multi-Processor Mode(Valid only in asynchronous mode)                 */
9780         __IO uint8_t   STOP     :  1;               /*!< Stop Bit Length(Valid only in asynchronous mode)                      */
9781         __IO uint8_t   PM       :  1;               /*!< Parity Mode (Valid only when the PE bit is 1)                         */
9782         __IO uint8_t   PE       :  1;               /*!< Parity Enable(Valid only in asynchronous mode)                        */
9783         __IO uint8_t   CHR      :  1;               /*!< Character Length(Valid only in asynchronous mode)                     */
9784         __IO uint8_t   CM       :  1;               /*!< Communications Mode                                                   */
9785       } SMR_b;                                      /*!< BitSize                                                               */
9786     };
9787   };
9788 
9789   union {
9790     __IO uint8_t   BRR;                             /*!< Bit Rate Register                                                     */
9791 
9792     struct {
9793       __IO uint8_t   BRR        :  8;               /*!< BRR is an 8-bit register that adjusts the bit rate.                   */
9794     } BRR_b;                                        /*!< BitSize                                                               */
9795   };
9796 
9797   union {
9798     union {
9799       __IO uint8_t   SCR_SMCI;                      /*!< Serial Control Register (SCMR.SMIF =1)                                */
9800 
9801       struct {
9802         __IO uint8_t   CKE      :  2;               /*!< Clock Enable                                                          */
9803         __IO uint8_t   TEIE     :  1;               /*!< This bit should be "0" in smart card interface mode.                  */
9804         __IO uint8_t   MPIE     :  1;               /*!< This bit should be "0" in smart card interface mode.                  */
9805         __IO uint8_t   RE       :  1;               /*!< Receive Enable                                                        */
9806         __IO uint8_t   TE       :  1;               /*!< Transmit Enable                                                       */
9807         __IO uint8_t   RIE      :  1;               /*!< Receive Interrupt Enable                                              */
9808         __IO uint8_t   TIE      :  1;               /*!< Transmit Interrupt Enable                                             */
9809       } SCR_SMCI_b;                                 /*!< BitSize                                                               */
9810     };
9811 
9812     union {
9813       __IO uint8_t   SCR;                           /*!< Serial Control Register (SCMR.SMIF = 0)                               */
9814 
9815       struct {
9816         __IO uint8_t   CKE      :  2;               /*!< Clock Enable                                                          */
9817         __IO uint8_t   TEIE     :  1;               /*!< Transmit End Interrupt Enable                                         */
9818         __IO uint8_t   MPIE     :  1;               /*!< Multi-Processor Interrupt Enable(Valid in asynchronous mode
9819                                                          when SMR.MP = 1)                                                      */
9820         __IO uint8_t   RE       :  1;               /*!< Receive Enable                                                        */
9821         __IO uint8_t   TE       :  1;               /*!< Transmit Enable                                                       */
9822         __IO uint8_t   RIE      :  1;               /*!< Receive Interrupt Enable                                              */
9823         __IO uint8_t   TIE      :  1;               /*!< Transmit Interrupt Enable                                             */
9824       } SCR_b;                                      /*!< BitSize                                                               */
9825     };
9826   };
9827 
9828   union {
9829     __IO uint8_t   TDR;                             /*!< Transmit Data Register                                                */
9830 
9831     struct {
9832       __IO uint8_t   TDR        :  8;               /*!< TDR is an 8-bit register that stores transmit data.                   */
9833     } TDR_b;                                        /*!< BitSize                                                               */
9834   };
9835 
9836   union {
9837     union {
9838       __IO uint8_t   SSR_SMCI;                      /*!< Serial Status Register(SCMR.SMIF = 1)                                 */
9839 
9840       struct {
9841         __IO uint8_t   MPBT     :  1;               /*!< This bit should be 0 in smart card interface mode.                    */
9842         __I  uint8_t   MPB      :  1;               /*!< This bit should be 0 in smart card interface mode.                    */
9843         __I  uint8_t   TEND     :  1;               /*!< Transmit End Flag                                                     */
9844         __IO uint8_t   PER      :  1;               /*!< Parity Error Flag                                                     */
9845         __IO uint8_t   ERS      :  1;               /*!< Error Signal Status Flag                                              */
9846         __IO uint8_t   ORER     :  1;               /*!< Overrun Error Flag                                                    */
9847         __IO uint8_t   RDRF     :  1;               /*!< Receive Data Full Flag                                                */
9848         __IO uint8_t   TDRE     :  1;               /*!< Transmit Data Empty Flag                                              */
9849       } SSR_SMCI_b;                                 /*!< BitSize                                                               */
9850     };
9851 
9852     union {
9853       __IO uint8_t   SSR_FIFO;                      /*!< Serial Status Register(SCMR.SMIF = 0 and FCR.FM=1)                    */
9854 
9855       struct {
9856         __IO uint8_t   DR       :  1;               /*!< Receive Data Ready flag(Valid only in asynchronous mode(including
9857                                                          multi-processor) and FIFO selected)                                   */
9858              uint8_t            :  1;
9859         __IO uint8_t   TEND     :  1;               /*!< Transmit End Flag                                                     */
9860         __IO uint8_t   PER      :  1;               /*!< Parity Error Flag                                                     */
9861         __IO uint8_t   FER      :  1;               /*!< Framing Error Flag                                                    */
9862         __IO uint8_t   ORER     :  1;               /*!< Overrun Error Flag                                                    */
9863         __IO uint8_t   RDF      :  1;               /*!< Receive FIFO data full flag                                           */
9864         __IO uint8_t   TDFE     :  1;               /*!< Transmit FIFO data empty flag                                         */
9865       } SSR_FIFO_b;                                 /*!< BitSize                                                               */
9866     };
9867 
9868     union {
9869       __IO uint8_t   SSR;                           /*!< Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0)                    */
9870 
9871       struct {
9872         __IO uint8_t   MPBT     :  1;               /*!< Multi-Processor Bit Transfer. Sets the multi-processor bit for
9873                                                          adding to the transmission frame                                      */
9874         __I  uint8_t   MPB      :  1;               /*!< Multi-Processor Bit. Value of the multi-processor bit in the
9875                                                          reception frame                                                       */
9876         __I  uint8_t   TEND     :  1;               /*!< Transmit End Flag                                                     */
9877         __IO uint8_t   PER      :  1;               /*!< Parity Error Flag                                                     */
9878         __IO uint8_t   FER      :  1;               /*!< Framing Error Flag                                                    */
9879         __IO uint8_t   ORER     :  1;               /*!< Overrun Error Flag                                                    */
9880         __IO uint8_t   RDRF     :  1;               /*!< Receive Data Full Flag                                                */
9881         __IO uint8_t   TDRE     :  1;               /*!< Transmit Data Empty Flag                                              */
9882       } SSR_b;                                      /*!< BitSize                                                               */
9883     };
9884   };
9885 
9886   union {
9887     __IO uint8_t   RDR;                             /*!< Receive Data Register                                                 */
9888 
9889     struct {
9890       __IO uint8_t   RDR        :  8;               /*!< RDR is an 8-bit register that stores receive data.                    */
9891     } RDR_b;                                        /*!< BitSize                                                               */
9892   };
9893 
9894   union {
9895     __IO uint8_t   SCMR;                            /*!< Smart Card Mode Register                                              */
9896 
9897     struct {
9898       __IO uint8_t   SMIF       :  1;               /*!< Smart Card Interface Mode Select                                      */
9899            uint8_t              :  1;
9900       __IO uint8_t   SINV       :  1;               /*!< Transmitted/Received Data InvertSet this bit to "0" if operation
9901                                                          is to be in simple I2C mode.                                          */
9902       __IO uint8_t   SDIR       :  1;               /*!< Transmitted/Received Data Transfer DirectionNOTE: The setting
9903                                                          is invalid and a fixed data length of 8 bits is used in modes
9904                                                           other than asynchronous mode.Set this bit to "1" if operation
9905                                                           is to be in simple I2C mode.                                         */
9906       __IO uint8_t   CHR1       :  1;               /*!< Character Length 1(Only valid in asynchronous mode)                   */
9907            uint8_t              :  2;
9908       __IO uint8_t   BCP2       :  1;               /*!< Base Clock Pulse 2Selects the number of base clock cycles in
9909                                                          combination with the SMR.BCP[1:0] bits                                */
9910     } SCMR_b;                                       /*!< BitSize                                                               */
9911   };
9912 
9913   union {
9914     __IO uint8_t   SEMR;                            /*!< Serial Extended Mode Register                                         */
9915 
9916     struct {
9917            uint8_t              :  2;
9918       __IO uint8_t   BRME       :  1;               /*!< Bit Modulation Enable                                                 */
9919       __IO uint8_t   ABCSE      :  1;               /*!< Asynchronous Mode Extended Base Clock Select1(Valid only in
9920                                                          asynchronous mode and SCR.CKE[1]=0)                                   */
9921       __IO uint8_t   ABCS       :  1;               /*!< Asynchronous Mode Base Clock Select(Valid only in asynchronous
9922                                                          mode)                                                                 */
9923       __IO uint8_t   NFEN       :  1;               /*!< Digital Noise Filter Function Enable(The NFEN bit should be
9924                                                          0 without simple I2C mode and asynchronous mode.)In asynchronous
9925                                                           mode, for RXDn input only. In simple I2C mode, for RXDn/TxDn
9926                                                           input.                                                               */
9927       __IO uint8_t   BGDM       :  1;               /*!< Baud Rate Generator Double-Speed Mode Select(Only valid the
9928                                                          CKE[1] bit in SCR is 0 in asynchronous mode).                         */
9929       __IO uint8_t   RXDESEL    :  1;               /*!< Asynchronous Start Bit Edge Detection Select(Valid only in asynchronous
9930                                                          mode)                                                                 */
9931     } SEMR_b;                                       /*!< BitSize                                                               */
9932   };
9933 
9934   union {
9935     __IO uint8_t   SNFR;                            /*!< Noise Filter Setting Register                                         */
9936 
9937     struct {
9938       __IO uint8_t   NFCS       :  3;               /*!< Noise Filter Clock Select                                             */
9939     } SNFR_b;                                       /*!< BitSize                                                               */
9940   };
9941 
9942   union {
9943     __IO uint8_t   SIMR1;                           /*!< I2C Mode Register 1                                                   */
9944 
9945     struct {
9946       __IO uint8_t   IICM       :  1;               /*!< Simple I2C Mode Select                                                */
9947            uint8_t              :  2;
9948       __IO uint8_t   IICDL      :  5;               /*!< SSDA Delay Output SelectCycles below are of the clock signal
9949                                                          from the on-chip baud rate generator.                                 */
9950     } SIMR1_b;                                      /*!< BitSize                                                               */
9951   };
9952 
9953   union {
9954     __IO uint8_t   SIMR2;                           /*!< I2C Mode Register 2                                                   */
9955 
9956     struct {
9957       __IO uint8_t   IICINTM    :  1;               /*!< I2C Interrupt Mode Select                                             */
9958       __IO uint8_t   IICCSC     :  1;               /*!< Clock Synchronization                                                 */
9959            uint8_t              :  3;
9960       __IO uint8_t   IICACKT    :  1;               /*!< ACK Transmission Data                                                 */
9961     } SIMR2_b;                                      /*!< BitSize                                                               */
9962   };
9963 
9964   union {
9965     __IO uint8_t   SIMR3;                           /*!< I2C Mode Register 3                                                   */
9966 
9967     struct {
9968       __IO uint8_t   IICSTAREQ  :  1;               /*!< Start Condition Generation                                            */
9969       __IO uint8_t   IICRSTAREQ :  1;               /*!< Restart Condition Generation                                          */
9970       __IO uint8_t   IICSTPREQ  :  1;               /*!< Stop Condition Generation                                             */
9971       __IO uint8_t   IICSTIF    :  1;               /*!< Issuing of Start, Restart, or Stop Condition Completed Flag(When
9972                                                          0 is written to IICSTIF, it is cleared to 0.)                         */
9973       __IO uint8_t   IICSDAS    :  2;               /*!< SDA Output Select                                                     */
9974       __IO uint8_t   IICSCLS    :  2;               /*!< SCL Output Select                                                     */
9975     } SIMR3_b;                                      /*!< BitSize                                                               */
9976   };
9977 
9978   union {
9979     __IO uint8_t   SISR;                            /*!< I2C Status Register                                                   */
9980 
9981     struct {
9982       __I  uint8_t   IICACKR    :  1;               /*!< ACK Reception Data Flag                                               */
9983     } SISR_b;                                       /*!< BitSize                                                               */
9984   };
9985 
9986   union {
9987     __IO uint8_t   SPMR;                            /*!< SPI Mode Register                                                     */
9988 
9989     struct {
9990       __IO uint8_t   SSE        :  1;               /*!< SSn# Pin Function Enable                                              */
9991       __IO uint8_t   CTSE       :  1;               /*!< CTS Enable                                                            */
9992       __IO uint8_t   MSS        :  1;               /*!< Master or slave mode selection                                        */
9993            uint8_t              :  1;
9994       __IO uint8_t   MFF        :  1;               /*!< Mode Fault Flag                                                       */
9995            uint8_t              :  1;
9996       __IO uint8_t   CKPOL      :  1;               /*!< Clock Polarity Select                                                 */
9997       __IO uint8_t   CKPH       :  1;               /*!< Clock Phase Select                                                    */
9998     } SPMR_b;                                       /*!< BitSize                                                               */
9999   };
10000 
10001   union {
10002     union {
10003       __O  uint16_t  FTDR;                          /*!< Transmit FIFO Data Register (FCRL.FM=1)                               */
10004 
10005       struct {
10006         __O  uint16_t  TDAT     :  9;               /*!< Serial transmit data (Valid only in asynchronous mode(including
10007                                                          multi-processor) or clock synchronous mode, and FIFO selected)        */
10008         __O  uint16_t  MPBT     :  1;               /*!< Multi-processor transfer bit flag(Valid only in asynchronous
10009                                                          mode and SMR.MP=1 and FIFO selected)                                  */
10010       } FTDR_b;                                     /*!< BitSize                                                               */
10011     };
10012 
10013     union {
10014       __O  uint16_t  TDRHL;                         /*!< Transmit Data Register                                                */
10015 
10016       struct {
10017         __O  uint16_t  TDRL     :  8;               /*!< TDRL is a 8-bit register that stores transmit data low byte.          */
10018         __O  uint16_t  TDRH     :  8;               /*!< TDRH is a 8-bit register that stores transmit data high byte.         */
10019       } TDRHL_b;                                    /*!< BitSize                                                               */
10020     };
10021   };
10022 
10023   union {
10024     union {
10025       __I  uint8_t   FRDRH;                          /*!< Receive FIFO Data Register (stores High byte)                        */
10026 
10027       struct {
10028 
10029         __I  uint8_t   RDAT     :  1;                /*!< Serial receive data 9th bit(Valid only in asynchronous mode(including
10030                                                             multi-processor) or clock synchronous mode, and FIFO selected)     */
10031         __I  uint8_t   MPB      :  1;                /*!< Multi-processor bit flag(Valid only in asynchronous mode with
10032                                                             SMR.MP=1 and FIFO selected) It can read multi-processor bit
10033                                                             corresponded to serial receive data(RDATA[8:0])                    */
10034         __I  uint8_t   DR       :  1;                /*!< Receive data ready flag(It is same as SSR.DR)                        */
10035         __I  uint8_t   PER      :  1;                /*!< Parity error flag                                                    */
10036         __I  uint8_t   FER      :  1;                /*!< Framing error flag                                                   */
10037         __I  uint8_t   ORER     :  1;                /*!< Overrun error flag(It is same as SSR.ORER)                           */
10038         __I  uint8_t   RDF      :  1;                /*!< Receive FIFO data full flag(It is same as SSR.RDF)                   */
10039       } FRDRH_b;                                     /*!< BitSize                                                              */
10040     };
10041 
10042     union {
10043       __I  uint8_t   RDRH;                           /*!< Receive Data Register High byte.                                     */
10044 
10045       struct {
10046         __I  uint8_t   RDRH     :  8;               /*!< RDRH is an 8-bit register that stores receive data high byte.         */
10047       } RDRH_b;                                     /*!< BitSize                                                               */
10048     };
10049   };
10050 
10051   union {
10052     union {
10053       __I  uint8_t   FRDRL;                        /*!< Receive FIFO Data Register (stores Lower byte)                         */
10054         struct {
10055         __I  uint8_t   RDAT     :  8;              /*!< Serial receive data store 8-bit (Valid only in asynchronous mode
10056                                                      (including multi-processor) or clock synchronous mode, and FIFO selected) */
10057         } FRDRL_b;                                 /*!< BitSize                                                                */
10058     };
10059 
10060     union {
10061       __I  uint8_t   RDRL;                         /*!< Receive Data Register low byte.                                        */
10062         struct {
10063         __I  uint8_t   RDRL     :  8;              /*!< RDRL is an 8-bit register that stores receive data low byte.           */
10064         } RDRL_b;                                  /*!< BitSize                                                                */
10065     };
10066   };
10067 
10068   union {
10069     __IO uint8_t   MDDR;                            /*!< Modulation Duty Register                                              */
10070 
10071     struct {
10072       __IO uint8_t   MDDR       :  8;               /*!< MDDR corrects the bit rate adjusted by the BRR register.              */
10073     } MDDR_b;                                       /*!< BitSize                                                               */
10074   };
10075 
10076   union {
10077     __IO uint8_t   DCCR;                            /*!< Data Compare Match Control Register                                   */
10078 
10079     struct {
10080       __IO uint8_t   DCMF       :  1;               /*!< Data Compare Match Flag                                               */
10081            uint8_t              :  2;
10082       __IO uint8_t   DPER       :  1;               /*!< Data Compare Match Parity Error Flag                                  */
10083       __IO uint8_t   DFER       :  1;               /*!< Data Compare Match Framing Error Flag                                 */
10084            uint8_t              :  1;
10085       __IO uint8_t   IDSEL      :  1;               /*!< ID frame select Bit(Valid only in asynchronous mode(including
10086                                                          multi-processor)                                                      */
10087       __IO uint8_t   DCME       :  1;               /*!< Data Compare Match Enable(Valid only in asynchronous mode(including
10088                                                          multi-processor)                                                      */
10089     } DCCR_b;                                       /*!< BitSize                                                               */
10090   };
10091 
10092   union {
10093     __IO uint16_t  FCR;                             /*!< FIFO Control Register                                                 */
10094 
10095     struct {
10096       __IO uint16_t  FM         :  1;               /*!< FIFO Mode Select(Valid only in asynchronous mode(including multi-processor
10097                                                          ) or clock synchronous mode)                                          */
10098       __IO uint16_t  RFRST      :  1;               /*!< Receive FIFO Data Register Reset(Valid only in FCR.FM=1)              */
10099       __IO uint16_t  TFRST      :  1;               /*!< Transmit FIFO Data Register Reset(Valid only in FCR.FM=1)             */
10100       __IO uint16_t  DRES       :  1;               /*!< Receive data ready error select bit(When detecting a reception
10101                                                          data ready, the interrupt request is selected.)                       */
10102       __IO uint16_t  TTRG       :  4;               /*!< Transmit FIFO data trigger number(Valid only in asynchronous
10103                                                          mode(including multi-processor) or clock synchronous mode)            */
10104       __IO uint16_t  RTRG       :  4;               /*!< Receive FIFO data trigger number                                      */
10105       __IO uint16_t  RSTRG      :  4;               /*!< RTS# Output Active Trigger Number Select(Valid only in asynchronous
10106                                                          mode(including multi-processor) or clock synchronous mode)            */
10107     } FCR_b;                                        /*!< BitSize                                                               */
10108   };
10109 
10110   union {
10111     __I  uint16_t  FDR;                             /*!< FIFO Data Count Register                                              */
10112 
10113     struct {
10114       __I  uint16_t  R          :  5;               /*!< Receive FIFO Data CountIndicate the quantity of receive data
10115                                                          stored in FRDRH and FRDRL(Valid only in asynchronous mode(including
10116                                                           multi-processor) or clock synchronous mode, while FCR.FM=1)          */
10117            uint16_t             :  3;
10118       __I  uint16_t  T          :  5;               /*!< Transmit FIFO Data CountIndicate the quantity of non-transmit
10119                                                          data stored in FTDRH and FTDRL(Valid only in asynchronous mode(including
10120                                                           multi-processor) or clock synchronous mode, while FCR.FM=1)          */
10121     } FDR_b;                                        /*!< BitSize                                                               */
10122   };
10123 
10124   union {
10125     __I  uint16_t  LSR;                             /*!< Line Status Register                                                  */
10126 
10127     struct {
10128       __I  uint16_t  ORER       :  1;               /*!< Overrun Error Flag (Valid only in asynchronous mode(including
10129                                                          multi-processor) or clock synchronous mode, and FIFO selected)        */
10130            uint16_t             :  1;
10131       __I  uint16_t  FNUM       :  5;               /*!< Framing Error CountIndicates the quantity of data with a framing
10132                                                          error among the receive data stored in the receive FIFO data
10133                                                           register (FRDRH and FRDRL).                                          */
10134            uint16_t             :  1;
10135       __I  uint16_t  PNUM       :  5;               /*!< Parity Error CountIndicates the quantity of data with a parity
10136                                                          error among the receive data stored in the receive FIFO data
10137                                                           register (FRDRH and FRDRL).                                          */
10138     } LSR_b;                                        /*!< BitSize                                                               */
10139   };
10140 
10141   union {
10142     __IO uint16_t  CDR;                             /*!< Compare Match Data Register                                           */
10143 
10144     struct {
10145       __IO uint16_t  CMPD       :  9;               /*!< Compare Match DataCompare data pattern for address match wake-up
10146                                                          function                                                              */
10147     } CDR_b;                                        /*!< BitSize                                                               */
10148   };
10149 
10150   union {
10151     __IO uint8_t   SPTR;                            /*!< Serial Port Register                                                  */
10152 
10153     struct {
10154       __I  uint8_t   RXDMON     :  1;               /*!< Serial input data monitor bit(The state of the RXD terminal
10155                                                          is shown.)                                                            */
10156       __IO uint8_t   SPB2DT     :  1;               /*!< Serial port break data select bit(The output level of TxD terminal
10157                                                          is selected when SCR.TE = "0".)                                       */
10158       __IO uint8_t   SPB2IO     :  1;               /*!< Serial port break I/O bit(It's selected whether the value of
10159                                                          SPB2DT is output to TxD terminal.)                                    */
10160     } SPTR_b;                                       /*!< BitSize                                                               */
10161   };
10162 } R_SCI0_Type;
10163 
10164 
10165 
10166 
10167 /* ================================================================================ */
10168 /* ================                     R_RSPI0                    ================ */
10169 /* ================================================================================ */
10170 
10171 
10172 /**
10173   * @brief Serial Peripheral Interface 0 (R_RSPI0)
10174   */
10175 
10176 typedef struct {                                    /*!< R_RSPI0 Structure                                                     */
10177 
10178   union {
10179     __IO uint8_t   SPCR;                            /*!< RSPI Control Register                                                 */
10180 
10181     struct {
10182       __IO uint8_t   SPMS       :  1;               /*!< RSPI Mode Select                                                      */
10183       __IO uint8_t   TXMD       :  1;               /*!< Communications Operating Mode Select                                  */
10184       __IO uint8_t   MODFEN     :  1;               /*!< Mode Fault Error Detection Enable                                     */
10185       __IO uint8_t   MSTR       :  1;               /*!< RSPI Master/Slave Mode Select                                         */
10186       __IO uint8_t   SPEIE      :  1;               /*!< RSPI Error Interrupt Enable                                           */
10187       __IO uint8_t   SPTIE      :  1;               /*!< Transmit Buffer Empty Interrupt Enable                                */
10188       __IO uint8_t   SPE        :  1;               /*!< RSPI Function Enable                                                  */
10189       __IO uint8_t   SPRIE      :  1;               /*!< RSPI Receive Buffer Full Interrupt Enable                             */
10190     } SPCR_b;                                       /*!< BitSize                                                               */
10191   };
10192 
10193   union {
10194     __IO uint8_t   SSLP;                            /*!< RSPI Slave Select Polarity Register                                   */
10195 
10196     struct {
10197       __IO uint8_t   SSL0P      :  1;               /*!< SSL0 Signal Polarity Setting                                          */
10198       __IO uint8_t   SSL1P      :  1;               /*!< SSL1 Signal Polarity Setting                                          */
10199       __IO uint8_t   SSL2P      :  1;               /*!< SSL2 Signal Polarity Setting                                          */
10200       __IO uint8_t   SSL3P      :  1;               /*!< SSL3 Signal Polarity Setting                                          */
10201     } SSLP_b;                                       /*!< BitSize                                                               */
10202   };
10203 
10204   union {
10205     __IO uint8_t   SPPCR;                           /*!< RSPI Pin Control Register                                             */
10206 
10207     struct {
10208       __IO uint8_t   SPLP       :  1;               /*!< RSPI Loopback                                                         */
10209       __IO uint8_t   SPLP2      :  1;               /*!< RSPI Loopback 2                                                       */
10210            uint8_t              :  2;
10211       __IO uint8_t   MOIFV      :  1;               /*!< MOSI Idle Fixed Value                                                 */
10212       __IO uint8_t   MOIFE      :  1;               /*!< MOSI Idle Value Fixing Enable                                         */
10213     } SPPCR_b;                                      /*!< BitSize                                                               */
10214   };
10215 
10216   union {
10217     __IO uint8_t   SPSR;                            /*!< RSPI Status Register                                                  */
10218 
10219     struct {
10220       __IO uint8_t   OVRF       :  1;               /*!< Overrun Error Flag                                                    */
10221       __IO uint8_t   IDLNF      :  1;               /*!< RSPI Idle Flag                                                        */
10222       __IO uint8_t   MODF       :  1;               /*!< Mode Fault Error Flag                                                 */
10223       __IO uint8_t   PERF       :  1;               /*!< Parity Error Flag                                                     */
10224       __IO uint8_t   UDRF       :  1;               /*!< Underrun Error Flag(When MODF is 0, This bit is invalid.)             */
10225       __IO uint8_t   SPTEF      :  1;               /*!< RSPI Transmit Buffer Empty Flag                                       */
10226            uint8_t              :  1;
10227       __IO uint8_t   SPRF       :  1;               /*!< RSPI Receive Buffer Full Flag                                         */
10228     } SPSR_b;                                       /*!< BitSize                                                               */
10229   };
10230 
10231   union {
10232     union {
10233       __IO uint32_t  SPDR;                          /*!< RSPI Data Register                                                    */
10234 
10235       struct {
10236         __IO uint32_t  SPDR     : 32;               /*!< SPDR is the interface with the buffers that hold data for transmission
10237                                                          and reception by the RSPI.When accessing in word (SPDCR.SPLW=1),
10238                                                           access SPDR.                                                         */
10239       } SPDR_b;                                     /*!< BitSize                                                               */
10240     };
10241 
10242     union {
10243       __IO uint16_t  SPDR_HA;                       /*!< RSPI Data Register ( halfword access )                                */
10244 
10245       struct {
10246         __IO uint16_t  SPDR_HA  : 16;               /*!< SPDR is the interface with the buffers that hold data for transmission
10247                                                          and reception by the RSPI.When accessing in halfword (SPDCR.SPLW=0),
10248                                                           access SPDR_HA.                                                      */
10249       } SPDR_HA_b;                                  /*!< BitSize                                                               */
10250     };
10251   };
10252 
10253   union {
10254     __IO uint8_t   SPSCR;                           /*!< RSPI Sequence Control Register                                        */
10255 
10256     struct {
10257       __IO uint8_t   SPSLN      :  3;               /*!< RSPI Sequence Length SpecificationThe order in which the SPCMD0
10258                                                          to SPCMD07 registers are to be referenced is changed in accordance
10259                                                           with the sequence length that is set in these bits. The relationship
10260                                                           among the setting of these bits, sequence length, and SPCMD0
10261                                                           to SPCMD7 registers referenced by the RSPI is shown above. However,
10262                                                           the RSPI in slave mode always references SPCMD0.                     */
10263     } SPSCR_b;                                      /*!< BitSize                                                               */
10264   };
10265 
10266   union {
10267     __I  uint8_t   SPSSR;                           /*!< RSPI Sequence Status Register                                         */
10268 
10269     struct {
10270       __I  uint8_t   SPCP       :  3;               /*!< RSPI Command Pointer                                                  */
10271            uint8_t              :  1;
10272       __I  uint8_t   SPRCM      :  3;               /*!< RSPI Error Command                                                    */
10273     } SPSSR_b;                                      /*!< BitSize                                                               */
10274   };
10275 
10276   union {
10277     __IO uint8_t   SPBR;                            /*!< RSPI Bit Rate Register                                                */
10278 
10279     struct {
10280       __IO uint8_t   SPR        :  8;               /*!< SPBR sets the bit rate in master mode.                                */
10281     } SPBR_b;                                       /*!< BitSize                                                               */
10282   };
10283 
10284   union {
10285     __IO uint8_t   SPDCR;                           /*!< RSPI Data Control Register                                            */
10286 
10287     struct {
10288       __IO uint8_t   SPFC       :  2;               /*!< Number of Frames Specification                                        */
10289            uint8_t              :  2;
10290       __IO uint8_t   SPRDTD     :  1;               /*!< RSPI Receive/Transmit Data Selection                                  */
10291       __IO uint8_t   SPLW       :  1;               /*!< RSPI Long-Word Access/Word Access Specification                       */
10292     } SPDCR_b;                                      /*!< BitSize                                                               */
10293   };
10294 
10295   union {
10296     __IO uint8_t   SPCKD;                           /*!< RSPI Clock Delay Register                                             */
10297 
10298     struct {
10299       __IO uint8_t   SCKDL      :  3;               /*!< RSPCK Delay Setting                                                   */
10300     } SPCKD_b;                                      /*!< BitSize                                                               */
10301   };
10302 
10303   union {
10304     __IO uint8_t   SSLND;                           /*!< RSPI Slave Select Negation Delay Register                             */
10305 
10306     struct {
10307       __IO uint8_t   SLNDL      :  3;               /*!< SSL Negation Delay Setting                                            */
10308     } SSLND_b;                                      /*!< BitSize                                                               */
10309   };
10310 
10311   union {
10312     __IO uint8_t   SPND;                            /*!< RSPI Next-Access Delay Register                                       */
10313 
10314     struct {
10315       __IO uint8_t   SPNDL      :  3;               /*!< RSPI Next-Access Delay Setting                                        */
10316     } SPND_b;                                       /*!< BitSize                                                               */
10317   };
10318 
10319   union {
10320     __IO uint8_t   SPCR2;                           /*!< RSPI Control Register 2                                               */
10321 
10322     struct {
10323       __IO uint8_t   SPPE       :  1;               /*!< Parity Enable                                                         */
10324       __IO uint8_t   SPOE       :  1;               /*!< Parity Mode                                                           */
10325       __IO uint8_t   SPIIE      :  1;               /*!< RSPCK Auto-Stop Function Enable                                       */
10326       __IO uint8_t   PTE        :  1;               /*!< RSPI Idle Interrupt Enable                                            */
10327       __IO uint8_t   SCKASE     :  1;               /*!< Parity Self-Testing                                                   */
10328     } SPCR2_b;                                      /*!< BitSize                                                               */
10329   };
10330 
10331   union {
10332     __IO uint16_t  SPCMDn[8];                       /*!< RSPI Command Register %s                                              */
10333 
10334     struct {
10335       __IO uint16_t  CPHA       :  1;               /*!< RSPCK Phase Setting                                                   */
10336       __IO uint16_t  CPOL       :  1;               /*!< RSPCK Polarity Setting                                                */
10337       __IO uint16_t  BRDV       :  2;               /*!< Bit Rate Division Setting                                             */
10338       __IO uint16_t  SSLA       :  3;               /*!< SSL Signal Assertion Setting                                          */
10339       __IO uint16_t  SSLKP      :  1;               /*!< SSL Signal Level Keeping                                              */
10340       __IO uint16_t  SPB        :  4;               /*!< RSPI Data Length Setting                                              */
10341       __IO uint16_t  LSBF       :  1;               /*!< RSPI LSB First                                                        */
10342       __IO uint16_t  SPNDEN     :  1;               /*!< RSPI Next-Access Delay Enable                                         */
10343       __IO uint16_t  SLNDEN     :  1;               /*!< SSL Negation Delay Setting Enable                                     */
10344       __IO uint16_t  SCKDEN     :  1;               /*!< RSPCK Delay Setting Enable                                            */
10345     } SPCMDn_b[8];                                  /*!< BitSize                                                               */
10346   };
10347 
10348   union {
10349     __IO uint8_t   SPDCR2;                          /*!< RSPI swap setting bit.                                                */
10350 
10351     struct {
10352       __IO uint8_t   BYSW        :  1;              /*!< BitSize                                                               */
10353     } SPDCR2_b;
10354   };
10355 } R_RSPI0_Type;
10356 
10357 
10358 /* ================================================================================ */
10359 /* ================                      R_CRC                     ================ */
10360 /* ================================================================================ */
10361 
10362 
10363 /**
10364   * @brief CRC Calculator (R_CRC)
10365   */
10366 
10367 typedef struct {                                    /*!< R_CRC Structure                                                       */
10368 
10369   union {
10370     __IO uint8_t   CRCCR0;                          /*!< CRC Control Register0                                                 */
10371 
10372     struct {
10373       __IO uint8_t   GPS        :  3;               /*!< CRC Generating Polynomial Switching                                   */
10374            uint8_t              :  3;
10375       __IO uint8_t   LMS        :  1;               /*!< CRC Calculation Switching                                             */
10376       __O  uint8_t   DORCIR     :  1;               /*!< CRCDOR Register Clear                                                 */
10377     } CRCCR0_b;                                     /*!< BitSize                                                               */
10378   };
10379 
10380   union {
10381     __IO uint8_t   CRCCR1;                          /*!< CRC Control Register1                                                 */
10382 
10383     struct {
10384            uint8_t              :  6;
10385       __IO uint8_t   CRCSWR     :  1;               /*!< Snoop-on-write/read switch bit                                        */
10386       __IO uint8_t   CRCSEN     :  1;               /*!< Snoop enable bit                                                      */
10387     } CRCCR1_b;                                     /*!< BitSize                                                               */
10388   };
10389 
10390   union {
10391     __I  uint16_t  RESERVED;
10392 
10393     union {
10394       __IO uint32_t  CRCDIR;                        /*!< CRC Data Input Register                                               */
10395 
10396       struct {
10397         __IO uint32_t  CRCDIR   : 32;               /*!< Calculation input Data (Case of CRC-32, CRC-32C )                     */
10398       } CRCDIR_b;                                   /*!< BitSize                                                               */
10399     };
10400     __I  uint16_t  RESERVED1;
10401 
10402     union {
10403       __IO uint8_t   CRCDIR_BY;                     /*!< CRC Data Input Register (byte access)                                 */
10404 
10405       struct {
10406         __IO uint8_t   CRCDIR_BY:  8;               /*!< Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT
10407                                                          )                                                                     */
10408       } CRCDIR_BY_b;                                /*!< BitSize                                                               */
10409     };
10410   };
10411 
10412   union {
10413     union {
10414       __IO uint32_t  CRCDOR;                        /*!< CRC Data Output Register                                              */
10415 
10416       struct {
10417         __IO uint32_t  CRCDOR   : 32;               /*!< Calculation output Data (Case of CRC-32, CRC-32C )                    */
10418       } CRCDOR_b;                                   /*!< BitSize                                                               */
10419     };
10420 
10421     union {
10422       __IO uint16_t  CRCDOR_HA;                     /*!< CRC Data Output Register (halfword access)                            */
10423 
10424       struct {
10425         __IO uint16_t  CRCDOR_HA: 16;               /*!< Calculation output Data (Case of CRC-16 or CRC-CCITT )                */
10426       } CRCDOR_HA_b;                                /*!< BitSize                                                               */
10427     };
10428 
10429     union {
10430       __IO uint8_t   CRCDOR_BY;                     /*!< CRC Data Output Register (Low Upper Byte)                             */
10431 
10432       struct {
10433         __IO uint8_t   CRCDOR_BY:  8;               /*!< Calculation output Data (Case of CRC-8 )                              */
10434       } CRCDOR_BY_b;                                /*!< BitSize                                                               */
10435     };
10436   };
10437 
10438   union {
10439     __IO uint16_t  CRCSAR;                          /*!< Snoop Address Register                                                */
10440 
10441     struct {
10442       __IO uint16_t  CRCSA      : 14;               /*!< snoop address bitSet the I/O register address to snoop                */
10443     } CRCSAR_b;                                     /*!< BitSize                                                               */
10444   };
10445 } R_CRC_Type;
10446 
10447 
10448 /* ================================================================================ */
10449 /* ================                     R_GPTB0                    ================ */
10450 /* ================================================================================ */
10451 
10452 
10453 /**
10454   * @brief General PWM Timer 0 (Type-B) (R_GPTB0)
10455   */
10456 
10457 typedef struct {                                    /*!< R_GPTB0 Structure                                                     */
10458 
10459   union {
10460     __IO uint32_t  GTWP;                            /*!< General PWM Timer Write-Protection Register                           */
10461 
10462     struct {
10463       __IO uint32_t  WP         :  1;               /*!< Register Write Disable                                                */
10464            uint32_t             :  7;
10465       __O  uint32_t  PRKEY      :  8;               /*!< GTWP Key Code                                                         */
10466       __IO uint32_t             :  16;
10467     } GTWP_b;                                       /*!< BitSize                                                               */
10468   };
10469 
10470   union {
10471     __IO uint32_t  GTSTR;                           /*!< General PWM Timer Software Start Register                             */
10472 
10473     struct {
10474       __IO uint32_t  CSTRT0     :  1;               /*!< Channel 0 GTCNT Count StartRead data shows each channel's counter
10475                                                          status (GTCR.CST bit). 0 means counter stop. 1 means counter
10476                                                           running.                                                             */
10477       __IO uint32_t  CSTRT1     :  1;               /*!< Channel 1 GTCNT Count StartRead data shows each channel's counter
10478                                                          status (GTCR.CST bit). 0 means counter stop. 1 means counter
10479                                                           running.                                                             */
10480       __IO uint32_t  CSTRT2     :  1;               /*!< Channel 2 GTCNT Count StartRead data shows each channel's counter
10481                                                          status (GTCR.CST bit). 0 means counter stop. 1 means counter
10482                                                           running.                                                             */
10483       __IO uint32_t  CSTRT3     :  1;               /*!< Channel 3 GTCNT Count StartRead data shows each channel's counter
10484                                                          status (GTCR.CST bit). 0 means counter stop. 1 means counter
10485                                                           running.                                                             */
10486       __IO uint32_t  CSTRT4     :  1;               /*!< Channel 4 GTCNT Count StartRead data shows each channel's counter
10487                                                          status (GTCR.CST bit). 0 means counter stop. 1 means counter
10488                                                           running.                                                             */
10489       __IO uint32_t  CSTRT5     :  1;               /*!< Channel 5 GTCNT Count StartRead data shows each channel's counter
10490                                                          status (GTCR.CST bit). 0 means counter stop. 1 means counter
10491                                                           running.                                                             */
10492       __IO uint32_t  CSTRT6     :  1;               /*!< Channel 6 GTCNT Count StartRead data shows each channel's counter
10493                                                          status (GTCR.CST bit). 0 means counter stop. 1 means counter
10494                                                           running.                                                             */
10495       __IO uint32_t  CSTRT7     :  1;               /*!< Channel 7 GTCNT Count StartRead data shows each channel's counter
10496                                                          status (GTCR.CST bit). 0 means counter stop. 1 means counter
10497                                                           running.                                                             */
10498       __IO uint32_t  CSTRT8     :  1;               /*!< Channel 8 GTCNT Count StartRead data shows each channel's counter
10499                                                          status (GTCR.CST bit). 0 means counter stop. 1 means counter
10500                                                           running.                                                             */
10501       __IO uint32_t  CSTRT9     :  1;               /*!< Channel 9 GTCNT Count StartRead data shows each channel's counter
10502                                                          status (GTCR.CST bit). 0 means counter stop. 1 means counter
10503                                                           running.                                                             */
10504       __IO uint32_t  CSTRT10    :  1;               /*!< Channel 10 GTCNT Count StartRead data shows each channel's counter
10505                                                          status (GTCR.CST bit). 0 means counter stop. 1 means counter
10506                                                           running.                                                             */
10507       __IO uint32_t  CSTRT11    :  1;               /*!< Channel 11 GTCNT Count StartRead data shows each channel's counter
10508                                                          status (GTCR.CST bit). 0 means counter stop. 1 means counter
10509                                                           running.                                                             */
10510       __IO uint32_t  CSTRT12    :  1;               /*!< Channel 12 GTCNT Count StartRead data shows each channel's counter
10511                                                          status (GTCR.CST bit). 0 means counter stop. 1 means counter
10512                                                           running.                                                             */
10513       __IO uint32_t  CSTRT13    :  1;               /*!< Channel 13 GTCNT Count StartRead data shows each channel's counter
10514                                                          status (GTCR.CST bit). 0 means counter stop. 1 means counter
10515                                                           running.                                                             */
10516       __IO uint32_t             :  18;
10517     } GTSTR_b;                                      /*!< BitSize                                                               */
10518   };
10519 
10520   union {
10521     __IO uint32_t  GTSTP;                           /*!< General PWM Timer Software Stop Register                              */
10522 
10523     struct {
10524       __IO uint32_t  CSTOP0     :  1;               /*!< Channel 0 GTCNT Count StopRead data shows each channel's counter
10525                                                          status (GTCR.CST bit). 0 means counter running. 1 means counter
10526                                                           stop.                                                                */
10527       __IO uint32_t  CSTOP1     :  1;               /*!< Channel 1 GTCNT Count StopRead data shows each channel's counter
10528                                                          status (GTCR.CST bit). 0 means counter running. 1 means counter
10529                                                           stop.                                                                */
10530       __IO uint32_t  CSTOP2     :  1;               /*!< Channel 2 GTCNT Count StopRead data shows each channel's counter
10531                                                          status (GTCR.CST bit). 0 means counter running. 1 means counter
10532                                                           stop.                                                                */
10533       __IO uint32_t  CSTOP3     :  1;               /*!< Channel 3 GTCNT Count StopRead data shows each channel's counter
10534                                                          status (GTCR.CST bit). 0 means counter running. 1 means counter
10535                                                           stop.                                                                */
10536       __IO uint32_t  CSTOP4     :  1;               /*!< Channel 4 GTCNT Count StopRead data shows each channel's counter
10537                                                          status (GTCR.CST bit). 0 means counter running. 1 means counter
10538                                                           stop.                                                                */
10539       __IO uint32_t  CSTOP5     :  1;               /*!< Channel 5 GTCNT Count StopRead data shows each channel's counter
10540                                                          status (GTCR.CST bit). 0 means counter running. 1 means counter
10541                                                           stop.                                                                */
10542       __IO uint32_t  CSTOP6     :  1;               /*!< Channel 6 GTCNT Count StopRead data shows each channel's counter
10543                                                          status (GTCR.CST bit). 0 means counter running. 1 means counter
10544                                                           stop.                                                                */
10545       __IO uint32_t  CSTOP7     :  1;               /*!< Channel 7 GTCNT Count StopRead data shows each channel's counter
10546                                                          status (GTCR.CST bit). 0 means counter running. 1 means counter
10547                                                           stop.                                                                */
10548       __IO uint32_t  CSTOP8     :  1;               /*!< Channel 8 GTCNT Count StopRead data shows each channel's counter
10549                                                          status (GTCR.CST bit). 0 means counter running. 1 means counter
10550                                                           stop.                                                                */
10551       __IO uint32_t  CSTOP9     :  1;               /*!< Channel 9 GTCNT Count StopRead data shows each channel's counter
10552                                                          status (GTCR.CST bit). 0 means counter running. 1 means counter
10553                                                           stop.                                                                */
10554       __IO uint32_t  CSTOP10    :  1;               /*!< Channel 10 GTCNT Count StopRead data shows each channel's counter
10555                                                          status (GTCR.CST bit). 0 means counter running. 1 means counter
10556                                                           stop.                                                                */
10557       __IO uint32_t  CSTOP11    :  1;               /*!< Channel 11 GTCNT Count StopRead data shows each channel's counter
10558                                                          status (GTCR.CST bit). 0 means counter running. 1 means counter
10559                                                           stop.                                                                */
10560       __IO uint32_t  CSTOP12    :  1;               /*!< Channel 12 GTCNT Count StopRead data shows each channel's counter
10561                                                          status (GTCR.CST bit). 0 means counter running. 1 means counter
10562                                                           stop.                                                                */
10563       __IO uint32_t  CSTOP13    :  1;               /*!< Channel 13 GTCNT Count StopRead data shows each channel's counter
10564                                                          status (GTCR.CST bit). 0 means counter running. 1 means counter
10565                                                           stop.                                                                */
10566       __IO uint32_t             :  18;
10567     } GTSTP_b;                                      /*!< BitSize                                                               */
10568   };
10569 
10570   union {
10571     __O  uint32_t  GTCLR;                           /*!< General PWM Timer Software Clear Register                             */
10572 
10573     struct {
10574       __O  uint32_t  CCLR0      :  1;               /*!< Channel 0 GTCNT Count Clear                                           */
10575       __O  uint32_t  CCLR1      :  1;               /*!< Channel 1 GTCNT Count Clear                                           */
10576       __O  uint32_t  CCLR2      :  1;               /*!< Channel 2 GTCNT Count Clear                                           */
10577       __O  uint32_t  CCLR3      :  1;               /*!< Channel 3 GTCNT Count Clear                                           */
10578       __O  uint32_t  CCLR4      :  1;               /*!< Channel 4 GTCNT Count Clear                                           */
10579       __O  uint32_t  CCLR5      :  1;               /*!< Channel 5 GTCNT Count Clear                                           */
10580       __O  uint32_t  CCLR6      :  1;               /*!< Channel 6 GTCNT Count Clear                                           */
10581       __O  uint32_t  CCLR7      :  1;               /*!< Channel 7 GTCNT Count Clear                                           */
10582       __O  uint32_t  CCLR8      :  1;               /*!< Channel 8 GTCNT Count Clear                                           */
10583       __O  uint32_t  CCLR9      :  1;               /*!< Channel 9 GTCNT Count Clear                                           */
10584       __O  uint32_t  CCLR10     :  1;               /*!< Channel 10 GTCNT Count Clear                                          */
10585       __O  uint32_t  CCLR11     :  1;               /*!< Channel 11 GTCNT Count Clear                                          */
10586       __O  uint32_t  CCLR12     :  1;               /*!< Channel 12 GTCNT Count Clear                                          */
10587       __O  uint32_t  CCLR13     :  1;               /*!< Channel 13 GTCNT Count Clear                                          */
10588       __O uint32_t              :  18;
10589     } GTCLR_b;                                      /*!< BitSize                                                               */
10590   };
10591 
10592   union {
10593     __IO uint32_t  GTSSR;                           /*!< General PWM Timer Start Source Select Register                        */
10594 
10595     struct {
10596       __IO uint32_t  SSGTRGAR   :  1;               /*!< GTETRGA Pin Rising Input Source Counter Start Enable                  */
10597       __IO uint32_t  SSGTRGAF   :  1;               /*!< GTETRGA Pin Falling Input Source Counter Start Enable                 */
10598       __IO uint32_t  SSGTRGBR   :  1;               /*!< GTETRGB Pin Rising Input Source Counter Start Enable                  */
10599       __IO uint32_t  SSGTRGBF   :  1;               /*!< GTETRGB Pin Falling Input Source Counter Start Enable                 */
10600       __IO uint32_t  SSGTRGCR   :  1;               /*!< GTETRGC Pin Rising Input Source Counter Start Enable                  */
10601       __IO uint32_t  SSGTRGCF   :  1;               /*!< GTETRGC Pin Falling Input Source Counter Start Enable                 */
10602       __IO uint32_t  SSGTRGDR   :  1;               /*!< GTETRGD Pin Rising Input Source Counter Start Enable                  */
10603       __IO uint32_t  SSGTRGDF   :  1;               /*!< GTETRGD Pin Falling Input Source Counter Start Enable                 */
10604       __IO uint32_t  SSCARBL    :  1;               /*!< GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter
10605                                                          Start Enable                                                          */
10606       __IO uint32_t  SSCARBH    :  1;               /*!< GTIOCA Pin Rising Input during GTIOCB Value High Source Counter
10607                                                          Start Enable                                                          */
10608       __IO uint32_t  SSCAFBL    :  1;               /*!< GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter
10609                                                          Start Enable                                                          */
10610       __IO uint32_t  SSCAFBH    :  1;               /*!< GTIOCA Pin Falling Input during GTIOCB Value High Source Counter
10611                                                          Start Enable                                                          */
10612       __IO uint32_t  SSCBRAL    :  1;               /*!< GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter
10613                                                          Start Enable                                                          */
10614       __IO uint32_t  SSCBRAH    :  1;               /*!< GTIOCB Pin Rising Input during GTIOCA Value High Source Counter
10615                                                          Start Enable                                                          */
10616       __IO uint32_t  SSCBFAL    :  1;               /*!< GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter
10617                                                          Start Enable                                                          */
10618       __IO uint32_t  SSCBFAH    :  1;               /*!< GTIOCB Pin Falling Input during GTIOCA Value High Source Counter
10619                                                          Start Enable                                                          */
10620       __IO uint32_t  SSELCA     :  1;               /*!< ELCA Event Source Counter Start Enable                                */
10621       __IO uint32_t  SSELCB     :  1;               /*!< ELCB Event Source Counter Start Enable                                */
10622       __IO uint32_t  SSELCC     :  1;               /*!< ELCC Event Source Counter Start Enable                                */
10623       __IO uint32_t  SSELCD     :  1;               /*!< ELCD Event Source Counter Start Enable                                */
10624       __IO uint32_t  SSELCE     :  1;               /*!< ELCE Event Source Counter Start Enable                                */
10625       __IO uint32_t  SSELCF     :  1;               /*!< ELCF Event Source Counter Start Enable                                */
10626       __IO uint32_t  SSELCG     :  1;               /*!< ELCG Event Source Counter Start Enable                                */
10627       __IO uint32_t  SSELCH     :  1;               /*!< ELCH Event Source Counter Start Enable                                */
10628            uint32_t             :  7;
10629       __IO uint32_t  CSTRT      :  1;               /*!< Software Source Counter Start Enable                                  */
10630     } GTSSR_b;                                      /*!< BitSize                                                               */
10631   };
10632 
10633   union {
10634     __IO uint32_t  GTPSR;                           /*!< General PWM Timer Stop Source Select Register                         */
10635 
10636     struct {
10637       __IO uint32_t  PSGTRGAR   :  1;               /*!< GTETRGA Pin Rising Input Source Counter Stop Enable                   */
10638       __IO uint32_t  PSGTRGAF   :  1;               /*!< GTETRGA Pin Falling Input Source Counter Stop Enable                  */
10639       __IO uint32_t  PSGTRGBR   :  1;               /*!< GTETRGB Pin Rising Input Source Counter Stop Enable                   */
10640       __IO uint32_t  PSGTRGBF   :  1;               /*!< GTETRGB Pin Falling Input Source Counter Stop Enable                  */
10641       __IO uint32_t  PSGTRGCR   :  1;               /*!< GTETRGC Pin Rising Input Source Counter Stop Enable                   */
10642       __IO uint32_t  PSGTRGCF   :  1;               /*!< GTETRGC Pin Falling Input Source Counter Stop Enable                  */
10643       __IO uint32_t  PSGTRGDR   :  1;               /*!< GTETRGD Pin Rising Input Source Counter Stop Enable                   */
10644            uint32_t             :  1;
10645       __IO uint32_t  PSCARBL    :  1;               /*!< GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter
10646                                                          Stop Enable                                                           */
10647       __IO uint32_t  PSCARBH    :  1;               /*!< GTIOCA Pin Rising Input during GTIOCB Value High Source Counter
10648                                                          Stop Enable                                                           */
10649       __IO uint32_t  PSCAFBL    :  1;               /*!< GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter
10650                                                          Stop Enable                                                           */
10651       __IO uint32_t  PSCAFBH    :  1;               /*!< GTIOCA Pin Falling Input during GTIOCB Value High Source Counter
10652                                                          Stop Enable                                                           */
10653       __IO uint32_t  PSCBRAL    :  1;               /*!< GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter
10654                                                          Stop Enable                                                           */
10655       __IO uint32_t  PSCBRAH    :  1;               /*!< GTIOCB Pin Rising Input during GTIOCA Value High Source Counter
10656                                                          Stop Enable                                                           */
10657       __IO uint32_t  PSCBFAL    :  1;               /*!< GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter
10658                                                          Stop Enable                                                           */
10659       __IO uint32_t  PSCBFAH    :  1;               /*!< GTIOCB Pin Falling Input during GTIOCA Value High Source Counter
10660                                                          Stop Enable                                                           */
10661       __IO uint32_t  PSELCA     :  1;               /*!< ELCA Event Source Counter Stop Enable                                 */
10662       __IO uint32_t  PSELCB     :  1;               /*!< ELCB Event Source Counter Stop Enable                                 */
10663       __IO uint32_t  PSELCC     :  1;               /*!< ELCC Event Source Counter Stop Enable                                 */
10664       __IO uint32_t  PSELCD     :  1;               /*!< ELCD Event Source Counter Stop Enable                                 */
10665       __IO uint32_t  PSELCE     :  1;               /*!< ELCE Event Source Counter Stop Enable                                 */
10666       __IO uint32_t  PSELCF     :  1;               /*!< ELCF Event Source Counter Stop Enable                                 */
10667       __IO uint32_t  PSELCG     :  1;               /*!< ELCG Event Source Counter Stop Enable                                 */
10668       __IO uint32_t  PSELCH     :  1;               /*!< ELCH Event Source Counter Stop Enable                                 */
10669            uint32_t             :  7;
10670       __IO uint32_t  CSTOP      :  1;               /*!< Software Source Counter Stop Enable                                   */
10671     } GTPSR_b;                                      /*!< BitSize                                                               */
10672   };
10673 
10674   union {
10675     __IO uint32_t  GTCSR;                           /*!< General PWM Timer Clear Source Select Register                        */
10676 
10677     struct {
10678       __IO uint32_t  CSGTRGAR   :  1;               /*!< GTETRGA Pin Rising Input Source Counter Clear Enable                  */
10679       __IO uint32_t  CSGTRGAF   :  1;               /*!< GTETRGA Pin Falling Input Source Counter Clear Enable                 */
10680       __IO uint32_t  CSGTRGBR   :  1;               /*!< GTETRGB Pin Rising Input Source Counter Clear Enable                  */
10681       __IO uint32_t  CSGTRGBF   :  1;               /*!< GTETRGB Pin Falling Input Source Counter Clear Enable                 */
10682       __IO uint32_t  CSGTRGCR   :  1;               /*!< GTETRGC Pin Rising Input Source Counter Clear Enable                  */
10683       __IO uint32_t  CSGTRGCF   :  1;               /*!< GTETRGC Pin Falling Input Source Counter Clear Enable                 */
10684       __IO uint32_t  CSGTRGDR   :  1;               /*!< GTETRGD Pin Rising Input Source Counter Clear Enable                  */
10685       __IO uint32_t  CSGTRGDF   :  1;               /*!< GTETRGD Pin Falling Input Source Counter Clear Enable                 */
10686       __IO uint32_t  CSCARBL    :  1;               /*!< GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter
10687                                                          Clear Enable                                                          */
10688       __IO uint32_t  CSCARBH    :  1;               /*!< GTIOCA Pin Rising Input during GTIOCB Value High Source Counter
10689                                                          Clear Enable                                                          */
10690       __IO uint32_t  CSCAFBL    :  1;               /*!< GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter
10691                                                          Clear Enable                                                          */
10692       __IO uint32_t  CSCAFBH    :  1;               /*!< GTIOCA Pin Falling Input during GTIOCB Value High Source Counter
10693                                                          Clear Enable                                                          */
10694       __IO uint32_t  CSCBRAL    :  1;               /*!< GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter
10695                                                          Clear Enable                                                          */
10696       __IO uint32_t  CSCBRAH    :  1;               /*!< GTIOCB Pin Rising Input during GTIOCA Value High Source Counter
10697                                                          Clear Enable                                                          */
10698       __IO uint32_t  CSCBFAL    :  1;               /*!< GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter
10699                                                          Clear Enable                                                          */
10700       __IO uint32_t  CSCBFAH    :  1;               /*!< GTIOCB Pin Falling Input during GTIOCA Value High Source Counter
10701                                                          Clear Enable                                                          */
10702       __IO uint32_t  CSELCA     :  1;               /*!< ELCA Event Source Counter Clear Enable                                */
10703       __IO uint32_t  CSELCB     :  1;               /*!< ELCB Event Source Counter Clear Enable                                */
10704       __IO uint32_t  CSELCC     :  1;               /*!< ELCC Event Source Counter Clear Enable                                */
10705       __IO uint32_t  CSELCD     :  1;               /*!< ELCD Event Source Counter Clear Enable                                */
10706       __IO uint32_t  CSELCE     :  1;               /*!< ELCE Event Source Counter Clear Enable                                */
10707       __IO uint32_t  CSELCF     :  1;               /*!< ELCF Event Source Counter Clear Enable                                */
10708       __IO uint32_t  CSELCG     :  1;               /*!< ELCG Event Source Counter Clear Enable                                */
10709       __IO uint32_t  CSELCH     :  1;               /*!< ELCH Event Source Counter Clear Enable                                */
10710            uint32_t             :  7;
10711       __IO uint32_t  CCLR       :  1;               /*!< Software Source Counter Clear Enable                                  */
10712     } GTCSR_b;                                      /*!< BitSize                                                               */
10713   };
10714 
10715   union {
10716     __IO uint32_t  GTUPSR;                          /*!< General PWM Timer Up Count Source Select Register                     */
10717 
10718     struct {
10719       __IO uint32_t  USGTRGAR   :  1;               /*!< GTETRGA Pin Rising Input Source Counter Count Up Enable               */
10720       __IO uint32_t  USGTRGAF   :  1;               /*!< GTETRGA Pin Falling Input Source Counter Count Up Enable              */
10721       __IO uint32_t  USGTRGBR   :  1;               /*!< GTETRGB Pin Rising Input Source Counter Count Up Enable               */
10722       __IO uint32_t  USGTRGBF   :  1;               /*!< GTETRGB Pin Falling Input Source Counter Count Up Enable              */
10723       __IO uint32_t  USGTRGCR   :  1;               /*!< GTETRGC Pin Rising Input Source Counter Count Up Enable               */
10724       __IO uint32_t  USGTRGCF   :  1;               /*!< GTETRGC Pin Falling Input Source Counter Count Up Enable              */
10725       __IO uint32_t  USGTRGDR   :  1;               /*!< GTETRGD Pin Rising Input Source Counter Count Up Enable               */
10726       __IO uint32_t  USGTRGDF   :  1;               /*!< GTETRGD Pin Falling Input Source Counter Count Up Enable              */
10727       __IO uint32_t  USCARBL    :  1;               /*!< GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter
10728                                                          Count Up Enable                                                       */
10729       __IO uint32_t  USCARBH    :  1;               /*!< GTIOCA Pin Rising Input during GTIOCB Value High Source Counter
10730                                                          Count Up Enable                                                       */
10731       __IO uint32_t  USCAFBL    :  1;               /*!< GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter
10732                                                          Count Up Enable                                                       */
10733       __IO uint32_t  USCAFBH    :  1;               /*!< GTIOCA Pin Falling Input during GTIOCB Value High Source Counter
10734                                                          Count Up Enable                                                       */
10735       __IO uint32_t  USCBRAL    :  1;               /*!< GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter
10736                                                          Count Up Enable                                                       */
10737       __IO uint32_t  USCBRAH    :  1;               /*!< GTIOCB Pin Rising Input during GTIOCA Value High Source Counter
10738                                                          Count Up Enable                                                       */
10739       __IO uint32_t  USCBFAL    :  1;               /*!< GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter
10740                                                          Count Up Enable                                                       */
10741       __IO uint32_t  USCBFAH    :  1;               /*!< GTIOCB Pin Falling Input during GTIOCA Value High Source Counter
10742                                                          Count Up Enable                                                       */
10743       __IO uint32_t  USELCA     :  1;               /*!< ELCA Event Source Counter Count Up Enable                             */
10744       __IO uint32_t  USELCB     :  1;               /*!< ELCB Event Source Counter Count Up Enable                             */
10745       __IO uint32_t  USELCC     :  1;               /*!< ELCC Event Source Counter Count Up Enable                             */
10746       __IO uint32_t  USELCD     :  1;               /*!< ELCD Event Source Counter Count Up Enable                             */
10747       __IO uint32_t  USELCE     :  1;               /*!< ELCE Event Source Counter Count Up Enable                             */
10748       __IO uint32_t  USELCF     :  1;               /*!< ELCF Event Source Counter Count Up Enable                             */
10749       __IO uint32_t  USELCG     :  1;               /*!< ELCG Event Source Counter Count Up Enable                             */
10750       __IO uint32_t  USELCH     :  1;               /*!< ELCH Event Source Counter Count Up Enable                             */
10751     } GTUPSR_b;                                     /*!< BitSize                                                               */
10752   };
10753 
10754   union {
10755     __IO uint32_t  GTDNSR;                          /*!< General PWM Timer Down Count Source Select Register                   */
10756 
10757     struct {
10758       __IO uint32_t  DSGTRGAR   :  1;               /*!< GTETRGA Pin Rising Input Source Counter Count Down Enable             */
10759       __IO uint32_t  DSGTRGAF   :  1;               /*!< GTETRGA Pin Falling Input Source Counter Count Down Enable            */
10760       __IO uint32_t  DSGTRGBR   :  1;               /*!< GTETRGB Pin Rising Input Source Counter Count Down Enable             */
10761       __IO uint32_t  DSGTRGBF   :  1;               /*!< GTETRGB Pin Falling Input Source Counter Count Down Enable            */
10762       __IO uint32_t  DSGTRGCR   :  1;               /*!< GTETRGC Pin Rising Input Source Counter Count Down Enable             */
10763       __IO uint32_t  DSGTRGCF   :  1;               /*!< GTETRGC Pin Falling Input Source Counter Count Down Enable            */
10764       __IO uint32_t  DSGTRGDR   :  1;               /*!< GTETRGD Pin Rising Input Source Counter Count Down Enable             */
10765       __IO uint32_t  DSGTRGDF   :  1;               /*!< GTETRGD Pin Falling Input Source Counter Count Down Enable            */
10766       __IO uint32_t  DSCARBL    :  1;               /*!< GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter
10767                                                          Count Down Enable                                                     */
10768       __IO uint32_t  DSCARBH    :  1;               /*!< GTIOCA Pin Rising Input during GTIOCB Value High Source Counter
10769                                                          Count Down Enable                                                     */
10770       __IO uint32_t  DSCAFBL    :  1;               /*!< GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter
10771                                                          Count Down Enable                                                     */
10772       __IO uint32_t  DSCAFBH    :  1;               /*!< GTIOCA Pin Falling Input during GTIOCB Value High Source Counter
10773                                                          Count Down Enable                                                     */
10774       __IO uint32_t  DSCBRAL    :  1;               /*!< GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter
10775                                                          Count Down Enable                                                     */
10776       __IO uint32_t  DSCBRAH    :  1;               /*!< GTIOCB Pin Rising Input during GTIOCA Value High Source Counter
10777                                                          Count Down Enable                                                     */
10778       __IO uint32_t  DSCBFAL    :  1;               /*!< GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter
10779                                                          Count Down Enable                                                     */
10780       __IO uint32_t  DSCBFAH    :  1;               /*!< GTIOCB Pin Falling Input during GTIOCA Value High Source Counter
10781                                                          Count Down Enable                                                     */
10782       __IO uint32_t  DSELCA     :  1;               /*!< ELCA Event Source Counter Count Down Enable                           */
10783       __IO uint32_t  DSELCB     :  1;               /*!< ELCB Event Source Counter Count Down Enable                           */
10784       __IO uint32_t  DSELCC     :  1;               /*!< ELCC Event Source Counter Count Down Enable                           */
10785       __IO uint32_t  DSELCD     :  1;               /*!< ELCD Event Source Counter Count Down Enable                           */
10786       __IO uint32_t  DSELCE     :  1;               /*!< ELCE Event Source Counter Count Down Enable                           */
10787       __IO uint32_t  DSELCF     :  1;               /*!< ELCF Event Source Counter Count Down Enable                           */
10788       __IO uint32_t  DSELCG     :  1;               /*!< ELCG Event Source Counter Count Down Enable                           */
10789       __IO uint32_t  DSELCH     :  1;               /*!< ELCH Event Source Counter Count Down Enable                           */
10790     } GTDNSR_b;                                     /*!< BitSize                                                               */
10791   };
10792 
10793   union {
10794     __IO uint32_t  GTICASR;                         /*!< General PWM Timer Input Capture Source Select Register A              */
10795 
10796     struct {
10797       __IO uint32_t  ASGTRGAR   :  1;               /*!< GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable           */
10798       __IO uint32_t  ASGTRGAF   :  1;               /*!< GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable          */
10799       __IO uint32_t  ASGTRGBR   :  1;               /*!< GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable           */
10800       __IO uint32_t  ASGTRGBF   :  1;               /*!< GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable          */
10801       __IO uint32_t  ASGTRGCR   :  1;               /*!< GTETRGC Pin Rising Input Source GTCCRA Input Capture Enable           */
10802       __IO uint32_t  ASGTRGCF   :  1;               /*!< GTETRGC Pin Falling Input Source GTCCRA Input Capture Enable          */
10803       __IO uint32_t  ASGTRGDR   :  1;               /*!< GTETRGD Pin Rising Input Source GTCCRA Input Capture Enable           */
10804       __IO uint32_t  ASGTRGDF   :  1;               /*!< GTETRGD Pin Falling Input Source GTCCRA Input Capture Enable          */
10805       __IO uint32_t  ASCARBL    :  1;               /*!< GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA
10806                                                          Input Capture Enable                                                  */
10807       __IO uint32_t  ASCARBH    :  1;               /*!< GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA
10808                                                          Input Capture Enable                                                  */
10809       __IO uint32_t  ASCAFBL    :  1;               /*!< GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA
10810                                                          Input Capture Enable                                                  */
10811       __IO uint32_t  ASCAFBH    :  1;               /*!< GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA
10812                                                          Input Capture Enable                                                  */
10813       __IO uint32_t  ASCBRAL    :  1;               /*!< GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA
10814                                                          Input Capture Enable                                                  */
10815       __IO uint32_t  ASCBRAH    :  1;               /*!< GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA
10816                                                          Input Capture Enable                                                  */
10817       __IO uint32_t  ASCBFAL    :  1;               /*!< GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA
10818                                                          Input Capture Enable                                                  */
10819       __IO uint32_t  ASCBFAH    :  1;               /*!< GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA
10820                                                          Input Capture Enable                                                  */
10821       __IO uint32_t  ASELCA     :  1;               /*!< ELCA Event Source GTCCRA Input Capture Enable                         */
10822       __IO uint32_t  ASELCB     :  1;               /*!< ELCB Event Source GTCCRA Input Capture Enable                         */
10823       __IO uint32_t  ASELCC     :  1;               /*!< ELCC Event Source GTCCRA Input Capture Enable                         */
10824       __IO uint32_t  ASELCD     :  1;               /*!< ELCD Event Source GTCCRA Input Capture Enable                         */
10825       __IO uint32_t  ASELCE     :  1;               /*!< ELCE Event Source GTCCRA Input Capture Enable                         */
10826       __IO uint32_t  ASELCF     :  1;               /*!< ELCF Event Source GTCCRA Input Capture Enable                         */
10827       __IO uint32_t  ASELCG     :  1;               /*!< ELCG Event Source GTCCRA Input Capture Enable                         */
10828       __IO uint32_t  ASELCH     :  1;               /*!< ELCH Event Source GTCCRA Input Capture Enable                         */
10829     } GTICASR_b;                                    /*!< BitSize                                                               */
10830   };
10831 
10832   union {
10833     __IO uint32_t  GTICBSR;                         /*!< General PWM Timer Input Capture Source Select Register B              */
10834 
10835     struct {
10836       __IO uint32_t  BSGTRGAR   :  1;               /*!< GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable           */
10837       __IO uint32_t  BSGTRGAF   :  1;               /*!< GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable          */
10838       __IO uint32_t  BSGTRGBR   :  1;               /*!< GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable           */
10839       __IO uint32_t  BSGTRGBF   :  1;               /*!< GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable          */
10840       __IO uint32_t  BSGTRGCR   :  1;               /*!< GTETRGC Pin Rising Input Source GTCCRB Input Capture Enable           */
10841       __IO uint32_t  BSGTRGCF   :  1;               /*!< GTETRGC Pin Falling Input Source GTCCRB Input Capture Enable          */
10842       __IO uint32_t  BSGTRGDR   :  1;               /*!< GTETRGD Pin Rising Input Source GTCCRB Input Capture Enable           */
10843       __IO uint32_t  BSGTRGDF   :  1;               /*!< GTETRGD Pin Falling Input Source GTCCRB Input Capture Enable          */
10844       __IO uint32_t  BSCARBL    :  1;               /*!< GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB
10845                                                          Input Capture Enable                                                  */
10846       __IO uint32_t  BSCARBH    :  1;               /*!< GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB
10847                                                          Input Capture Enable                                                  */
10848       __IO uint32_t  BSCAFBL    :  1;               /*!< GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB
10849                                                          Input Capture Enable                                                  */
10850       __IO uint32_t  BSCAFBH    :  1;               /*!< GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB
10851                                                          Input Capture Enable                                                  */
10852       __IO uint32_t  BSCBRAL    :  1;               /*!< GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRB
10853                                                          Input Capture Enable                                                  */
10854       __IO uint32_t  BSCBRAH    :  1;               /*!< GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRB
10855                                                          Input Capture Enable                                                  */
10856       __IO uint32_t  BSCBFAL    :  1;               /*!< GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRB
10857                                                          Input Capture Enable                                                  */
10858       __IO uint32_t  BSCBFAH    :  1;               /*!< GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRB
10859                                                          Input Capture Enable                                                  */
10860       __IO uint32_t  BSELCA     :  1;               /*!< ELCA Event Source GTCCRB Input Capture Enable                         */
10861       __IO uint32_t  BSELCB     :  1;               /*!< ELCB Event Source GTCCRB Input Capture Enable                         */
10862       __IO uint32_t  BSELCC     :  1;               /*!< ELCC Event Source GTCCRB Input Capture Enable                         */
10863       __IO uint32_t  BSELCD     :  1;               /*!< ELCD Event Source GTCCRB Input Capture Enable                         */
10864       __IO uint32_t  BSELCE     :  1;               /*!< ELCE Event Source GTCCRB Input Capture Enable                         */
10865       __IO uint32_t  BSELCF     :  1;               /*!< ELCF Event Source GTCCRB Input Capture Enable                         */
10866       __IO uint32_t  BSELCG     :  1;               /*!< ELCG Event Source GTCCRB Input Capture Enable                         */
10867       __IO uint32_t  BSELCH     :  1;               /*!< ELCH Event Source GTCCRB Input Capture Enable                         */
10868     } GTICBSR_b;                                    /*!< BitSize                                                               */
10869   };
10870 
10871   union {
10872     __IO uint32_t  GTCR;                            /*!< General PWM Timer Control Register                                    */
10873 
10874     struct {
10875       __IO uint32_t  CST        :  1;               /*!< Count Start                                                           */
10876            uint32_t             :  7;
10877       __IO uint32_t  ICDS       :  1;               /*!< Input Capture Behavior Select During Counter Stop                     */
10878            uint32_t             :  7;
10879       __IO uint32_t  MD         :  3;               /*!< Mode Select                                                           */
10880            uint32_t             :  5;
10881       __IO uint32_t  TPCS       :  3;               /*!< Timer Prescaler Select                                                */
10882     } GTCR_b;                                       /*!< BitSize                                                               */
10883   };
10884 
10885   union {
10886     __IO uint32_t  GTUDDTYC;                        /*!< General PWM Timer Count Direction and Duty Setting Register           */
10887 
10888     struct {
10889       __IO uint32_t  UD         :  1;               /*!< Count Direction Setting                                               */
10890       __IO uint32_t  UDF        :  1;               /*!< Forcible Count Direction Setting                                      */
10891            uint32_t             : 14;
10892       __IO uint32_t  OADTY      :  2;               /*!< GTIOCA Output Duty Setting                                            */
10893       __IO uint32_t  OADTYF     :  1;               /*!< Forcible GTIOCA Output Duty Setting                                   */
10894       __IO uint32_t  OADTYR     :  1;               /*!< GTIOCA Output Value Selecting after Releasing 0%/100% Duty Setting    */
10895            uint32_t             :  4;
10896       __IO uint32_t  OBDTY      :  2;               /*!< GTIOCB Output Duty Setting                                            */
10897       __IO uint32_t  OBDTYF     :  1;               /*!< Forcible GTIOCB Output Duty Setting                                   */
10898       __IO uint32_t  OBDTYR     :  1;               /*!< GTIOCB Output Value Selecting after Releasing 0%/100% Duty Setting    */
10899     } GTUDDTYC_b;                                   /*!< BitSize                                                               */
10900   };
10901 
10902   union {
10903     __IO uint32_t  GTIOR;                           /*!< General PWM Timer I/O Control Register                                */
10904 
10905     struct {
10906       __IO uint32_t  GTIOA      :  5;               /*!< GTIOCA Pin Function Select                                            */
10907            uint32_t             :  1;
10908       __IO uint32_t  OADFLT     :  1;               /*!< GTIOCA Pin Output Value Setting at the Count Stop                     */
10909       __IO uint32_t  OAHLD      :  1;               /*!< GTIOCA Pin Output Setting at the Start/Stop Count                     */
10910       __IO uint32_t  OAE        :  1;               /*!< GTIOCA Pin Output Enable                                              */
10911       __IO uint32_t  OADF       :  2;               /*!< GTIOCA Pin Disable Value Setting                                      */
10912            uint32_t             :  2;
10913       __IO uint32_t  NFAEN      :  1;               /*!< Noise Filter A Enable                                                 */
10914       __IO uint32_t  NFCSA      :  2;               /*!< Noise Filter A Sampling Clock Select                                  */
10915       __IO uint32_t  GTIOB      :  5;               /*!< GTIOCB Pin Function Select                                            */
10916            uint32_t             :  1;
10917       __IO uint32_t  OBDFLT     :  1;               /*!< GTIOCB Pin Output Value Setting at the Count Stop                     */
10918       __IO uint32_t  OBHLD      :  1;               /*!< GTIOCB Pin Output Setting at the Start/Stop Count                     */
10919       __IO uint32_t  OBE        :  1;               /*!< GTIOCB Pin Output Enable                                              */
10920       __IO uint32_t  OBDF       :  2;               /*!< GTIOCB Pin Disable Value Setting                                      */
10921            uint32_t             :  2;
10922       __IO uint32_t  NFBEN      :  1;               /*!< Noise Filter B Enable                                                 */
10923       __IO uint32_t  NFCSB      :  2;               /*!< Noise Filter B Sampling Clock Select                                  */
10924     } GTIOR_b;                                      /*!< BitSize                                                               */
10925   };
10926 
10927   union {
10928     __IO uint32_t  GTINTAD;                         /*!< General PWM Timer Interrupt Output Setting Register                   */
10929 
10930     struct {
10931            uint32_t             : 24;
10932       __IO uint32_t  GRP        :  2;               /*!< Output Disable Source Select                                          */
10933            uint32_t             :  3;
10934       __IO uint32_t  GRPABH     :  1;               /*!< Same Time Output Level High Disable Request Enable                    */
10935       __IO uint32_t  GRPABL     :  1;               /*!< Same Time Output Level Low Disable Request Enable                     */
10936     } GTINTAD_b;                                    /*!< BitSize                                                               */
10937   };
10938 
10939   union {
10940     __IO uint32_t  GTST;                            /*!< General PWM Timer Status Register                                     */
10941 
10942     struct {
10943       __IO uint32_t  TCFA       :  1;               /*!< Input Capture/Compare Match Flag A                                    */
10944       __IO uint32_t  TCFB       :  1;               /*!< Input Capture/Compare Match Flag B                                    */
10945       __IO uint32_t  TCFC       :  1;               /*!< Input Compare Match Flag C                                            */
10946       __IO uint32_t  TCFD       :  1;               /*!< Input Compare Match Flag D                                            */
10947       __IO uint32_t  TCFE       :  1;               /*!< Input Compare Match Flag E                                            */
10948       __IO uint32_t  TCFF       :  1;               /*!< Input Compare Match Flag F                                            */
10949       __IO uint32_t  TCPFO      :  1;               /*!< Overflow Flag                                                         */
10950       __IO uint32_t  TCFPU      :  1;               /*!< Underflow Flag                                                        */
10951            uint32_t             :  7;
10952       __I  uint32_t  TUCF       :  1;               /*!< Count Direction Flag                                                  */
10953       __IO uint32_t  ADTRAUF    :  1;               /*!< GTADTRA Compare Match (Up-Counting) A/D Converter Start Request
10954                                                          Interrupt Enable                                                      */
10955       __IO uint32_t  ADTRADF    :  1;               /*!< GTADTRA Compare Match(Down-Counting) A/D Converter Start Request
10956                                                          Flag                                                                  */
10957       __IO uint32_t  ADTRBUF    :  1;               /*!< GTADTRB Compare Match(Up-Counting) A/D Converter Start Request
10958                                                          Flag                                                                  */
10959       __IO uint32_t  ADTRBDF    :  1;               /*!< GTADTRB Compare Match(Down-Counting) A/D Converter Start Request
10960                                                          Flag                                                                  */
10961            uint32_t             :  4;
10962       __I  uint32_t  ODF        :  1;               /*!< Output Disable Flag                                                   */
10963            uint32_t             :  4;
10964       __I  uint32_t  OABHF      :  1;               /*!< Same Time Output Level High Disable Request Enable                    */
10965       __I  uint32_t  OABLF      :  1;               /*!< Same Time Output Level Low Disable Request Enable                     */
10966     } GTST_b;                                       /*!< BitSize                                                               */
10967   };
10968 
10969   union {
10970     __IO uint32_t  GTBER;                           /*!< General PWM Timer Buffer Enable Register                              */
10971 
10972     struct {
10973       __IO uint32_t  BD         :  2;               /*!< BD[1]: GTPR Buffer Operation DisableBD[0]: GTCCR Buffer Operation
10974                                                          Disable                                                               */
10975            uint32_t             : 14;
10976       __IO uint32_t  CCRA       :  2;               /*!< GTCCRA Buffer Operation                                               */
10977       __IO uint32_t  CCRB       :  2;               /*!< GTCCRB Buffer Operation                                               */
10978       __IO uint32_t  PR         :  2;               /*!< GTPR Buffer Operation                                                 */
10979       __O  uint32_t  CCRSWT     :  1;               /*!< GTCCRA and GTCCRB Forcible Buffer OperationThis bit is read
10980                                                          as 0.                                                                 */
10981     } GTBER_b;                                      /*!< BitSize                                                               */
10982   };
10983   __I  uint32_t  RESERVED;
10984 
10985   union {
10986     __IO uint32_t  GTCNT;                           /*!< General PWM Timer Counter                                             */
10987 
10988     struct {
10989       __IO uint32_t  GTCNT      : 32;               /*!< Counter                                                               */
10990     } GTCNT_b;                                      /*!< BitSize                                                               */
10991   };
10992 
10993   union {
10994     __IO uint32_t  GTCCRA;                          /*!< General PWM Timer Compare Capture Register A                          */
10995 
10996     struct {
10997       __IO uint32_t  GTCCRA     : 32;               /*!< Compare Capture Register A                                            */
10998     } GTCCRA_b;                                     /*!< BitSize                                                               */
10999   };
11000 
11001   union {
11002     __IO uint32_t  GTCCRB;                          /*!< General PWM Timer Compare Capture Register B                          */
11003 
11004     struct {
11005       __IO uint32_t  GTCCRB     : 32;               /*!< Compare Capture Register B                                            */
11006     } GTCCRB_b;                                     /*!< BitSize                                                               */
11007   };
11008 
11009   union {
11010     __IO uint32_t  GTCCRC;                          /*!< General PWM Timer Compare Capture Register C                          */
11011 
11012     struct {
11013       __IO uint32_t  GTCCRC     : 32;               /*!< Compare Capture Register C                                            */
11014     } GTCCRC_b;                                     /*!< BitSize                                                               */
11015   };
11016 
11017   union {
11018     __IO uint32_t  GTCCRE;                          /*!< General PWM Timer Compare Capture Register E                          */
11019 
11020     struct {
11021       __IO uint32_t  GTCCRE     : 32;               /*!< Compare Capture Register E                                            */
11022     } GTCCRE_b;                                     /*!< BitSize                                                               */
11023   };
11024 
11025   union {
11026     __IO uint32_t  GTCCRD;                          /*!< General PWM Timer Compare Capture Register D                          */
11027 
11028     struct {
11029       __IO uint32_t  GTCCRD     : 32;               /*!< Compare Capture Register D                                            */
11030     } GTCCRD_b;                                     /*!< BitSize                                                               */
11031   };
11032 
11033   union {
11034     __IO uint32_t  GTCCRF;                          /*!< General PWM Timer Compare Capture Register F                          */
11035 
11036     struct {
11037       __IO uint32_t  GTCCRF     : 32;               /*!< Compare Capture Register F                                            */
11038     } GTCCRF_b;                                     /*!< BitSize                                                               */
11039   };
11040 
11041   union {
11042     __IO uint32_t  GTPR;                            /*!< General PWM Timer Cycle Setting Register                              */
11043 
11044     struct {
11045       __IO uint32_t  GTPR       : 32;               /*!< Cycle Setting Register                                                */
11046     } GTPR_b;                                       /*!< BitSize                                                               */
11047   };
11048 
11049   union {
11050     __IO uint32_t  GTPBR;                           /*!< General PWM Timer Cycle Setting Buffer Register                       */
11051 
11052     struct {
11053       __IO uint32_t  GTPBR      : 32;               /*!< Cycle Setting Buffer Register                                         */
11054     } GTPBR_b;                                      /*!< BitSize                                                               */
11055   };
11056   __I  uint32_t  RESERVED1[7];
11057 
11058   union {
11059     __IO uint32_t  GTDTCR;                          /*!< General PWM Timer Dead Time Control Register                          */
11060 
11061     struct {
11062       __IO uint32_t  TDE        :  1;               /*!< Negative-Phase Waveform Setting                                       */
11063       __IO uint32_t             :  31;
11064     } GTDTCR_b;                                     /*!< BitSize                                                               */
11065   };
11066 
11067   union {
11068     __IO uint32_t  GTDVU;                           /*!< General PWM Timer Dead Time Value Register U                          */
11069 
11070     struct {
11071       __IO uint32_t  GTDVU      : 32;               /*!< Dead Time Value Register U                                            */
11072     } GTDVU_b;                                      /*!< BitSize                                                               */
11073   };
11074 } R_GPTB0_Type;
11075 
11076 
11077 /* ================================================================================ */
11078 /* ================                    R_GPT_OPS                   ================ */
11079 /* ================================================================================ */
11080 
11081 
11082 /**
11083   * @brief Output Phase Switching Controller (R_GPT_OPS)
11084   */
11085 
11086 typedef struct {                                    /*!< R_GPT_OPS Structure                                                   */
11087 
11088   union {
11089     __IO uint32_t  OPSCR;                           /*!< Output Phase Switching Control Register                               */
11090 
11091     struct {
11092       __IO uint32_t  UF         :  1;               /*!< Input Phase Soft Setting WFThis bit sets the input phase by
11093                                                          the software settings.This bit setting is valid when the OPSCR.FB
11094                                                           bit = 1.                                                             */
11095       __IO uint32_t  VF         :  1;               /*!< Input Phase Soft Setting VFThis bit sets the input phase by
11096                                                          the software settings.This bit setting is valid when the OPSCR.FB
11097                                                           bit = 1.                                                             */
11098       __IO uint32_t  WF         :  1;               /*!< Input Phase Soft Setting UFThis bit sets the input phase by
11099                                                          the software settings.This bit setting is valid when the OPSCR.FB
11100                                                           bit = 1.                                                             */
11101            uint32_t             :  1;
11102       __I  uint32_t  U          :  1;               /*!< Input U-Phase MonitorThis bit monitors the state of the input
11103                                                          phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Software
11104                                                           settings (UF/VF/WF)                                                  */
11105       __I  uint32_t  V          :  1;               /*!< Input V-Phase MonitorThis bit monitors the state of the input
11106                                                          phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Software
11107                                                           settings (UF/VF/WF)                                                  */
11108       __I  uint32_t  W          :  1;               /*!< Input W-Phase MonitorThis bit monitors the state of the input
11109                                                          phase.OPSCR.FB=0:External input monitoring by PCLKOPSCR.FB=1:Software
11110                                                           settings (UF/VF/WF)                                                  */
11111            uint32_t             :  1;
11112       __IO uint32_t  EN         :  1;               /*!< Enable-Phase Output Control                                           */
11113            uint32_t             :  7;
11114       __IO uint32_t  FB         :  1;               /*!< External Feedback Signal EnableThis bit selects the input phase
11115                                                          from the software settings and external input.                        */
11116       __IO uint32_t  P          :  1;               /*!< Positive-Phase Output (P) Control                                     */
11117       __IO uint32_t  N          :  1;               /*!< Negative-Phase Output (N) Control                                     */
11118       __IO uint32_t  INV        :  1;               /*!< Invert-Phase Output Control                                           */
11119       __IO uint32_t  RV         :  1;               /*!< Output phase rotation direction reversal                              */
11120       __IO uint32_t  ALIGN      :  1;               /*!< Input phase alignment                                                 */
11121            uint32_t             :  2;
11122       __IO uint32_t  GRP        :  2;               /*!< Output disabled source selection                                      */
11123       __IO uint32_t  GODF       :  1;               /*!< Group output disable function                                         */
11124            uint32_t             :  2;
11125       __IO uint32_t  NFEN       :  1;               /*!< External Input Noise Filter Enable                                    */
11126       __IO uint32_t  NFCS       :  2;               /*!< External Input Noise Filter Clock selectionNoise filter sampling
11127                                                          clock setting of the external input.                                  */
11128     } OPSCR_b;                                      /*!< BitSize                                                               */
11129   };
11130 } R_GPT_OPS_Type;
11131 
11132 
11133 /* ================================================================================ */
11134 /* ================                    R_GPT_ODC                   ================ */
11135 /* ================================================================================ */
11136 
11137 
11138 /**
11139   * @brief Output Delay Control (R_GPT_ODC)
11140   */
11141 
11142 typedef struct {                                    /*!< R_GPT_ODC Structure                                                   */
11143 
11144     union {
11145       __IO uint16_t  GTDLYCR;                       /*!< PWM Output Delay Control Register                                     */
11146 
11147       struct {
11148         __IO uint16_t  DLLEN    :  1;               /*!< DLL Operation Enable                                                  */
11149         __IO uint16_t  DLYRST   :  1;               /*!< PWM Delay Generation Circuit Reset                                    */
11150       } GTDLYCR_b;                                  /*!< BitSize                                                               */
11151     };
11152 
11153     union {
11154       __IO uint16_t  GTDLYCR2;                      /*!< PWM Output Delay Control Register2                                    */
11155 
11156       struct {
11157         __IO uint16_t  DLYBS0 :  1;                 /*!< PWM Delay Generation Circuit bypass for channel 0                     */
11158         __IO uint16_t  DLYBS1 :  1;                 /*!< PWM Delay Generation Circuit bypass for channel 1                     */
11159         __IO uint16_t  DLYBS2 :  1;                 /*!< PWM Delay Generation Circuit bypass for channel 2                     */
11160         __IO uint16_t  DLYBS3 :  1;                 /*!< PWM Delay Generation Circuit bypass for channel 3                     */
11161              uint16_t         :  4;
11162         __IO uint16_t  DLYEN0 :  1;                 /*!< PWM Delay Generation Circuit enable for channel 0                     */
11163         __IO uint16_t  DLYEN1 :  1;                 /*!< PWM Delay Generation Circuit enable for channel 1                     */
11164         __IO uint16_t  DLYEN2 :  1;                 /*!< PWM Delay Generation Circuit enable for channel 2                     */
11165         __IO uint16_t  DLYEN3 :  1;                 /*!< PWM Delay Generation Circuit enable for channel 3                     */
11166     } GTDLYCR2_b;                                   /*!< BitSize                                                               */
11167   };
11168   __I  uint8_t RESERVED[5 * 4];
11169   R_GPT_ODC_GTDLYRnRC0_Type GTDLYRnRC0[4];          /*!< GTIOC%s Rising Output Delay Register Cluster 0                        */
11170   R_GPT_ODC_GTDLYFnRC0_Type GTDLYFnRC0[4];          /*!< GTIOC%s Falling Output Delay Register Cluster 0                       */
11171 } R_GPT_ODC_Type;
11172 
11173 
11174 /* ================================================================================ */
11175 /* ================                     R_KINT                     ================ */
11176 /* ================================================================================ */
11177 
11178 
11179 /**
11180   * @brief Key Interrupt (R_KINT)
11181   */
11182 
11183 typedef struct {                                    /*!< R_KINT Structure                                                      */
11184 
11185   union {
11186     __IO uint8_t   KRCTL;                           /*!< Key Return Control Register                                           */
11187 
11188     struct {
11189       __IO uint8_t   KREG       :  1;               /*!< Usage of Key Interrupt Flags (KRF0 to KRF7)                           */
11190            uint8_t              :  6;
11191       __IO uint8_t   KRMD       :  1;               /*!< Selection of Detection Edge (KR0 to KR7)                              */
11192     } KRCTL_b;                                      /*!< BitSize                                                               */
11193   };
11194   __I  uint8_t   RESERVED[3];
11195 
11196   union {
11197     __IO uint8_t   KRF;                             /*!< Key Return Flag Register                                              */
11198 
11199     struct {
11200       __IO uint8_t   KRF0       :  1;               /*!< Key interrupt flag 0                                                  */
11201       __IO uint8_t   KRF1       :  1;               /*!< Key interrupt flag 1                                                  */
11202       __IO uint8_t   KRF2       :  1;               /*!< Key interrupt flag 2                                                  */
11203       __IO uint8_t   KRF3       :  1;               /*!< Key interrupt flag 3                                                  */
11204       __IO uint8_t   KRF4       :  1;               /*!< Key interrupt flag 4                                                  */
11205       __IO uint8_t   KRF5       :  1;               /*!< Key interrupt flag 5                                                  */
11206       __IO uint8_t   KRF6       :  1;               /*!< Key interrupt flag 6                                                  */
11207       __IO uint8_t   KRF7       :  1;               /*!< Key interrupt flag 7                                                  */
11208     } KRF_b;                                        /*!< BitSize                                                               */
11209   };
11210   __I  uint8_t   RESERVED1[3];
11211 
11212   union {
11213     __IO uint8_t   KRM;                             /*!< Key Return Mode Register                                              */
11214 
11215     struct {
11216       __IO uint8_t   KRM0       :  1;               /*!< Key interrupt mode control 0                                          */
11217       __IO uint8_t   KRM1       :  1;               /*!< Key interrupt mode control 1                                          */
11218       __IO uint8_t   KRM2       :  1;               /*!< Key interrupt mode control 2                                          */
11219       __IO uint8_t   KRM3       :  1;               /*!< Key interrupt mode control 3                                          */
11220       __IO uint8_t   KRM4       :  1;               /*!< Key interrupt mode control 4                                          */
11221       __IO uint8_t   KRM5       :  1;               /*!< Key interrupt mode control 5                                          */
11222       __IO uint8_t   KRM6       :  1;               /*!< Key interrupt mode control 6                                          */
11223       __IO uint8_t   KRM7       :  1;               /*!< Key interrupt mode control 7                                          */
11224     } KRM_b;                                        /*!< BitSize                                                               */
11225   };
11226 } R_KINT_Type;
11227 
11228 
11229 /* ================================================================================ */
11230 /* ================                     R_CTSU                     ================ */
11231 /* ================================================================================ */
11232 
11233 
11234 /**
11235   * @brief Capacitive Touch Sensing Unit (R_CTSU)
11236   */
11237 
11238 typedef struct {                                    /*!< R_CTSU Structure                                                      */
11239 
11240   union {
11241     __IO uint8_t   CTSUCR0;                         /*!< CTSU Control Register 0                                               */
11242 
11243     struct {
11244       __IO uint8_t   CTSUSTRT   :  1;               /*!< CTSU Measurement Operation Start                                      */
11245       __IO uint8_t   CTSUCAP    :  1;               /*!< CTSU Measurement Operation Start Trigger Select                       */
11246       __IO uint8_t   CTSUSNZ    :  1;               /*!< CTSU Wait State Power-Saving Enable                                   */
11247       __IO uint8_t   CTSUIOC    :  1;               /*!< CTSU Transmit Pin Control                                             */
11248       __IO uint8_t   CTSUINIT   :  1;               /*!< CTSU Control Block Initialization                                     */
11249     } CTSUCR0_b;                                    /*!< BitSize                                                               */
11250   };
11251 
11252   union {
11253     __IO uint8_t   CTSUCR1;                         /*!< CTSU Control Register 1                                               */
11254 
11255     struct {
11256       __IO uint8_t   CTSUPON    :  1;               /*!< CTSU Power Supply Enable                                              */
11257       __IO uint8_t   CTSUCSW    :  1;               /*!< CTSU LPF Capacitance Charging Control                                 */
11258       __IO uint8_t   CTSUATUNE0 :  1;               /*!< CTSU Power Supply Operating Mode Setting                              */
11259       __IO uint8_t   CTSUATUNE1 :  1;               /*!< CTSU Power Supply Capacity Adjustment                                 */
11260       __IO uint8_t   CTSUCLK    :  2;               /*!< CTSU Operating Clock Select                                           */
11261       __IO uint8_t   CTSUMD     :  2;               /*!< CTSU Measurement Mode Select                                          */
11262     } CTSUCR1_b;                                    /*!< BitSize                                                               */
11263   };
11264 
11265   union {
11266     __IO uint8_t   CTSUSDPRS;                       /*!< CTSU Synchronous Noise Reduction Setting Register                     */
11267 
11268     struct {
11269       __IO uint8_t   CTSUPRRATIO:  4;               /*!< CTSU Measurement Time and Pulse Count Adjustment                      */
11270       __IO uint8_t   CTSUPRMODE :  2;               /*!< CTSU Base Period and Pulse Count Setting                              */
11271       __IO uint8_t   CTSUSOFF   :  1;               /*!< CTSU High-Pass Noise Reduction Function Off Setting                   */
11272     } CTSUSDPRS_b;                                  /*!< BitSize                                                               */
11273   };
11274 
11275   union {
11276     __IO uint8_t   CTSUSST;                         /*!< CTSU Sensor Stabilization Wait Control Register                       */
11277 
11278     struct {
11279       __IO uint8_t   CTSUSST    :  8;               /*!< CTSU Sensor Stabilization Wait ControlNOTE: The value of these
11280                                                          bits should be fixed to 00010000b.                                    */
11281     } CTSUSST_b;                                    /*!< BitSize                                                               */
11282   };
11283 
11284   union {
11285     __IO uint8_t   CTSUMCH0;                        /*!< CTSU Measurement Channel Register 0                                   */
11286 
11287     struct {
11288       __IO uint8_t   CTSUMCH0   :  4;               /*!< CTSU Measurement Channel 0                                            */
11289     } CTSUMCH0_b;                                   /*!< BitSize                                                               */
11290   };
11291 
11292   union {
11293     __IO uint8_t   CTSUMCH1;                        /*!< CTSU Measurement Channel Register 1                                   */
11294 
11295     struct {
11296       __IO uint8_t   CTSUMCH1   :  4;               /*!< CTSU Measurement Channel 1                                            */
11297     } CTSUMCH1_b;                                   /*!< BitSize                                                               */
11298   };
11299 
11300   union {
11301     __IO uint8_t   CTSUCHAC0;                       /*!< CTSU Channel Enable Control Register 0                                */
11302 
11303     struct {
11304       __IO uint8_t   CTSUCHAC0  :  8;               /*!< CTSU Channel Enable Control 0                                         */
11305     } CTSUCHAC0_b;                                  /*!< BitSize                                                               */
11306   };
11307 
11308   union {
11309     __IO uint8_t   CTSUCHAC1;                       /*!< CTSU Channel Enable Control Register 1                                */
11310 
11311     struct {
11312       __IO uint8_t   CTSUCHAC1  :  8;               /*!< CTSU Channel Enable Control 1                                         */
11313     } CTSUCHAC1_b;                                  /*!< BitSize                                                               */
11314   };
11315 
11316   union {
11317     __IO uint8_t   CTSUCHAC2;                       /*!< CTSU Channel Enable Control Register 2                                */
11318 
11319     struct {
11320       __IO uint8_t   CTSUCHAC2  :  8;               /*!< CTSU Channel Enable Control 2                                         */
11321     } CTSUCHAC2_b;                                  /*!< BitSize                                                               */
11322   };
11323 
11324   union {
11325     __IO uint8_t   CTSUCHAC3;                       /*!< CTSU Channel Enable Control Register 3                                */
11326 
11327     struct {
11328       __IO uint8_t   CTSUCHAC3  :  8;               /*!< CTSU Channel Enable Control 3                                         */
11329     } CTSUCHAC3_b;                                  /*!< BitSize                                                               */
11330   };
11331 
11332   union {
11333     __IO uint8_t   CTSUCHAC4;                       /*!< CTSU Channel Enable Control Register 4                                */
11334 
11335     struct {
11336       __IO uint8_t   CTSUCHAC4  :  4;               /*!< CTSU Channel Enable Control 4                                         */
11337     } CTSUCHAC4_b;                                  /*!< BitSize                                                               */
11338   };
11339 
11340   union {
11341     __IO uint8_t   CTSUCHTRC0;                      /*!< CTSU Channel Transmit/Receive Control Register 0                      */
11342 
11343     struct {
11344       __IO uint8_t   CTSUCHTRC0 :  8;               /*!< CTSU Channel Transmit/Receive Control 0                               */
11345     } CTSUCHTRC0_b;                                 /*!< BitSize                                                               */
11346   };
11347 
11348   union {
11349     __IO uint8_t   CTSUCHTRC1;                      /*!< CTSU Channel Transmit/Receive Control Register 1                      */
11350 
11351     struct {
11352       __IO uint8_t   CTSUCHTRC1  :  8;               /*!< CTSU Channel Transmit/Receive Control 1                               */
11353     } CTSUCHTRC1_b;                                 /*!< BitSize                                                               */
11354   };
11355 
11356   union {
11357     __IO uint8_t   CTSUCHTRC2;                      /*!< CTSU Channel Transmit/Receive Control Register 2                      */
11358 
11359     struct {
11360       __IO uint8_t   CTSUCHTRC2  :  8;               /*!< CTSU Channel Transmit/Receive Control 2                               */
11361     } CTSUCHTRC2_b;                                 /*!< BitSize                                                               */
11362   };
11363 
11364   union {
11365     __IO uint8_t   CTSUCHTRC3;                      /*!< CTSU Channel Transmit/Receive Control Register 3                      */
11366 
11367     struct {
11368       __IO uint8_t   CTSUCHTRC3  :  8;               /*!< CTSU Channel Transmit/Receive Control 3                               */
11369     } CTSUCHTRC3_b;                                 /*!< BitSize                                                               */
11370   };
11371 
11372     union {
11373     __IO uint8_t   CTSUCHTRC4;                      /*!< CTSU Channel Transmit/Receive Control Register 4                      */
11374 
11375     struct {
11376       __IO uint8_t   CTSUCHTRC4  :  4;               /*!< CTSU Channel Transmit/Receive Control 4                               */
11377     } CTSUCHTRC4_b;                                 /*!< BitSize                                                               */
11378   };
11379 
11380   union {
11381     __IO uint8_t   CTSUDCLKC;                       /*!< CTSU High-Pass Noise Reduction Control Register                       */
11382 
11383     struct {
11384       __IO uint8_t   CTSUSSMOD  :  2;               /*!< CTSU Diffusion Clock Mode SelectNOTE: This bit should be set
11385                                                          to 00b.                                                               */
11386            uint8_t              :  2;
11387       __IO uint8_t   CTSUSSCNT  :  2;               /*!< CTSU Diffusion Clock Mode ControlNOTE: This bit should be set
11388                                                          to 11b.                                                               */
11389     } CTSUDCLKC_b;                                  /*!< BitSize                                                               */
11390   };
11391 
11392   union {
11393     __IO uint8_t   CTSUST;                          /*!< CTSU Status Register                                                  */
11394 
11395     struct {
11396       __IO uint8_t   CTSUSTC    :  3;               /*!< CTSU Measurement Status Counter                                       */
11397            uint8_t              :  1;
11398       __IO uint8_t   CTSUDTSR   :  1;               /*!< CTSU Data Transfer Status Flag                                        */
11399       __IO uint8_t   CTSUSOVF   :  1;               /*!< CTSU Sensor Counter Overflow Flag                                     */
11400       __IO uint8_t   CTSUROVF   :  1;               /*!< CTSU Reference Counter Overflow Flag                                  */
11401       __IO uint8_t   CTSUPS     :  1;               /*!< CTSU Mutual Capacitance Status Flag                                   */
11402     } CTSUST_b;                                     /*!< BitSize                                                               */
11403   };
11404 
11405   union {
11406     __IO uint16_t  CTSUSSC;                         /*!< CTSU High-Pass Noise Reduction Spectrum Diffusion Control Register
11407                                                                                                                                */
11408 
11409     struct {
11410            uint16_t             :  8;
11411       __IO uint16_t  CTSUSSDIV  :  4;               /*!< CTSU Spectrum Diffusion Frequency Division Setting                    */
11412     } CTSUSSC_b;                                    /*!< BitSize                                                               */
11413   };
11414 
11415   union {
11416     __IO uint16_t  CTSUSO0;                         /*!< CTSU Sensor Offset Register 0                                         */
11417 
11418     struct {
11419       __IO uint16_t  CTSUSO     : 10;               /*!< CTSU Sensor Offset AdjustmentCurrent offset amount is CTSUSO
11420                                                          ( 0 to 1023 )                                                         */
11421       __IO uint16_t  CTSUSNUM   :  6;               /*!< CTSU Measurement Count Setting                                        */
11422     } CTSUSO0_b;                                    /*!< BitSize                                                               */
11423   };
11424 
11425   union {
11426     __IO uint16_t  CTSUSO1;                         /*!< CTSU Sensor Offset Register 1                                         */
11427 
11428     struct {
11429       __IO uint16_t  CTSURICOA  :  8;               /*!< CTSU Reference ICO Current AdjustmentCurrent offset amount is
11430                                                          CTSUSO ( 0 to 255 )                                                   */
11431       __IO uint16_t  CTSUSDPA   :  5;               /*!< CTSU Base Clock SettingOperating clock divided by ( CTSUSDPA
11432                                                          + 1 ) x 2                                                             */
11433       __IO uint16_t  CTSUICOG   :  2;               /*!< CTSU ICO Gain Adjustment                                              */
11434     } CTSUSO1_b;                                    /*!< BitSize                                                               */
11435   };
11436 
11437   union {
11438     __IO uint16_t  CTSUSC;                          /*!< CTSU Sensor Counter                                                   */
11439 
11440     struct {
11441       __IO uint16_t  CTSUSC     : 16;               /*!< CTSU Sensor CounterThese bits indicate the measurement result
11442                                                          of the CTSU. These bits indicate FFFFh when an overflow occurs.       */
11443     } CTSUSC_b;                                     /*!< BitSize                                                               */
11444   };
11445 
11446   union {
11447     __IO uint16_t  CTSURC;                          /*!< CTSU Reference Counter                                                */
11448 
11449     struct {
11450       __IO uint16_t  CTSURC     : 16;               /*!< CTSU Reference Counter                                                */
11451     } CTSURC_b;                                     /*!< BitSize                                                               */
11452   };
11453 
11454   union {
11455     __IO uint16_t  CTSUERRS;                        /*!< CTSU Error Status Register                                            */
11456 
11457     struct {
11458            uint16_t             : 15;
11459       __IO uint16_t  CTSUICOMP  :  1;               /*!< TSCAP Voltage Error Monitor                                           */
11460     } CTSUERRS_b;                                   /*!< BitSize                                                               */
11461   };
11462 } R_CTSU_Type;
11463 
11464 
11465 
11466 
11467 
11468 /* ================================================================================ */
11469 /* ================                     R_AGT0                     ================ */
11470 /* ================================================================================ */
11471 
11472 
11473 /**
11474   * @brief Asynchronous General purpose Timer 0 (R_AGT0)
11475   */
11476 
11477 typedef struct {                                    /*!< R_AGT0 Structure                                                      */
11478 
11479   union {
11480     __IO uint16_t  AGT;                             /*!< AGT Counter Register                                                  */
11481 
11482     struct {
11483       __IO uint16_t  AGT        : 16;               /*!< 16bit counter and reload registerNOTE : When 1 is written to
11484                                                          the TSTOP bit in the AGTCRn register, the 16-bit counter is
11485                                                           forcibly stopped and set to FFFFH.                                   */
11486     } AGT_b;                                        /*!< BitSize                                                               */
11487   };
11488 
11489   union {
11490     __IO uint16_t  AGTCMA;                          /*!< AGT Compare Match A Register                                          */
11491 
11492     struct {
11493       __IO uint16_t  AGTCMA     : 16;               /*!< AGT Compare Match A RegisterNOTE : When 1 is written to the
11494                                                          TSTOP bit in the AGTCRn register, set to FFFFH                        */
11495     } AGTCMA_b;                                     /*!< BitSize                                                               */
11496   };
11497 
11498   union {
11499     __IO uint16_t  AGTCMB;                          /*!< AGT Compare Match B Register                                          */
11500 
11501     struct {
11502       __IO uint16_t  AGTCMB     : 16;               /*!< AGT Compare Match B RegisterNOTE : When 1 is written to the
11503                                                          TSTOP bit in the AGTCR register, set to FFFFH                         */
11504     } AGTCMB_b;                                     /*!< BitSize                                                               */
11505   };
11506   __I  uint16_t  RESERVED;
11507 
11508   union {
11509     __IO uint8_t   AGTCR;                           /*!< AGT Control Register                                                  */
11510 
11511     struct {
11512       __IO uint8_t   TSTART     :  1;               /*!< AGT count start                                                       */
11513       __I  uint8_t   TCSTF      :  1;               /*!< AGT count status flag                                                 */
11514       __O  uint8_t   TSTOP      :  1;               /*!< AGT count forced stop                                                 */
11515            uint8_t              :  1;
11516       __IO uint8_t   TEDGF      :  1;               /*!< Active edge judgement flag(This bit is cleared by writing "0"
11517                                                          in this bit. )                                                        */
11518       __IO uint8_t   TUNDF      :  1;               /*!< AGT underflow flag(This bit is cleared by writing "0" in this
11519                                                          bit. )                                                                */
11520       __IO uint8_t   TCMAF      :  1;               /*!< AGT compare match A flag(This bit is cleared by writing "0"
11521                                                          in this bit. )                                                        */
11522       __IO uint8_t   TCMBF      :  1;               /*!< AGT compare match B flag(This bit is cleared by writing "0"
11523                                                          in this bit. )                                                        */
11524     } AGTCR_b;                                      /*!< BitSize                                                               */
11525   };
11526 
11527   union {
11528     __IO uint8_t   AGTMR1;                          /*!< AGT Mode Register 1                                                   */
11529 
11530     struct {
11531       __IO uint8_t   TMOD       :  3;               /*!< AGT operating mode select                                             */
11532       __IO uint8_t   TEDGPL     :  1;               /*!< AGTIO edge polarity select                                            */
11533       __IO uint8_t   TCK        :  3;               /*!< AGT count source select                                               */
11534     } AGTMR1_b;                                     /*!< BitSize                                                               */
11535   };
11536 
11537   union {
11538     __IO uint8_t   AGTMR2;                          /*!< AGT Mode Register 2                                                   */
11539 
11540     struct {
11541       __IO uint8_t   CKS        :  3;               /*!< fsub/LOCO count source clock frequency division ratio select          */
11542            uint8_t              :  4;
11543       __IO uint8_t   LPM        :  1;               /*!< AGT Low Power Mode                                                    */
11544     } AGTMR2_b;                                     /*!< BitSize                                                               */
11545   };
11546   __I  uint8_t   RESERVED1;
11547 
11548   union {
11549     __IO uint8_t   AGTIOC;                          /*!< AGT I/O Control Register                                              */
11550 
11551     struct {
11552       __IO uint8_t   TEDGSEL    :  1;               /*!< I/O polarity switchFunction varies depending on the operating
11553                                                          mode.                                                                 */
11554            uint8_t              :  1;
11555       __IO uint8_t   TOE        :  1;               /*!< AGTO output enable                                                    */
11556            uint8_t              :  1;
11557       __IO uint8_t   TIPF       :  2;               /*!< AGTIO input filter select                                             */
11558       __IO uint8_t   TIOGT      :  2;               /*!< AGTIO count control                                                   */
11559     } AGTIOC_b;                                     /*!< BitSize                                                               */
11560   };
11561 
11562   union {
11563     __IO uint8_t   AGTISR;                          /*!< AGT Event Pin Select Register                                         */
11564 
11565     struct {
11566            uint8_t              :  2;
11567       __IO uint8_t   EEPS       :  1;               /*!< AGTEE polarity selection                                              */
11568     } AGTISR_b;                                     /*!< BitSize                                                               */
11569   };
11570 
11571   union {
11572     __IO uint8_t   AGTCMSR;                         /*!< AGT Compare Match Function Select Register                            */
11573 
11574     struct {
11575       __IO uint8_t   TCMEA      :  1;               /*!< Compare match A register enable                                       */
11576       __IO uint8_t   TOEA       :  1;               /*!< AGTOA output enable                                                   */
11577       __IO uint8_t   TOPOLA     :  1;               /*!< AGTOA polarity select                                                 */
11578            uint8_t              :  1;
11579       __IO uint8_t   TCMEB      :  1;               /*!< Compare match B register enable                                       */
11580       __IO uint8_t   TOEB       :  1;               /*!< AGTOB output enable                                                   */
11581       __IO uint8_t   TOPOLB     :  1;               /*!< AGTOB polarity select                                                 */
11582     } AGTCMSR_b;                                    /*!< BitSize                                                               */
11583   };
11584 
11585   union {
11586     __IO uint8_t   AGTIOSEL;                        /*!< AGT Pin Select Register                                               */
11587 
11588     struct {
11589       __IO uint8_t   SEL        :  2;               /*!< AGTIO pin select                                                      */
11590            uint8_t              :  2;
11591       __IO uint8_t   TIES       :  1;               /*!< AGTIO input enable                                                    */
11592     } AGTIOSEL_b;                                   /*!< BitSize                                                               */
11593   };
11594 } R_AGT0_Type;
11595 
11596 
11597 
11598 /* =========================================================================================================================== */
11599 /* ================                                           R_OPAMP                                           ================ */
11600 /* Note: 9/12/17 - The following structure for OPAMP was hand edited using the output from the R7FS1JA7.svd output file      */
11601 /* =========================================================================================================================== */
11602 
11603 
11604 /**
11605   * @brief OperationalAmplifier (R_OPAMP)
11606   */
11607 
11608 typedef struct {                                /*!< (@ 0x40086800) R_OPAMP Structure                                            */
11609 
11610     __IM  uint8_t   RESERVED0[8];
11611 
11612   union {
11613     __IOM uint8_t AMPMC;                        /*!< (@ 0x00000000) Operational amplifier mode control register                */
11614 
11615     struct {
11616       __IM  uint8_t             : 6;
11617       __IOM uint8_t AMPSP       : 2;            /*!< [7..6] OPAMP Operation mode selection                                     */
11618     } AMPMC_b;
11619   } ;
11620 
11621   union {
11622     __IOM uint8_t AMPTRM;                       /*!< (@ 0x00000001) Operational amplifier trigger mode control register        */
11623 
11624     struct {
11625       __IOM uint8_t AMPTRM00    : 1;            /*!< [0..0] OPAMP function activation/stop trigger control                     */
11626       __IOM uint8_t AMPTRM01    : 1;            /*!< [1..1] OPAMP function activation/stop trigger control                     */
11627       __IOM uint8_t AMPTRM10    : 1;            /*!< [2..2] OPAMP function activation/stop trigger control                     */
11628       __IOM uint8_t AMPTRM11    : 1;            /*!< [3..3] OPAMP function activation/stop trigger control                     */
11629       __IOM uint8_t AMPTRM20    : 1;            /*!< [4..4] OPAMP function activation/stop trigger control                     */
11630       __IOM uint8_t AMPTRM21    : 1;            /*!< [5..5] OPAMP function activation/stop trigger control                     */
11631     } AMPTRM_b;
11632   } ;
11633 
11634   union {
11635     __IOM uint8_t AMPTRS;                       /*!< (@ 0x00000002) Operational Amplifier Activation Trigger Select
11636                                                                     Register                                                   */
11637 
11638     struct {
11639       __IOM uint8_t AMPTRS      : 2;            /*!< [1..0] Activation Trigger SelectionNote: Do not change the value
11640                                                      of the AMPTRS register after setting the AMPTRM register.                 */
11641     } AMPTRS_b;
11642   } ;
11643 
11644   union {
11645     __IOM uint8_t AMPC;                         /*!< (@ 0x00000003) Operational amplifier control register                     */
11646 
11647     struct {
11648       __IOM uint8_t AMPE0       : 1;            /*!< [0..0] Operation control of operational amplifier 0                       */
11649       __IOM uint8_t AMPE1       : 1;            /*!< [1..1] Operation control of operational amplifier 1                       */
11650       __IOM uint8_t AMPE2       : 1;            /*!< [2..2] Operation control of operational amplifier 2                       */
11651       __IM  uint8_t             : 4;
11652       __IOM uint8_t IREFE       : 1;            /*!< [7..7] Reference Current Circuit Operation Control                        */
11653     } AMPC_b;
11654   } ;
11655 
11656   union {
11657     __IM  uint8_t AMPMON;                       /*!< (@ 0x00000004) Operational amplifier monitor register                     */
11658 
11659     struct {
11660       __IM  uint8_t AMPMON0     : 1;            /*!< [0..0] OPAMP0 Status                                                      */
11661       __IM  uint8_t AMPMON1     : 1;            /*!< [1..1] OPAMP1 Status                                                      */
11662       __IM  uint8_t AMPMON2     : 1;            /*!< [2..2] OPAMP2 Status                                                      */
11663     } AMPMON_b;
11664   } ;
11665   __IM  uint8_t   RESERVED;
11666 
11667   union {
11668     __IOM uint8_t AMP0OS;                       /*!< (@ 0x00000006) Operational Amplifier 0 Output Select Register             */
11669 
11670     struct {
11671       __IOM uint8_t AMPOS0      : 1;            /*!< [0..0] AMP1- pin select                                                   */
11672       __IOM uint8_t AMPOS1      : 1;            /*!< [1..1] AMP1+ pin select                                                   */
11673       __IOM uint8_t AMPOS2      : 1;            /*!< [2..2] AMP2- pin select                                                   */
11674       __IOM uint8_t AMPOS3      : 1;            /*!< [3..3] AMP2+ pin select                                                   */
11675     } AMP0OS_b;
11676   } ;
11677 
11678   union {
11679     __IOM uint8_t AMP0MS;                       /*!< (@ 0x00000007) Operational Amplifier 0 Minus Input Select Register        */
11680 
11681     struct {
11682       __IOM uint8_t AMPMS0      : 1;            /*!< [0..0] AMP0- pin select                                                   */
11683       __IOM uint8_t AMPMS1      : 1;            /*!< [1..1] AMP0+ pin select                                                   */
11684       __IOM uint8_t AMPMS2      : 1;            /*!< [2..2] AMP1- pin select                                                   */
11685       __IOM uint8_t AMPMS3      : 1;            /*!< [3..3] AMP1+ pin select                                                   */
11686       __IOM uint8_t AMPMS4      : 1;            /*!< [4..4] AMP2- pin select                                                   */
11687       __IM  uint8_t             : 2;
11688       __IOM uint8_t AMPMS7      : 1;            /*!< [7..7] OPAMP0 output select                                               */
11689     } AMP0MS_b;
11690   } ;
11691 
11692   union {
11693     __IOM uint8_t AMP0PS;                       /*!< (@ 0x00000008) Operational Amplifier 0 Plus Input Select Register         */
11694 
11695     struct {
11696       __IOM uint8_t AMPPS0      : 1;            /*!< [0..0] AMP0+ pin select                                                   */
11697       __IOM uint8_t AMPPS1      : 1;            /*!< [1..1] AMP1- pin select                                                   */
11698       __IOM uint8_t AMPPS2      : 1;            /*!< [2..2] AMP1+pin select                                                    */
11699       __IOM uint8_t AMPPS3      : 1;            /*!< [3..3] AMP2+ pin select                                                   */
11700       __IM  uint8_t             : 3;
11701       __IOM uint8_t AMPPS7      : 1;            /*!< [7..7] DAC12 output select                                                */
11702     } AMP0PS_b;
11703   } ;
11704   __IM  uint8_t   RESERVED1;
11705 
11706   union {
11707     __IOM uint8_t AMP1MS;                       /*!< (@ 0x0000000A) Operational Amplifier 1 Minus Input Select Register        */
11708 
11709     struct {
11710       __IOM uint8_t AMPMS0      : 1;            /*!< [0..0] AMP1- pin select                                                   */
11711       __IM  uint8_t             : 6;
11712       __IOM uint8_t AMPMS7      : 1;            /*!< [7..7] OPAMP1 output select                                               */
11713     } AMP1MS_b;
11714   } ;
11715 
11716   union {
11717     __IOM uint8_t AMP1PS;                       /*!< (@ 0x0000000B) Operational Amplifier 1 Plus Input Select Register         */
11718 
11719     struct {
11720       __IOM uint8_t AMPPS0      : 1;            /*!< [0..0] AMP1- pin select                                                   */
11721       __IOM uint8_t AMPPS1      : 1;            /*!< [1..1] AMP1+ pin select                                                   */
11722       __IOM uint8_t AMPPS2      : 1;            /*!< [2..2] AMP2- pin select                                                   */
11723       __IOM uint8_t AMPPS3      : 1;            /*!< [3..3] AMP2+ pin select                                                   */
11724       __IM  uint8_t             : 3;
11725       __IOM uint8_t AMPPS7      : 1;            /*!< [7..7] OPAMP2 output select                                               */
11726     } AMP1PS_b;
11727   } ;
11728   __IM  uint8_t   RESERVED2;
11729 
11730   union {
11731     __IOM uint8_t AMP2MS;                       /*!< (@ 0x0000000D) Operational Amplifier 2 Minus Input Select Register        */
11732 
11733     struct {
11734       __IOM uint8_t AMPMS0      : 1;            /*!< [0..0] AMP2- pin select                                                   */
11735       __IM  uint8_t             : 6;
11736       __IOM uint8_t AMPMS7      : 1;            /*!< [7..7] OPAMP2 output select                                               */
11737     } AMP2MS_b;
11738   } ;
11739 
11740   union {
11741     __IOM uint8_t AMP2PS;                       /*!< (@ 0x0000000E) Operational Amplifier 2 Plus Input Select Register         */
11742 
11743     struct {
11744       __IOM uint8_t AMPPS0      : 1;            /*!< [0..0] AMP2- pin select                                                   */
11745       __IOM uint8_t AMPPS1      : 1;            /*!< [1..1] AMP2+ pin select                                                   */
11746       __IM  uint8_t             : 5;
11747       __IOM uint8_t AMPPS7      : 1;            /*!< [7..7] DAC8 channel 1output select                                        */
11748     } AMP2PS_b;
11749   } ;
11750   __IM  uint8_t   RESERVED3;
11751   __IM  uint16_t  RESERVED4;
11752 
11753   union {
11754     __IOM uint8_t AMPCPC;                       /*!< (@ 0x00000012) Operational Amplifier Switch Charge Pump Control
11755                                                                     Register                                                   */
11756 
11757     struct {
11758       __IOM uint8_t PUMP0EN     : 1;            /*!< [0..0] Charge Pump for AMP0 Enable                                        */
11759       __IOM uint8_t PUMP1EN     : 1;            /*!< [1..1] Charge Pump for AMP1 Enable                                        */
11760       __IOM uint8_t PUMP2EN     : 1;            /*!< [2..2] Charge Pump for AMP2 Enable                                        */
11761     } AMPCPC_b;
11762   } ;
11763   __IM  uint8_t   RESERVED5;
11764   __IM  uint16_t  RESERVED6;
11765   __IM  uint8_t   RESERVED7;
11766 
11767   union {
11768     __IOM uint8_t AMPUOTE;                      /*!< (@ 0x00000017) Operational Amplifier User Offset Trimming Enable
11769                                                                     Register                                                   */
11770 
11771     struct {
11772       __IOM uint8_t AMP0TE      : 1;            /*!< [0..0] AMP0OT write enable                                                */
11773       __IOM uint8_t AMP1TE      : 1;            /*!< [1..1] AMP1OT write enable                                                */
11774       __IOM uint8_t AMP2TE      : 1;            /*!< [2..2] AMP2OT write enable                                                */
11775     } AMPUOTE_b;
11776   } ;
11777 
11778   union {
11779     __IOM uint8_t AMP0OTP;                      /*!< (@ 0x00000018) Operational Amplifier 0 Offset Trimming Pch Register       */
11780 
11781     struct {
11782       __IOM uint8_t TRMP        : 5;            /*!< [4..0] AMP0 input offset trimming Pch side                                */
11783     } AMP0OTP_b;
11784   } ;
11785 
11786   union {
11787     __IOM uint8_t AMP0OTN;                      /*!< (@ 0x00000019) Operational Amplifier 0 Offset Trimming Nch Register       */
11788 
11789     struct {
11790       __IOM uint8_t TRMN        : 5;            /*!< [4..0] AMP0 input offset trimming Nch side                                */
11791     } AMP0OTN_b;
11792   } ;
11793 
11794   union {
11795     __IOM uint8_t AMP1OTP;                      /*!< (@ 0x0000001A) Operational Amplifier 1 Offset Trimming Pch Register       */
11796 
11797     struct {
11798       __IOM uint8_t TRMP        : 5;            /*!< [4..0] AMP1 input offset trimming Pch side                                */
11799     } AMP1OTP_b;
11800   } ;
11801 
11802   union {
11803     __IOM uint8_t AMP1OTN;                      /*!< (@ 0x0000001B) Operational Amplifier 1 Offset Trimming Nch Register       */
11804 
11805     struct {
11806       __IOM uint8_t TRMN        : 5;            /*!< [4..0] AMP1 input offset trimming Nch side                                */
11807     } AMP1OTN_b;
11808   } ;
11809 
11810   union {
11811     __IOM uint8_t AMP2OTP;                      /*!< (@ 0x0000001C) Operational Amplifier 2 Offset Trimming Pch Register       */
11812 
11813     struct {
11814       __IOM uint8_t TRMP        : 5;            /*!< [4..0] AMP2 input offset trimming Pch side                                */
11815     } AMP2OTP_b;
11816   } ;
11817 
11818   union {
11819     __IOM uint8_t AMP2OTN;                      /*!< (@ 0x0000001D) Operational Amplifier 2 Offset Trimming Nch Register       */
11820 
11821     struct {
11822       __IOM uint8_t TRMN        : 5;            /*!< [4..0] AMP2 input offset trimming Nch side                                */
11823     } AMP2OTN_b;
11824   } ;
11825 } R_OPAMP_Type;                                   /*!< Size = 30 (0x1e)                                                          */
11826 
11827 
11828 
11829 /* =========================================================================================================================== */
11830 /* ================                                          R_SDADC24                                          ================ */
11831 /* Note: 9/12/17 - The following structure for SDADC24 was hand edited using the output from the R7FS1JA7.svd output file      */
11832 /* =========================================================================================================================== */
11833 
11834 
11835 /**
11836   * @brief 24-Bit Sigma-Delta A/D Converter (R_SDADC24)
11837   */
11838 
11839 typedef struct {                                /*!< (@ 0x4009C000) SDADC24 Structure                                          */
11840 
11841   union {
11842     __IOM uint16_t STC1;                        /*!< (@ 0x00000000) Startup Control Register 1                                 */
11843 
11844     struct {
11845       __IOM uint16_t CLKDIV     : 4;            /*!< [3..0] SDADC24 reference clock division select                            */
11846       __IM  uint16_t            : 3;
11847       __IOM uint16_t SDADLPM    : 1;            /*!< [7..7] A/D conversion operation mode select                               */
11848       __IOM uint16_t VSBIAS     : 4;            /*!< [11..8] Reference voltage select                                          */
11849       __IM  uint16_t            : 3;
11850       __IOM uint16_t VREFSEL    : 1;            /*!< [15..15] VREF mode select                                                 */
11851     } STC1_b;
11852   } ;
11853   __IM  uint16_t  RESERVED;
11854 
11855   union {
11856     __IOM uint8_t STC2;                         /*!< (@ 0x00000004) Startup Control Register 2                                 */
11857 
11858     struct {
11859       __IOM uint8_t BGRPON      : 1;            /*!< [0..0] BGR part power control                                             */
11860       __IOM uint8_t ADCPON      : 1;            /*!< [1..1] ADC reference supply part power control                            */
11861       __IOM uint8_t ADFPWDS     : 1;            /*!< [2..2] ADREG forced power-down mode                                       */
11862     } STC2_b;
11863   } ;
11864   __IM  uint8_t   RESERVED1;
11865   __IM  uint16_t  RESERVED2;
11866 
11867   union {
11868     __IOM uint32_t PGAC0;                       /*!< (@ 0x00000008) Input Multiplexer 0 Setting Register                       */
11869 
11870     struct {
11871       __IOM uint32_t PGAGC      : 5;            /*!< [4..0] Gain selection of a programmable gain instrumentation
11872                                                      amplifier ( Gset1, Gset2, Gtotal )                                        */
11873       __IOM uint32_t PGAOSR     : 3;            /*!< [7..5] Oversampling ratio select                                          */
11874       __IOM uint32_t PGAOFS     : 5;            /*!< [12..8] Offset voltage select                                             */
11875       __IM  uint32_t            : 1;
11876       __IOM uint32_t PGAPOL     : 1;            /*!< [14..14] Polarity select                                                  */
11877       __IOM uint32_t PGASEL     : 1;            /*!< [15..15] Analog Channel Input Mode Select                                 */
11878       __IOM uint32_t PGACTM     : 5;            /*!< [20..16] Coefficient (m) selection of the A/D conversion count
11879                                                      (N) in AUTOSCAN                                                           */
11880       __IOM uint32_t PGACTN     : 3;            /*!< [23..21] Coefficient (n) selection of the A/D conversion count
11881                                                      (N) in AUTOSCAN                                                           */
11882       __IOM uint32_t PGAAVN     : 2;            /*!< [25..24] Selection of the number of data to be averaged                   */
11883       __IOM uint32_t PGAAVE     : 2;            /*!< [27..26] Selection of averaging processing                                */
11884       __IOM uint32_t PGAREV     : 1;            /*!< [28..28] Single-End Input A/D Converted Data Inversion Select             */
11885       __IM  uint32_t            : 1;
11886       __IOM uint32_t PGACVE     : 1;            /*!< [30..30] Calibration enable                                               */
11887       __IOM uint32_t PGAASN     : 1;            /*!< [31..31] Selection of the mode for specifying the number of
11888                                                      A/D conversions in ADSCAN                                                 */
11889     } PGAC0_b;
11890   } ;
11891 
11892   union {
11893     __IOM uint32_t PGAC1;                       /*!< (@ 0x0000000C) Input Multiplexer 1 Setting Register                       */
11894 
11895     struct {
11896       __IOM uint32_t PGAGC      : 5;            /*!< [4..0] Gain selection of a programmable gain instrumentation
11897                                                      amplifier ( Gset1, Gset2, Gtotal )                                        */
11898       __IOM uint32_t PGAOSR     : 3;            /*!< [7..5] Oversampling ratio select                                          */
11899       __IOM uint32_t PGAOFS     : 5;            /*!< [12..8] Offset voltage select                                             */
11900       __IM  uint32_t            : 1;
11901       __IOM uint32_t PGAPOL     : 1;            /*!< [14..14] Polarity select                                                  */
11902       __IOM uint32_t PGASEL     : 1;            /*!< [15..15] Analog Channel Input Mode Select                                 */
11903       __IOM uint32_t PGACTM     : 5;            /*!< [20..16] Coefficient (m) selection of the A/D conversion count
11904                                                      (N) in AUTOSCAN                                                           */
11905       __IOM uint32_t PGACTN     : 3;            /*!< [23..21] Coefficient (n) selection of the A/D conversion count
11906                                                      (N) in AUTOSCAN                                                           */
11907       __IOM uint32_t PGAAVN     : 2;            /*!< [25..24] Selection of the number of data to be averaged                   */
11908       __IOM uint32_t PGAAVE     : 2;            /*!< [27..26] Selection of averaging processing                                */
11909       __IOM uint32_t PGAREV     : 1;            /*!< [28..28] Single-End Input A/D Converted Data Inversion Select             */
11910       __IM  uint32_t            : 1;
11911       __IOM uint32_t PGACVE     : 1;            /*!< [30..30] Calibration enable                                               */
11912       __IOM uint32_t PGAASN     : 1;            /*!< [31..31] Selection of the mode for specifying the number of
11913                                                      A/D conversions in ADSCAN                                                 */
11914     } PGAC1_b;
11915   } ;
11916 
11917   union {
11918     __IOM uint32_t PGAC2;                       /*!< (@ 0x00000010) Input Multiplexer 2 Setting Register                       */
11919 
11920     struct {
11921       __IOM uint32_t PGAGC      : 5;            /*!< [4..0] Gain selection of a programmable gain instrumentation
11922                                                      amplifier ( Gset1, Gset2, Gtotal )                                        */
11923       __IOM uint32_t PGAOSR     : 3;            /*!< [7..5] Oversampling ratio select                                          */
11924       __IOM uint32_t PGAOFS     : 5;            /*!< [12..8] Offset voltage select                                             */
11925       __IM  uint32_t            : 1;
11926       __IOM uint32_t PGAPOL     : 1;            /*!< [14..14] Polarity select                                                  */
11927       __IOM uint32_t PGASEL     : 1;            /*!< [15..15] Analog Channel Input Mode Select                                 */
11928       __IOM uint32_t PGACTM     : 5;            /*!< [20..16] Coefficient (m) selection of the A/D conversion count
11929                                                      (N) in AUTOSCAN                                                           */
11930       __IOM uint32_t PGACTN     : 3;            /*!< [23..21] Coefficient (n) selection of the A/D conversion count
11931                                                      (N) in AUTOSCAN                                                           */
11932       __IOM uint32_t PGAAVN     : 2;            /*!< [25..24] Selection of the number of data to be averaged                   */
11933       __IOM uint32_t PGAAVE     : 2;            /*!< [27..26] Selection of averaging processing                                */
11934       __IOM uint32_t PGAREV     : 1;            /*!< [28..28] Single-End Input A/D Converted Data Inversion Select             */
11935       __IM  uint32_t            : 1;
11936       __IOM uint32_t PGACVE     : 1;            /*!< [30..30] Calibration enable                                               */
11937       __IOM uint32_t PGAASN     : 1;            /*!< [31..31] Selection of the mode for specifying the number of
11938                                                      A/D conversions in ADSCAN                                                 */
11939     } PGAC2_b;
11940   } ;
11941 
11942   union {
11943     __IOM uint32_t PGAC3;                       /*!< (@ 0x00000014) Input Multiplexer 3 Setting Register                       */
11944 
11945     struct {
11946       __IOM uint32_t PGAGC      : 5;            /*!< [4..0] Gain selection of a programmable gain instrumentation
11947                                                      amplifier ( Gset1, Gset2, Gtotal )                                        */
11948       __IOM uint32_t PGAOSR     : 3;            /*!< [7..5] Oversampling ratio select                                          */
11949       __IOM uint32_t PGAOFS     : 5;            /*!< [12..8] Offset voltage select                                             */
11950       __IM  uint32_t            : 1;
11951       __IOM uint32_t PGAPOL     : 1;            /*!< [14..14] Polarity select                                                  */
11952       __IOM uint32_t PGASEL     : 1;            /*!< [15..15] Analog Channel Input Mode Select                                 */
11953       __IOM uint32_t PGACTM     : 5;            /*!< [20..16] Coefficient (m) selection of the A/D conversion count
11954                                                      (N) in AUTOSCAN                                                           */
11955       __IOM uint32_t PGACTN     : 3;            /*!< [23..21] Coefficient (n) selection of the A/D conversion count
11956                                                      (N) in AUTOSCAN                                                           */
11957       __IOM uint32_t PGAAVN     : 2;            /*!< [25..24] Selection of the number of data to be averaged                   */
11958       __IOM uint32_t PGAAVE     : 2;            /*!< [27..26] Selection of averaging processing                                */
11959       __IOM uint32_t PGAREV     : 1;            /*!< [28..28] Single-End Input A/D Converted Data Inversion Select             */
11960       __IM  uint32_t            : 1;
11961       __IOM uint32_t PGACVE     : 1;            /*!< [30..30] Calibration enable                                               */
11962       __IOM uint32_t PGAASN     : 1;            /*!< [31..31] Selection of the mode for specifying the number of
11963                                                      A/D conversions in ADSCAN                                                 */
11964     } PGAC3_b;
11965   } ;
11966 
11967   union {
11968     __IOM uint32_t PGAC4;                       /*!< (@ 0x00000018) Input Multiplexer 4 Setting Register                       */
11969 
11970     struct {
11971       __IOM uint32_t PGAGC      : 5;            /*!< [4..0] Gain selection of a programmable gain instrumentation
11972                                                      amplifier ( Gset1, Gset2, Gtotal )                                        */
11973       __IOM uint32_t PGAOSR     : 3;            /*!< [7..5] Oversampling ratio select                                          */
11974       __IOM uint32_t PGAOFS     : 5;            /*!< [12..8] Offset voltage select                                             */
11975       __IM  uint32_t            : 1;
11976       __IOM uint32_t PGAPOL     : 1;            /*!< [14..14] Polarity select                                                  */
11977       __IOM uint32_t PGASEL     : 1;            /*!< [15..15] Analog Channel Input Mode Select                                 */
11978       __IOM uint32_t PGACTM     : 5;            /*!< [20..16] Coefficient (m) selection of the A/D conversion count
11979                                                      (N) in AUTOSCAN                                                           */
11980       __IOM uint32_t PGACTN     : 3;            /*!< [23..21] Coefficient (n) selection of the A/D conversion count
11981                                                      (N) in AUTOSCAN                                                           */
11982       __IOM uint32_t PGAAVN     : 2;            /*!< [25..24] Selection of the number of data to be averaged                   */
11983       __IOM uint32_t PGAAVE     : 2;            /*!< [27..26] Selection of averaging processing                                */
11984       __IOM uint32_t PGAREV     : 1;            /*!< [28..28] Single-End Input A/D Converted Data Inversion Select             */
11985       __IM  uint32_t            : 1;
11986       __IOM uint32_t PGACVE     : 1;            /*!< [30..30] Calibration enable                                               */
11987       __IOM uint32_t PGAASN     : 1;            /*!< [31..31] Selection of the mode for specifying the number of
11988                                                      A/D conversions in ADSCAN                                                 */
11989     } PGAC4_b;
11990   } ;
11991 
11992   union {
11993     __IOM uint32_t ADC1;                        /*!< (@ 0x0000001C) Sigma-delta A/D Converter Control Register 1               */
11994 
11995     struct {
11996       __IOM uint32_t SDADSCM    : 1;            /*!< [0..0] Selection of autoscan mode                                         */
11997       __IM  uint32_t            : 3;
11998       __IOM uint32_t SDADTMD    : 1;            /*!< [4..4] Selection of A/D conversion trigger signal                         */
11999       __IM  uint32_t            : 3;
12000       __IOM uint32_t SDADBMP    : 5;            /*!< [12..8] A/D conversion control of the signal from input multiplexer       */
12001       __IM  uint32_t            : 3;
12002       __IOM uint32_t PGADISA    : 1;            /*!< [16..16] Control of disconnection detection                               */
12003       __IOM uint32_t PGADISC    : 1;            /*!< [17..17] Disconnection Detection Assist Setting                           */
12004       __IM  uint32_t            : 2;
12005       __IOM uint32_t PGASLFT    : 1;            /*!< [20..20] PGA offset self-diagnosis enable                                 */
12006     } ADC1_b;
12007   } ;
12008 
12009   union {
12010     __IOM uint8_t ADC2;                         /*!< (@ 0x00000020) Sigma-delta A/D Converter Control Register 2               */
12011 
12012     struct {
12013       __IOM uint8_t SDADST      : 1;            /*!< [0..0] Control of A/D conversion                                          */
12014     } ADC2_b;
12015   } ;
12016   __IM  uint8_t   RESERVED3;
12017   __IM  uint16_t  RESERVED4;
12018 
12019   union {
12020     __IOM uint32_t ADCR;                        /*!< (@ 0x00000024) Sigma-delta A/D Converter Conversion Result Register       */
12021 
12022     struct {
12023       __IM  uint32_t SDADCRD    : 24;           /*!< [23..0] The 24-bit A/D conversion result                                  */
12024       __IM  uint32_t SDADCRS    : 1;            /*!< [24..24] Status of an A/D conversion result                               */
12025       __IM  uint32_t SDADCRC    : 3;            /*!< [27..25] Channel number for an A/D conversion result                      */
12026     } ADCR_b;
12027   } ;
12028 
12029   union {
12030     __IM  uint32_t ADAR;                        /*!< (@ 0x00000028) Sigma-delta A/D Converter Average Value Register           */
12031 
12032     struct {
12033       __IM  uint32_t SDADMVD    : 24;           /*!< [23..0] The 24-bit A/D average value                                      */
12034       __IM  uint32_t SDADMVS    : 1;            /*!< [24..24] Status of an A/D conversion result                               */
12035       __IM  uint32_t SDADMVC    : 3;            /*!< [27..25] Channel number for an A/D conversion result                      */
12036     } ADAR_b;
12037   } ;
12038   __IM  uint32_t  RESERVED5;
12039 
12040   union {
12041     __IOM uint8_t CLBC;                         /*!< (@ 0x00000030) Calibration Control Register                               */
12042 
12043     struct {
12044       __IOM uint8_t CLBMD       : 2;            /*!< [1..0] These bits are read as 0. The write value should be 0.             */
12045     } CLBC_b;
12046   } ;
12047   __IM  uint8_t   RESERVED6;
12048   __IM  uint16_t  RESERVED7;
12049 
12050   union {
12051     __IOM uint8_t CLBSTR;                       /*!< (@ 0x00000034) Calibration Start Control Register                         */
12052 
12053     struct {
12054       __IOM uint8_t CLBST       : 1;            /*!< [0..0] Calibration start control                                          */
12055     } CLBSTR_b;
12056   } ;
12057   __IM  uint8_t   RESERVED8;
12058   __IM  uint16_t  RESERVED9;
12059   __IM  uint32_t  RESERVED10;
12060 
12061   union {
12062     __IM  uint8_t CLBSSR;                       /*!< (@ 0x0000003C) Calibration Status Register                                */
12063 
12064     struct {
12065       __IM  uint8_t CLBSS       : 1;            /*!< [0..0] Calibration status                                                 */
12066     } CLBSSR_b;
12067   } ;
12068 } R_SDADC24_Type;                                 /*!< Size = 61 (0x3d)                                                          */
12069 
12070 
12071 /* ================================================================================ */
12072 /* ================                     R_USBFS                    ================ */
12073 /* ================================================================================ */
12074 
12075 
12076 /**
12077   * @brief USB 2.0 FS Host/Function Module (R_USBFS)
12078   */
12079 
12080 typedef struct {                                    /*!< R_USBFS Structure                                                     */
12081 
12082   union {
12083     __IO uint16_t  SYSCFG;                          /*!< System Configuration Control Register                                 */
12084 
12085     struct {
12086       __IO uint16_t  USBE       :  1;               /*!< USB Operation Enable                                                  */
12087            uint16_t             :  3;
12088       __IO uint16_t  DPRPU      :  1;               /*!< D+Line Resistor Control                                               */
12089       __IO uint16_t  DRPD       :  1;               /*!< D+/D-Line Resistor Control                                            */
12090       __IO uint16_t  DCFM       :  1;               /*!< Controller Function Select                                            */
12091            uint16_t             :  3;
12092       __IO uint16_t  SCKE       :  1;               /*!< USB Clock Enable                                                      */
12093     } SYSCFG_b;                                     /*!< BitSize                                                               */
12094   };
12095   __I  uint16_t  RESERVED;
12096 
12097   union {
12098     __I  uint16_t  SYSSTS0;                         /*!< System Configuration Status Register 0                                */
12099 
12100     struct {
12101       __I  uint16_t  LNST       :  2;               /*!< USB Data Line Status Monitor                                          */
12102       __I  uint16_t  IDMON      :  1;               /*!< External ID0 Input Pin Monitor                                        */
12103            uint16_t             :  2;
12104       __I  uint16_t  SOFEA      :  1;               /*!< Active Monitor When the Host Controller is Selected.                  */
12105       __I  uint16_t  HTACT      :  1;               /*!< USB Host Sequencer Status Monitor                                     */
12106            uint16_t             :  7;
12107       __I  uint16_t  OVCMON     :  2;               /*!< External USB0_OVRCURA/ USB0_OVRCURB Input Pin MonitorThe OCVMON[1]
12108                                                          bit indicates the status of the USBHS_OVRCURA pin. The OCVMON[0]
12109                                                           bit indicates the status of the USBHS_OVRCURB pin.                   */
12110     } SYSSTS0_b;                                    /*!< BitSize                                                               */
12111   };
12112   __I  uint16_t  RESERVED1;
12113 
12114   union {
12115     __IO uint16_t  DVSTCTR0;                        /*!< Device State Control Register 0                                       */
12116 
12117     struct {
12118       __I  uint16_t  RHST       :  3;               /*!< USB Bus Reset Status                                                  */
12119            uint16_t             :  1;
12120       __IO uint16_t  UACT       :  1;               /*!< USB Bus Enable                                                        */
12121       __IO uint16_t  RESUME     :  1;               /*!< Resume Output                                                         */
12122       __IO uint16_t  USBRST     :  1;               /*!< USB Bus Reset Output                                                  */
12123       __IO uint16_t  RWUPE      :  1;               /*!< Wakeup Detection Enable                                               */
12124       __IO uint16_t  WKUP       :  1;               /*!< Wakeup Output                                                         */
12125       __IO uint16_t  VBUSEN     :  1;               /*!< USB0_VBUSEN Output Pin Control                                        */
12126       __IO uint16_t  EXICEN     :  1;               /*!< USB0_EXICEN Output Pin Control                                        */
12127       __IO uint16_t  HNPBTOA    :  1;               /*!< Host Negotiation Protocol (HNP) Control This bit is used when
12128                                                          switching from device B to device A while in OTG mode. If the
12129                                                           HNPBTOA bit is 1, the internal function control keeps the suspended
12130                                                           state until the HNP processing ends even though SYSCFG.DPRPU
12131                                                           = 0 or SYSCFG.DCFM = 1 is set.                                       */
12132     } DVSTCTR0_b;                                   /*!< BitSize                                                               */
12133   };
12134   __I  uint16_t  RESERVED2[5];
12135 
12136   union {
12137     __IO uint16_t  CFIFO;                           /*!< CFIFO Port Register                                                   */
12138 
12139     struct {
12140       __IO uint16_t  FIFOPORT   : 16;               /*!< FIFO PortRead receive data from the FIFO buffer or write transmit
12141                                                          data to the FIFO buffer by accessing these bits.                      */
12142     } CFIFO_b;                                      /*!< BitSize                                                               */
12143   };
12144   __I  uint16_t  RESERVED3;
12145 
12146   union {
12147     __IO uint16_t  D0FIFO;                          /*!< D0FIFO Port Register                                                  */
12148 
12149     struct {
12150       __IO uint16_t  FIFOPORT   : 16;               /*!< FIFO PortRead receive data from the FIFO buffer or write transmit
12151                                                          data to the FIFO buffer by accessing these bits.                      */
12152     } D0FIFO_b;                                     /*!< BitSize                                                               */
12153   };
12154   __I  uint16_t  RESERVED4;
12155 
12156   union {
12157     __IO uint16_t  D1FIFO;                          /*!< D1FIFO Port Register                                                  */
12158 
12159     struct {
12160       __IO uint16_t  FIFOPORT   : 16;               /*!< FIFO PortRead receive data from the FIFO buffer or write transmit
12161                                                          data to the FIFO buffer by accessing these bits.                      */
12162     } D1FIFO_b;                                     /*!< BitSize                                                               */
12163   };
12164   __I  uint16_t  RESERVED5;
12165 
12166   union {
12167     __IO uint16_t  CFIFOSEL;                        /*!< CFIFO Port Select Register                                            */
12168 
12169     struct {
12170       __IO uint16_t  CURPIPE    :  4;               /*!< CFIFO Port Access Pipe Specification                                  */
12171            uint16_t             :  1;
12172       __IO uint16_t  ISEL       :  1;               /*!< CFIFO Port Access Direction When DCP is Selected                      */
12173            uint16_t             :  2;
12174       __IO uint16_t  BIGEND     :  1;               /*!< CFIFO Port Endian Control                                             */
12175            uint16_t             :  1;
12176       __IO uint16_t  MBW        :  1;               /*!< CFIFO Port Access Bit Width                                           */
12177            uint16_t             :  3;
12178       __IO uint16_t  REW        :  1;               /*!< Buffer Pointer Rewind                                                 */
12179       __IO uint16_t  RCNT       :  1;               /*!< Read Count Mode                                                       */
12180     } CFIFOSEL_b;                                   /*!< BitSize                                                               */
12181   };
12182 
12183   union {
12184     __IO uint16_t  CFIFOCTR;                        /*!< CFIFO Port Control Register                                           */
12185 
12186     struct {
12187       __I  uint16_t  DTLN       :  9;               /*!< Receive Data LengthIndicates the length of the receive data.          */
12188            uint16_t             :  4;
12189       __I  uint16_t  FRDY       :  1;               /*!< FIFO Port Ready                                                       */
12190       __IO uint16_t  BCLR       :  1;               /*!< CPU Buffer Clear                                                      */
12191       __IO uint16_t  BVAL       :  1;               /*!< Buffer Memory Valid Flag                                              */
12192     } CFIFOCTR_b;                                   /*!< BitSize                                                               */
12193   };
12194   __I  uint32_t  RESERVED6;
12195 
12196   union {
12197     __IO uint16_t  D0FIFOSEL;                       /*!< D0FIFO Port Select Register                                           */
12198 
12199     struct {
12200       __IO uint16_t  CURPIPE    :  4;               /*!< FIFO Port Access Pipe Specification                                   */
12201            uint16_t             :  4;
12202       __IO uint16_t  BIGEND     :  1;               /*!< FIFO Port Endian Control                                              */
12203            uint16_t             :  1;
12204       __IO uint16_t  MBW        :  1;               /*!< FIFO Port Access Bit Width                                            */
12205            uint16_t             :  1;
12206       __IO uint16_t  DREQE      :  1;               /*!< DMA/DTC Transfer Request Enable                                       */
12207       __IO uint16_t  DCLRM      :  1;               /*!< Auto Buffer Memory Clear Mode Accessed after Specified Pipe
12208                                                          Data is Read                                                          */
12209       __IO uint16_t  REW        :  1;               /*!< Buffer Pointer Rewind                                                 */
12210       __IO uint16_t  RCNT       :  1;               /*!< Read Count Mode                                                       */
12211     } D0FIFOSEL_b;                                  /*!< BitSize                                                               */
12212   };
12213 
12214   union {
12215     __IO uint16_t  D0FIFOCTR;                       /*!< D0FIFO Port Control Register                                          */
12216 
12217     struct {
12218       __I  uint16_t  DTLN       :  9;               /*!< Receive Data LengthIndicates the length of the receive data.          */
12219            uint16_t             :  4;
12220       __I  uint16_t  FRDY       :  1;               /*!< FIFO Port Ready                                                       */
12221       __IO uint16_t  BCLR       :  1;               /*!< CPU Buffer Clear                                                      */
12222       __IO uint16_t  BVAL       :  1;               /*!< Buffer Memory Valid Flag                                              */
12223     } D0FIFOCTR_b;                                  /*!< BitSize                                                               */
12224   };
12225 
12226   union {
12227     __IO uint16_t  D1FIFOSEL;                       /*!< D1FIFO Port Select Register                                           */
12228 
12229     struct {
12230       __IO uint16_t  CURPIPE    :  4;               /*!< FIFO Port Access Pipe Specification                                   */
12231            uint16_t             :  4;
12232       __IO uint16_t  BIGEND     :  1;               /*!< FIFO Port Endian Control                                              */
12233            uint16_t             :  1;
12234       __IO uint16_t  MBW        :  1;               /*!< FIFO Port Access Bit Width                                            */
12235            uint16_t             :  1;
12236       __IO uint16_t  DREQE      :  1;               /*!< DMA/DTC Transfer Request Enable                                       */
12237       __IO uint16_t  DCLRM      :  1;               /*!< Auto Buffer Memory Clear Mode Accessed after Specified Pipe
12238                                                          Data is Read                                                          */
12239       __IO uint16_t  REW        :  1;               /*!< Buffer Pointer Rewind                                                 */
12240       __IO uint16_t  RCNT       :  1;               /*!< Read Count Mode                                                       */
12241     } D1FIFOSEL_b;                                  /*!< BitSize                                                               */
12242   };
12243 
12244   union {
12245     __IO uint16_t  D1FIFOCTR;                       /*!< D1FIFO Port Control Register                                          */
12246 
12247     struct {
12248       __I  uint16_t  DTLN       :  9;               /*!< Receive Data LengthIndicates the length of the receive data.          */
12249            uint16_t             :  4;
12250       __I  uint16_t  FRDY       :  1;               /*!< FIFO Port Ready                                                       */
12251       __IO uint16_t  BCLR       :  1;               /*!< CPU Buffer Clear                                                      */
12252       __IO uint16_t  BVAL       :  1;               /*!< Buffer Memory Valid Flag                                              */
12253     } D1FIFOCTR_b;                                  /*!< BitSize                                                               */
12254   };
12255 
12256   union {
12257     __IO uint16_t  INTENB0;                         /*!< Interrupt Enable Register 0                                           */
12258 
12259     struct {
12260            uint16_t             :  8;
12261       __IO uint16_t  BRDYE      :  1;               /*!< Buffer Ready Interrupt Enable                                         */
12262       __IO uint16_t  NRDYE      :  1;               /*!< Buffer Not Ready Response Interrupt Enable                            */
12263       __IO uint16_t  BEMPE      :  1;               /*!< Buffer Empty Interrupt Enable                                         */
12264       __IO uint16_t  CTRE       :  1;               /*!< Control Transfer Stage Transition Interrupt Enable                    */
12265       __IO uint16_t  DVSE       :  1;               /*!< Device State Transition Interrupt Enable                              */
12266       __IO uint16_t  SOFE       :  1;               /*!< Frame Number Update Interrupt Enable                                  */
12267       __IO uint16_t  RSME       :  1;               /*!< Resume Interrupt Enable                                               */
12268       __IO uint16_t  VBSE       :  1;               /*!< VBUS Interrupt Enable                                                 */
12269     } INTENB0_b;                                    /*!< BitSize                                                               */
12270   };
12271 
12272   union {
12273     __IO uint16_t  INTENB1;                         /*!< Interrupt Enable Register 1                                           */
12274 
12275     struct {
12276            uint16_t             :  4;
12277       __IO uint16_t  SACKE      :  1;               /*!< Setup Transaction Normal Response Interrupt Enable                    */
12278       __IO uint16_t  SIGNE      :  1;               /*!< Setup Transaction Error Interrupt Enable                              */
12279       __IO uint16_t  EOFERRE    :  1;               /*!< EOF Error Detection Interrupt Enable                                  */
12280            uint16_t             :  4;
12281       __IO uint16_t  ATTCHE     :  1;               /*!< Connection Detection Interrupt Enable                                 */
12282       __IO uint16_t  DTCHE      :  1;               /*!< Disconnection Detection Interrupt Enable                              */
12283            uint16_t             :  1;
12284       __IO uint16_t  BCHGE      :  1;               /*!< USB Bus Change Interrupt Enable                                       */
12285       __IO uint16_t  OVRCRE     :  1;               /*!< Overcurrent Input Change Interrupt Enable                             */
12286     } INTENB1_b;                                    /*!< BitSize                                                               */
12287   };
12288   __I  uint16_t  RESERVED7;
12289 
12290   union {
12291     __IO uint16_t  BRDYENB;                         /*!< BRDY Interrupt Enable Register                                        */
12292 
12293     struct {
12294       __IO uint16_t  PIPE0BRDY  :  1;               /*!< BRDY Interrupt Enable for PIPE0                                       */
12295       __IO uint16_t  PIPE1BRDY  :  1;               /*!< BRDY Interrupt Enable for PIPE1                                       */
12296       __IO uint16_t  PIPE2BRDY  :  1;               /*!< BRDY Interrupt Enable for PIPE2                                       */
12297       __IO uint16_t  PIPE3BRDY  :  1;               /*!< BRDY Interrupt Enable for PIPE3                                       */
12298       __IO uint16_t  PIPE4BRDY  :  1;               /*!< BRDY Interrupt Enable for PIPE4                                       */
12299       __IO uint16_t  PIPE5BRDY  :  1;               /*!< BRDY Interrupt Enable for PIPE5                                       */
12300       __IO uint16_t  PIPE6BRDY  :  1;               /*!< BRDY Interrupt Enable for PIPE6                                       */
12301       __IO uint16_t  PIPE7BRDY  :  1;               /*!< BRDY Interrupt Enable for PIPE7                                       */
12302       __IO uint16_t  PIPE8BRDY  :  1;               /*!< BRDY Interrupt Enable for PIPE8                                       */
12303       __IO uint16_t  PIPE9BRDY  :  1;               /*!< BRDY Interrupt Enable for PIPE9                                       */
12304     } BRDYENB_b;                                    /*!< BitSize                                                               */
12305   };
12306 
12307   union {
12308     __IO uint16_t  NRDYENB;                         /*!< NRDY Interrupt Enable Register                                        */
12309 
12310     struct {
12311       __IO uint16_t  PIPE0NRDY  :  1;               /*!< NRDY Interrupt Enable for PIPE0                                       */
12312       __IO uint16_t  PIPE1NRDY  :  1;               /*!< NRDY Interrupt Enable for PIPE1                                       */
12313       __IO uint16_t  PIPE2NRDY  :  1;               /*!< NRDY Interrupt Enable for PIPE2                                       */
12314       __IO uint16_t  PIPE3NRDY  :  1;               /*!< NRDY Interrupt Enable for PIPE3                                       */
12315       __IO uint16_t  PIPE4NRDY  :  1;               /*!< NRDY Interrupt Enable for PIPE4                                       */
12316       __IO uint16_t  PIPE5NRDY  :  1;               /*!< NRDY Interrupt Enable for PIPE5                                       */
12317       __IO uint16_t  PIPE6NRDY  :  1;               /*!< NRDY Interrupt Enable for PIPE6                                       */
12318       __IO uint16_t  PIPE7NRDY  :  1;               /*!< NRDY Interrupt Enable for PIPE7                                       */
12319       __IO uint16_t  PIPE8NRDY  :  1;               /*!< NRDY Interrupt Enable for PIPE8                                       */
12320       __IO uint16_t  PIPE9NRDY  :  1;               /*!< NRDY Interrupt Enable for PIPE9                                       */
12321     } NRDYENB_b;                                    /*!< BitSize                                                               */
12322   };
12323 
12324   union {
12325     __IO uint16_t  BEMPENB;                         /*!< BEMP Interrupt Enable Register                                        */
12326 
12327     struct {
12328       __IO uint16_t  PIPE0BEMP  :  1;               /*!< BEMP Interrupt Enable for PIPE0                                       */
12329       __IO uint16_t  PIPE1BEMP  :  1;               /*!< BEMP Interrupt Enable for PIPE1                                       */
12330       __IO uint16_t  PIPE2BEMP  :  1;               /*!< BEMP Interrupt Enable for PIPE2                                       */
12331       __IO uint16_t  PIPE3BEMP  :  1;               /*!< BEMP Interrupt Enable for PIPE3                                       */
12332       __IO uint16_t  PIPE4BEMP  :  1;               /*!< BEMP Interrupt Enable for PIPE4                                       */
12333       __IO uint16_t  PIPE5BEMP  :  1;               /*!< BEMP Interrupt Enable for PIPE5                                       */
12334       __IO uint16_t  PIPE6BEMP  :  1;               /*!< BEMP Interrupt Enable for PIPE6                                       */
12335       __IO uint16_t  PIPE7BEMP  :  1;               /*!< BEMP Interrupt Enable for PIPE7                                       */
12336       __IO uint16_t  PIPE8BEMP  :  1;               /*!< BEMP Interrupt Enable for PIPE8                                       */
12337       __IO uint16_t  PIPE9BEMP  :  1;               /*!< BEMP Interrupt Enable for PIPE9                                       */
12338     } BEMPENB_b;                                    /*!< BitSize                                                               */
12339   };
12340 
12341   union {
12342     __IO uint16_t  SOFCFG;                          /*!< SOF Output Configuration Register                                     */
12343 
12344     struct {
12345            uint16_t             :  4;
12346       __I  uint16_t  EDGESTS    :  1;               /*!< Edge Interrupt Output Status Monitor                                  */
12347            uint16_t             :  1;
12348       __IO uint16_t  BRDYM      :  1;               /*!< BRDY Interrupt Status Clear Timing                                    */
12349            uint16_t             :  1;
12350       __IO uint16_t  TRNENSEL   :  1;               /*!< Transaction-Enabled Time Select                                       */
12351     } SOFCFG_b;                                     /*!< BitSize                                                               */
12352   };
12353   __I  uint16_t  RESERVED8;
12354 
12355   union {
12356     __IO uint16_t  INTSTS0;                         /*!< Interrupt Status Register 0                                           */
12357 
12358     struct {
12359       __I  uint16_t  CTSQ       :  3;               /*!< Control Transfer Stage                                                */
12360       __IO uint16_t  VALID      :  1;               /*!< USB Request Reception                                                 */
12361       __I  uint16_t  DVSQ       :  3;               /*!< Device State                                                          */
12362       __I  uint16_t  VBSTS      :  1;               /*!< VBUS Input Status                                                     */
12363       __I  uint16_t  BRDY       :  1;               /*!< Buffer Ready Interrupt Status                                         */
12364       __I  uint16_t  NRDY       :  1;               /*!< Buffer Not Ready Interrupt Status                                     */
12365       __I  uint16_t  BEMP       :  1;               /*!< Buffer Empty Interrupt Status                                         */
12366       __IO uint16_t  CTRT       :  1;               /*!< Control Transfer Stage Transition Interrupt Status                    */
12367       __IO uint16_t  DVST       :  1;               /*!< Device State Transition Interrupt Status                              */
12368       __IO uint16_t  SOFR       :  1;               /*!< Frame Number Refresh Interrupt Status                                 */
12369       __IO uint16_t  RESM       :  1;               /*!< Resume Interrupt Status                                               */
12370       __IO uint16_t  VBINT      :  1;               /*!< VBUS Interrupt Status                                                 */
12371     } INTSTS0_b;                                    /*!< BitSize                                                               */
12372   };
12373 
12374   union {
12375     __IO uint16_t  INTSTS1;                         /*!< Interrupt Status Register 1                                           */
12376 
12377     struct {
12378            uint16_t             :  4;
12379       __IO uint16_t  SACK       :  1;               /*!< Setup Transaction Normal Response Interrupt Status                    */
12380       __IO uint16_t  SIGN       :  1;               /*!< Setup Transaction Error Interrupt Status                              */
12381       __IO uint16_t  EOFERR     :  1;               /*!< EOF Error Detection Interrupt Status                                  */
12382            uint16_t             :  4;
12383       __IO uint16_t  ATTCH      :  1;               /*!< ATTCH Interrupt Status                                                */
12384       __IO uint16_t  DTCH       :  1;               /*!< USB Disconnection Detection Interrupt Status                          */
12385            uint16_t             :  1;
12386       __IO uint16_t  BCHG       :  1;               /*!< USB Bus Change Interrupt Status                                       */
12387       __IO uint16_t  OVRCR      :  1;               /*!< Overcurrent Input Change Interrupt Status                             */
12388     } INTSTS1_b;                                    /*!< BitSize                                                               */
12389   };
12390   __I  uint16_t  RESERVED9;
12391 
12392   union {
12393     __IO uint16_t  BRDYSTS;                         /*!< BRDY Interrupt Status Register                                        */
12394 
12395     struct {
12396       __IO uint16_t  PIPE0BRDY  :  1;               /*!< BRDY Interrupt Status for PIPE0                                       */
12397       __IO uint16_t  PIPE1BRDY  :  1;               /*!< BRDY Interrupt Status for PIPE1                                       */
12398       __IO uint16_t  PIPE2BRDY  :  1;               /*!< BRDY Interrupt Status for PIPE2                                       */
12399       __IO uint16_t  PIPE3BRDY  :  1;               /*!< BRDY Interrupt Status for PIPE3                                       */
12400       __IO uint16_t  PIPE4BRDY  :  1;               /*!< BRDY Interrupt Status for PIPE4                                       */
12401       __IO uint16_t  PIPE5BRDY  :  1;               /*!< BRDY Interrupt Status for PIPE5                                       */
12402       __IO uint16_t  PIPE6BRDY  :  1;               /*!< BRDY Interrupt Status for PIPE6                                       */
12403       __IO uint16_t  PIPE7BRDY  :  1;               /*!< BRDY Interrupt Status for PIPE7                                       */
12404       __IO uint16_t  PIPE8BRDY  :  1;               /*!< BRDY Interrupt Status for PIPE8                                       */
12405       __IO uint16_t  PIPE9BRDY  :  1;               /*!< BRDY Interrupt Status for PIPE9                                       */
12406     } BRDYSTS_b;                                    /*!< BitSize                                                               */
12407   };
12408 
12409   union {
12410     __IO uint16_t  NRDYSTS;                         /*!< NRDY Interrupt Status Register                                        */
12411 
12412     struct {
12413       __IO uint16_t  PIPE0NRDY  :  1;               /*!< NRDY Interrupt Status for PIPE0                                       */
12414       __IO uint16_t  PIPE1NRDY  :  1;               /*!< NRDY Interrupt Status for PIPE1                                       */
12415       __IO uint16_t  PIPE2NRDY  :  1;               /*!< NRDY Interrupt Status for PIPE2                                       */
12416       __IO uint16_t  PIPE3NRDY  :  1;               /*!< NRDY Interrupt Status for PIPE3                                       */
12417       __IO uint16_t  PIPE4NRDY  :  1;               /*!< NRDY Interrupt Status for PIPE4                                       */
12418       __IO uint16_t  PIPE5NRDY  :  1;               /*!< NRDY Interrupt Status for PIPE5                                       */
12419       __IO uint16_t  PIPE6NRDY  :  1;               /*!< NRDY Interrupt Status for PIPE6                                       */
12420       __IO uint16_t  PIPE7NRDY  :  1;               /*!< NRDY Interrupt Status for PIPE7                                       */
12421       __IO uint16_t  PIPE8NRDY  :  1;               /*!< NRDY Interrupt Status for PIPE8                                       */
12422       __IO uint16_t  PIPE9NRDY  :  1;               /*!< NRDY Interrupt Status for PIPE9                                       */
12423     } NRDYSTS_b;                                    /*!< BitSize                                                               */
12424   };
12425 
12426   union {
12427     __IO uint16_t  BEMPSTS;                         /*!< BEMP Interrupt Status Register                                        */
12428 
12429     struct {
12430       __IO uint16_t  PIPE0BEMP  :  1;               /*!< BEMP Interrupt Status for PIPE0                                       */
12431       __IO uint16_t  PIPE1BEMP  :  1;               /*!< BEMP Interrupt Status for PIPE1                                       */
12432       __IO uint16_t  PIPE2BEMP  :  1;               /*!< BEMP Interrupt Status for PIPE2                                       */
12433       __IO uint16_t  PIPE3BEMP  :  1;               /*!< BEMP Interrupt Status for PIPE3                                       */
12434       __IO uint16_t  PIPE4BEMP  :  1;               /*!< BEMP Interrupt Status for PIPE4                                       */
12435       __IO uint16_t  PIPE5BEMP  :  1;               /*!< BEMP Interrupt Status for PIPE5                                       */
12436       __IO uint16_t  PIPE6BEMP  :  1;               /*!< BEMP Interrupt Status for PIPE6                                       */
12437       __IO uint16_t  PIPE7BEMP  :  1;               /*!< BEMP Interrupt Status for PIPE7                                       */
12438       __IO uint16_t  PIPE8BEMP  :  1;               /*!< BEMP Interrupt Status for PIPE8                                       */
12439       __IO uint16_t  PIPE9BEMP  :  1;               /*!< BEMP Interrupt Status for PIPE9                                       */
12440     } BEMPSTS_b;                                    /*!< BitSize                                                               */
12441   };
12442 
12443   union {
12444     __IO uint16_t  FRMNUM;                          /*!< Frame Number Register                                                 */
12445 
12446     struct {
12447       __I  uint16_t  FRNM       : 11;               /*!< Frame NumberLatest frame number                                       */
12448            uint16_t             :  3;
12449       __IO uint16_t  CRCE       :  1;               /*!< Receive Data Error                                                    */
12450       __IO uint16_t  OVRN       :  1;               /*!< Overrun/Underrun Detection Status                                     */
12451     } FRMNUM_b;                                     /*!< BitSize                                                               */
12452   };
12453 
12454   union {
12455     __IO uint16_t  DVCHGR;                          /*!< Device State Change Register                                          */
12456 
12457     struct {
12458            uint16_t             : 15;
12459       __IO uint16_t  DVCHG      :  1;               /*!< Device State Change                                                   */
12460     } DVCHGR_b;                                     /*!< BitSize                                                               */
12461   };
12462 
12463   union {
12464     __IO uint16_t  USBADDR;                         /*!< USB Address Register                                                  */
12465 
12466     struct {
12467       __IO uint16_t  USBADDR    :  7;               /*!< USB AddressWhen the function controller is selected, these bits
12468                                                          indicate the USB address assigned by the host when the SET_ADDRESS
12469                                                           request is successfully processed.                                   */
12470            uint16_t             :  1;
12471       __IO uint16_t  STSRECOV   :  4;               /*!< Status Recovery                                                       */
12472     } USBADDR_b;                                    /*!< BitSize                                                               */
12473   };
12474   __I  uint16_t  RESERVED10;
12475 
12476   union {
12477     __IO uint16_t  USBREQ;                          /*!< USB Request Type Register                                             */
12478 
12479     struct {
12480       __IO uint16_t  BMREQUESTTYPE:  8;             /*!< Request TypeThese bits store the USB request bmRequestType value.     */
12481       __IO uint16_t  BREQUEST   :  8;               /*!< RequestThese bits store the USB request bRequest value.               */
12482     } USBREQ_b;                                     /*!< BitSize                                                               */
12483   };
12484 
12485   union {
12486     __IO uint16_t  USBVAL;                          /*!< USB Request Value Register                                            */
12487 
12488     struct {
12489       __IO uint16_t  WVALUE     : 16;               /*!< ValueThese bits store the USB request wValue value.                   */
12490     } USBVAL_b;                                     /*!< BitSize                                                               */
12491   };
12492 
12493   union {
12494     __IO uint16_t  USBINDX;                         /*!< USB Request Index Register                                            */
12495 
12496     struct {
12497       __IO uint16_t  WINDEX     : 16;               /*!< IndexThese bits store the USB request wIndex value.                   */
12498     } USBINDX_b;                                    /*!< BitSize                                                               */
12499   };
12500 
12501   union {
12502     __IO uint16_t  USBLENG;                         /*!< USB Request Length Register                                           */
12503 
12504     struct {
12505       __IO uint16_t  WLENGTH    : 16;               /*!< LengthThese bits store the USB request wLength value.                 */
12506     } USBLENG_b;                                    /*!< BitSize                                                               */
12507   };
12508 
12509   union {
12510     __IO uint16_t  DCPCFG;                          /*!< DCP Configuration Register                                            */
12511 
12512     struct {
12513            uint16_t             :  4;
12514       __IO uint16_t  DIR        :  1;               /*!< Transfer Direction                                                    */
12515            uint16_t             :  2;
12516       __IO uint16_t  SHTNAK     :  1;               /*!< Pipe Disabled at End of Transfer                                      */
12517     } DCPCFG_b;                                     /*!< BitSize                                                               */
12518   };
12519 
12520   union {
12521     __IO uint16_t  DCPMAXP;                         /*!< DCP Maximum Packet Size Register                                      */
12522 
12523     struct {
12524       __IO uint16_t  MXPS       :  7;               /*!< Maximum Packet SizeThese bits set the maximum amount of data
12525                                                          (maximum packet size) in payloads for the DCP.                        */
12526            uint16_t             :  5;
12527       __IO uint16_t  DEVSEL     :  4;               /*!< Device Select                                                         */
12528     } DCPMAXP_b;                                    /*!< BitSize                                                               */
12529   };
12530 
12531   union {
12532     __IO uint16_t  DCPCTR;                          /*!< DCP Control Register                                                  */
12533 
12534     struct {
12535       __IO uint16_t  PID        :  2;               /*!< Response PID                                                          */
12536       __IO uint16_t  CCPL       :  1;               /*!< Control Transfer End Enable                                           */
12537            uint16_t             :  2;
12538       __I  uint16_t  PBUSY      :  1;               /*!< Pipe Busy                                                             */
12539       __I  uint16_t  SQMON      :  1;               /*!< Sequence Toggle Bit Monitor                                           */
12540       __IO uint16_t  SQSET      :  1;               /*!< Sequence Toggle Bit Set                                               */
12541       __IO uint16_t  SQCLR      :  1;               /*!< Sequence Toggle Bit Clear                                             */
12542            uint16_t             :  2;
12543       __IO uint16_t  SUREQCLR   :  1;               /*!< SUREQ Bit Clear                                                       */
12544            uint16_t             :  2;
12545       __IO uint16_t  SUREQ      :  1;               /*!< Setup Token Transmission                                              */
12546       __I  uint16_t  BSTS       :  1;               /*!< Buffer Status                                                         */
12547     } DCPCTR_b;                                     /*!< BitSize                                                               */
12548   };
12549   __I  uint16_t  RESERVED11;
12550 
12551   union {
12552     __IO uint16_t  PIPESEL;                         /*!< Pipe Window Select Register                                           */
12553 
12554     struct {
12555       __IO uint16_t  PIPESEL    :  4;               /*!< Pipe Window Select                                                    */
12556     } PIPESEL_b;                                    /*!< BitSize                                                               */
12557   };
12558   __I  uint16_t  RESERVED12;
12559 
12560   union {
12561     __IO uint16_t  PIPECFG;                         /*!< Pipe Configuration Register                                           */
12562 
12563     struct {
12564       __IO uint16_t  EPNUM      :  4;               /*!< Endpoint NumberThese bits specify the endpoint number for the
12565                                                          selected pipe.Setting 0000b means unused pipe.                        */
12566       __IO uint16_t  DIR        :  1;               /*!< Transfer Direction                                                    */
12567            uint16_t             :  2;
12568       __IO uint16_t  SHTNAK     :  1;               /*!< Pipe Disabled at End of Transfer                                      */
12569            uint16_t             :  1;
12570       __IO uint16_t  DBLB       :  1;               /*!< Double Buffer Mode                                                    */
12571       __IO uint16_t  BFRE       :  1;               /*!< BRDY Interrupt Operation Specification                                */
12572            uint16_t             :  3;
12573       __IO uint16_t  TYPE       :  2;               /*!< Transfer Type                                                         */
12574     } PIPECFG_b;                                    /*!< BitSize                                                               */
12575   };
12576   __I  uint16_t  RESERVED13;
12577 
12578   union {
12579     __IO uint16_t  PIPEMAXP;                        /*!< Pipe Maximum Packet Size Register                                     */
12580 
12581     struct {
12582       __IO uint16_t  MXPS       :  9;               /*!< Maximum Packet SizePIPE1 and PIPE2: 1 byte (001h) to 256 bytes
12583                                                          (100h)PIPE3 to PIPE5: 8 bytes (008h), 16 bytes (010h), 32 bytes
12584                                                           (020h), 64 bytes (040h) (Bits [8:7] and [2:0] are not provided.)PIPE6
12585                                                           to PIPE9: 1 byte (001h) to 64 bytes (040h) (Bits [8:7] are not
12586                                                           provided.)                                                           */
12587            uint16_t             :  3;
12588       __IO uint16_t  DEVSEL     :  4;               /*!< Device Select                                                         */
12589     } PIPEMAXP_b;                                   /*!< BitSize                                                               */
12590   };
12591 
12592   union {
12593     __IO uint16_t  PIPEPERI;                        /*!< Pipe Cycle Control Register                                           */
12594 
12595     struct {
12596       __IO uint16_t  IITV       :  3;               /*!< Interval Error Detection IntervalSpecifies the interval error
12597                                                          detection timing for the selected pipe in terms of frames, which
12598                                                           is expressed as nth power of 2.                                      */
12599            uint16_t             :  9;
12600       __IO uint16_t  IFIS       :  1;               /*!< Isochronous IN Buffer Flush                                           */
12601     } PIPEPERI_b;                                   /*!< BitSize                                                               */
12602   };
12603 
12604   union {
12605     __IO uint16_t  PIPE1CTR;                        /*!< Pipe %s Control Register                                              */
12606 
12607     struct {
12608       __IO uint16_t  PID        :  2;               /*!< Response PID                                                          */
12609            uint16_t             :  3;
12610       __I  uint16_t  PBUSY      :  1;               /*!< Pipe Busy                                                             */
12611       __I  uint16_t  SQMON      :  1;               /*!< Sequence Toggle Bit Confirmation                                      */
12612       __IO uint16_t  SQSET      :  1;               /*!< Sequence Toggle Bit Set                                               */
12613       __IO uint16_t  SQCLR      :  1;               /*!< Sequence Toggle Bit Clear                                             */
12614       __IO uint16_t  ACLRM      :  1;               /*!< Auto Buffer Clear Mode                                                */
12615       __IO uint16_t  ATREPM     :  1;               /*!< Auto Response Mode                                                    */
12616            uint16_t             :  3;
12617       __I  uint16_t  INBUFM     :  1;               /*!< Transmit Buffer Monitor                                               */
12618       __I  uint16_t  BSTS       :  1;               /*!< Buffer Status                                                         */
12619     } PIPE1CTR_b;                                   /*!< BitSize                                                               */
12620   };
12621 
12622   union {
12623     __IO uint16_t  PIPE2CTR;                        /*!< Pipe %s Control Register                                              */
12624 
12625     struct {
12626       __IO uint16_t  PID        :  2;               /*!< Response PID                                                          */
12627            uint16_t             :  3;
12628       __I  uint16_t  PBUSY      :  1;               /*!< Pipe Busy                                                             */
12629       __I  uint16_t  SQMON      :  1;               /*!< Sequence Toggle Bit Confirmation                                      */
12630       __IO uint16_t  SQSET      :  1;               /*!< Sequence Toggle Bit Set                                               */
12631       __IO uint16_t  SQCLR      :  1;               /*!< Sequence Toggle Bit Clear                                             */
12632       __IO uint16_t  ACLRM      :  1;               /*!< Auto Buffer Clear Mode                                                */
12633       __IO uint16_t  ATREPM     :  1;               /*!< Auto Response Mode                                                    */
12634            uint16_t             :  3;
12635       __I  uint16_t  INBUFM     :  1;               /*!< Transmit Buffer Monitor                                               */
12636       __I  uint16_t  BSTS       :  1;               /*!< Buffer Status                                                         */
12637     } PIPE2CTR_b;                                   /*!< BitSize                                                               */
12638   };
12639 
12640   union {
12641     __IO uint16_t  PIPE3CTR;                        /*!< Pipe %s Control Register                                              */
12642 
12643     struct {
12644       __IO uint16_t  PID        :  2;               /*!< Response PID                                                          */
12645            uint16_t             :  3;
12646       __I  uint16_t  PBUSY      :  1;               /*!< Pipe Busy                                                             */
12647       __I  uint16_t  SQMON      :  1;               /*!< Sequence Toggle Bit Confirmation                                      */
12648       __IO uint16_t  SQSET      :  1;               /*!< Sequence Toggle Bit Set                                               */
12649       __IO uint16_t  SQCLR      :  1;               /*!< Sequence Toggle Bit Clear                                             */
12650       __IO uint16_t  ACLRM      :  1;               /*!< Auto Buffer Clear Mode                                                */
12651       __IO uint16_t  ATREPM     :  1;               /*!< Auto Response Mode                                                    */
12652            uint16_t             :  3;
12653       __I  uint16_t  INBUFM     :  1;               /*!< Transmit Buffer Monitor                                               */
12654       __I  uint16_t  BSTS       :  1;               /*!< Buffer Status                                                         */
12655     } PIPE3CTR_b;                                   /*!< BitSize                                                               */
12656   };
12657 
12658   union {
12659     __IO uint16_t  PIPE4CTR;                        /*!< Pipe %s Control Register                                              */
12660 
12661     struct {
12662       __IO uint16_t  PID        :  2;               /*!< Response PID                                                          */
12663            uint16_t             :  3;
12664       __I  uint16_t  PBUSY      :  1;               /*!< Pipe Busy                                                             */
12665       __I  uint16_t  SQMON      :  1;               /*!< Sequence Toggle Bit Confirmation                                      */
12666       __IO uint16_t  SQSET      :  1;               /*!< Sequence Toggle Bit Set                                               */
12667       __IO uint16_t  SQCLR      :  1;               /*!< Sequence Toggle Bit Clear                                             */
12668       __IO uint16_t  ACLRM      :  1;               /*!< Auto Buffer Clear Mode                                                */
12669       __IO uint16_t  ATREPM     :  1;               /*!< Auto Response Mode                                                    */
12670            uint16_t             :  3;
12671       __I  uint16_t  INBUFM     :  1;               /*!< Transmit Buffer Monitor                                               */
12672       __I  uint16_t  BSTS       :  1;               /*!< Buffer Status                                                         */
12673     } PIPE4CTR_b;                                   /*!< BitSize                                                               */
12674   };
12675 
12676   union {
12677     __IO uint16_t  PIPE5CTR;                        /*!< Pipe %s Control Register                                              */
12678 
12679     struct {
12680       __IO uint16_t  PID        :  2;               /*!< Response PID                                                          */
12681            uint16_t             :  3;
12682       __I  uint16_t  PBUSY      :  1;               /*!< Pipe Busy                                                             */
12683       __I  uint16_t  SQMON      :  1;               /*!< Sequence Toggle Bit Confirmation                                      */
12684       __IO uint16_t  SQSET      :  1;               /*!< Sequence Toggle Bit Set                                               */
12685       __IO uint16_t  SQCLR      :  1;               /*!< Sequence Toggle Bit Clear                                             */
12686       __IO uint16_t  ACLRM      :  1;               /*!< Auto Buffer Clear Mode                                                */
12687       __IO uint16_t  ATREPM     :  1;               /*!< Auto Response Mode                                                    */
12688            uint16_t             :  3;
12689       __I  uint16_t  INBUFM     :  1;               /*!< Transmit Buffer Monitor                                               */
12690       __I  uint16_t  BSTS       :  1;               /*!< Buffer Status                                                         */
12691     } PIPE5CTR_b;                                   /*!< BitSize                                                               */
12692   };
12693 
12694   union {
12695     __IO uint16_t  PIPE6CTR;                        /*!< Pipe %s Control Register                                              */
12696 
12697     struct {
12698       __IO uint16_t  PID        :  2;               /*!< Response PID                                                          */
12699            uint16_t             :  3;
12700       __I  uint16_t  PBUSY      :  1;               /*!< Pipe Busy                                                             */
12701       __I  uint16_t  SQMON      :  1;               /*!< Sequence Toggle Bit Confirmation                                      */
12702       __IO uint16_t  SQSET      :  1;               /*!< Sequence Toggle Bit Set                                               */
12703       __IO uint16_t  SQCLR      :  1;               /*!< Sequence Toggle Bit Clear                                             */
12704       __IO uint16_t  ACLRM      :  1;               /*!< Auto Buffer Clear Mode                                                */
12705            uint16_t             :  5;
12706       __I  uint16_t  BSTS       :  1;               /*!< Buffer Status                                                         */
12707     } PIPE6CTR_b;                                   /*!< BitSize                                                               */
12708   };
12709 
12710   union {
12711     __IO uint16_t  PIPE7CTR;                        /*!< Pipe %s Control Register                                              */
12712 
12713     struct {
12714       __IO uint16_t  PID        :  2;               /*!< Response PID                                                          */
12715            uint16_t             :  3;
12716       __I  uint16_t  PBUSY      :  1;               /*!< Pipe Busy                                                             */
12717       __I  uint16_t  SQMON      :  1;               /*!< Sequence Toggle Bit Confirmation                                      */
12718       __IO uint16_t  SQSET      :  1;               /*!< Sequence Toggle Bit Set                                               */
12719       __IO uint16_t  SQCLR      :  1;               /*!< Sequence Toggle Bit Clear                                             */
12720       __IO uint16_t  ACLRM      :  1;               /*!< Auto Buffer Clear Mode                                                */
12721            uint16_t             :  5;
12722       __I  uint16_t  BSTS       :  1;               /*!< Buffer Status                                                         */
12723     } PIPE7CTR_b;                                   /*!< BitSize                                                               */
12724   };
12725 
12726   union {
12727     __IO uint16_t  PIPE8CTR;                        /*!< Pipe %s Control Register                                              */
12728 
12729     struct {
12730       __IO uint16_t  PID        :  2;               /*!< Response PID                                                          */
12731            uint16_t             :  3;
12732       __I  uint16_t  PBUSY      :  1;               /*!< Pipe Busy                                                             */
12733       __I  uint16_t  SQMON      :  1;               /*!< Sequence Toggle Bit Confirmation                                      */
12734       __IO uint16_t  SQSET      :  1;               /*!< Sequence Toggle Bit Set                                               */
12735       __IO uint16_t  SQCLR      :  1;               /*!< Sequence Toggle Bit Clear                                             */
12736       __IO uint16_t  ACLRM      :  1;               /*!< Auto Buffer Clear Mode                                                */
12737            uint16_t             :  5;
12738       __I  uint16_t  BSTS       :  1;               /*!< Buffer Status                                                         */
12739     } PIPE8CTR_b;                                   /*!< BitSize                                                               */
12740   };
12741 
12742   union {
12743     __IO uint16_t  PIPE9CTR;                        /*!< Pipe %s Control Register                                              */
12744 
12745     struct {
12746       __IO uint16_t  PID        :  2;               /*!< Response PID                                                          */
12747            uint16_t             :  3;
12748       __I  uint16_t  PBUSY      :  1;               /*!< Pipe Busy                                                             */
12749       __I  uint16_t  SQMON      :  1;               /*!< Sequence Toggle Bit Confirmation                                      */
12750       __IO uint16_t  SQSET      :  1;               /*!< Sequence Toggle Bit Set                                               */
12751       __IO uint16_t  SQCLR      :  1;               /*!< Sequence Toggle Bit Clear                                             */
12752       __IO uint16_t  ACLRM      :  1;               /*!< Auto Buffer Clear Mode                                                */
12753            uint16_t             :  5;
12754       __I  uint16_t  BSTS       :  1;               /*!< Buffer Status                                                         */
12755     } PIPE9CTR_b;                                   /*!< BitSize                                                               */
12756   };
12757   __I  uint16_t  RESERVED14[7];
12758 
12759   union {
12760     __IO uint16_t  PIPE1TRE;                        /*!< Pipe %s Transaction Counter Enable Register                           */
12761 
12762     struct {
12763            uint16_t             :  8;
12764       __IO uint16_t  TRCLR      :  1;               /*!< Transaction Counter Clear                                             */
12765       __IO uint16_t  TRENB      :  1;               /*!< Transaction Counter Enable                                            */
12766     } PIPE1TRE_b;                                   /*!< BitSize                                                               */
12767   };
12768 
12769   union {
12770     __IO uint16_t  PIPE1TRN;                        /*!< Pipe %s Transaction Counter Register                                  */
12771 
12772     struct {
12773       __IO uint16_t  TRNCNT     : 16;               /*!< Transaction Counter                                                   */
12774     } PIPE1TRN_b;                                   /*!< BitSize                                                               */
12775   };
12776 
12777   union {
12778     __IO uint16_t  PIPE2TRE;                        /*!< Pipe %s Transaction Counter Enable Register                           */
12779 
12780     struct {
12781            uint16_t             :  8;
12782       __IO uint16_t  TRCLR      :  1;               /*!< Transaction Counter Clear                                             */
12783       __IO uint16_t  TRENB      :  1;               /*!< Transaction Counter Enable                                            */
12784     } PIPE2TRE_b;                                   /*!< BitSize                                                               */
12785   };
12786 
12787   union {
12788     __IO uint16_t  PIPE2TRN;                        /*!< Pipe %s Transaction Counter Register                                  */
12789 
12790     struct {
12791       __IO uint16_t  TRNCNT     : 16;               /*!< Transaction Counter                                                   */
12792     } PIPE2TRN_b;                                   /*!< BitSize                                                               */
12793   };
12794 
12795   union {
12796     __IO uint16_t  PIPE3TRE;                        /*!< Pipe %s Transaction Counter Enable Register                           */
12797 
12798     struct {
12799            uint16_t             :  8;
12800       __IO uint16_t  TRCLR      :  1;               /*!< Transaction Counter Clear                                             */
12801       __IO uint16_t  TRENB      :  1;               /*!< Transaction Counter Enable                                            */
12802     } PIPE3TRE_b;                                   /*!< BitSize                                                               */
12803   };
12804 
12805   union {
12806     __IO uint16_t  PIPE3TRN;                        /*!< Pipe %s Transaction Counter Register                                  */
12807 
12808     struct {
12809       __IO uint16_t  TRNCNT     : 16;               /*!< Transaction Counter                                                   */
12810     } PIPE3TRN_b;                                   /*!< BitSize                                                               */
12811   };
12812 
12813   union {
12814     __IO uint16_t  PIPE4TRE;                        /*!< Pipe %s Transaction Counter Enable Register                           */
12815 
12816     struct {
12817            uint16_t             :  8;
12818       __IO uint16_t  TRCLR      :  1;               /*!< Transaction Counter Clear                                             */
12819       __IO uint16_t  TRENB      :  1;               /*!< Transaction Counter Enable                                            */
12820     } PIPE4TRE_b;                                   /*!< BitSize                                                               */
12821   };
12822 
12823   union {
12824     __IO uint16_t  PIPE4TRN;                        /*!< Pipe %s Transaction Counter Register                                  */
12825 
12826     struct {
12827       __IO uint16_t  TRNCNT     : 16;               /*!< Transaction Counter                                                   */
12828     } PIPE4TRN_b;                                   /*!< BitSize                                                               */
12829   };
12830 
12831   union {
12832     __IO uint16_t  PIPE5TRE;                        /*!< Pipe %s Transaction Counter Enable Register                           */
12833 
12834     struct {
12835            uint16_t             :  8;
12836       __IO uint16_t  TRCLR      :  1;               /*!< Transaction Counter Clear                                             */
12837       __IO uint16_t  TRENB      :  1;               /*!< Transaction Counter Enable                                            */
12838     } PIPE5TRE_b;                                   /*!< BitSize                                                               */
12839   };
12840 
12841   union {
12842     __IO uint16_t  PIPE5TRN;                        /*!< Pipe %s Transaction Counter Register                                  */
12843 
12844     struct {
12845       __IO uint16_t  TRNCNT     : 16;               /*!< Transaction Counter                                                   */
12846     } PIPE5TRN_b;                                   /*!< BitSize                                                               */
12847   };
12848   __I  uint32_t  RESERVED15[3];
12849 
12850   union {
12851     __IO uint16_t  USBBCCTRL0;                      /*!< BC Control Register 0                                                 */
12852 
12853     struct {
12854       __IO uint16_t  RPDME0     :  1;               /*!< D- Pin Pull-Down Control                                              */
12855       __IO uint16_t  IDPSRCE0   :  1;               /*!< D+ Pin IDPSRC Output Control                                          */
12856       __IO uint16_t  IDMSINKE0  :  1;               /*!< D- Pin 0.6 V Input Detection (Comparator and Sink) Control            */
12857       __IO uint16_t  VDPSRCE0   :  1;               /*!< D+ Pin VDPSRC (0.6 V) Output Control                                  */
12858       __IO uint16_t  IDPSINKE0  :  1;               /*!< D+ Pin 0.6 V Input Detection (Comparator and Sink) Control            */
12859       __IO uint16_t  VDMSRCE0   :  1;               /*!< D- Pin VDMSRC (0.6 V) Output Control                                  */
12860            uint16_t             :  1;
12861       __IO uint16_t  BATCHGE0   :  1;               /*!< BC (Battery Charger) Function Ch0 General Enable Control              */
12862       __IO uint16_t  CHGDETSTS0 :  1;               /*!< D- Pin 0.6 V Input Detection Status                                   */
12863       __IO uint16_t  PDDETSTS0  :  1;               /*!< D+ Pin 0.6 V Input Detection Status                                   */
12864     } USBBCCTRL0_b;                                 /*!< BitSize                                                               */
12865   };
12866   __I  uint16_t  RESERVED16[13];
12867 
12868   union {
12869     __IO uint16_t  USBMC;                           /*!< USB Module Control Register                                           */
12870 
12871     struct {
12872       __IO uint16_t  VDDUSBE    :  1;               /*!< USB Reference Power Supply Circuit On/Off Control                     */
12873            uint16_t             :  6;
12874       __IO uint16_t  VDCEN      :  1;               /*!< USB Regulator On/Off Control                                          */
12875     } USBMC_b;                                      /*!< BitSize                                                               */
12876   };
12877   __I  uint16_t  RESERVED17;
12878 
12879   union {
12880     __IO uint16_t  DEVADDn[6];                      /*!< Device Address %s Configuration Register                              */
12881 
12882     struct {
12883            uint16_t             :  6;
12884       __IO uint16_t  USBSPD     :  2;               /*!< Transfer Speed of Communication Target Device                         */
12885     } DEVADDn_b[6];                                 /*!< BitSize                                                               */
12886   };
12887   __I  uint32_t  RESERVED18[5];
12888 
12889   union {
12890     __IO uint32_t  PHYSLEW;                         /*!< PHY Cross Point Adjustment Register                                   */
12891 
12892     struct {
12893       __IO uint32_t  SLEWR00    :  1;               /*!< Receiver Cross Point Adjustment 00                                    */
12894       __IO uint32_t  SLEWR01    :  1;               /*!< Receiver Cross Point Adjustment 01                                    */
12895       __IO uint32_t  SLEWF00    :  1;               /*!< Receiver Cross Point Adjustment 00                                    */
12896       __IO uint32_t  SLEWF01    :  1;               /*!< Receiver Cross Point Adjustment 01                                    */
12897     } PHYSLEW_b;                                    /*!< BitSize                                                               */
12898   };
12899   __I  uint32_t  RESERVED19[195];
12900 
12901   union {
12902     __IO uint32_t  DPUSR0R;                         /*!< Deep Standby USB Transceiver Control/Pin Monitoring Register          */
12903 
12904     struct {
12905       __IO uint32_t  SRPC0      :  1;               /*!< USB Single End Receiver Control                                       */
12906       __IO uint32_t  RPUE0      :  1;               /*!< DP Pull-Up Resistor Control                                           */
12907            uint32_t             :  1;
12908       __IO uint32_t  DRPD0      :  1;               /*!< D+/D- Pull-Down Resistor Control                                      */
12909       __IO uint32_t  FIXPHY0    :  1;               /*!< USB Transceiver Output Fix                                            */
12910            uint32_t             : 11;
12911       __I  uint32_t  DP0        :  1;               /*!< USB0 D+ InputIndicates the D+ input signal of the USB.                */
12912       __I  uint32_t  DM0        :  1;               /*!< USB D-InputIndicates the D- input signal of the USB.                  */
12913            uint32_t             :  2;
12914       __I  uint32_t  DOVCA0     :  1;               /*!< USB OVRCURA InputIndicates the OVRCURA input signal of the USB.       */
12915       __I  uint32_t  DOVCB0     :  1;               /*!< USB OVRCURB InputIndicates the OVRCURB input signal of the USB.       */
12916            uint32_t             :  1;
12917       __I  uint32_t  DVBSTS0    :  1;               /*!< USB VBUS InputIndicates the VBUS input signal of the USB.             */
12918     } DPUSR0R_b;                                    /*!< BitSize                                                               */
12919   };
12920 
12921   union {
12922     __IO uint32_t  DPUSR1R;                         /*!< Deep Standby USB Suspend/Resume Interrupt Register                    */
12923 
12924     struct {
12925       __IO uint32_t  DPINTE0    :  1;               /*!< USB DP Interrupt Enable/Clear                                         */
12926       __IO uint32_t  DMINTE0    :  1;               /*!< USB DM Interrupt Enable/Clear                                         */
12927            uint32_t             :  2;
12928       __IO uint32_t  DOVRCRAE0  :  1;               /*!< USB OVRCURA Interrupt Enable/Clear                                    */
12929       __IO uint32_t  DOVRCRBE0  :  1;               /*!< USB OVRCURB Interrupt Enable/Clear                                    */
12930            uint32_t             :  1;
12931       __IO uint32_t  DVBSE0     :  1;               /*!< USB VBUS Interrupt Enable/Clear                                       */
12932            uint32_t             :  8;
12933       __I  uint32_t  DPINT0     :  1;               /*!< USB DP Interrupt Source Recovery                                      */
12934       __I  uint32_t  DMINT0     :  1;               /*!< USB DM Interrupt Source Recovery                                      */
12935            uint32_t             :  2;
12936       __I  uint32_t  DOVRCRA0   :  1;               /*!< USB OVRCURA Interrupt Source Recovery                                 */
12937       __I  uint32_t  DOVRCRB0   :  1;               /*!< USB OVRCURB Interrupt Source Recovery                                 */
12938            uint32_t             :  1;
12939       __I  uint32_t  DVBINT0    :  1;               /*!< USB VBUS Interrupt Source Recovery                                    */
12940     } DPUSR1R_b;                                    /*!< BitSize                                                               */
12941   };
12942 } R_USBFS_Type;
12943 
12944 
12945 /* ================================================================================ */
12946 /* ================                     R_FACI                     ================ */
12947 /* ================================================================================ */
12948 
12949 
12950 /**
12951   * @brief Flash Application Command Interface (R_FACI)
12952   */
12953 
12954 typedef struct {                                    /*!< R_FACI Structure                                                      */
12955   __I  uint32_t  RESERVED[36];
12956   __IO uint8_t   DFLCTL;                            /*!< Flash P/E Mode Control Register                                       */
12957   __I  uint8_t   RESERVED1[111];
12958 
12959   union {
12960     __IO uint8_t   FPMCR;                           /*!< Flash P/E Mode Control Register                                       */
12961 
12962     struct {
12963            uint8_t              :  1;
12964       __IO uint8_t   FMS0       :  1;               /*!< Flash Operating Mode Select 0FMS2,1,0: 000: Read mode 011: Discharge
12965                                                          mode 1 111: Discharge mode 2 101: Code Flash P/E mode 010: Data
12966                                                           flash P/E mode Others: Setting prohibited.                           */
12967            uint8_t              :  1;
12968       __IO uint8_t   RPDIS      :  1;               /*!< Code Flash P/E Disable                                                */
12969       __IO uint8_t   FMS1       :  1;               /*!< The bit to make data flash a programming modeRefer to the description
12970                                                          of the FMS0 bit.                                                      */
12971            uint8_t              :  1;
12972       __IO uint8_t   VLPE       :  1;               /*!< Low-Voltage P/E Mode Enable                                           */
12973       __IO uint8_t   FMS2       :  1;               /*!< Flash Operating Mode Select 2.Refer to the description of the
12974                                                          FMS0 bit.                                                             */
12975     } FPMCR_b;                                      /*!< BitSize                                                               */
12976   };
12977   __I  uint8_t   RESERVED2[3];
12978 
12979   union {
12980     __IO uint8_t   FASR;                            /*!< Flash Area Select Register                                            */
12981 
12982     struct {
12983       __IO uint8_t   EXS        :  1;               /*!< Extra area select                                                     */
12984     } FASR_b;                                       /*!< BitSize                                                               */
12985   };
12986   __I  uint8_t   RESERVED3[3];
12987 
12988   union {
12989     __IO uint16_t  FSARL;                           /*!< Flash Processing Start Address Register L                             */
12990 
12991     struct {
12992       __IO uint16_t  FSAR15_0   : 16;               /*!< Start address                                                         */
12993     } FSARL_b;                                      /*!< BitSize                                                               */
12994   };
12995   __I  uint16_t  RESERVED4[3];
12996 
12997   union {
12998     __IO uint16_t  FSARH;                           /*!< Flash Processing Start Address Register H                             */
12999 
13000     struct {
13001       __IO uint16_t  FSAR20_16  :  5;               /*!< Start address                                                         */
13002            uint16_t             :  4;
13003       __IO uint16_t  FSAR31_25  :  7;               /*!< Start address                                                         */
13004     } FSARH_b;                                      /*!< BitSize                                                               */
13005   };
13006   __I  uint16_t  RESERVED5;
13007 
13008   union {
13009     __IO uint8_t   FCR;                             /*!< Flash Control Register                                                */
13010 
13011     struct {
13012       __IO uint8_t   CMD        :  4;               /*!< Software Command Setting                                              */
13013       __IO uint8_t   DRC        :  1;               /*!< Data Read Completion                                                  */
13014            uint8_t              :  1;
13015       __IO uint8_t   STOP       :  1;               /*!< Forced Processing Stop                                                */
13016       __IO uint8_t   OPST       :  1;               /*!< Processing Start                                                      */
13017     } FCR_b;                                        /*!< BitSize                                                               */
13018   };
13019   __I  uint8_t   RESERVED6[3];
13020 
13021   union {
13022     __IO uint16_t  FEARL;                           /*!< Flash Processing End Address Register L                               */
13023 
13024     struct {
13025       __IO uint16_t  FEAR15_0   : 16;               /*!< End address                                                           */
13026     } FEARL_b;                                      /*!< BitSize                                                               */
13027   };
13028   __I  uint16_t  RESERVED7[3];
13029 
13030   union {
13031     __IO uint32_t  FEARH;                           /*!< Flash Processing End Address Register H                               */
13032 
13033     struct {
13034       __IO uint32_t  FEAR20_16  :  5;               /*!< End address                                                           */
13035            uint32_t             :  4;
13036       __IO uint32_t  FEAR31_25  :  7;               /*!< End address                                                           */
13037     } FEARH_b;                                      /*!< BitSize                                                               */
13038   };
13039 
13040   union {
13041     __IO uint32_t  FRESETR;                         /*!< Flash Reset Register                                                  */
13042 
13043     struct {
13044       __IO uint32_t  FRESET     :  1;               /*!< Software Reset of the registers                                       */
13045     } FRESETR_b;                                    /*!< BitSize                                                               */
13046   };
13047 
13048   union {
13049     __I  uint32_t  FSTATR00;                        /*!< Flash Status Register00                                               */
13050 
13051     struct {
13052       __I  uint32_t  ERERR0     :  1;               /*!< Erase Error Flag0                                                     */
13053       __I  uint32_t  PRGERR0    :  1;               /*!< Program Error Flag0                                                   */
13054       __I  uint32_t  PRGERR01   :  1;               /*!< Program Error Flag 01                                                 */
13055       __I  uint32_t  BCERR0     :  1;               /*!< Blank Check Error Flag0                                               */
13056       __I  uint32_t  ILGLERR    :  1;               /*!< Illegal Command Error Flag                                            */
13057       __I  uint32_t  EILGLERR   :  1;               /*!< Extra Area Illegal Command Error Flag                                 */
13058     } FSTATR00_b;                                   /*!< BitSize                                                               */
13059   };
13060 
13061   union {
13062     __I  uint32_t  FSTATR1;                         /*!< Flash Status Register1                                                */
13063 
13064     struct {
13065            uint32_t             :  1;
13066       __I  uint32_t  DRRDY      :  1;               /*!< Data read request                                                     */
13067            uint32_t             :  4;
13068       __I  uint32_t  FRDY       :  1;               /*!< End status signal of a sequencer                                      */
13069       __I  uint32_t  EXRDY      :  1;               /*!< End status signal of a Extra programming sequencer                    */
13070     } FSTATR1_b;                                    /*!< BitSize                                                               */
13071   };
13072 
13073   union {
13074     __IO uint32_t  FWBL0;                           /*!< Flash Write Buffer Register L0                                        */
13075 
13076     struct {
13077       __IO uint32_t  WDATA      : 16;               /*!< Program data of the program command                                   */
13078     } FWBL0_b;                                      /*!< BitSize                                                               */
13079   };
13080   __I  uint32_t  RESERVED8;
13081 
13082   union {
13083     __IO uint32_t  FWBH0;                           /*!< Flash Write Buffer Register H0                                        */
13084 
13085     struct {
13086       __IO uint32_t  WDATA      : 16;               /*!< Program data of the program command                                   */
13087     } FWBH0_b;                                      /*!< BitSize                                                               */
13088   };
13089 
13090   union {
13091     __I  uint32_t  FSTATR01;                        /*!< Flash Status Register01                                               */
13092 
13093     struct {
13094       __I  uint32_t  ERERR1     :  1;               /*!< Erase Error Flag1                                                     */
13095       __I  uint32_t  PRGERR1    :  1;               /*!< Program Error Flag1                                                   */
13096            uint32_t             :  1;
13097       __I  uint32_t  BCERR1     :  1;               /*!< Blank Check Error Flag1                                               */
13098     } FSTATR01_b;                                   /*!< BitSize                                                               */
13099   };
13100 
13101   union {
13102     __IO uint32_t  FWBL1;                           /*!< Flash Write Buffer Register L1                                        */
13103 
13104     struct {
13105       __IO uint32_t  WDATA47_32 : 16;               /*!< Program data of the program command                                   */
13106     } FWBL1_b;                                      /*!< BitSize                                                               */
13107   };
13108 
13109   union {
13110     __IO uint32_t  FWBH1;                           /*!< Flash Write Buffer Register H1                                        */
13111 
13112     struct {
13113       __IO uint32_t  WDATA63_48 : 16;               /*!< Program data of the program command                                   */
13114     } FWBH1_b;                                      /*!< BitSize                                                               */
13115   };
13116 
13117   union {
13118     __I  uint32_t  FRBL1;                           /*!< Flash Read Buffer Register L1                                         */
13119 
13120     struct {
13121       __I  uint32_t  RDATA47_32 : 16;               /*!< Read data of the consecutive read command                             */
13122     } FRBL1_b;                                      /*!< BitSize                                                               */
13123   };
13124 
13125   union {
13126     __I  uint32_t  FRBH1;                           /*!< Flash Read Buffer Register H1                                         */
13127 
13128     struct {
13129       __I  uint32_t  RDATA63_48 : 16;               /*!< Read data of the consecutive read command                             */
13130     } FRBH1_b;                                      /*!< BitSize                                                               */
13131   };
13132   __I  uint32_t  RESERVED9[12];
13133 
13134   union {
13135     __O  uint32_t  FPR;                             /*!< Protection Unlock Register                                            */
13136 
13137     struct {
13138       __O  uint32_t  FPR        :  8;               /*!< Protection Unlock Register                                            */
13139     } FPR_b;                                        /*!< BitSize                                                               */
13140   };
13141 
13142   union {
13143     __I  uint32_t  FPSR;                            /*!< Protection Unlock Status Register                                     */
13144 
13145     struct {
13146       __I  uint32_t  PERR       :  1;               /*!< Protect Error Flag                                                    */
13147     } FPSR_b;                                       /*!< BitSize                                                               */
13148   };
13149 
13150   union {
13151     __I  uint32_t  FRBL0;                           /*!< Flash Read Buffer Register L0                                         */
13152 
13153     struct {
13154       __I  uint32_t  RDATA      : 16;               /*!< Read data of the consecutive read command                             */
13155     } FRBL0_b;                                      /*!< BitSize                                                               */
13156   };
13157   __I  uint32_t  RESERVED10;
13158 
13159   union {
13160     __I  uint32_t  FRBH0;                           /*!< Flash Read Buffer Register H0                                         */
13161 
13162     struct {
13163       __I  uint32_t  RDATA      : 16;               /*!< Read data of the consecutive read command                             */
13164     } FRBH0_b;                                      /*!< BitSize                                                               */
13165   };
13166   __I  uint32_t  RESERVED11[11];
13167 
13168   union {
13169     __I  uint32_t  FSCMR;                           /*!< Flash Start-Up Setting Monitor Register                               */
13170 
13171     struct {
13172            uint32_t             :  8;
13173       __I  uint32_t  SASMF      :  1;               /*!< Start-up Area Setting Monitor Flag                                    */
13174            uint32_t             :  5;
13175       __I  uint32_t  FSPR       :  1;               /*!< Access Window Protection Flag                                         */
13176     } FSCMR_b;                                      /*!< BitSize                                                               */
13177   };
13178   __I  uint32_t  RESERVED12;
13179 
13180   union {
13181     __I  uint32_t  FAWSMR;                          /*!< Flash Access Window Start Address Monitor Register                    */
13182 
13183     struct {
13184       __I  uint32_t  FAWS       : 12;               /*!< Flash Access Window Start Address                                     */
13185     } FAWSMR_b;                                     /*!< BitSize                                                               */
13186   };
13187   __I  uint32_t  RESERVED13;
13188 
13189   union {
13190     __I  uint32_t  FAWEMR;                          /*!< Flash Access Window End Address Monitor Register                      */
13191 
13192     struct {
13193       __I  uint32_t  FAWE       : 12;               /*!< Flash Access Window End Address                                       */
13194     } FAWEMR_b;                                     /*!< BitSize                                                               */
13195   };
13196   __I  uint32_t  RESERVED14;
13197 
13198   union {
13199     __IO uint32_t  FISR;                            /*!< Flash Initial Setting Register                                        */
13200 
13201     struct {
13202       __IO uint32_t  PCKA       :  5;               /*!< Peripheral Clock Notification                                         */
13203            uint32_t             :  1;
13204       __IO uint32_t  SAS        :  2;               /*!< Temporary boot swap mode                                              */
13205     } FISR_b;                                       /*!< BitSize                                                               */
13206   };
13207 
13208   union {
13209     __IO uint32_t  FEXCR;                           /*!< Flash Extra Area Control Register                                     */
13210 
13211     struct {
13212       __IO uint32_t  CMD        :  3;               /*!< Processing Start)                                                     */
13213            uint32_t             :  4;
13214       __IO uint32_t  OPST       :  1;               /*!< Software Command Setting                                              */
13215     } FEXCR_b;                                      /*!< BitSize                                                               */
13216   };
13217 
13218   union {
13219     __I  uint32_t  FEAML;                           /*!< Flash Error Address Monitor Register L                                */
13220 
13221     struct {
13222       __I  uint32_t  FEAM       : 16;               /*!< Flash Error Address Monitor Register                                  */
13223     } FEAML_b;                                      /*!< BitSize                                                               */
13224   };
13225   __I  uint32_t  RESERVED15;
13226 
13227   union {
13228     __I  uint32_t  FEAMH;                           /*!< Flash Error Address Monitor Register H                                */
13229 
13230     struct {
13231       __I  uint32_t  FEAM       : 16;               /*!< Flash Error Address Monitor Register                                  */
13232     } FEAMH_b;                                      /*!< BitSize                                                               */
13233   };
13234   __I  uint32_t  RESERVED16;
13235 
13236   union {
13237     __I  uint32_t  FSTATR2;                         /*!< Flash Status Register2                                                */
13238 
13239     struct {
13240       __I  uint32_t  ERERR      :  1;               /*!< Erase Error Flag                                                      */
13241       __I  uint32_t  PRGERR1    :  1;               /*!< Program Error Flag                                                    */
13242       __IO uint32_t  PRGERR01   :  1;               /*!< Program Error Flag 01                                                 */
13243       __I  uint32_t  BCERR      :  1;               /*!< Blank Check Error Flag                                                */
13244       __I  uint32_t  ILGLERR    :  1;               /*!< Illegal Command Error Flag                                            */
13245       __I  uint32_t  EILGLERR   :  1;               /*!< Extra Area Illegal Command Error Flag                                 */
13246     } FSTATR2_b;                                    /*!< BitSize                                                               */
13247   };
13248  // __I  uint16_t  RESERVED17[223];
13249     __I  uint16_t  RESERVED17[7903];
13250 
13251 
13252   __IO uint16_t  FENTRYR;                           /*!< Flash P/E Mode Entry Register                                         */
13253   __I  uint32_t  RESERVED18[3];
13254   __IO uint8_t   FLWAITR;                           /*!< Flash Wait Cycle Register                                             */
13255 } R_FACI_Type;
13256 
13257 /* =========================================================================================================================== */
13258 /* ================                                        R_SDADC0                                           ================ */
13259 /* =========================================================================================================================== */
13260 
13261 
13262 /**
13263   * @brief R_SDADC0 (R_SDADC0)
13264   */
13265 
13266 typedef struct {                                /*!< (@ 0x4009C000) SDADC0 Structure                                           */
13267 
13268   union {
13269     __IOM uint16_t STC1;                        /*!< (@ 0x00000000) Startup Control Register 1                                 */
13270 
13271     struct {
13272       __IOM uint16_t CLKDIV     : 4;            /*!< [3..0] SDADC24 Reference Clock Division                                   */
13273       __IM  uint16_t            : 3;
13274       __IOM uint16_t SDADLPM    : 1;            /*!< [7..7] A/D conversion operation model select                              */
13275       __IOM uint16_t VSBIAS     : 4;            /*!< [11..8] VSBIAS                                                            */
13276       __IM  uint16_t            : 3;
13277       __IOM uint16_t VREFSEL    : 1;            /*!< [15..15] VREFSEL                                                          */
13278     } STC1_b;
13279   } ;
13280   __IM  uint16_t  RESERVED;
13281 
13282   union {
13283     __IOM uint8_t STC2;                         /*!< (@ 0x00000004) Startup Control Register 2                                 */
13284 
13285     struct {
13286       __IOM uint8_t BGRPON      : 1;            /*!< [0..0] BGRPON                                                             */
13287       __IOM uint8_t ADCPON      : 1;            /*!< [1..1] ADCPON                                                             */
13288       __IOM uint8_t ADFPWDS     : 1;            /*!< [2..2] ADFPWDS                                                            */
13289     } STC2_b;
13290   } ;
13291   __IM  uint8_t   RESERVED1;
13292   __IM  uint16_t  RESERVED2;
13293 
13294   union {
13295     __IOM uint32_t PGAC[5];                     /*!< (@ 0x00000008) Input Multiplexer [0..4] Setting Register                  */
13296 
13297     struct {
13298       __IOM uint32_t PGAGC      : 5;            /*!< [4..0] Gain selection of a programmable gain instrumentation
13299                                                      amplifier ( Gset1, Gset2, Gtotal )                                        */
13300       __IOM uint32_t PGAOSR     : 3;            /*!< [7..5] Oversampling ratio select                                          */
13301       __IOM uint32_t PGAOFS     : 5;            /*!< [12..8] Offset voltage select                                             */
13302       __IM  uint32_t            : 1;
13303       __IOM uint32_t PGAPOL     : 1;            /*!< [14..14] Polarity select                                                  */
13304       __IOM uint32_t PGASEL     : 1;            /*!< [15..15] Analog Channel Input Mode Select                                 */
13305       __IOM uint32_t PGACTM     : 5;            /*!< [20..16] Coefficient (m) selection of the A/D conversion count
13306                                                      (N) in AUTOSCAN                                                           */
13307       __IOM uint32_t PGACTN     : 3;            /*!< [23..21] Coefficient (n) selection of the A/D conversion count
13308                                                      (N) in AUTOSCAN                                                           */
13309       __IOM uint32_t PGAAVN     : 2;            /*!< [25..24] Selection of the number of data to be averaged                   */
13310       __IOM uint32_t PGAAVE     : 2;            /*!< [27..26] Selection of averaging processing                                */
13311       __IOM uint32_t PGAREV     : 1;            /*!< [28..28] Single-End Input A/D Converted Data Inversion Select             */
13312       __IM  uint32_t            : 1;
13313       __IOM uint32_t PGACVE     : 1;            /*!< [30..30] Calibration enable                                               */
13314       __IOM uint32_t PGAASN     : 1;            /*!< [31..31] Selection of the mode for specifying the number of
13315                                                      A/D conversions in ADSCAN                                                 */
13316     } PGAC_b[5];
13317   } ;
13318 
13319   union {
13320     __IOM uint32_t ADC1;                        /*!< (@ 0x0000001C) Sigma-Delta A/D Converter Control Register 1               */
13321 
13322     struct {
13323       __IOM uint32_t SDADSCM    : 1;            /*!< [0..0] Selection of autoscan mode                                         */
13324       __IM  uint32_t            : 3;
13325       __IOM uint32_t SDADTMD    : 1;            /*!< [4..4] Selection of A/D conversion trigger signal                         */
13326       __IM  uint32_t            : 3;
13327       __IOM uint32_t SDADBMP    : 5;            /*!< [12..8] A/D conversion control of the signal from input multiplexer       */
13328       __IM  uint32_t            : 3;
13329       __IOM uint32_t PGADISA    : 1;            /*!< [16..16] Control of disconnection detection                               */
13330       __IOM uint32_t PGADISC    : 1;            /*!< [17..17] Disconnection Detection Assist Setting                           */
13331       __IM  uint32_t            : 2;
13332       __IOM uint32_t PGASLFT    : 1;            /*!< [20..20] PGA offset self-diagnosis enable                                 */
13333     } ADC1_b;
13334   } ;
13335 
13336   union {
13337     __IOM uint8_t ADC2;                         /*!< (@ 0x00000020) Sigma-Delta A/D Converter Control Register 2               */
13338 
13339     struct {
13340       __IOM uint8_t SDADST      : 1;            /*!< [0..0] Control of A/D conversion                                          */
13341     } ADC2_b;
13342   } ;
13343   __IM  uint8_t   RESERVED3;
13344   __IM  uint16_t  RESERVED4;
13345 
13346   union {
13347     __IOM uint32_t ADCR;                        /*!< (@ 0x00000024) Sigma-delta A/D Converter Conversion Result Register       */
13348 
13349     struct {
13350       __IM  uint32_t SDADCRD    : 24;           /*!< [23..0] The 24-bit A/D conversion result                                  */
13351       __IM  uint32_t SDADCRS    : 1;            /*!< [24..24] Status of an A/D conversion result                               */
13352       __IM  uint32_t SDADCRC    : 3;            /*!< [27..25] Channel number for an A/D conversion result                      */
13353     } ADCR_b;
13354   } ;
13355 
13356   union {
13357     __IM  uint32_t ADAR;                        /*!< (@ 0x00000028) Sigma-delta A/D Converter Average Value Register           */
13358 
13359     struct {
13360       __IM  uint32_t SDADMVD    : 24;           /*!< [23..0] The 24-bit A/D average value                                      */
13361       __IM  uint32_t SDADMVS    : 1;            /*!< [24..24] Status of an A/D conversion result                               */
13362       __IM  uint32_t SDADMVC    : 3;            /*!< [27..25] Channel number for an A/D conversion result                      */
13363     } ADAR_b;
13364   } ;
13365   __IM  uint32_t  RESERVED5;
13366 
13367   union {
13368     __IOM uint8_t CLBC;                         /*!< (@ 0x00000030) Calibration Control Register                               */
13369 
13370     struct {
13371       __IOM uint8_t CLBMD       : 2;            /*!< [1..0] These bits are read as 0. The write value should be 0.             */
13372     } CLBC_b;
13373   } ;
13374   __IM  uint8_t   RESERVED6;
13375   __IM  uint16_t  RESERVED7;
13376 
13377   union {
13378     __IOM uint8_t CLBSTR;                       /*!< (@ 0x00000034) Calibration Start Control Register                         */
13379 
13380     struct {
13381       __IOM uint8_t CLBST       : 1;            /*!< [0..0] Calibration start control                                          */
13382     } CLBSTR_b;
13383   } ;
13384   __IM  uint8_t   RESERVED8;
13385   __IM  uint16_t  RESERVED9;
13386   __IM  uint32_t  RESERVED10;
13387 
13388   union {
13389     __IM  uint8_t CLBSSR;                       /*!< (@ 0x0000003C) Calibration Status Register                                */
13390 
13391     struct {
13392       __IM  uint8_t CLBSS       : 1;            /*!< [0..0] Calibration status                                                 */
13393     } CLBSSR_b;
13394   } ;
13395 } R_SDADC0_Type;                                /*!< Size = 61 (0x3d)                                                          */
13396 
13397 
13398 
13399 
13400 
13401 
13402 /* --------  End of section using anonymous unions and disabling warnings  -------- */
13403 #if   defined (__CC_ARM)
13404   #pragma pop
13405 #elif defined (__ICCARM__)
13406   /* leave anonymous unions enabled */
13407 #elif (__ARMCC_VERSION >= 6010050)
13408   #pragma clang diagnostic pop
13409 #elif defined (__GNUC__)
13410   /* anonymous unions are enabled by default */
13411 #elif defined (__TMS470__)
13412   /* anonymous unions are enabled by default */
13413 #elif defined (__TASKING__)
13414   #pragma warning restore
13415 #elif defined (__CSMC__)
13416   /* anonymous unions are enabled by default */
13417 #else
13418   #warning Not supported compiler type
13419 #endif
13420 
13421 
13422 
13423 
13424 /* ================================================================================ */
13425 /* ================              Peripheral memory map             ================ */
13426 /* ================================================================================ */
13427 
13428 #define R_MMPU_BASE                     0x40000000UL
13429 #define R_SMPU_BASE                     0x40000C00UL
13430 #define R_SPMON_BASE                    0x40000D00UL
13431 #define R_SRAM_BASE                     0x40002000UL
13432 #define R_BUS_BASE                      0x40003000UL
13433 #define R_DTC_BASE                      0x40005400UL
13434 #define R_ICU_BASE                      0x40006000UL
13435 #define R_DBG_BASE                      0x4001B000UL
13436 #define R_ROMC_BASE                     0x4001C000UL
13437 #define R_SYSTEM_BASE                   0x4001E000UL
13438 #define R_IOPORT0_BASE                  0x40040000UL
13439 #define R_IOPORT1_BASE                  0x40040020UL
13440 #define R_IOPORT2_BASE                  0x40040040UL
13441 #define R_IOPORT3_BASE                  0x40040060UL
13442 #define R_IOPORT4_BASE                  0x40040080UL
13443 #define R_IOPORT5_BASE                  0x400400A0UL
13444 #define R_IOPORT9_BASE                  0x40040120UL
13445 #define R_PFS_BASE                      0x40040800UL
13446 #define R_PMISC_BASE                    0x40040D00UL
13447 #define R_ELC_BASE                      0x40041000UL
13448 #define R_POEG_BASE                     0x40042000UL
13449 #define R_RTC_BASE                      0x40044000UL
13450 #define R_WDT_BASE                      0x40044200UL
13451 #define R_IWDT_BASE                     0x40044400UL
13452 #define R_CAC_BASE                      0x40044600UL
13453 #define R_MSTP_BASE                     0x40047000UL
13454 #define R_SSI0_BASE                     0x4004E000UL
13455 #define R_SSI1_BASE                     0x4004E100UL
13456 #define R_CAN0_BASE                     0x40050000UL
13457 #define R_IIC0_BASE                     0x40053000UL
13458 #define R_IIC1_BASE                     0x40053100UL
13459 #define R_DOC_BASE                      0x40054100UL
13460 #define R_S16ADC_BASE                   0x4005C000UL
13461 #define R_DAC_BASE                      0x4005E000UL
13462 #define R_SCI0_BASE                     0x40070000UL
13463 #define R_SCI1_BASE                     0x40070020UL
13464 #define R_SCI9_BASE                     0x40070120UL
13465 #define R_RSPI0_BASE                    0x40072000UL
13466 #define R_RSPI1_BASE                    0x40072100UL
13467 #define R_CRC_BASE                      0x40074000UL
13468 #define R_GPTB0_BASE                    0x40078000UL
13469 #define R_GPTB1_BASE                    0x40078100UL
13470 #define R_GPTB2_BASE                    0x40078200UL
13471 #define R_GPTB3_BASE                    0x40078300UL
13472 #define R_GPTB4_BASE                    0x40078400UL
13473 #define R_GPTB5_BASE                    0x40078500UL
13474 #define R_GPTB6_BASE                    0x40078600UL
13475 #define R_GPT_OPS_BASE                  0x40078FF0UL
13476 #define R_GPT_ODC_BASE                  0x4007B000UL
13477 #define R_KINT_BASE                     0x40080000UL
13478 #define R_CTSU_BASE                     0x40081000UL
13479 #define R_AGT0_BASE                     0x40084000UL
13480 #define R_AGT1_BASE                     0x40084100UL
13481 #define R_ACMPHS0_BASE                  0x40085000UL
13482 #define R_ACMPLP_BASE                   0x40085E00UL
13483 #define R_OPAMP_BASE                    0x400867F8UL
13484 #define R_SDADC24_BASE                  0x4009C000UL
13485 #define R_DALI_BASE                     0x4008F000UL
13486 #define R_USBFS_BASE                    0x40090000UL
13487 #define R_DAC8_BASE                     0x4009E000UL
13488 #define R_FACI_BASE                     0x407EC000UL
13489 #define R_TSN_BASE                      0x407EC228UL
13490 #define R_TSN_CAL_BASE                  0x407EC228UL
13491 #define R_SDADC0_BASE                   0x4009C000UL
13492 
13493 
13494 /* ================================================================================ */
13495 /* ================             Peripheral declaration             ================ */
13496 /* ================================================================================ */
13497 
13498 #define R_ACMPHS0                       ((R_ACMPHS0_Type          *) R_ACMPHS0_BASE)
13499 #define R_ACMPLP                        ((R_ACMPLP_Type           *) R_ACMPLP_BASE)
13500 #define R_MMPU                          ((R_MMPU_Type             *) R_MMPU_BASE)
13501 #define R_SMPU                          ((R_SMPU_Type             *) R_SMPU_BASE)
13502 #define R_SPMON                         ((R_SPMON_Type            *) R_SPMON_BASE)
13503 #define R_SRAM                          ((R_SRAM_Type             *) R_SRAM_BASE)
13504 #define R_BUS                           ((R_BUS_Type              *) R_BUS_BASE)
13505 #define R_DTC                           ((R_DTC_Type              *) R_DTC_BASE)
13506 #define R_ICU                           ((R_ICU_Type              *) R_ICU_BASE)
13507 #define R_DBG                           ((R_DBG_Type              *) R_DBG_BASE)
13508 #define R_ROMC                          ((R_ROMC_Type             *) R_ROMC_BASE)
13509 #define R_SYSTEM                        ((R_SYSTEM_Type           *) R_SYSTEM_BASE)
13510 #define R_IOPORT0                       ((R_IOPORT0_Type          *) R_IOPORT0_BASE)
13511 #define R_IOPORT1                       ((R_IOPORT1_Type          *) R_IOPORT1_BASE)
13512 #define R_IOPORT2                       ((R_IOPORT1_Type          *) R_IOPORT2_BASE)
13513 #define R_IOPORT3                       ((R_IOPORT1_Type          *) R_IOPORT3_BASE)
13514 #define R_IOPORT4                       ((R_IOPORT1_Type          *) R_IOPORT4_BASE)
13515 #define R_IOPORT5                       ((R_IOPORT0_Type          *) R_IOPORT5_BASE)
13516 #define R_IOPORT9                       ((R_IOPORT0_Type          *) R_IOPORT9_BASE)
13517 #define R_PFS                           ((R_PFS_Type              *) R_PFS_BASE)
13518 #define R_PMISC                         ((R_PMISC_Type            *) R_PMISC_BASE)
13519 #define R_ELC                           ((R_ELC_Type              *) R_ELC_BASE)
13520 #define R_POEG                          ((R_POEG_Type             *) R_POEG_BASE)
13521 #define R_RTC                           ((R_RTC_Type              *) R_RTC_BASE)
13522 #define R_WDT                           ((R_WDT_Type              *) R_WDT_BASE)
13523 #define R_IWDT                          ((R_IWDT_Type             *) R_IWDT_BASE)
13524 #define R_CAC                           ((R_CAC_Type              *) R_CAC_BASE)
13525 #define R_MSTP                          ((R_MSTP_Type             *) R_MSTP_BASE)
13526 #define R_SSI0                          ((R_SSI0_Type             *) R_SSI0_BASE)
13527 #define R_SSI1                          ((R_SSI0_Type             *) R_SSI1_BASE)
13528 #define R_CAN0                          ((R_CAN0_Type             *) R_CAN0_BASE)
13529 #define R_IIC0                          ((R_IIC0_Type             *) R_IIC0_BASE)
13530 #define R_IIC1                          ((R_IIC0_Type             *) R_IIC1_BASE)
13531 #define R_DOC                           ((R_DOC_Type              *) R_DOC_BASE)
13532 #define R_S16ADC                        ((R_S16ADC_Type           *) R_S16ADC_BASE)
13533 #define R_TSN                           ((R_TSN_Calibration_Type  *) R_TSN_BASE)
13534 #define R_TSN_CAL                       ((R_TSN_Calibration_Type  *) R_TSN_CAL_BASE)
13535 #define R_DAC                           ((R_DAC_Type              *) R_DAC_BASE)
13536 #define R_SCI0                          ((R_SCI0_Type             *) R_SCI0_BASE)
13537 #define R_SCI1                          ((R_SCI0_Type             *) R_SCI1_BASE)
13538 #define R_SCI9                          ((R_SCI0_Type             *) R_SCI9_BASE)
13539 #define R_RSPI0                         ((R_RSPI0_Type            *) R_RSPI0_BASE)
13540 #define R_RSPI1                         ((R_RSPI0_Type            *) R_RSPI1_BASE)
13541 #define R_CRC                           ((R_CRC_Type              *) R_CRC_BASE)
13542 #define R_GPTB0                         ((R_GPTB0_Type            *) R_GPTB0_BASE)
13543 #define R_GPTB1                         ((R_GPTB0_Type            *) R_GPTB1_BASE)
13544 #define R_GPTB2                         ((R_GPTB0_Type            *) R_GPTB2_BASE)
13545 #define R_GPTB3                         ((R_GPTB0_Type            *) R_GPTB3_BASE)
13546 #define R_GPTB4                         ((R_GPTB0_Type            *) R_GPTB4_BASE)
13547 #define R_GPTB5                         ((R_GPTB0_Type            *) R_GPTB5_BASE)
13548 #define R_GPTB6                         ((R_GPTB0_Type            *) R_GPTB6_BASE)
13549 #define R_GPT_OPS                       ((R_GPT_OPS_Type          *) R_GPT_OPS_BASE)
13550 #define R_GPT_ODC                       ((R_GPT_ODC_Type          *) R_GPT_ODC_BASE)
13551 #define R_KINT                          ((R_KINT_Type             *) R_KINT_BASE)
13552 #define R_CTSU                          ((R_CTSU_Type             *) R_CTSU_BASE)
13553 #define R_AGT0                          ((R_AGT0_Type             *) R_AGT0_BASE)
13554 #define R_AGT1                          ((R_AGT0_Type             *) R_AGT1_BASE)
13555 #define R_OPAMP                         ((R_OPAMP_Type            *) R_OPAMP_BASE)
13556 #define R_SDADC24                       ((R_SDADC24_Type          *) R_SDADC24_BASE)
13557 #define R_USBFS                         ((R_USBFS_Type            *) R_USBFS_BASE)
13558 #define R_FACI                          ((R_FACI_Type             *) R_FACI_BASE)
13559 #define R_SDADC0                        ((R_SDADC0_Type           *) R_SDADC0_BASE)
13560 #define R_DAC8                          ((R_DAC8_Type             *) R_DAC8_BASE)
13561 
13562 /** @} */ /* End of group Device_Peripheral_Registers */
13563 /** @} */ /* End of group R7FS1JAx */
13564 /** @} */ /* End of group Renesas */
13565 
13566 #ifdef __cplusplus
13567 }
13568 #endif
13569 
13570 
13571 #endif  /* R7FS1JAX_H */
13572 
13573