Home
last modified time | relevance | path

Searched refs:SPI_I2SPR_ODD_Pos (Results 1 – 25 of 25) sorted by relevance

/btstack/port/stm32-f4discovery-usb/Drivers/CMSIS/Device/ST/STM32F4xx/Include/
H A Dstm32f410rx.h5750 #define SPI_I2SPR_ODD_Pos (8U) macro
5751 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
H A Dstm32f410tx.h5700 #define SPI_I2SPR_ODD_Pos (8U) macro
5701 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
H A Dstm32f410cx.h5746 #define SPI_I2SPR_ODD_Pos (8U) macro
5747 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
H A Dstm32f401xe.h5781 #define SPI_I2SPR_ODD_Pos (8U) macro
5782 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
H A Dstm32f401xc.h5781 #define SPI_I2SPR_ODD_Pos (8U) macro
5782 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
H A Dstm32f411xe.h5812 #define SPI_I2SPR_ODD_Pos (8U) macro
5813 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
H A Dstm32f412cx.h10386 #define SPI_I2SPR_ODD_Pos (8U) macro
10387 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
H A Dstm32f405xx.h11266 #define SPI_I2SPR_ODD_Pos (8U) macro
11267 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
H A Dstm32f415xx.h11551 #define SPI_I2SPR_ODD_Pos (8U) macro
11552 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
H A Dstm32f412zx.h11396 #define SPI_I2SPR_ODD_Pos (8U) macro
11397 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
H A Dstm32f407xx.h11602 #define SPI_I2SPR_ODD_Pos (8U) macro
11603 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
H A Dstm32f412vx.h11376 #define SPI_I2SPR_ODD_Pos (8U) macro
11377 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
H A Dstm32f413xx.h12037 #define SPI_I2SPR_ODD_Pos (8U) macro
12038 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
H A Dstm32f423xx.h12187 #define SPI_I2SPR_ODD_Pos (8U) macro
12188 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
H A Dstm32f412rx.h11363 #define SPI_I2SPR_ODD_Pos (8U) macro
11364 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
H A Dstm32f417xx.h11884 #define SPI_I2SPR_ODD_Pos (8U) macro
11885 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
H A Dstm32f446xx.h12777 #define SPI_I2SPR_ODD_Pos (8U) macro
12778 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
H A Dstm32f427xx.h12747 #define SPI_I2SPR_ODD_Pos (8U) macro
12748 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
H A Dstm32f437xx.h13049 #define SPI_I2SPR_ODD_Pos (8U) macro
13050 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
H A Dstm32f429xx.h13103 #define SPI_I2SPR_ODD_Pos (8U) macro
13104 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
H A Dstm32f439xx.h13397 #define SPI_I2SPR_ODD_Pos (8U) macro
13398 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
H A Dstm32f469xx.h16118 #define SPI_I2SPR_ODD_Pos (8U) macro
16119 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
H A Dstm32f479xx.h16415 #define SPI_I2SPR_ODD_Pos (8U) macro
16416 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
/btstack/port/stm32-l073rz-nucleo-em9304/Drivers/CMSIS/Device/ST/STM32L0xx/Include/
H A Dstm32l073xx.h5573 #define SPI_I2SPR_ODD_Pos (8U) macro
5574 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
/btstack/port/stm32-f4discovery-cc256x/Drivers/CMSIS/Device/ST/STM32F4xx/Include/
H A Dstm32f407xx.h11618 #define SPI_I2SPR_ODD_Pos (8U) macro
11619 #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */