rx_fifo_trigger (reference) in projects: btstack

Searched refs:rx_fifo_trigger (Results 1 – 6 of 6) sorted by relevance

/btstack/port/renesas-tb-s1ja-cc256x/template/btstack_example/synergy/ssp/inc/driver/instances/
H A D	r_sci_uart.h	`131 sci_uart_rx_fifo_trigger_t rx_fifo_trigger; member`
/btstack/port/renesas-ek-ra6m4a-da14531/e2-project/ra/fsp/inc/instances/
H A D	r_sci_uart.h	`187 …sci_uart_rx_fifo_trigger_t rx_fifo_trigger; ///< Receive FIFO trigger level, unused if channel… member`
/btstack/port/renesas-tb-s1ja-cc256x/template/btstack_example/src/synergy_gen/
H A D	hal_data.c	`136 ….bitrate_modulation = true, .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_1, .baud_rate_error_x_1000…`
/btstack/port/renesas-ek-ra6m4a-da14531/e2-project/ra_gen/
H A D	hal_data.c	`172 ….rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, .p_baud_setting = &g_uart0_baud_setting, .flow_co…`
/btstack/port/renesas-ek-ra6m4a-da14531/e2-project/ra/fsp/src/r_sci_uart/
H A D	r_sci_uart.c	`1437 … fcr \|= (((p_ctrl->fifo_depth - 1U) & p_extend->rx_fifo_trigger) & SCI_UART_FCR_TRIGGER_MASK) << in r_sci_uart_fifo_cfg()`
/btstack/port/renesas-tb-s1ja-cc256x/template/btstack_example/synergy/ssp/src/driver/r_sci_uart/
H A D	r_sci_uart.c	`1108 … uint16_t rx_fifo_setting = (uint16_t) (fifo_trigger_mask & (uint16_t) p_extend->rx_fifo_trigger); in r_sci_uart_fifo_cfg()`