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Searched refs:source_clock (Results 1 – 5 of 5) sorted by relevance

/btstack/port/renesas-tb-s1ja-cc256x/template/btstack_example/synergy/ssp/src/driver/r_cgc/
H A Dr_cgc.c115 static uint32_t r_cgc_clockhz_calculate (cgc_clock_t source_clock, cgc_sys_clock_div_t divider);
398 … CGC_ERROR_RETURN(HW_CGC_ClockSourceValidCheck(p_pll_cfg->source_clock), SSP_ERR_INVALID_ARGUMENT); in R_CGC_ClocksCfg()
399 …CGC_ERROR_RETURN(CGC_CLOCK_CHANGE_STOP != options[p_pll_cfg->source_clock], SSP_ERR_INVALID_ARGUME… in R_CGC_ClocksCfg()
1387 err = R_CGC_ClockStart(p_pll_cfg->source_clock, (cgc_clock_cfg_t *)p_clk_cfg); in r_cgc_clock_start_stop()
1390 err = r_cgc_stabilization_wait(p_pll_cfg->source_clock); in r_cgc_clock_start_stop()
1783 …CGC_ERROR_RETURN(r_cgc_clock_run_state_get(gp_system_reg, p_clock_cfg->source_clock), SSP_ERR_MAIN… in r_cgc_prepare_pll_clock()
1791 …r_cgc_pll_clocksource_set(gp_system_reg, p_clock_cfg->source_clock); // configure PLL source clock… in r_cgc_prepare_pll_clock()
2347 if ((CGC_CLOCK_MAIN_OSC != cfg->source_clock) && (CGC_CLOCK_HOCO != cfg->source_clock)) in r_cgc_clockcfg_valid_check()
2442 static uint32_t r_cgc_clockhz_calculate (cgc_clock_t source_clock, cgc_sys_clock_div_t divider) in r_cgc_clockhz_calculate() argument
2445 return (uint32_t) ((g_clock_freq[source_clock]) >> (uint32_t)divider); in r_cgc_clockhz_calculate()
/btstack/port/renesas-ek-ra6m4a-da14531/e2-project/ra/fsp/src/bsp/mcu/all/
H A Dbsp_mcu_api.h55 bsp_clocks_source_t source_clock; ///< OCTACLK source clock member
H A Dbsp_clocks.c1287 .source_clock = (bsp_clocks_source_t) BSP_CFG_OCTA_SOURCE, in bsp_clock_init()
1588 …R_SYSTEM->OCTACKCR = (uint8_t) (p_octaclk_setting->source_clock | R_SYSTEM_OCTACKCR_OCTACKSREQ_… in R_BSP_OctaclkUpdate()
1591 R_SYSTEM->OCTACKCR = (uint8_t) p_octaclk_setting->source_clock; in R_BSP_OctaclkUpdate()
1611 uint32_t source_clock = g_clock_freq[clock]; in R_BSP_SourceClockHzGet() local
1613 return source_clock; in R_BSP_SourceClockHzGet()
/btstack/port/renesas-tb-s1ja-cc256x/template/btstack_example/synergy/ssp/inc/driver/api/
H A Dr_cgc_api.h124 cgc_clock_t source_clock; ///< PLL source clock (S7G2 only). member
/btstack/port/renesas-ek-ra6m4a-da14531/e2-project/ra/fsp/inc/api/
H A Dr_cgc_api.h163 cgc_clock_t source_clock; ///< PLL source clock (main oscillator or HOCO) member