Searched refs:reg (Results 1 – 15 of 15) sorted by relevance
6 reg = 0x57 variable8 while not (len(bits) and reg==0x57):9 if reg & 0x3f < num_channels and reg & 0x40:10 channels[reg & 0x3f] = len(bits)11 bit = (reg & 1)13 reg >>= 114 reg |= (bit << 6)15 reg ^= (bit << 2)
7 #register.c: $(plugin_src) $(ALL_DISSECTORS_SRC) $(top_srcdir)/tools/make-dissector-reg \8 # $(top_srcdir)/tools/make-dissector-reg.py11 # $(PYTHON) $(top_srcdir)/tools/make-dissector-reg.py $(srcdir) \15 # $(top_srcdir)/tools/make-dissector-reg $(srcdir) \23 ${CMAKE_SOURCE_DIR}/tools/make-dissector-reg.py29 ${CMAKE_SOURCE_DIR}/tools/make-dissector-reg30 ${CMAKE_SOURCE_DIR}/tools/make-dissector-reg.py
83 plugin.c: $(DISSECTOR_SRC) $(top_srcdir)/tools/make-dissector-reg \84 $(top_srcdir)/tools/make-dissector-reg.py87 $(PYTHON) $(top_srcdir)/tools/make-dissector-reg.py $(srcdir) \91 $(top_srcdir)/tools/make-dissector-reg $(srcdir) \
82 plugin.c: $(DISSECTOR_SRC) moduleinfo.h ../../tools/make-dissector-reg.py86 plugin.c: $(DISSECTOR_SRC) moduleinfo.h ../../tools/make-dissector-reg88 @$(SH) ../../tools/make-dissector-reg . plugin $(DISSECTOR_SRC)
674 uint16_t reg, count; in crcgen() local676 reg = (reverse(UAP) << 8) & 0xff00; in crcgen()681 reg = (reg >> 1) | (((reg & 0x0001) ^ (bit & 0x01))<<15); in crcgen()684 reg ^= ((reg & 0x8000)>>5); in crcgen()687 reg ^= ((reg & 0x8000)>>12); in crcgen()689 return reg; in crcgen()